•Project 4 Questions •Reminder: Midterm Exam on Tuesday...

CMSC 313 Lecture 15

• Project 4 Questions

• Reminder: Midterm Exam on Tuesday 10/26• Interrupts

• Cache Memory [time permitting]

UMBC, CMSC313, Richard Chang <[email protected]>

Mohamed Younis CMCS 313, Computer Organization and Assembly Language 3

Motivating Example; An Assembly language program for printing data

MOV EDX, 378H ;Printer Data PortMOV ECX, 0 ;Use ECX as the loop counter

XYZ: MOV AL, [ABC + ECX] ;ABC is the beginning of the memory area; that characters are being printed from

OUT [DX], AL ;Send a character to the printerINC ECXCMP ECX, 100000 ; print this many charactersJL XYZ

Issues:! What about difference in speed between the processor and printer?

! What about the buffer size of the printer?" Small buffer can lead to some lost data that will not get printed

Communication with input/output devices needs handshaking protocolsCommunication with input/output devices needs handshaking protocols


Communicating with I/O Devices! The OS needs to know when:

➨ The I/O device has completed an operation➨ The I/O operation has encountered an error

! This can be accomplished in two different ways:➨ Polling:

" The I/O device put information in a status register" The OS periodically check the status register

➨ I/O Interrupt:" An I/O interrupt is an externally stimulated event, asynchronous to

instruction execution but does NOT prevent instruction completion" Whenever an I/O device needs attention from the processor, it

interrupts the processor from what it is currently doing" Some processors deal with interrupts as special exceptions

* Slide is partially a courtesy of Dave Patterson

These schemes requires heavy processor’s involvement and suitable only for low bandwidth devices such as the keyboardThese schemes requires heavy processor’s involvement and suitable only for low bandwidth devices such as the keyboard


Polling: Programmed I/O

! Advantage:" Simple: the processor is totally in control and does all the work

! Disadvantage:" Polling overhead can consume a lot of CPU time

CPU

IOC

device

Memory

Is thedata

ready?

readdata

storedata

yes no

done? noyes

busy wait loopnot an efficient

way to use the CPUunless the device

is very fast!

but checks for I/O completion can bedispersed among

computation intensive code

* Slide is courtesy of Dave Patterson


" The fetch-execute cycle is a program-driven model of computation" Computers are not totally program driven as they are also hardware driven" An I/O interrupt is an externally stimulated event, asynchronous to instruction

execution but does NOT prevent instruction completion" Whenever an I/O device needs attention from the processor, it interrupts the

processor from what it is currently doing" Processors typically have one or multiple interrupt pins for device interface

External Interrupt

CPU Memory I/O(Printer)

Address Bus

Data Bus

Interrupt Line


Interrupt Driven Data Transfer

! Advantage:" User program progress is only halted during actual transfer

! Disadvantage: special hardware is needed to:" Cause an interrupt (I/O device)" Detect an interrupt (processor)" Save the proper states to resume after the interrupt (processor)

addsubandornop

readstore...rtimemory

userprogram(1) I/O

interrupt

(2) save PC

(3) interruptservice addr

interruptserviceroutine(4)

CPU

IOC

device

Memory

:



"The 80386 has only one interrupt pin and relies on an interrupt controller to interface and prioritize the different I/O devices

" Interrupt handling follows the following steps:➊ Complete current instruction ➋ Save current program counter and flags into the stack➌ Get interrupt number responsible for the signal from interrupt controller➍ Find the address of the appropriate interrupt service routine ➎ Transfer control to interrupt service routine

" A special interrupt acknowledge bus cycle is used to read interrupt number" Interrupt controller has ports that are accessible through IN and OUT

80386 Interrupt Handling

CPU Memory I/O

Address Bus

Data Bus

Interrupt Line

InterruptController

IRQ Bus


Gate #255

. . .

Gate #1

Gate #4

Gate #3

Gate #2

Gate #0

Gate #5

b + 2040

b + 8

b + 32

b + 24

b + 16

b

b + 40

Address

Interrupt Descriptor Table

ISR AddressUpper 2 Bytes Type ISR Address

Lower 2 Bytes

63 4847 16 15 04443 4039

" The address of an ISR is fetched from an interrupt descriptor table

" IDT register is loaded by operating system and points to the interrupt descriptor table

" Each entry is 8 bytes indicating address of ISR and type of interrupt (trap, fault etc.)

" RESET and non-maskable (NMI) interrupts use distinct processor pins

" NMI is used to for parity error or power supply problems and thus cannot be disabled


! Since the 80386 has one interrupt pin, an interrupt controller is needed to handle multiple input and output devices

! The Intel 8259 is a programmable interrupt controller that can be used either singly or in a two-tier configuration

The 8259 Interrupt Controller

Slave8259#1

Master8259

Slave8259#2

Slave8259#8

...

! When used as a master, the 8259 can interface with up to 8 slaves

! Since the 8259 controller can be a master or a slave, the interrupt request lines must be programmable

! Programming the 8259 chips takes place at boot time using the OUT commands

! The order of the interrupt lines reflects the priority assigned to them


The ISA Architecture

Master8259

IRQ 0IRQ 1

IRQ 3IRQ 4IRQ 5IRQ 6IRQ 7

Slave8259

IRQ 8IRQ 9

IRQ 11IRQ 12IRQ 13IRQ 14IRQ 15

IRQ 10

! The ISA architecture is set by IBM competitors and standardizes:" The interrupt controller circuitry" Many IRQ assignments" Many I/O port assignments" The signals and connections made available to expansion cards

! A one-master-one-slave configuration is the norm for ISA architecture

! Priority is assigned in the following order: IRQ 0, IRQ 1, IRQ 8, …, IRQ 15, IRQ 3, …, IRQ 7


IRQ ALLOCATION INTRRUPT NUM BER IRQ 0 System Tim er 08H IRQ 1 Keyboard 09H IRQ 3 Seria l Port #2 OBH IRQ 4 Seria l Port # 1 O CH IRQ 5 Paralle l Port #2 O DH IRQ 6 Floppy Controller OEH IRQ 7 Paralle l Port # 1 O FH IRQ 8 Real tim e clock 70H IRQ 9 available 71 H IRQ 10 available 72H IRQ 11 available 73H IRQ 12 M ouse 74H IRQ 13 87 ERRO R line 75H IRQ 14 Hard drive contro ller 76H IRQ 15 available 77H

ISA Interrupt Routings

linux1% cat /proc/interrupts


I/O Interrupt vs. Exception! An I/O interrupt is just like the exceptions except:

" An I/O interrupt is asynchronous" Further information needs to be conveyed" Typically exceptions are more urgent than interrupts

! An I/O interrupt is asynchronous with respect to instruction execution:" I/O interrupt is not associated with any instruction" I/O interrupt does not prevent any instruction from completion

• You can pick your own convenient point to take an interrupt

! I/O interrupt is more complicated than exception:" Needs to convey the identity of the device generating the interrupt" Interrupt requests can have different urgencies:

• Interrupt request needs to be prioritized• Priority indicates urgency of dealing with the interrupt• High speed devices usually receive highest priority



Internal and Software Interrupt! Exceptions:

" Exceptions do not use the interrupt acknowledge bus cycle but are still handled by a numbered ISR

" Examples: divide by zero, unknown instruction code, access violation, …

! Software Interrupts:" The INT instruction makes interrupt service routines accessible to

programmers" Syntax: “INT imm” with imm

indicating interrupt number" Returning from an ISR is like

RET, except it enables interrupts

! Fault and Traps:" When an instruction causes an exception and is retried after handling it,

the exception is called a fault (e.g. page fault)" When control is passed to the next instruction after handling an exception

or interrupt, such exception is called a trap (e.g. division overflow)

Ordinary subroutine

Interrupt service routine

Invoke CALL INT Terminate RET IRET

Built-in Hardware Exceptions


Allocation Int #Division Overflow 00HSingle Step 01HNMI 02HBreakpoint 03HInterrupt on Overflow 04HBOUND out of range 05HInvalid Machine Code 06H87 not available 07HDouble Fault 08H87 Segment Overrun 09HInvalid Task State Segment 0AHSegment Not Present 0BHStack Overflow 0CHGeneral Protection Error 0DHPage Fault 0EH(reserved) 0FH87 Error 10H

Vol. 3 5-43

INTERRUPT AND EXCEPTION HANDLING

Interrupt 13—General Protection Exception (#GP)

Exception Class Fault.

Description

Indicates that the processor detected one of a class of protection violations called “general-protection violations.” The conditions that cause this exception to be generated comprise all theprotection violations that do not cause other exceptions to be generated (such as, invalid-TSS,segment-not-present, stack-fault, or page-fault exceptions). The following conditions causegeneral-protection exceptions to be generated:

• Exceeding the segment limit when accessing the CS, DS, ES, FS, or GS segments.

• Exceeding the segment limit when referencing a descriptor table (except during a taskswitch or a stack switch).

• Transferring execution to a segment that is not executable.

• Writing to a code segment or a read-only data segment.

• Reading from an execute-only code segment.

• Loading the SS register with a segment selector for a read-only segment (unless theselector comes from a TSS during a task switch, in which case an invalid-TSS exceptionoccurs).

• Loading the SS, DS, ES, FS, or GS register with a segment selector for a system segment.

• Loading the DS, ES, FS, or GS register with a segment selector for an execute-only codesegment.

• Loading the SS register with the segment selector of an executable segment or a nullsegment selector.

• Loading the CS register with a segment selector for a data segment or a null segmentselector.

• Accessing memory using the DS, ES, FS, or GS register when it contains a null segmentselector.

• Switching to a busy task during a call or jump to a TSS.

• Using a segment selector on a non-IRET task switch that points to a TSS descriptor in thecurrent LDT. TSS descriptors can only reside in the GDT. This condition causes a #TSexception during an IRET task switch.

• Violating any of the privilege rules described in Chapter 4, Protection.

• Exceeding the instruction length limit of 15 bytes (this only can occur when redundantprefixes are placed before an instruction).

• Loading the CR0 register with a set PG flag (paging enabled) and a clear PE flag(protection disabled).

5-46 Vol. 3

INTERRUPT AND EXCEPTION HANDLING

Interrupt 14—Page-Fault Exception (#PF)

Exception Class Fault.

Description

Indicates that, with paging enabled (the PG flag in the CR0 register is set), the processor detectedone of the following conditions while using the page-translation mechanism to translate a linearaddress to a physical address:

• The P (present) flag in a page-directory or page-table entry needed for the addresstranslation is clear, indicating that a page table or the page containing the operand is notpresent in physical memory.

• The procedure does not have sufficient privilege to access the indicated page (that is, aprocedure running in user mode attempts to access a supervisor-mode page).

• Code running in user mode attempts to write to a read-only page. In the Intel486 and laterprocessors, if the WP flag is set in CR0, the page fault will also be triggered by coderunning in supervisor mode that tries to write to a read-only user-mode page.

• One or more reserved bits in page directory entry are set to 1. See description below ofRSVD error code flag

The exception handler can recover from page-not-present conditions and restart the program ortask without any loss of program continuity. It can also restart the program or task after a privi-lege violation, but the problem that caused the privilege violation may be uncorrectable.

Exception Error Code

Yes (special format). The processor provides the page-fault handler with two items of informa-tion to aid in diagnosing the exception and recovering from it:

• An error code on the stack. The error code for a page fault has a format different from thatfor other exceptions (see Figure 5-7). The error code tells the exception handler fourthings:

— The P flag indicates whether the exception was due to a not-present page (0) or toeither an access rights violation or the use of a reserved bit (1).

— The W/R flag indicates whether the memory access that caused the exception was aread (0) or write (1).

— The U/S flag indicates whether the processor was executing at user mode (1) orsupervisor mode (0) at the time of the exception.

— The RSVD flag indicates that the processor detected 1s in reserved bits of the pagedirectory, when the PSE or PAE flags in control register CR4 are set to 1. (The PSEflag is only available in the Pentium 4, Intel Xeon, P6 family, and Pentium processors,and the PAE flag is only available on the Pentium 4, Intel Xeon, and P6 familyprocessors. In earlier IA-32 processor, the bit position of the RSVD flag is reserved.)


C LibraryFunctions

SystemCommands

SystemCalls

OperatingSystem

HardwareInterrupts

System Calls

;This program makes a system call;

global mainmain: MOV EAX, 4 ;Write is system call #4

MOV EBX, 1 ;1 is number for standard outputMOV ECX, ABC ;ABC is the string pointerMOV EDX, 13 ;Write 13 bytesINT 80H ;System call interruptRET

ABC: db "Hello world!", 0AH,0

main() {char s[] = "Hello world!\n";write(1,s,13);

}

! Linux conventions: parameters are stored left to right order in registers EBX, ECX, EDX, EDI and ESI respectively


Privileged ModePrivilege Levels! The difference between kernel mode and user mode is in the privilege level

! The 80386 has 4 privilege levels, two of them are used in Linux" Level 0: system level (Linux kernel)" Level 3: user level (user processes)

! The CPL register stores the current privilege level and is reset during the execution of system calls

! Privileged instructions, such as LIDT that set interrupt tables can execute only when CPL = 0

Stack Issues! System calls have to use different stack since the user processes will have

write access to them (imagine a process passing the stack pointer as a parameter forcing the system call to overwrite its own stack

! There is a different stack pointer for every privilege level stored in the task state segment

Summary: Types of Interrupts

• Hardware vs SoftwareHardware: I/O, clock tick, power failure, exceptions

Software: INT instruction

• External vs Internal Hardware InterruptsExternal interrupts are generated by CPU’s interrupt pin

Internal interrupts (exceptions): div by zero, single step, page fault, bad opcode, stack overflow, protection, ...

• Synchronous vs Asynchronous Hardware Int.Synchronous interrupts occur at exactly the same place every time the program is executed. E.g., bad opcode, div by zero, illegal memory address.

Asynchronous interrupts occur at unpredictable times relative to the program. E.g., I/O, clock ticks.


Summary: Interrupt SequenceDevice sends signal to interrupt controller.

Controller uses IRQ# for interrupt # and priority.

Controller sends signal to CPU if the CPU is not already processing an interrupt with higher priority.

CPU finishes executing the current instruction

CPU saves EFLAGS & return address on the stack.

CPU gets interrupt # from controller using I/O ops.

CPU finds “gate” in Interrupt Description Table.

CPU switches to Interrupt Service Routine (ISR). This may include a change in privilege level. IF cleared.


Interrupt Sequence (cont.)ISR saves registers if necessary.

ISR, after initial processing, sets IF to allow interrupts.

ISR processes the interrupt.

ISR restores registers if necessary.

ISR sends End of Interrupt (EOI) to controller.

ISR returns from interrupt using IRET. EFLAGS (inlcuding IF) & return address restored.

CPU executes the next instruction.

Interrupt controller waits for next interrupt and manages pending interrupts.


CACHE MEMORY


Recap Virtual Memory

• Not enough physical memoryUses disk space to simulate extra memory

Pages not being used can be swapped out(how and when you’ll learn in CMSC 421 Operating Systems)

Thrashing: pages constantly written to and retrieved from disk(time to buy more RAM)

• FragmentationContiguous blocks of virtual memory do not have to map to contiguous sections of real memory

• Memory protectionEach process has its own page table

Shared pages are read-only

User processes cannot alter the page table (must be supervisor)


Chapter 7: Memory7-3

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring

The Memory Hierarchy

Registers

Cache

Main memory

Secondary storage (disks)

Off-line storage (tape)

Fast and expensive

Slow and inexpensive

Increasing performance andincreasing cost



Placement of Cache in a ComputerSystem

CPU400 MHz

MainMemory10 MHz

Bus 66 MHz

MainMemory10 MHz

Bus 66 MHz

CPU

Cache

400 MHz

Without cache With cache

• The locality principle : a recently referenced memory location islikely to be referenced again ( temporal locality ); a neighbor of arecently referenced memory location is likely to be referenced(spatial locality ).



An Associative Mapping Scheme for aCache Memory

Slot 0

Slot 1

Slot 2

Slot 214–1

.

.

.

.

.

.

Block 0

Block 1

Block 128

Block 129

Block 227–1

Cache Memory

Main Memory

TagValid Dirty

32 words per block

27

.

.

.



Associative Mapping Example• Consider how an access to memory location (A035F014) 16 is

mapped to the cache for a 2 32 word memory. The memory is di-vided into 2 27 blocks of 2 5 = 32 words per block, and the cacheconsists of 2 14 slots:

27 bits 5 bits

Tag Word

Tag Word

1 0 1 0 0 0 0 0 0 0 1 1 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 1 0 1 0 0

• If the addressed word is in the cache, it will be found in word (14) 16of a slot that has tag (501AF80) 16, which is made up of the 27 mostsignificant bits of the address. If the addressed word is not in thecache, then the block corresponding to tag field (501AF80) 16 isbrought into an available slot in the cache from the main memory,and the memory reference is then satisfied from the cache.



Replacement Policies• When there are no available slots in which to place a block, a re-

placement policy is implemented. The replacement policy gov-erns the choice of which slot is freed up for the new block.

• Replacement policies are used for associative and set-associativemapping schemes, and also for virtual memory.

• Least recently used (LRU)

• First-in/first-out (FIFO)

• Least frequently used (LFU)

• Random

• Optimal (used for analysis only – look backward in time and re-verse-engineer the best possible strategy for a particular se-quence of memory references.)



A Direct Mapping Scheme for CacheMemory

Slot 0

Slot 1

Slot 2

Slot 214–1

.

..

.

.

.

.

.

.

Block 0

Block 1

Block 2

Block 2

Block 227

+1

Cache Memory

Main Memory

TagValid Dirty

32 words per block

13

14

14



Direct Mapping Example• For a direct mapped cache, each main memory block can be

mapped to only one slot, but each slot can receive more than oneblock. Consider how an access to memory location (A035F014) 16is mapped to the cache for a 2 32 word memory. The memory is di-vided into 2 27 blocks of 2 5 = 32 words per block, and the cacheconsists of 2 14 slots:

• If the addressed word is in the cache, it will be found in word (14) 16of slot (2F80) 16, which will have a tag of (1406) 16.

13 bits 5 bits14 bits

Tag WordSlot

Tag Word

1 0 1 0 0 0 0 0 0 0 1 1 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 1 0 1 0 0

Slot



A Set Associative Mapping Schemefor a Cache Memory

Slot 0

Slot 1

Slot 2

Slot 214–1

.

.

.

.

.

.

.

.

.

Block 0

Block 1

Block 213

Block 213+1

Block 227–1

Cache

Main Memory

TagValid Dirty

32 words per block

Set 0

Set 1

Set 213–1

14



Set-Associative Mapping Example• Consider how an access to memory location (A035F014) 16 is

mapped to the cache for a 2 32 word memory. The memory is di-vided into 2 27 blocks of 2 5 = 32 words per block, there are twoblocks per set, and the cache consists of 2 14 slots:

• The leftmost 14 bits form the tag field, followed by 13 bits for theset field, followed by five bits for the word field:

Tag WordSet

14 bits 5 bits13 bits

Tag Word

1 0 1 0 0 0 0 0 0 0 1 1 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 1 0 1 0 0

Set



Cache Read and Write Policies Cache

Read Cache

Write

Data is in the cache

Data is not in the cache

Data is in the cache

Data is not in the cache

Forward to CPU.

Write Through: Write data to both cache and main memory,

Write Back: Write data to cache only. Defer main memory write until block is flushed.

Load Through: Forward the word as cache line is filled, -or- Fill cache line and then forward word.

Write Allocate: Bring line into cache, then update it, -or- Write No-AllocatUpdate main memory only.

-or-



The Memory Hierarchy

Registers

Cache

Main memory

Secondary storage (disks)

Off-line storage (tape)

Fast and expensive

Slow and inexpensive

Increasing performance andincreasing cost

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• Digital Logic


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