Project Datasheet for SiPM -...

PSoC® Creator™Project Datasheet for SiPM

Creation Time: 01/16/2019 12:00:32User: TELECOMITALIA\SO000466

Project: SiPMTool: PSoC Creator 4.1 Update 1

Cypress Semiconductor198 Champion Court

San Jose, CA 95134-1709Phone (USA): 800.858.1810Phone (Intl): 408.943.2600

http://www.cypress.com

Copyright

SiPM Datasheet 01/16/2019 12:00

CopyrightCopyright © 2019 Cypress Semiconductor Corporation. All rights reserved. Any design information orcharacteristics specifically provided by our customer or other third party inputs contained in this document are notintended to be claimed under Cypress's copyright.

TrademarksPSoC and CapSense are registered trademarks of Cypress Semiconductor Corporation. PSoC Creator is atrademark of Cypress Semiconductor Corporation. All other trademarks or registered trademarks referencedherein are the property of their respective owners.

Philips I2C Patent RightsPurchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a licenseunder the Philips I2C Patent Rights to use these components in an I2C system, provided that the systemconforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 PhilipsSemiconductors has a new trade name, NXP Semiconductors.

DisclaimerCYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THISMATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY ANDFITNESS FOR A PARTICULAR PURPOSE. While reasonable precautions have been taken, Cypress assumesno responsibility for any errors that may appear in this document. Cypress reserves the right to make changeswithout further notice to the materials described herein. Cypress does not assume any liability arising out of theapplication or use of any product or circuit described herein. Cypress does not authorize its products for use ascritical components in life support systems where a malfunction or failure may reasonably be expected to result insignificant injury to the user. The inclusion of a Cypress product in a life support systems application implies thatthe manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Flash Code ProtectionCypress products meet the specifications contained in their particular Cypress PSoC Datasheets. Cypressbelieves that its family of PSoC products is one of the most secure families of its kind on the market today,regardless of how they are used. There may be methods, unknown to Cypress, that can breach the codeprotection features. Any of these methods, to our knowledge, would be dishonest and possibly illegal. NeitherCypress nor any other semiconductor manufacturer can guarantee the security of their code. Code protectiondoes not mean that we are guaranteeing the product as 'unbreakable.'

Cypress is willing to work with the customer who is concerned about the integrity of their code. Code protection isconstantly evolving. We at Cypress are committed to continuously improving the code protection features of ourproducts.

Contents


Table of Contents

1 Overview............................................................................................................................................... 12 Pins....................................................................................................................................................... 3

2.1 Hardware Pins........................................................................................................................... 42.2 Hardware Ports.......................................................................................................................... 72.3 Software Pins............................................................................................................................. 9

3 System Settings.................................................................................................................................. 113.1 System Configuration............................................................................................................... 113.2 System Debug Settings........................................................................................................... 113.3 System Operating Conditions.................................................................................................. 11

4 Clocks................................................................................................................................................. 124.1 System Clocks......................................................................................................................... 134.2 Local and Design Wide Clocks................................................................................................ 13

5 Interrupts and DMAs........................................................................................................................... 155.1 Interrupts.................................................................................................................................. 155.2 DMAs....................................................................................................................................... 15

6 Flash Memory..................................................................................................................................... 167 Design Contents................................................................................................................................. 17

7.1 Schematic Sheet: Clock........................................................................................................... 177.2 Schematic Sheet: trimPot - Bias - TimerPulse - LCD.............................................................. 187.3 Schematic Sheet: SiPM Pulse................................................................................................. 197.4 Schematic Sheet: Counters - PWM......................................................................................... 207.5 Schematic Sheet: Temperature Measure................................................................................ 217.6 Schematic Sheet: Commands - UART.................................................................................... 22

8 Components....................................................................................................................................... 238.1 Component type: ADC_SAR [v3.0].......................................................................................... 23

8.1.1 Instance ADC_Pulse..................................................................................................... 238.1.2 Instance ADC_TrimPot..................................................................................................23

8.2 Component type: AMuxHw [v1.50].......................................................................................... 248.2.1 Instance AMuxHw_RS.................................................................................................. 24

8.3 Component type: CharLCD [v2.20].......................................................................................... 248.3.1 Instance LCD................................................................................................................. 24

8.4 Component type: Comp [v2.0]................................................................................................. 258.4.1 Instance Comp.............................................................................................................. 25

8.5 Component type: Counter [v3.0].............................................................................................. 258.5.1 Instance Counter_Pulse................................................................................................ 258.5.2 Instance Counter_Time................................................................................................. 27

8.6 Component type: cy_sync [v1.0].............................................................................................. 288.6.1 Instance Sync_A........................................................................................................... 288.6.2 Instance Sync_B........................................................................................................... 288.6.3 Instance Sync_Clock_1................................................................................................. 298.6.4 Instance Sync_Clock_2................................................................................................. 298.6.5 Instance Sync_Clock_3................................................................................................. 29

8.7 Component type: Debouncer [v1.0]......................................................................................... 298.7.1 Instance Debouncer_Ctrl...............................................................................................298.7.2 Instance Debouncer_Start.............................................................................................30

8.8 Component type: DVDAC [v2.10]............................................................................................ 308.8.1 Instance DVDAC_SiPMBias..........................................................................................30

8.9 Component type: EdgeDetect [v1.0]........................................................................................ 318.9.1 Instance EdgeDetect..................................................................................................... 31

8.10 Component type: PulseConvert [v1.0]................................................................................... 318.10.1 Instance PulseConvert_LED....................................................................................... 31

8.11 Component type: PWM [v3.30].............................................................................................. 318.11.1 Instance PWM_Hold....................................................................................................318.11.2 Instance PWM_Minute................................................................................................ 338.11.3 Instance PWM_Reset..................................................................................................348.11.4 Instance PWM_Timer.................................................................................................. 35

8.12 Component type: Timer [v2.70].............................................................................................. 368.12.1 Instance Timer_Pulse..................................................................................................36

Contents


8.13 Component type: USBFS [v3.10]........................................................................................... 388.13.1 Instance USBUART_MCA...........................................................................................38

8.14 Component type: VDAC8 [v1.90]........................................................................................... 408.14.1 Instance VDAC8_Vref................................................................................................. 40

9 Other Resources.................................................................................................................................42

1 Overview

SiPM Datasheet 01/16/2019 12:00 1

1 Overview

The Cypress PSoC 5 is a family of 32-bit devices with the following characteristics:

• High-performance 32-bit ARM Cortex-M3 core with a nested vectored interrupt controller (NVIC)and a high-performance DMA controller

• Digital system that includes configurable Universal Digital Blocks (UDBs) and specific functionperipherals, such as USB, I2C and SPI

• Analog subsystem that includes 20-bit Delta Sigma converters (ADC), SAR ADCs, 8-bit DACsthat can be configured for 12-bit operation, comparators, op amps and configurable switchedcapacitor (SC) and continuous time (CT) blocks to create PGAs, TIAs, mixers, and more

• Several types of memory elements, including SRAM, flash, and EEPROM• Programming and debug system through JTAG, serial wire debug (SWD), and single wire

viewer (SWV)• Flexible routing to all pins

Figure 1 shows the major components of a typical CY8C58LP series member PSoC 5LP device. Fordetails on all the systems listed above, please refer to the PSoC 5LP Technical Reference Manual .

Figure 1. CY8C58LP Device Series Block Diagram

http://www.cypress.com/go/CY8C58LP

http://www.cypress.com/go/psoc5lp_trm

1 Overview

SiPM Datasheet 01/16/2019 12:00 2

Table 1 lists the key characteristics of this device.

Table 1. Device CharacteristicsName Value

Part Number CY8C5868AXI-LP035Package Name 100-TQFPFamily PSoC 5LPSeries CY8C58LPMax CPU speed (MHz) 67Flash size (kB) 256SRAM size (kB) 64EEPROM size (bytes) 2048Vdd range (V) 1.71 to 5.5Automotive qualified No (Industrial Grade Only)Temp range (Celsius) -40 to 85JTAG ID 0x2E123069

NOTE: The CPU speed noted above is the maximum available speed. The CPU is clocked by BusClock, listed in the System Clocks section below.

Table 2 lists the device resources that this design uses:

Table 2. Device ResourcesResource Type Used Free Max % Used

Digital Clocks 7 1 8 87.50 %Analog Clocks 0 4 4 0.00 %CapSense Buffers 0 2 2 0.00 %Digital Filter Block 0 1 1 0.00 %Interrupts 19 13 32 59.38 %IO 26 46 72 36.11 %Segment LCD 0 1 1 0.00 %CAN 2.0b 0 1 1 0.00 %I2C 0 1 1 0.00 %USB 1 0 1 100.00 %DMA Channels 1 23 24 4.17 %Timer 2 2 4 50.00 %UDBMacrocells 44 148 192 22.92 %Unique P-terms 60 324 384 15.63 %Total P-terms 66Datapath Cells 14 10 24 58.33 %Status Cells 7 17 24 29.17 %StatusI Registers 5Sync Cells (x5) 2

Control Cells 5 19 24 20.83 %Control Registers 5

Opamp 0 4 4 0.00 %Comparator 1 3 4 25.00 %Delta-Sigma ADC 0 1 1 0.00 %LPF 0 2 2 0.00 %SAR ADC 2 0 2 100.00 %Analog (SC/CT) Blocks 0 4 4 0.00 %DACVIDAC 2 2 4 50.00 %

2 Pins

SiPM Datasheet 01/16/2019 12:00 3

2 Pins

Figure 2 shows the pin layout of this device.

Figure 2. Device Pin Layout

2 Pins

SiPM Datasheet 01/16/2019 12:00 4

2.1 Hardware Pins

Table 3 contains information about the pins on this device in device pin order. (No connection ["n/c"]pins have been omitted.)

Table 3. Device Pins

Pin Port Name Type Drive Mode Reset State1 P2[5] \LCD:LCDPort[5]\ Software

In/OutStrong drive HiZ Analog Unb

2 P2[6] \LCD:LCDPort[6]\ SoftwareIn/Out

Strong drive HiZ Analog Unb

3 P2[7] GPIO [unused] HiZ Analog Unb4 P12[4] SIO [unused] HiZ Analog Unb5 P12[5] SIO [unused] HiZ Analog Unb6 P6[4] GPIO [unused] HiZ Analog Unb7 P6[5] VoltInput Analog HiZ analog HiZ Analog Unb8 P6[6] GPIO [unused] HiZ Analog Unb9 P6[7] GPIO [unused] HiZ Analog Unb10 VSSB VSSB Dedicated11 IND IND Dedicated12 VB VB Dedicated13 VBAT VBAT Dedicated14 VSSD VSSD Power15 XRES_N XRES_N Dedicated16 P5[0] GPIO [unused] HiZ Analog Unb17 P5[1] GPIO [unused] HiZ Analog Unb18 P5[2] GPIO [unused] HiZ Analog Unb19 P5[3] GPIO [unused] HiZ Analog Unb20 P1[0] Debug:SWD_IO Reserved21 P1[1] Debug:SWD_CK Reserved22 P1[2] GPIO [unused] HiZ Analog Unb23 P1[3] Debug:SWV Reserved24 P1[4] GPIO [unused] HiZ Analog Unb25 P1[5] GPIO [unused] HiZ Analog Unb26 VDDIO1 VDDIO1 Power27 P1[6] GPIO [unused] HiZ Analog Unb28 P1[7] GPIO [unused] HiZ Analog Unb29 P12[6] SIO [unused] HiZ Analog Unb30 P12[7] SIO [unused] HiZ Analog Unb31 P5[4] GPIO [unused] HiZ Analog Unb32 P5[5] GPIO [unused] HiZ Analog Unb33 P5[6] GPIO [unused] HiZ Analog Unb34 P5[7] GPIO [unused] HiZ Analog Unb35 P15[6] \USBUART_MCA:Dp\ Analog HiZ analog HiZ Analog Unb36 P15[7] \USBUART_MCA:Dm\ Analog HiZ analog HiZ Analog Unb37 VDDD VDDD Power38 VSSD VSSD Power39 VCCD VCCD Power42 P15[0] GPIO [unused] HiZ Analog Unb43 P15[1] GPIO [unused] HiZ Analog Unb44 P3[0] GPIO [unused] HiZ Analog Unb45 P3[1] GPIO [unused] HiZ Analog Unb46 P3[2] GPIO [unused] HiZ Analog Unb

2 Pins

SiPM Datasheet 01/16/2019 12:00 5

Pin Port Name Type Drive Mode Reset State47 P3[3] GPIO [unused] HiZ Analog Unb48 P3[4] GPIO [unused] HiZ Analog Unb49 P3[5] GPIO [unused] HiZ Analog Unb50 VDDIO3 VDDIO3 Power51 P3[6] GPIO [unused] HiZ Analog Unb52 P3[7] GPIO [unused] HiZ Analog Unb53 P12[0] SIO [unused] HiZ Analog Unb54 P12[1] SIO [unused] HiZ Analog Unb55 P15[2] GPIO [unused] HiZ Analog Unb56 P15[3] GPIO [unused] HiZ Analog Unb63 VCCA VCCA Power64 VSSA VSSA Power65 VDDA VDDA Power66 VSSD VSSD Power67 P12[2] SIO [unused] HiZ Analog Unb68 P12[3] SIO [unused] HiZ Analog Unb69 P4[0] SiPMBiasOut Analog HiZ analog HiZ Analog Unb70 P4[1] Comp_OUT Dgtl Out Strong drive HiZ Analog Unb71 P0[0] GPIO [unused] HiZ Analog Unb72 P0[1] GPIO [unused] HiZ Analog Unb73 P0[2] \ADC_Pulse:Bypass\ Analog HiZ analog HiZ Analog Unb74 P0[3] GPIO [unused] HiZ Analog Unb75 VDDIO0 VDDIO0 Power76 P0[4] GPIO [unused] HiZ Analog Unb77 P0[5] GPIO [unused] HiZ Analog Unb78 P0[6] GPIO [unused] HiZ Analog Unb79 P0[7] GPIO [unused] HiZ Analog Unb80 P4[2] Cap A/D Out HiZ analog HiZ Analog Unb81 P4[3] SiPMPulse Analog HiZ analog HiZ Analog Unb82 P4[4] Hold_OUT Dgtl Out Strong drive HiZ Analog Unb83 P4[5] Reset_OUT Dgtl Out Strong drive HiZ Analog Unb84 P4[6] Sampling_OUT Software


85 P4[7] GND Analog HiZ analog HiZ Analog Unb86 VCCD VCCD Power87 VSSD VSSD Power88 VDDD VDDD Power89 P6[0] GPIO [unused] HiZ Analog Unb90 P6[1] Start_Count Dgtl In Res pull up HiZ Analog Unb91 P6[2] Cmd_LED Software


92 P6[3] Pulse_LED Dgtl Out Strong drive HiZ Analog Unb93 P15[4] GPIO [unused] HiZ Analog Unb94 P15[5] Ctrl_Disp Dgtl In Res pull up HiZ Analog Unb95 P2[0] \LCD:LCDPort[0]\ Software










2 Pins

SiPM Datasheet 01/16/2019 12:00 6

Pin Port Name Type Drive Mode Reset State100 VDDIO2 VDDIO2 Power

Abbreviations used in Table 3 have the following meanings:• HiZ Analog Unb = Hi-Z Analog Unbuffered• HiZ analog = High impedance analog• Dgtl Out = Digital Output• A/D Out = Analog / Digital Output• Dgtl In = Digital Input• Res pull up = Resistive pull up

2 Pins

SiPM Datasheet 01/16/2019 12:00 7

2.2 Hardware Ports

Table 4 contains information about the pins on this device in device port order. (No connection ["n/c"],power and dedicated pins have been omitted.)

Table 4. Device Ports

Port Pin Name Type Drive Mode Reset StateP0[0] 71 GPIO [unused] HiZ Analog UnbP0[1] 72 GPIO [unused] HiZ Analog UnbP0[2] 73 \ADC_Pulse:Bypass\ Analog HiZ analog HiZ Analog UnbP0[3] 74 GPIO [unused] HiZ Analog UnbP0[4] 76 GPIO [unused] HiZ Analog UnbP0[5] 77 GPIO [unused] HiZ Analog UnbP0[6] 78 GPIO [unused] HiZ Analog UnbP0[7] 79 GPIO [unused] HiZ Analog UnbP1[0] 20 Debug:SWD_IO ReservedP1[1] 21 Debug:SWD_CK ReservedP1[2] 22 GPIO [unused] HiZ Analog UnbP1[3] 23 Debug:SWV ReservedP1[4] 24 GPIO [unused] HiZ Analog UnbP1[5] 25 GPIO [unused] HiZ Analog UnbP1[6] 27 GPIO [unused] HiZ Analog UnbP1[7] 28 GPIO [unused] HiZ Analog UnbP12[0] 53 SIO [unused] HiZ Analog UnbP12[1] 54 SIO [unused] HiZ Analog UnbP12[2] 67 SIO [unused] HiZ Analog UnbP12[3] 68 SIO [unused] HiZ Analog UnbP12[4] 4 SIO [unused] HiZ Analog UnbP12[5] 5 SIO [unused] HiZ Analog UnbP12[6] 29 SIO [unused] HiZ Analog UnbP12[7] 30 SIO [unused] HiZ Analog UnbP15[0] 42 GPIO [unused] HiZ Analog UnbP15[1] 43 GPIO [unused] HiZ Analog UnbP15[2] 55 GPIO [unused] HiZ Analog UnbP15[3] 56 GPIO [unused] HiZ Analog UnbP15[4] 93 GPIO [unused] HiZ Analog UnbP15[5] 94 Ctrl_Disp Dgtl In Res pull up HiZ Analog UnbP15[6] 35 \USBUART_MCA:Dp\ Analog HiZ analog HiZ Analog UnbP15[7] 36 \USBUART_MCA:Dm\ Analog HiZ analog HiZ Analog UnbP2[0] 95 \LCD:LCDPort[0]\ Software


P2[1] 96 \LCD:LCDPort[1]\ SoftwareIn/Out












2 Pins

SiPM Datasheet 01/16/2019 12:00 8

Port Pin Name Type Drive Mode Reset StateP2[7] 3 GPIO [unused] HiZ Analog UnbP3[0] 44 GPIO [unused] HiZ Analog UnbP3[1] 45 GPIO [unused] HiZ Analog UnbP3[2] 46 GPIO [unused] HiZ Analog UnbP3[3] 47 GPIO [unused] HiZ Analog UnbP3[4] 48 GPIO [unused] HiZ Analog UnbP3[5] 49 GPIO [unused] HiZ Analog UnbP3[6] 51 GPIO [unused] HiZ Analog UnbP3[7] 52 GPIO [unused] HiZ Analog UnbP4[0] 69 SiPMBiasOut Analog HiZ analog HiZ Analog UnbP4[1] 70 Comp_OUT Dgtl Out Strong drive HiZ Analog UnbP4[2] 80 Cap A/D Out HiZ analog HiZ Analog UnbP4[3] 81 SiPMPulse Analog HiZ analog HiZ Analog UnbP4[4] 82 Hold_OUT Dgtl Out Strong drive HiZ Analog UnbP4[5] 83 Reset_OUT Dgtl Out Strong drive HiZ Analog UnbP4[6] 84 Sampling_OUT Software


P4[7] 85 GND Analog HiZ analog HiZ Analog UnbP5[0] 16 GPIO [unused] HiZ Analog UnbP5[1] 17 GPIO [unused] HiZ Analog UnbP5[2] 18 GPIO [unused] HiZ Analog UnbP5[3] 19 GPIO [unused] HiZ Analog UnbP5[4] 31 GPIO [unused] HiZ Analog UnbP5[5] 32 GPIO [unused] HiZ Analog UnbP5[6] 33 GPIO [unused] HiZ Analog UnbP5[7] 34 GPIO [unused] HiZ Analog UnbP6[0] 89 GPIO [unused] HiZ Analog UnbP6[1] 90 Start_Count Dgtl In Res pull up HiZ Analog UnbP6[2] 91 Cmd_LED Software


P6[3] 92 Pulse_LED Dgtl Out Strong drive HiZ Analog UnbP6[4] 6 GPIO [unused] HiZ Analog UnbP6[5] 7 VoltInput Analog HiZ analog HiZ Analog UnbP6[6] 8 GPIO [unused] HiZ Analog UnbP6[7] 9 GPIO [unused] HiZ Analog Unb

Abbreviations used in Table 4 have the following meanings:• HiZ Analog Unb = Hi-Z Analog Unbuffered• HiZ analog = High impedance analog• Dgtl In = Digital Input• Res pull up = Resistive pull up• Dgtl Out = Digital Output• A/D Out = Analog / Digital Output

2 Pins

SiPM Datasheet 01/16/2019 12:00 9

2.3 Software Pins

Table 5 contains information about the software pins on this device in alphabetical order. (Onlysoftware-accessible pins are shown.)

Table 5. Software Pins

Name Port Type Reset State\ADC_Pulse:Bypass\ P0[2] Analog HiZ Analog Unb\LCD:LCDPort[0]\ P2[0] Software

In/OutHiZ Analog Unb

\LCD:LCDPort[1]\ P2[1] SoftwareIn/Out

HiZ Analog Unb


HiZ Analog Unb


HiZ Analog Unb


HiZ Analog Unb


HiZ Analog Unb


HiZ Analog Unb

\USBUART_MCA:Dm\ P15[7] Analog HiZ Analog Unb\USBUART_MCA:Dp\ P15[6] Analog HiZ Analog UnbCap P4[2] A/D Out HiZ Analog UnbCmd_LED P6[2] Software


Comp_OUT P4[1] Dgtl Out HiZ Analog UnbCtrl_Disp P15[5] Dgtl In HiZ Analog UnbDebug:SWD_CK P1[1] ReservedDebug:SWD_IO P1[0] ReservedDebug:SWV P1[3] ReservedGND P4[7] Analog HiZ Analog UnbGPIO [unused] P0[3] HiZ Analog UnbGPIO [unused] P0[1] HiZ Analog UnbGPIO [unused] P3[7] HiZ Analog UnbGPIO [unused] P3[6] HiZ Analog UnbGPIO [unused] P3[3] HiZ Analog UnbGPIO [unused] P3[4] HiZ Analog UnbGPIO [unused] P3[5] HiZ Analog UnbGPIO [unused] P15[3] HiZ Analog UnbGPIO [unused] P0[5] HiZ Analog UnbGPIO [unused] P0[4] HiZ Analog UnbGPIO [unused] P0[6] HiZ Analog UnbGPIO [unused] P0[0] HiZ Analog UnbGPIO [unused] P15[2] HiZ Analog UnbGPIO [unused] P0[7] HiZ Analog UnbGPIO [unused] P3[2] HiZ Analog UnbGPIO [unused] P1[4] HiZ Analog UnbGPIO [unused] P1[2] HiZ Analog UnbGPIO [unused] P5[3] HiZ Analog UnbGPIO [unused] P1[7] HiZ Analog UnbGPIO [unused] P1[6] HiZ Analog Unb

2 Pins

SiPM Datasheet 01/16/2019 12:00 10

Name Port Type Reset StateGPIO [unused] P1[5] HiZ Analog UnbGPIO [unused] P5[2] HiZ Analog UnbGPIO [unused] P6[6] HiZ Analog UnbGPIO [unused] P6[4] HiZ Analog UnbGPIO [unused] P2[7] HiZ Analog UnbGPIO [unused] P5[1] HiZ Analog UnbGPIO [unused] P5[0] HiZ Analog UnbGPIO [unused] P6[7] HiZ Analog UnbGPIO [unused] P6[0] HiZ Analog UnbGPIO [unused] P3[1] HiZ Analog UnbGPIO [unused] P15[0] HiZ Analog UnbGPIO [unused] P3[0] HiZ Analog UnbGPIO [unused] P15[1] HiZ Analog UnbGPIO [unused] P15[4] HiZ Analog UnbGPIO [unused] P5[4] HiZ Analog UnbGPIO [unused] P5[5] HiZ Analog UnbGPIO [unused] P5[7] HiZ Analog UnbGPIO [unused] P5[6] HiZ Analog UnbHold_OUT P4[4] Dgtl Out HiZ Analog UnbPulse_LED P6[3] Dgtl Out HiZ Analog UnbReset_OUT P4[5] Dgtl Out HiZ Analog UnbSampling_OUT P4[6] Software


SIO [unused] P12[6] HiZ Analog UnbSIO [unused] P12[5] HiZ Analog UnbSIO [unused] P12[7] HiZ Analog UnbSIO [unused] P12[1] HiZ Analog UnbSIO [unused] P12[3] HiZ Analog UnbSIO [unused] P12[2] HiZ Analog UnbSIO [unused] P12[0] HiZ Analog UnbSIO [unused] P12[4] HiZ Analog UnbSiPMBiasOut P4[0] Analog HiZ Analog UnbSiPMPulse P4[3] Analog HiZ Analog UnbStart_Count P6[1] Dgtl In HiZ Analog UnbVoltInput P6[5] Analog HiZ Analog Unb

Abbreviations used in Table 5 have the following meanings:• HiZ Analog Unb = Hi-Z Analog Unbuffered• A/D Out = Analog / Digital Output• Dgtl Out = Digital Output• Dgtl In = Digital Input

For more information on reading, writing and configuring pins, please refer to:• Pins chapter in the System Reference Guide

o CyPins API routines• Programming Application Interface section in the cy_pins component datasheet

http://www.cypress.com/go/comp_cy_boot

http://www.cypress.com/go/comp_cy_pins

3 System Settings

SiPM Datasheet 01/16/2019 12:00 11

3 System Settings

3.1 System Configuration

Table 6. System Configuration SettingsName Value

Device Configuration Mode CompressedEnable Error Correcting Code (ECC) FalseStore Configuration Data in ECC Memory TrueInstruction Cache Enabled TrueEnable Fast IMO During Startup TrueUnused Bonded IO Allow but warnHeap Size (bytes) 0x200Stack Size (bytes) 0x0800Include CMSIS Core Peripheral Library Files True

3.2 System Debug Settings

Table 7. System Debug SettingsName Value

Debug Select SWD+SWV (serialwire debug and

viewer)Enable Device Protection FalseEmbedded Trace (ETM) FalseUse Optional XRES False

3.3 System Operating Conditions

Table 8. System Operating ConditionsName Value

VDDA (V) 5VDDD (V) 5VDDIO0 (V) 5VDDIO1 (V) 5VDDIO2 (V) 5VDDIO3 (V) 5Variable VDDA FalseTemperature Range -40C -

85/125C

4 Clocks

SiPM Datasheet 01/16/2019 12:00 12

4 Clocks

The clock system includes these clock resources:• Four internal clock sources increase system integration:

o 3 to 74.7 MHz Internal Main Oscillator (IMO) ±1% at 3 MHzo 1 kHz, 33 kHz, and 100 kHz Internal Low Speed Oscillator (ILO) outputso 12 to 80 MHz clock doubler output, sourced from IMO, MHz External Crystal Oscillator

(MHzECO), and Digital System Interconnect (DSI)o 24 to 80 MHz fractional Phase-Locked Loop (PLL) sourced from IMO, MHzECO, and DSI

• Clock generated using a DSI signal from an external I/O pin or other logic• Two external clock sources provide high precision clocks:

o 4 to 25 MHz External Crystal Oscillator (MHzECO)o 32.768 kHz External Crystal Oscillator (kHzECO) for Real Time Clock (RTC)

• Dedicated 16-bit divider for bus clock• Eight individually sourced 16-bit clock dividers for the digital system peripherals• Four individually sourced 16-bit clock dividers with skew for the analog system peripherals• IMO has a USB mode that synchronizes to USB host traffic, requiring no external crystal for

USB. (USB equipped parts only)

Figure 3. System Clock Configuration

4 Clocks

SiPM Datasheet 01/16/2019 12:00 13

4.1 System Clocks

Table 9 lists the system clocks used in this design.

Table 9. System ClocksName Domain Source Desired

FreqNominalFreq

Accuracy(%)

Startat

Reset

Enabled

MASTER_CLK DIGITAL PLL_OUT ? MHz 48 MHz ±0.25 True TruePLL_OUT DIGITAL IMO 48 MHz 48 MHz ±0.25 True TrueUSB_CLK DIGITAL IMO 48 MHz 48 MHz ±0.25 False TrueBUS_CLK DIGITAL MASTER_CLK ? MHz 24 MHz ±0.25 True TrueIMO DIGITAL 24 MHz 24 MHz ±0.25 True TrueILO DIGITAL ? MHz 100 kHz -55,+100 True TrueXTAL 32kHz DIGITAL 32.768

kHz? MHz ±0 False False

Digital Signal DIGITAL ? MHz ? MHz ±0 False FalseXTAL DIGITAL 24 MHz ? MHz ±0 False False

4.2 Local and Design Wide Clocks

Local clocks drive individual analog and digital blocks. Design wide clocks are a user-definedoptimization, where two or more analog or digital blocks that share a common clock profile (frequency,etc) can be driven from the same clock divider output source.

Figure 4. Local and Design Wide Clock Configuration

Table 10 lists the local clocks used in this design.

Table 10. Local ClocksName Domain Source Desired

FreqNominalFreq

Accuracy(%)

Startat

Reset

Enabled

BUS_CLK DIGITAL BUS_CLK ? MHz 24 MHz ±0.25 True TrueDVDAC_-SiPMBias_-BUS_CLK

DIGITAL BUS_CLK ? MHz 24 MHz ±0.25 True True

ADC_Pulse_-theACLK

DIGITAL MASTER_CLK 12.6MHz

12 MHz ±0.25 True True

Clock_Sample DIGITAL MASTER_CLK 10 MHz 9.6 MHz ±0.25 True TrueADC_TrimPot_-theACLK

DIGITAL MASTER_CLK 1.6 MHz 1.6 MHz ±0.25 True True

DVDAC_-SiPMBias_-IntClock

DIGITAL MASTER_CLK 250 kHz 250 kHz ±0.25 True True

Clock_Timer DIGITAL ILO 1 kHz 1 kHz -55,+100 True TrueClock_Button DIGITAL ILO 200 Hz 200 Hz -55,+100 True True

4 Clocks

SiPM Datasheet 01/16/2019 12:00 14

Name Domain Source DesiredFreq

NominalFreq

Accuracy(%)

Startat

Reset

Enabled

Clock_LED DIGITAL ILO 100 Hz 100 Hz -55,+100 True True

For more information on clocking resources, please refer to:• Clocking System chapter in the PSoC 5LP Technical Reference Manual• Clocking chapter in the System Reference Guide

o CyPLL API routineso CyIMO API routineso CyILO API routineso CyMaster API routineso CyXTAL API routines



5 Interrupts and DMAs

SiPM Datasheet 01/16/2019 12:00 15

5 Interrupts and DMAs

5.1 Interrupts

This design contains the following interrupt components: (0 is the highest priority)

Table 11. InterruptsName Intr

NumVector Priority

CtrlInt 0 0 7CtrlLedInt 1 1 7PWMInt_Hold 2 2 7PWMInt_Reset 3 3 7StartInt 4 4 7StartLedInt 5 5 7TimerInt 6 6 7ADC_Pulse_IRQ 7 7 7ADC_TrimPot_IRQ 8 8 7USBUART_MCA_ep_1 9 9 7USBUART_MCA_ep_2 10 10 7USBUART_MCA_ep_3 11 11 7USBUART_MCA_dp_int 12 12 7PWMInt_Minute 17 17 7PWMInt 18 18 7USBUART_MCA_sof_int 21 21 7USBUART_MCA_arb_int 22 22 7USBUART_MCA_bus_reset 23 23 7USBUART_MCA_ep_0 24 24 7

For more information on interrupts, please refer to:• Interrupt Controller chapter in the PSoC 5LP Technical Reference Manual• Interrupts chapter in the System Reference Guide

o CyInt API routines and related registers• Datasheet for cy_isr component

5.2 DMAs

This design contains the following DMA components: (0 is the highest priority)

Table 12. DMAsName Priority Channel

NumberDVDAC_SiPMBias_DMA 2 0

For more information on DMAs, please refer to:• PHUB and DMAC chapter in the PSoC 5LP Technical Reference Manual• DMA chapter in the System Reference Guide

o DMA API routines and related registers• Datasheet for cy_dma component



http://www.cypress.com/go/comp_cy_isr



http://www.cypress.com/go/comp_cy_dma

6 Flash Memory

SiPM Datasheet 01/16/2019 12:00 16

6 Flash Memory

PSoC 5LP devices offer a host of Flash protection options and device security features that you canleverage to meet the security and protection requirements of an application. These requirementsrange from protecting configuration settings or Flash data to locking the entire device from externalaccess.

Table 13 lists the Flash protection settings for your design.

Table 13. Flash Protection SettingsStart

AddressEnd

AddressProtection Level

0x0 0x3FFFF U - Unprotected

Flash memory is organized as rows with each row of flash having 256 bytes. Each flash row can beassigned one of four protection levels:

• U - Unprotected• F - Factory Upgrade• R - Field Upgrade• W - Full Protection

For more information on Flash memory and protection, please refer to:• Flash Protection chapter in the PSoC 5LP Technical Reference Manual• Flash and EEPROM chapter in the System Reference Guide

o CyWrite API routineso CyFlash API routines



7 Design Contents

SiPM Datasheet 01/16/2019 12:00 17

7 Design Contents

This design's schematic content consists of the following 6 schematic sheets:

7.1 Schematic Sheet: Clock

Figure 5. Schematic Sheet: Clock

This schematic sheet contains the following component instances:• Instance PWM_Minute (type: PWM_v3_30)• Instance PWM_Timer (type: PWM_v3_30)• Instance Sync_Clock_1 (type: cy_sync_v1_0)• Instance Sync_Clock_2 (type: cy_sync_v1_0)• Instance Sync_Clock_3 (type: cy_sync_v1_0)

7 Design Contents

SiPM Datasheet 01/16/2019 12:00 18

7.2 Schematic Sheet: trimPot - Bias - TimerPulse - LCD

Figure 6. Schematic Sheet: trimPot - Bias - TimerPulse - LCD

This schematic sheet contains the following component instances:• Instance ADC_TrimPot (type: ADC_SAR_v3_0)• Instance DVDAC_SiPMBias (type: DVDAC_v2_10)• Instance LCD (type: CharLCD_v2_20)• Instance Sync_B (type: cy_sync_v1_0)• Instance Timer_Pulse (type: Timer_v2_70)

7 Design Contents

SiPM Datasheet 01/16/2019 12:00 19

7.3 Schematic Sheet: SiPM Pulse

Figure 7. Schematic Sheet: SiPM Pulse

This schematic sheet contains the following component instances:• Instance ADC_Pulse (type: ADC_SAR_v3_0)• Instance Comp (type: Comp_v2_0)• Instance EdgeDetect (type: EdgeDetect_v1_0)• Instance PulseConvert_LED (type: PulseConvert_v1_0)• Instance VDAC8_Vref (type: VDAC8_v1_90)

7 Design Contents

SiPM Datasheet 01/16/2019 12:00 20

7.4 Schematic Sheet: Counters - PWM

Figure 8. Schematic Sheet: Counters - PWM

This schematic sheet contains the following component instances:• Instance AMuxHw_RS (type: AMuxHw_v1_50)• Instance Counter_Pulse (type: Counter_v3_0)• Instance Counter_Time (type: Counter_v3_0)• Instance PWM_Hold (type: PWM_v3_30)• Instance PWM_Reset (type: PWM_v3_30)• Instance Sync_A (type: cy_sync_v1_0)

7 Design Contents

SiPM Datasheet 01/16/2019 12:00 21

7.5 Schematic Sheet: Temperature Measure

Figure 9. Schematic Sheet: Temperature Measure

7 Design Contents

SiPM Datasheet 01/16/2019 12:00 22

7.6 Schematic Sheet: Commands - UART

Figure 10. Schematic Sheet: Commands - UART

This schematic sheet contains the following component instances:• Instance Debouncer_Ctrl (type: Debouncer_v1_0)• Instance Debouncer_Start (type: Debouncer_v1_0)• Instance USBUART_MCA (type: USBFS_v3_10)

8 Components

SiPM Datasheet 01/16/2019 12:00 23

8 Components

8.1 Component type: ADC_SAR [v3.0]

8.1.1 Instance ADC_Pulse

Description: Successive approximation ADCInstance type: ADC_SAR [v3.0]Datasheet: online component datasheet for ADC_SAR

Table 14. Component Parameters for ADC_PulseParameter Name Value Description

ADC_Clock Internal Selects either the internal orexternal clock source.

ADC_Input_Range Vssa toVdda(SingleEnded)

Parameter used to choose theinput operating mode that best

supports the range of thesignals being measured.

ADC_Power High Power This parameter sets the powerlevel of the ADC.

ADC_Reference InternalVref,

bypassed

Selects the voltage referencesource and configuration.

ADC_Resolution 12 Sets the resolution of the ADCin bits.

ADC_SampleMode FreeRunning

Selects the mode that the ADCoperates in. This can be eitherfree-running or triggered mode.

Enable_next_out false This parameter enables the EndOf Sampling (eos) output

terminal.Ref_Voltage 2.5 Sets the reference voltage in

volts.rm_int false Removes internal interrupt

(IRQ)Sample_Rate 700000 Specifies the sample rate in Hz.User Comments Instance-specific comments.

8.1.2 Instance ADC_TrimPot

Description: Successive approximation ADCInstance type: ADC_SAR [v3.0]Datasheet: online component datasheet for ADC_SAR

Table 15. Component Parameters for ADC_TrimPotParameter Name Value Description

ADC_Clock Internal Selects either the internal orexternal clock source.

ADC_Input_Range Vssa toVdda(SingleEnded)

Parameter used to choose theinput operating mode that best

supports the range of thesignals being measured.

ADC_Power HighPower

This parameter sets the powerlevel of the ADC.

http://www.cypress.com/go/comp_ADC_SAR

http://www.cypress.com/go/comp_ADC_SAR

8 Components

SiPM Datasheet 01/16/2019 12:00 24

Parameter Name Value DescriptionADC_Reference Internal

VrefSelects the voltage referencesource and configuration.

ADC_Resolution 12 Sets the resolution of the ADCin bits.

ADC_SampleMode FreeRunning

Selects the mode that the ADCoperates in. This can be eitherfree-running or triggered mode.

Enable_next_out false This parameter enables the EndOf Sampling (eos) output

terminal.Ref_Voltage 1.65 Sets the reference voltage in

volts.rm_int false Removes internal interrupt

(IRQ)Sample_Rate 100000 Specifies the sample rate in Hz.User Comments Instance-specific comments.

8.2 Component type: AMuxHw [v1.50]

8.2.1 Instance AMuxHw_RS

Description: Multiplexer used to route analog signals.Instance type: AMuxHw [v1.50]Datasheet: online component datasheet for AMuxHw

Table 16. Component Parameters for AMuxHw_RSParameter Name Value DescriptionChannels 1 Channel count.Mode Switch Select between Mux or Switch

Mode.MuxType Single Select between single or

differential inputs.ShowEnable false Shows/Hides the enable

terminal.User Comments Instance-specific comments.

8.3 Component type: CharLCD [v2.20]

8.3.1 Instance LCD

Description: Character LCD ComponentInstance type: CharLCD [v2.20]Datasheet: online component datasheet for CharLCD

Table 17. Component Parameters for LCDParameter Name Value Description

ConversionRoutines true Defines if the conversionroutines will be included in the

project.CustomCharacterSet None Defines the type of custom

character set (User defined,Vertical or Horizontal bargraph).Based on the selection a look-up table with proper charactersrepresentation will be generated

in the source code.

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http://www.cypress.com/go/comp_CharLCD

8 Components

SiPM Datasheet 01/16/2019 12:00 25

Parameter Name Value DescriptionUser Comments Instance-specific comments.

8.4 Component type: Comp [v2.0]

8.4.1 Instance Comp

Description: Analog voltage comparator.Instance type: Comp [v2.0]Datasheet: online component datasheet for Comp

Table 18. Component Parameters for CompParameter Name Value DescriptionHysteresis Enable Enable to add output hysteresis.Pd_Override Disable Power down override to allow

comparator to continueoperating during sleep.

Polarity Non Inverting Allows output to be inverted.Speed Fast Set comparator response

speed.Sync Bypass Allows synchronization with

clock.User Comments Instance-specific comments.

8.5 Component type: Counter [v3.0]

8.5.1 Instance Counter_Pulse

Description: 8, 16, 24 or 32-bit CounterInstance type: Counter [v3.0]Datasheet: online component datasheet for Counter

Table 19. Component Parameters for Counter_PulseParameter Name Value Description

CaptureMode None Defines the functionality of thecapture input. Default is Nonewhich does not have a capture

input pinClockMode Up Counter Defines the operation of the

counter. \nBasic: Count isincremented on the rising edgeof the clock input. \n Clock_-And_Direction: Clock is

incremented or decremented onthe rising edge of the clock inputbased on the direction of theinput. \nClock_And_UpCnt_-

DwnCnt: Clock is anoversampling clock. On therising edge of UpCnt, the

counter is incremented and onthe rising edge of DwnCnt, the

counter is decremented.CompareMode Software

ControlledSpecifies the compare output

mode.

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http://www.cypress.com/go/comp_Counter

8 Components

SiPM Datasheet 01/16/2019 12:00 26

Parameter Name Value DescriptionCompareStatusEdgeSense true Specifies whether rising edge

sense for interrupt generationwith the Compare output will be

used. May be disabled toreduce resource usage.

CompareValue 16777215 Defines the compare value.Valid vales are from 0 to the

period value.EnableMode Software Only Choose which enable controls

the enable of the counter. Thiscan be either through softwarewith the control register, throughhardware with the input pin or acombination of both where bothmust be active for the counter to

be enabled.FixedFunction false Defines whether Fixed Function

Block usage is required.InterruptOnCapture false Enables the counter status

register to produce an interruptoutput signal on a capture

event.InterruptOnCompare false Enables the counter status

register to produce an interruptoutput signal on compare true.

InterruptOnOverUnderFlow false Enables the counter statusregister to produce an interruptoutput signal on over flow or

under flow.InterruptOnTC false Enables the counter status

register to produce an interruptoutput signal on terminal count.

Period 16777215 Defines the counter periodvalue in clock counts from 1 to

2^Width-1.ReloadOnCapture false Reloads the counter value to a

set value on a capture inputevent.

ReloadOnCompare false Reloads the counter value to aset value on a compare equal

event.ReloadOnOverUnder true Reloads the counter value to a

set value when overflow orunderflow is detected.

ReloadOnReset true Reloads the counter value to aset value when reset input is

high.Resolution 24 Defines the width of the counter.

It can be 8, 16, 24 or 32 (24 or32 cannot use Fixed Function

block).RunMode Continuous Define the hardware operation

to run continuously or run till aterminal count.

UseInterrupt true Allows for complete optimizationof resource usage down to

removing the status register ifnot required by the user.

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SiPM Datasheet 01/16/2019 12:00 27

Parameter Name Value DescriptionUser Comments Instance-specific comments.

8.5.2 Instance Counter_Time

Description: 8, 16, 24 or 32-bit CounterInstance type: Counter [v3.0]Datasheet: online component datasheet for Counter

Table 20. Component Parameters for Counter_TimeParameter Name Value Description

CaptureMode None Defines the functionality of thecapture input. Default is Nonewhich does not have a capture

input pinClockMode Up Counter Defines the operation of the

counter. \nBasic: Count isincremented on the rising edgeof the clock input. \n Clock_-And_Direction: Clock is

incremented or decremented onthe rising edge of the clock inputbased on the direction of theinput. \nClock_And_UpCnt_-

DwnCnt: Clock is anoversampling clock. On therising edge of UpCnt, the

counter is incremented and onthe rising edge of DwnCnt, the

counter is decremented.CompareMode Less Than Specifies the compare output

mode.CompareStatusEdgeSense true Specifies whether rising edge

sense for interrupt generationwith the Compare output will be

used. May be disabled toreduce resource usage.

CompareValue 16777215 Defines the compare value.Valid vales are from 0 to the

period value.EnableMode Software Only Choose which enable controls

the enable of the counter. Thiscan be either through softwarewith the control register, throughhardware with the input pin or acombination of both where bothmust be active for the counter to

be enabled.FixedFunction false Defines whether Fixed Function

Block usage is required.InterruptOnCapture false Enables the counter status

register to produce an interruptoutput signal on a capture

event.InterruptOnCompare false Enables the counter status

register to produce an interruptoutput signal on compare true.

http://www.cypress.com/go/comp_Counter

8 Components

SiPM Datasheet 01/16/2019 12:00 28

Parameter Name Value DescriptionInterruptOnOverUnderFlow false Enables the counter status

register to produce an interruptoutput signal on over flow or

under flow.InterruptOnTC false Enables the counter status

register to produce an interruptoutput signal on terminal count.

Period 16777215 Defines the counter periodvalue in clock counts from 1 to

2^Width-1.ReloadOnCapture false Reloads the counter value to a

set value on a capture inputevent.

ReloadOnCompare false Reloads the counter value to aset value on a compare equal

event.ReloadOnOverUnder true Reloads the counter value to a

set value when overflow orunderflow is detected.

ReloadOnReset true Reloads the counter value to aset value when reset input is

high.Resolution 24 Defines the width of the counter.

It can be 8, 16, 24 or 32 (24 or32 cannot use Fixed Function

block).RunMode Continuous Define the hardware operation

to run continuously or run till aterminal count.

UseInterrupt true Allows for complete optimizationof resource usage down to

removing the status register ifnot required by the user.

User Comments Instance-specific comments.

8.6 Component type: cy_sync [v1.0]

8.6.1 Instance Sync_A

Description: Synchronizes the input signal(s) to its input clockInstance type: cy_sync [v1.0]Datasheet: online component datasheet for cy_sync

Table 21. Component Parameters for Sync_AParameter Name Value DescriptionSignalWidth 1 This parameter configures the

number of signals that will besynchronized to the associated


8.6.2 Instance Sync_B


http://www.cypress.com/go/comp_cy_sync


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SiPM Datasheet 01/16/2019 12:00 29

Table 22. Component Parameters for Sync_BParameter Name Value DescriptionSignalWidth 1 This parameter configures the



8.6.3 Instance Sync_Clock_1


Table 23. Component Parameters for Sync_Clock_1Parameter Name Value DescriptionSignalWidth 1 This parameter configures the













8.7 Component type: Debouncer [v1.0]

8.7.1 Instance Debouncer_Ctrl




8 Components

SiPM Datasheet 01/16/2019 12:00 30

Description: Debounces the input digital signal from most types of switchesInstance type: Debouncer [v1.0]Datasheet: online component datasheet for Debouncer

Table 26. Component Parameters for Debouncer_CtrlParameter Name Value Description

EitherEdgeDetect true Specifies whether the positiveor negative edge detection isenabled for the component.

NegEdgeDetect true Specifies whether the negativeedge detection is enabled for

the component.PosEdgeDetect true Specifies whether the positive

edge detection is enabled forthe component.

SignalWidth 1 Determines the bus width ofinput and output terminals.


8.7.2 Instance Debouncer_Start

Description: Debounces the input digital signal from most types of switchesInstance type: Debouncer [v1.0]Datasheet: online component datasheet for Debouncer

Table 27. Component Parameters for Debouncer_StartParameter Name Value Description

EitherEdgeDetect true Specifies whether the positiveor negative edge detection isenabled for the component.

NegEdgeDetect true Specifies whether the negativeedge detection is enabled for

the component.PosEdgeDetect true Specifies whether the positive

edge detection is enabled forthe component.

SignalWidth 1 Determines the bus width ofinput and output terminals.


8.8 Component type: DVDAC [v2.10]

8.8.1 Instance DVDAC_SiPMBias

Description: 9 to 12 bit Dithered Voltage DACInstance type: DVDAC [v2.10]Datasheet: online component datasheet for DVDAC

Table 28. Component Parameters for DVDAC_SiPMBiasParameter Name Value Description

DAC_Range 4 Volt This parameter allows you toset one of the two voltage

ranges. This option cannot bechanged during runtime.

http://www.cypress.com/go/comp_debouncer

http://www.cypress.com/go/comp_debouncer

http://www.cypress.com/go/comp_DVDAC

8 Components

SiPM Datasheet 01/16/2019 12:00 31

Parameter Name Value DescriptionInitial_Value 2048 This parameter allows you to

set the DVDAC voltage value.The maximum value will depend

on the resolution selected.Refer to the DVDAC_SetValue()

function description in thiscomponent datasheet.

InternalClock true This parameter allows you toconfigure the component's clocksource: internal or external. This

option cannot be changedduring runtime.

InternalClockFreqHz 250000 When the clock source isconfigured to be internal, this

parameter defines thefrequency in Hz at which DMAis triggered. The parameteralsowrites the next value fromthe dithered array into theVDAC8 data register.

Resolution 12 Bits This parameter allows you toset the DVDAC resolution. Theresolution cannot be changed

during runtime.User Comments Instance-specific comments.

8.9 Component type: EdgeDetect [v1.0]

8.9.1 Instance EdgeDetect

Description: Edge DetectorInstance type: EdgeDetect [v1.0]Datasheet: online component datasheet for EdgeDetect

Table 29. Component Parameters for EdgeDetectParameter Name Value DescriptionEdgeType Rising Edge The edge type that this

component will detect.User Comments Instance-specific comments.

8.10 Component type: PulseConvert [v1.0]

8.10.1 Instance PulseConvert_LED

Description: Pulse ConverterInstance type: PulseConvert [v1.0]Datasheet: online component datasheet for PulseConvert

Table 30. Component Parameters for PulseConvert_LEDParameter Name Value DescriptionUser Comments Instance-specific comments.

8.11 Component type: PWM [v3.30]

8.11.1 Instance PWM_Hold

http://www.cypress.com/go/comp_edgedetect

http://www.cypress.com/go/comp_pulseconvert

8 Components

SiPM Datasheet 01/16/2019 12:00 32

Description: 8 or 16-bit Pulse Width ModulatorInstance type: PWM [v3.30]Datasheet: online component datasheet for PWM

Table 31. Component Parameters for PWM_HoldParameter Name Value Description

CaptureMode None Defines the functionality of thecapture Input. The parameterdetermines which signal on thecapture input is required to

capture the current count valueto the FIFO.

CompareStatusEdgeSense true Enables edge sense detectionon compare outputs for use in

edge sensitive interruptsCompareType1 Less Sets the compare value

comparison type setting for thecompare 1 output

CompareType2 Less Sets the compare valuecomparison type setting for the

compare 2 outputCompareValue1 1400 Compares Output 1 to valueCompareValue2 63 Compares Output 2 to valueDeadBand Disabled Defines whether dead band

outputs are desired or not.DeadTime 1 Defines the number of required

dead band clock cyclesDitherOffset 0.00 Allows the user to implement

dither to get more bits out of a 8or 16 bit PWM.

EnableMode SoftwareOnly

Specifies the method ofenabling the PWM. This can beeither hardware or software.

FixedFunction false Determines whether the fixedfunction counter timer is used or

the UDB implementation isused.

InterruptOnCMP1 true Enables the interrupt oncompare1 true event

InterruptOnCMP2 false Enables the interrupt oncompare2 true event

InterruptOnKill false Enables the interrupt on a killevent

InterruptOnTC false Enables the interrupt onterminal count event

KillMode Disabled Parameter to select the killmode for build time.

MinimumKillTime 1 Sets the minimum number ofclock cycles that a kill must beactive on the outputs when

KillMode is set to Minimum KillTime mode

Period 1439 Defines the PWM period valuePWMMode One

OutputDefines the overall mode of the

PWMResolution 16 Defines the bit width of the

PWM (8 or 16 bits)

http://www.cypress.com/go/comp_PWM

8 Components

SiPM Datasheet 01/16/2019 12:00 33

Parameter Name Value DescriptionRunMode One Shot

with MultiTrigger

Defines the run mode options tobe either continuous or one shot

TriggerMode RisingEdge

Determines the mode of startingthe PWM, i.e. triggering the

PWM counter to startUseInterrupt true Enables the placement and

usage of the status registerUser Comments Instance-specific comments.

8.11.2 Instance PWM_Minute


Table 32. Component Parameters for PWM_MinuteParameter Name Value Description




edge sensitive interruptsCompareType1 Less Sets the compare value







EnableMode Software Only Specifies the method ofenabling the PWM. This can beeither hardware or software.

FixedFunction true Determines whether the fixedfunction counter timer is used or






8 Components

SiPM Datasheet 01/16/2019 12:00 34

Parameter Name Value DescriptionInterruptOnTC true Enables the interrupt on

terminal count eventKillMode Asynchronous Parameter to select the kill

mode for build time.MinimumKillTime 1 Sets the minimum number of

clock cycles that a kill must beactive on the outputs when


Period 59999 Defines the PWM period valuePWMMode One Output Defines the overall mode of the


PWM (8 or 16 bits)RunMode Continuous Defines the run mode options to

be either continuous or one shotTriggerMode None Determines the mode of starting

the PWM, i.e. triggering thePWM counter to start

UseInterrupt true Enables the placement andusage of the status register


8.11.3 Instance PWM_Reset


Table 33. Component Parameters for PWM_ResetParameter Name Value Description




edge sensitive interruptsCompareType1 Greater or

EqualSets the compare value








8 Components

SiPM Datasheet 01/16/2019 12:00 35

Parameter Name Value DescriptionEnableMode Software

OnlySpecifies the method of

enabling the PWM. This can beeither hardware or software.

FixedFunction false Determines whether the fixedfunction counter timer is used or


InterruptOnCMP1 true Enables the interrupt oncompare1 true event




KillMode Disabled Parameter to select the killmode for build time.



Period 479 Defines the PWM period valuePWMMode One

OutputDefines the overall mode of the


PWM (8 or 16 bits)RunMode One Shot

with MultiTrigger

Defines the run mode options tobe either continuous or one shot

TriggerMode FallingEdge

Determines the mode of startingthe PWM, i.e. triggering the

PWM counter to startUseInterrupt true Enables the placement and

usage of the status registerUser Comments Instance-specific comments.

8.11.4 Instance PWM_Timer


Table 34. Component Parameters for PWM_TimerParameter Name Value Description




edge sensitive interrupts


8 Components

SiPM Datasheet 01/16/2019 12:00 36

Parameter Name Value DescriptionCompareType1 Less Sets the compare value







EnableMode Software Only Specifies the method ofenabling the PWM. This can beeither hardware or software.

FixedFunction true Determines whether the fixedfunction counter timer is used or






KillMode Asynchronous Parameter to select the killmode for build time.



Period 999 Defines the PWM period valuePWMMode One Output Defines the overall mode of the


PWM (8 or 16 bits)RunMode Continuous Defines the run mode options to

be either continuous or one shotTriggerMode None Determines the mode of starting

the PWM, i.e. triggering thePWM counter to start

UseInterrupt true Enables the placement andusage of the status register


8.12 Component type: Timer [v2.70]

8.12.1 Instance Timer_Pulse

Description: 8, 16, 24 or 32-bit TimerInstance type: Timer [v2.70]

8 Components

SiPM Datasheet 01/16/2019 12:00 37

Datasheet: online component datasheet for Timer

Table 35. Component Parameters for Timer_PulseParameter Name Value Description

CaptureAlternatingFall false Enables data capture on eitheredge but not until a valid falling

edge is detected first.CaptureAlternatingRise false Enables data capture on either

edge but not until a valid risingedge is detected first.

CaptureCount 2 The CaptureCount parameterworks as a divider on thehardware input "capture". A

CaptureCount value of 2 wouldresult in an actual capture

taking place every other timethe input "capture" is changed.

CaptureCounterEnabled false Enables the capture counter tocount capture events (up to127) before a capture is

triggered.CaptureMode Rising Edge This parameter defines the

capture input signalrequirements to trigger a valid

capture eventEnableMode Software Only This parameter specifies the

methods in enabling thecomponent. Hardware modemakes the enable input pinvisible. Software mode may

reduce the resource usage if notenabled.

FixedFunction false Configures the component touse fixed function HW block

instead of the UDBimplementation.

InterruptOnCapture true Parameter to check whetherinterrupt on a capture event is

enabled or disabled.InterruptOnFIFOFull false Parameter to check whether

interrupt on a FIFO Full event isenabled disabled.

InterruptOnTC false Parameter to check whetherinterrupt on a TC is enabled or

disabled.NumberOfCaptures 1 Number of captures allowed

until the counter is cleared ordisabled.

Period 499999999 Defines the timer period (This isalso the reload value whenterminal count is reached)

Resolution 32 Defines the resolution of thehardware. This parameter

affects how many bits are usedin the Period counter and

defines the maximum resolutionof the internal component

signals.

http://www.cypress.com/go/comp_Timer

8 Components

SiPM Datasheet 01/16/2019 12:00 38

Parameter Name Value DescriptionRunMode Continuous Defines the hardware to run

continuously, run until a terminalcount is reached or run until aninterrupt event is triggered.

TriggerMode None Defines the required triggerinput signal to cause a validtrigger enable of the timer


8.13 Component type: USBFS [v3.10]

8.13.1 Instance USBUART_MCA

Description: USB 2.0 Full Speed Device FrameworkInstance type: USBFS [v3.10]Datasheet: online component datasheet for USBFS

Table 36. Component Parameters for USBUART_MCAParameter Name Value Description

EnableBatteryChargDetect false This parameter allows to detecta charging supported USB hostport using the API functionUSBFS_DetectPortType().

EnableCDCApi true Enables additional high levelAPI's that allow the CDC deviceto be used similar to a UART

device.EnableMidiApi true Enables additional high level

MIDI API's.endpointMA MA_Static Endpoint memory allocationendpointMM EP_Manual Endpoint memory managementepDMAautoOptimization false This parameter enables

resource optimization for DMAwith Automatic Memory

Management mode. Set thisparameter value to true onlywhen a single IN endpoint ispresent in the device. Enablingthis parameter in a multi INendpoint device configurationcauses undesired effects.

extern_cls false This parameter allows for useror other component to

implement his own handler forClass requests. USBFS_-

DispatchClassRqst() functionshould be implemented if this

parameter enabled.extern_vbus false This parameter enables external

VBUSDET input.extern_vnd false This parameter allows for user

or other component toimplement his own handler forVendor specific requests.

USBFS_HandleVendorRqst()function should be implemented

if this parameter enabled.

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8 Components

SiPM Datasheet 01/16/2019 12:00 39

Parameter Name Value DescriptionextJackCount 0 Max number of External MIDI IN

Jack or OUT Jack descriptorsGen16bitEpAccessApi true This parameter defines whether

to generate APIs for the 16-bitsendpoint access.

HandleMscRequests true This parameter is used toenable handling MSC requests

and generate MSC APIs.isrGroupArbiter High This parameter defines the

interrupt group of the ArbiterInterrupt.

isrGroupBusReset Low This parameter defines theinterrupt group of the Bus Reset

Interrupt.isrGroupEp0 Medium This parameter defines the

interrupt group of the ControlEndpoint Interrupt (EP0).

isrGroupEp1 Medium This parameter defines theinterrupt group of the Data

Endpoint 1 Interrupt.isrGroupEp2 Medium This parameter defines the

interrupt group of the DataEndpoint 2 Interrupt.










isrGroupLpm High This parameter defines theinterrupt group of the LPM

Interrupt.isrGroupSof Low This parameter defines the

interrupt group of the Start ofFrame Interrupt.

max_interfaces_num 2 Defines maximum interfacesnumber

Mode false Specifies whether theimplementation will create API

for interfacing to UARTcomponent(s) for a

corresponding set of externalMIDI connections.

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SiPM Datasheet 01/16/2019 12:00 40

Parameter Name Value Descriptionmon_vbus false The mon_vbus parameter adds

a single VBUS monitor pin tothe design. This pin must beconnected to VBUS and mustbe assigned in the pin editor.

MscDescriptors Mass Storage Class DescriptorsMscLogicalUnitsNum 1 This parameter allows to specify

the number of logical units thatshould be supported by the

Mass Storage device.out_sof false The out_sof parameter enables

Start-of-Frame output.Pid F232 Product IDpowerpad_vbus false This parameter enables VBUS

power padProdactName This string is displayed by the

Operating System when it isinstalling the mass storagedevice as the Product Name.

ProdactRevision This string is displayed by theOperating System when

it is installing the mass storagedevice as the Product Revision.

rm_lpm_int true Removes LPM ISRUser Comments Instance-specific comments.VendorName This string is displayed by the

Operating System when it isinstalling the mass storagedevice as the Vendor Name.

Vid 04B4 Vendor ID

8.14 Component type: VDAC8 [v1.90]

8.14.1 Instance VDAC8_Vref

Description: 8-Bit Voltage DACInstance type: VDAC8 [v1.90]Datasheet: online component datasheet for VDAC8

Table 37. Component Parameters for VDAC8_VrefParameter Name Value DescriptionData_Source CPU or DMA (Data Bus) Selects the method in which the

data is written to the vDAC.Initial_Value 25 Configures the initial vDAC

output voltage. The output usesthe following relation: Initial

output voltage =value*(FullRange/255). This

calculated output voltage valueis invalid if DAC Bus is used.

Strobe_Mode Register Write Selects how the data is strobedinto the DAC. For a registerwrite, the data is strobed intothe DAC on each CPU or DMAwrite. If operating in Externalmode, an external data strobe

signal is required.

http://www.cypress.com/go/comp_VDAC8

8 Components

SiPM Datasheet 01/16/2019 12:00 41

Parameter Name Value DescriptionUser Comments Instance-specific comments.VDAC_Range 0 - 1.020V (4mV/bit) Specifies the full voltage scale

range of the vDACVDAC_Speed Low Speed Specifies the vDAC settling

speed. Note that the 'SlowSpeed' selection consumes less

power.Voltage 100 This parameter sets the voltage

value.

9 Other Resources

SiPM Datasheet 01/16/2019 12:00 42

9 Other Resources

The following documents contain important information on Cypress software APIs that might berelevant to this design:

• Standard Types and Defines chapter in the System Reference Guideo Software base typeso Hardware register typeso Compiler defineso Cypress API return codeso Interrupt types and macros

• Registerso The full PSoC 5LP register map is covered in the PSoC 5LP Registers Technical Reference

Manualo Register Access chapter in the System Reference Guide§ CY_GET API routines§ CY_SET API routines

• System Functions chapter in the System Reference Guideo General API routineso CyDelay API routineso CyVd Voltage Detect API routines

• Power Managemento Power Supply and Monitoring chapter in the PSoC 5LP Technical Reference Manualo Low Power Modes chapter in the PSoC 5LP Technical Reference Manualo Power Management chapter in the System Reference Guide§ CyPm API routines

• Watchdog Timer chapter in the System Reference Guideo CyWdt API routines

• Cache Managemento Cache Controller chapter in the PSoC 5LP Technical Reference Manualo Cache chapter in the System Reference Guide§ CyFlushCache() API routine


http://www.cypress.com/go/psoc5lp_trm_registers

http://www.cypress.com/go/psoc5lp_trm_registers









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