Project Document

WIRELESS BASED POWER LINE BREAKAGE MONITORING

SYNOPSIS

The project designed here is to monitor the breakage in power line and to transmit the condition to main station through wireless communication. The advantage of the project is that it displays the area where there is a break.

The main objective of the project is to reduce the human risk, and also to avoid fatal accidents. This project can be implemented for E.B, telephone lines and cable TV lines. The project will be useful for persons working in above departments, since they can the area where there is a breakage and can attend it easily.

The microcontroller is the main component of the project, the microcontroller use here is PIC 16F72, the breakage is identified by using power line sensors [PL 223], the status is transmitted through RF TX [TLP433] and received by RF RX [RLP433], a LCD shows the data and the warning buzzer will be glow when the power failure will be occurred.

By proper implementation the project will be very useful for the cabling departments and reduces their work load. This whole process is executed continuously so that the power line breakage is easily monitored automatically by the microcontroller so there is no need of man’s intervention. In this project microcontroller and sensors are used so the cost of the system is less, the accuracy and reliability is much higher. And also the water wastage is reduced.


BLOCK DIAGRAM

Transmitter section

Receiver section

RF Transmitter

Microcontroller

PIC16F72

LCD Display

Power Relays

Power line Sensing

RF Receiver

Microcontroller

PIC16F72

LCD Display

Buzzer


Circuit diagram

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R C 5 / S D OR C 6 / TX/ C KR C 7 / R X/ D T

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Power line communication

Power line communication (PLC), also called power line carrier, mains communication, power line telecom (PLT), or power line networking (PLN), are terms describing several different systems for using electric power lines to carry information over the powerline.

Introduction

Electrical power is transmitted over high voltage transmission lines, medium voltage distribution, and inside buildings at lower voltages. Powerline communications can be applied at each stage. Most PLC technologies limit themselves to one particular set of wires (for example, premises wiring), but some systems can cross between two levels (for example, both the distribution network and premises wiring).

All power line communications systems operate by impressing a modulated carrier signal on the wiring system. Different types of powerline communications use different frequency bands, depending on the signal transmission characteristics of the power wiring used. Since the power wiring system was originally intended for transmission of AC power, the power wire circuits have only a limited ability to carry higher frequencies. The propagation problem is a limiting factor for each type of power line communications.

Data rates over a power line communication system vary widely. Low-frequency (about 100-200 kHz) carriers impressed on high-voltage transmission lines may carry one or two analog voice circuits, or telemetry and control circuits with an equivalent data rate of a few hundred bits per second; however, these circuits may be many miles (kilometres) long. Higher data rates generally imply shorter ranges; a local area network operating at millions of bits per second may only cover one floor of an office building, but eliminates installation of dedicated network cabling.

High Frequency Communication (>=MHz)

High frequency communication may (re)use large portions of the radio spectrum for communication, or may use select (narrow) band(s), depending on the technology.

Home networking

Power line communications can also be used to interconnect home computers, peripherals or other networked consumer peripherals, although at present there is no universal standard for this type of application. Standards for power line home networking have been developed by a number of different companies within the framework of the HomePlug Powerline Alliance and the Universal Powerline Association.

Operation

Since the signals may travel a short distance outside the user's residence or business, like many other network standards, HomePlug includes the ability to set an encryption

http://en.wikipedia.org/w/index.php?title=Network_standard&action=edit

http://en.wikipedia.org/wiki/Universal_Powerline_Association

http://en.wikipedia.org/wiki/Universal_Powerline_Association

http://en.wikipedia.org/wiki/HomePlug_Powerline_Alliance

http://en.wikipedia.org/wiki/Local_area_network

http://en.wikipedia.org/wiki/AC_power

http://en.wikipedia.org/wiki/Grid_connection


password. As with many other networking products, most HomePlug devices are Secure by default. The HomePlug standards require that all devices are set to a default out-of-box password - although a common one. Users should change this password.

To simplify the process of configuring passwords on a HomePlug network, each device has a built-in master password, chosen at random by the manufacturer and hard-wired into the device, which is used only for setting the encryption passwords. A printed label on the device lists its master password.

The data at either end of the HomePlug link is not encrypted (unless an encrypted higher-layer protocol such as TLS or IPSEC being used), only the link between HomePlug devices is encrypted.

Since HomePlug devices typically function as transparent network bridges, computers running any operating system can use them for network access. However, some manufacturers only supply the password-setup software in a Microsoft Windows version; in other words, enabling encryption requires a computer running Windows [1]. Once the encryption password has been configured, Windows will no longer be needed, so in the case of a network where all computers run other systems a borrowed laptop could be used for initial setup purposes.

In residences and small businesses with Split phase wiring (common in North America), roughly half the 120-volt outlets in the building will be on each hot phase, and HomePlug signals may or may not be able to get from one side to the other. If one is unlucky, this may prevent some rooms from being connected via HomePlug.

Among other things, HomePlug brings back the ability to use Ethernet in bus topology, implied by its standard description (carrier sense multiple access and collision detection) and very desirable in some circumstances. This is achieved by use of advanced OFDM modulation that allows co-existence of several distinct data carriers in the same wire. The use of OFDM also allows turning off (masking) one or more of the sub-carriers which overlap previously allocated radio spectrum in a given geographic region. In North America, for instance, HomePlug AV only uses 917 of 1155 sub-carriers.[1]

Transmitting radio programs

Sometimes PLC was and is used for transmitting radio programs over powerlines. When operated in the AM radio band, it is known as a carrier current system. Such devices were in use in Germany, where it was called "Drahtfunk" and in Switzerland, where it was called "Telefonrundspruch" and used telephone lines. In the USSR PLC was very common for broadcasting, because PLC listeners cannot receive foreign transmissions. In Norway the radiation of PLC systems from powerlines was sometimes used for radio supply. These facilities were called Linjesender. In all cases the radio programme was fed by special transformers into the lines. In order to prevent uncontrolled propagation, filters for the carrier frequencies of the PLC systems were installed in substations and at line branches.

http://en.wikipedia.org/wiki/Linjesender

http://en.wikipedia.org/wiki/Norway

http://en.wikipedia.org/wiki/USSR

http://en.wikipedia.org/w/index.php?title=Telefonrundspruch&action=editredlink

http://en.wikipedia.org/wiki/Switzerland

http://en.wikipedia.org/w/index.php?title=Drahtfunk&action=editredlink

http://en.wikipedia.org/wiki/Germany

http://en.wikipedia.org/wiki/Carrier_current

http://en.wikipedia.org/wiki/#_note-AVharness

http://en.wikipedia.org/wiki/North_America

http://en.wikipedia.org/wiki/Radio_spectrum

http://en.wikipedia.org/wiki/Sub-carrier

http://en.wikipedia.org/wiki/OFDM

http://en.wikipedia.org/wiki/Ethernet

http://en.wikipedia.org/wiki/Split_phase

http://www.netgear.com/products/details/XE102.php

http://en.wikipedia.org/wiki/Operating_system

http://en.wikipedia.org/wiki/Network_bridge

http://en.wikipedia.org/wiki/IPSEC

http://en.wikipedia.org/wiki/Transport_Layer_Security

http://en.wikipedia.org/wiki/Hard-wire

http://en.wikipedia.org/wiki/Password

http://en.wikipedia.org/wiki/Secure_by_default


An example of the programs carried by "wire broadcasting" in Switzerland:

175 kHz Swiss Radio International 208 kHz RSR1 “la première” (French)

241 kHz “classical music”

274 kHz RSI1 “rete UN” (Italian)

307 kHz DRS1 (German)

340 kHz “easy music”

Utility applications

Utility companies use special coupling capacitors to connect medium-frequency radio transmitters to the power-frequency AC conductors. Frequencies used are in the range of 24 to 500 kHz, with transmitter power levels up to hundreds of watts. These signals may be impressed on one conductor, on two conductors or on all three conductors of a high-voltage AC transmission line. Several different PLC channels may be coupled onto one HV line. Filtering devices are applied at substations to prevent the carrier frequency current from being bypassed through the station apparatus and to ensure that distant faults do not affect the isolated segments of the PLC system. These circuits are used for control of switchgear, and for protection of transmission lines. For example, a protection relay can use a PLC channel to trip a line if a fault is detected between its two terminals, but to leave the line in operation if the fault is elsewhere on the system.

While utility companies use microwave and now, increasingly, fiber optic cables for their primary system communication needs, the power-line carrier apparatus may still be useful as a backup channel or for very simple low-cost installations that do not warrant a fibre drop.

Low Frequency (<kHz)

Utility

Such systems have long been a favorite at many utilities because it allows them to move large amounts of data over an infrastructure that they control. Many technologies are capable of performing multiple applications. For example, a communication system bought initially for automatic meter reading can sometimes also be used for load control or for demand response applications.

Automatic meter reading

PLC is one of the technologies used in the Automatic Meter Reading industry. Both one-way and two-way systems have been successfully used for decades. Interest in this application has grown substantially in recent history -- not so much because there is an

http://en.wikipedia.org/wiki/Demand_response

http://en.wikipedia.org/wiki/Load_control

http://en.wikipedia.org/wiki/Automatic_meter_reading

http://en.wikipedia.org/wiki/Capacitor

http://en.wikipedia.org/wiki/DRS

http://en.wikipedia.org/wiki/RSI

http://en.wikipedia.org/wiki/Swiss_Radio_International


interest in automating a manual process, but because there is an interest in obtaining fresh data from all metered points in order to better control and operate the system.

In a one-way (inbound only) system, readings "bubble up" from end devices (i.e. meters), through the communication infrastructure, to a "master station" which publishes the readings. A one-way system might be lower-cost than a two-way system, but also is difficult to reconfigure should the operating environment change.

In a two-way system (supporting both outbound and inbound), commands can be broadcast out from the master station to end devices (meters) -- allowing for reconfiguration of the network, or to obtain readings, or to convey messages, etc. The device at the end of the network may then respond (inbound) with a message that carries the desired value.

Load control

Outbound messages injected at a utility substation will propagate to all points downstream. This type of broadcast allows the communication system to simultaneously reach many thousands of devices -- all of which are known to have power, and have been previously identified as candidates for load shed.

Technology

Technology is available from designs based on a number of different non-compatible silicon vendors.

High Frequency

These include Intellon's INT6000 silicon which meets the HomePlug AV specification (not interoperable with HomePlug 1.0 or Intellon's proprietary 85 Mbit/s Turbo mode) or DS2 DSS9XXX series silicon which complies with Universal Powerline Association standards; and other solutions from Panasonic and SiConnect. Some solutions are based on OFDM modulation with 1536 carriers and TDD or FDD channel access method. DS2 silicon may operate between 1 and 34 MHz. It provides a high dynamic range (90 dB) and offers frequency division and time division repeating capabilities. These characteristics allow the implementation of quality of service (QoS) and class of service (CoS) capabilities. Technologies deliver speeds of up to 200 Mbit/s at the physical layer and 130 Mbit/s at the application layer although actual throughput rates are degraded by the attenuation and the level of noise.

Medium Frequency

The technology to communicate over a transmission line has been largely standardized by IEEE Std 643. Systems built to this standard are available from commercial vendors.

Low Frequency

Entire systems are available from commercial vendors.



LCD DISPLAY

INTRODUCTION

LCD stands for liquid crystal; this is a output device with a limited viewing angle. The choice of LCD as an output device was Because of its cost of use and is better with alphabets when compared with a 7-segment LED display. We have so many kinds of LCD today and our application requires a LCD with 2 lines and 16 characters per line, this gets data from the microcontroller and displays the same. It has 8 data lines, 3 control line, a supply voltage Vcc (+5v and a GND. This makes the whole device user friendly by showing the balance left in the card. This also shoes the card that is currently being used.

In recent years the LCD is finding widespread use replacing LED’s. This is due to the following reasons:

1. The declining prices of LCD’s.2. The ability to display numbers, characters and graphics. This is in contrast to LED’s,

which are limited to numbers and few characters.3. Incorporation of a refreshing controller into the LCD, there by relieving the CPU of the

task of refreshing the LCD .in contrast, the Led must be refreshed by the CPU to keep displaying the data.

4. Ease of programming for characters and graphics.

LCD PIN DESCRIPTIONS

VCC, VSS and VEE

While VCC and VSS provide +5v and ground respectively, VEE is used for controlling LCD contrast.

RS, REGISTER SELECT

There are two very important registers inside the LCD. The RS pin used for their selection as follows. If RS=0, the instruction command code register is selected, allowing the user to sent a command such as clear display, cursor at home ,etc .IF RS=1 the data register is selected, allowing the user to sent data to be displayed on the LCD.

R/W READ/WRITE

R/W input allows the user to write information to the LCD or read information from it.

R/W=1 when reading; R/W=0 when writing.

E, ENABLE

The enable pin is used by the LCD to latch information present to its data pins. When data is supplied to data pins, a high to low pulse must be applied to this pin in order for the LCD to latch in the data present at the data pins. This pulse must be a minimum of 450ns wide.


D0-D7

The 8-bit data pins, D0-D7, are used to sent information to LCD or read the contents of the LCD’s internal registers.

To display letters and numbers, we send ASCII codes for the letters A-Z, a-z, and numbers 0-9 to these pins while making RS=1.

There are also instruction command codes that can be send to the LCD to clear the display or force the cursor to the home position or blink the cursor.

We also use RS=0 to check the busy flag bit see if the LCD is ready to receive information. The busy flag is D7 and can be read when R/W=1 and RS=0, as follows, if R/W=1 ,RS=0. When D7=1, The LCD is busy taking care of internal operations and will not accept any new information. when D7=0, the LCD is ready to receive new information.

LCD COMMAND CODES

1 Clear display screen2 Return home4 Decrement cursor6 Increment cursor5 Shift display right7 Shift display left8 Display off, cursor offA Display off, cursor on C Display on, cursor offE Display on, cursor blinkingF Display on, cursor blinking10 Shift cursor position to left14 Shift cursor position to right18 Shift the entire display to the left1C Shift the entire display to the right80 Force cursor to beginning of the 1st line C0 Force cursor to beginning of the 2nd line38 2 lines and 2*7 matrix

LCD PANEL

A 16x2 Liquid Crystal Display


LCD PROGRAMMING CHART:


LCD CIRCUIT DIAGRAM

1 0

D B 0

E N V S S

1 0 K7

0

1 2

9

40

+5 V

V E E

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D B 2

20

D B 7

1 1 . 0 5 9 2

AT 89C52

3 1

1 9

1 8

9

1 21 31 41 5

12345678

3 93 83 73 63 53 43 33 2

2 12 22 32 42 52 62 72 8

1 71 62 93 01 11 0

E A / V P

X1

X2

R E S E T

I N T0I N T1T0T1

P 1 .0P 1 .1P 1 .2P 1 .3P 1 .4P 1 .5P 1 .6P 1 .7

P 0 .0P 0 .1P 0 .2P 0 .3P 0 .4P 0 .5P 0 .6P 0 .7

P 2 .0P 2 .1P 2 .2P 2 .3P 2 .4P 2 .5P 2 .6P 2 .7

R DW R

P S E NA L E / P

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12

0

1 mf

D B 3

D B 6

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1 4

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154

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6

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2

1 3

P O T

8-BIT INTERFACE


4-BIT INTERFACE.

The LCD requires either 8 or 11 I/O lines to communicate with. For the sake of this tutorial, we are going to use an 8-bit data bus--so we'll be using 11 of the 8051's I/O pins to interface with the LCD.

The EN line is used to tell the LCD that you are ready for it to execute an instruction that you've prepared on the data bus and on the other control lines. Note that the EN line must be raised/lowered before/after each instruction sent to the LCD regardless of whether that instruction is read or write, text or instruction. In short, you must always manipulate EN when communicating with the LCD. EN is the LCD's way of knowing that you are talking to it. If you don't raise/lower EN, the LCD doesn't know you're talking to it on the other lines.


CHARACTER SET

Character set for 5x7 dot font


INTERFACING 8051 WITH LCD

PROGRAMMING THE LCD:

Before you may really use the LCD, you must initialize and configure it. This is accomplished by sending a number of initialization instructions to the LCD.

The first instruction we send must tell the LCD whether we'll be communicating with it with an 8-bit or 4-bit data bus. We also select a 5x8 dot character font. These two options are selected by sending the command 38h to the LCD as a command. As you will recall from the last section, we mentioned that the RS line must be low if we are sending a command to the LCD. The second byte of the initialization sequence is the instruction 0Eh. Thus we must repeat the initialization code from above, but now with the instruction. Thus the the next code segment is:

The last byte we need to send is used to configure additional operational parameters of the LCD. We must send the value 06h.

Thus, the first character in the upper left-hanad corner is at address 00h. The following character position (character #2 on the first line) is address 01h, etc. This continues until we reach the 16th character of the first line which is at address 0Fh.

However, the first character of line 2, as shown in the memory map, is at address 40h. This means if we write a character to the last position of the first line and then write a second character, the second character will not appear on the second line. That is because the second character will effectively be written to address 10h--but the second line begins at address 40h.

Thus we need to send a command to the LCD that tells it to position the cursor on the second line. The "Set Cursor Position" instruction is 80h. To this we must add the address of the location where we wish to position the cursor.


POWER SUPPLY

Available power source is an Ac voltage arrives at 230V.Since our electronic circuits require only very minimal voltage and current we use step down power transformer. Step down transformer is designed in such a way that the input is 230V and output of 12V. Another thing is, that electronic circuits operate in DC where as available output of transformer is Ac of 12V. So rectifier circuit is used to convert AC to DC. Rectifier circuit consists of four diodes formed in bridge fashion so as to convert incoming AC to DC.

Even though output of rectifier circuit is DC it is not smooth or fixed DC. So filter circuits are used to convert rippling DC to smooth DC. The filter circuit is a capacitor, connected parallel to the output of rectifier circuit. This smooth DC voltage will be in the range of 12+volt. But we require only 5V supply for the operation of micro controllers and it’s supporting components. Here again regulator ICs such as 7805 is used to regulate the incoming 12VDC to fixed regulated 5V as output. This DC regulated 5V is applied to the circuits.

Even though the circuit is functioning with 5V, the relays are driven by 6V or 12V. For this purpose 7806/7812 regulator IC is additionally connected to the rectifier filter circuit. Thus 12V regulated is used for driving 12V relays.

VOLTAGE REGULATORS

THREE-TERMINAL REGULATORS

For most no critical applications the best choice for a voltage regulator is the simple –terminal type. It has only three connections (input, output, and ground) and is factory-trimmed to provide a fixed output. Typical of this type is the 78xx. The voltage is specified by the last two digits of the part number and can be any of the following: 05, 08,10, 12, 15,18, or 24. It is to make a +5 volt regulator, for instance, with one of these regulators. The capacitor across the output improves transient response and keeps the impedance low at high frequencies (an input capacitor of at least 0.33F should be used in addition if the regulator is located a considerable distance from the filter capacitors).

The 7800 series is available in plastic or metal power packages (same as power transistors). A low-power version, the 78Lxx, comes in the same plastic and metal packages as small-signal transistors. The 7900 series of negative regulators works the same way (with negative input voltage, of course). The 7800 series can provide up to 1 amp load current and has on-chip circuitry to prevent damage in the event of overheating or excessive load current; the chip simply shuts down, rather than blowing out. In addition, on-chip circuitry prevents operation outside the


Transistor safe operating area by reducing available output current for large input-output voltage differential. These regulators are in-expensive and easy to use, and they make it practical to design a system with many printed-circuit boards in which the unregulated dc is brought to each board and regulation is done locally on each circuit card.

Three - terminal fixed regulators come in some highly useful variants. The LP 2950 works just like a 7805, but draws only 75A of quiescent current (compared with the 7805’s 5mA or the 78L05’s 3mA); it also regulates with as little as a 0.4 volt drop from unregulated input to regulated output (called the “drop out voltage”), compared with 2 volts drop out for the classic 7805. The LM291 is also low-dropout, but you might call it milli power (0.4mA quiescent current), compared with the “micro power” LP 2950. Low-dropout regulators also come in high – current versions for example, the LT 1085/4/3 series from LTC (A, 5A, and 7.5A, respectively, with both + 5V and + 12V available in each type). Regulators like the LM 2984 are basically three-terminal fixed regulators, but with extra outputs to signal a microprocessor that power has failed, or resumed. Finally, regulators like the 4195 contain a pair of 3-terminal 15-volt regulators, one positive and one negative.

LM78XX Series Voltage RegulatorsGENERAL DESCRIPTION The LM78xx series of three terminal regulators is available with several fixed output voltages making them useful in a wide range of applications. One of these is local on card regulation, eliminating the distribution problems associated with single point regulation. The voltages available allow these regulators to be used in logic systems, instrumentation, HiFi, and other solid-state electronic equipment. Although designed primarily as fixed voltage regulators these devices can be used with external components to obtain adjustable voltages and currents.

The LM78XX series is available in an aluminum TO-3 package which will allow over 1.0A load current if adequate heat sinking is provided. Current limiting is included to limit the peak output current to a safe value. Safe area protection for the output transistor is provided to limit internal power dissipation. If internal power dissipation becomes too high for the heat sinking provided, the thermal shutdown circuit takes over preventing the IC from overheating.

Considerable effort was expanded to make the LM78XX series of regulators easy to use and minimize the number of external components. It is not necessary to bypass the output, although this does improve transient response. Input by-passing is needed only if the regulator is located far from the filter capacitor of the power supply.

Features Output current in excess of 1A Internal thermal overload protection No external components required Output transistor safe area protection Internal short circuit current limit Available in the aluminum TO-3 package


Voltage RangeLM7805C 5VLM7812C 12VLM7815C 15VLM7912C -12V

CIRCUIT DIAGRAM OF POWER SUPPLY UNIT

230 V /A C

+

1 0 0 0 M F / 2 5 V

1 3

2 4G N D

1 3V I N V O U T

0

7 8 0 5

0

12V - 0 (6V )/ 500 M A

1 K

- +

1 N 4 0 0 7B R I D G E

1

4

3

2

1N4007

+ 5 V cc

2

T RA NSFORM ER

1 0 4

L E D

INTRODUCTION TO RFID

Radio Frequency Identification (RFID) is a generic term that is used to describe a system that transmits the identity (in the form of a unique serial number) of an object or person wirelessly, using radio waves. It's grouped under the broad category of automatic identification technologies.

Auto-Video ID technologies include bar codes, optical character readers and some biometric technologies, such as retinal scans. The auto-ID technologies have been used to reduce the amount of time and labor needed to input data manually and to improve data accuracy.

The auto-Video ID technologies, such as bar code systems, often require a person to manually scan a label or tag to capture the data. RFID is designed to enable readers to capture data on tags and transmit it to a computer system without needing a person to be involved.

RFID, the technology of tomorrow, is here today. In fact, over a billion tags are in use worldwide, yielding benefits from livestock tracking to vehicle immobilization. This is such a huge number that it makes one question calling RFID an emerging technology.

In the most basic level, it identifies unique objects, processes, transactions or events. RFID does this by using a burst of radio waves to move information, much like carrier pigeons


were used to move information from point to point centuries ago. It is possible to explain RFID using only two basic building blocks - A Tag and a Reader. Of course, they may be configured in sophisticated ways to create large networks capable of staggering data flows.

A unique serial number is stored on a microchip that is the size of the period at the end of this sentence. A tiny antenna is also attached to the microchip. Together, the chip and antenna are called a tag. Typical tags range in size from a stamp to a credit card. The built-in antenna allows the tag to receive information from a device called a reader. When commanded by the reader the tag transmits information over the air using radio waves. The reader then converts the radio waves from the tag into digital information that's forwarded to a down stream computer.RFID (Radio Frequency Identification) systems include electronic devices called tags which essentially consist of a microchip, memory and an antenna. Microchips are the brains for the Tags.

Information which is sent or received from the radio waves is then stored or recalled from the memory. The antenna has only one task to do; however, that task has a direction. It handles communication from either the Tag to the Reader or from the Reader to the Tag. Think of the antenna as a language translator converting digital data into radio wave energy or vice-versa.

RADIO FREQUENCY

Radio Frequency (RF), any frequency within the electromagnetic spectrum associated with radio wave propagation. When an RF current is supplied to an antenna, an electromagnetic field is created that then is able to propagate through space. Many wireless technologies are based on RF field propagation.

These frequencies make up part of the electromagnetic radiation spectrum:

Ultra-low frequency (ULF) -- 0-3 Hz Extremely low frequency (ELF) -- 3 Hz - 3 kHz

Very low frequency (VLF) -- 3kHz - 30 kHz

Low frequency (LF) -- 30 kHz - 300 kHz

Medium frequency (MF) -- 300 kHz - 3 MHz

High frequency (HF) -- 3MHz - 30 MHz

Very high frequency (VHF) -- 30 MHz - 300 MHz

Ultra-high frequency (UHF)-- 300MHz - 3 GHz

Super high frequency (SHF) -- 3GHz - 30 GHz

Extremely high frequency (EHF) -- 30GHz - 300 GHz

ADVANTAGES OF RADIO WAVES


The big advantages of radio waves are their ability to penetrate hard surfaces at amazing speed. A radio wave travels around the earth 7 times in one second making it a very cost effective and capable information carrier.

A Tag physically attaches to something thereby allowing its location, condition or status to be tracked via information sent using radio waves. Decoding of a Tag occurs when it enters the antennas read zone. A read zone can be defined as the sweet spot of the antenna where radio waves may be sent and received in such a way that reliable communications take place between the Tag and the Reader. To further harden the communications on the radio link clever algorithms are able to resend or even repair damaged information.

RFID (Radio Frequency Identification [315, 418 and 433.92MHz]) tags come in a wide variety of sizes, shapes and forms but have common attributes, such as: low-energy transmits and receives antennas, data storage and operating circuitry. Tags come with and without batteries; they can be read only or read/write. Typically, tags without batteries (passive) are smaller and lighter than those that are active (with batteries), and less expensive.

When multiple tags are present in the antenna's sweet spot the Reader uses special ways to handle this work load. It tells tags to go to sleep and, therefore, talks to one at a time. Once data is sent by Tags and captured by the Reader, it is transferred through standard interfaces to a host computer, printer, database or programmable logic controller for storage or action.

Reader electronics may be stationary or handheld. They are linked to other software systems that control the flow of data. In some cases the readers must power, engage, download and retransmit data to the tag they encounter.

COMPONENTS OF RFID

An RFID (Radio Frequency Identification) system is always made up of two components: the transponder, which is located on the object to be identified, The detector or reader, which, depending upon design and the technology used, may be a read or write/read device.


FIG.1.1 READER AND THE TRANSPONDER-THE MAIN COMPONENTS OF RFID SYSTEM

A reader typically contains a high frequency module (transmitter and receiver), a control unit and a coupling element to the transponder. In addition, many readers are fitted with an additional interface (RS 232, RS 485) to enable it to forward the data received to another system (PC, robot control system). The main components of RFID (Radio Frequency Identification) system are as shown in the fig.1.1

The transponder, which represents the actual data carrying device of an RFID system, normally consists of a coupling element and an electronic microchip. When the transponder, which does not usually possess its own voltage supply (battery), is not within the response range of a reader it is totally passive. The transponder is only activated when it is within the response range of a reader. The power required to activate the transponder is supplied to the transponder through the coupling unit (contact less) as is the timing pulse and data.

OPERATING PRINCIPLES OF RFID SYSTEMS

There is a huge variety of different operating principles for RFID (Radio Frequency Identification) systems.

Inductive Coupling

An inductively coupled transponder comprises of an electronic data carrying device, usually a single microchip and a large area coil that functions as an antenna.

Inductively coupled transponders are almost always operated passively. This means that all the energy needed for the operation of the microchip has to be provided by the reader. For this purpose, the reader's antenna coil generates a strong, high frequency electro-magnetic field, which penetrates the cross-section of the coil area and the area around the coil. Because the wavelength of the frequency range used (< 135 kHz: 2400 m, 13.56 MHz: 22.1 m) is several times greater than the distance between the reader's antenna and the transponder, the electro-magnetic field may be treated as a simple magnetic alternating field with regard to the distance between transponder and antenna.

A small part of the emitted field penetrates the antenna coil of the transponder, which is some distance away from the coil of the reader. By induction, a voltage V i is generated in the transponder's antenna coil. This voltage is rectified and serves as the power supply for the data carrying device (microchip). A capacitor C1 is connected in parallel with the reader's antenna coil, the capacitance of which is selected such that it combines with the coil inductance of the antenna coil to form a parallel resonant circuit, with a resonant frequency that corresponds with the transmission frequency of the reader. Very high currents are generated in the antenna coil of the reader by resonance


step-up in the parallel resonant circuit, which can be used to generate the required field strengths for the operation of the remote transponder.

The antenna coil of the transponder and the capacitor C1 to form a resonant circuit tuned to the transmission frequency of the reader. The voltage V at the transponder coil reaches a maximum due to resonance step-up in the parallel resonant circuit. The inductive coupling of transponder and the reader as shown in fig.1.2.

FIG.1.2. INDUCTIVE COUPLING OF TRANSPONDER AND THE READER

The inductively coupled systems are based upon a transformer-type coupling between the primary coil in the reader and the secondary coil in the transponder. This is true when the distance between the coils does not exceed 0.16λ, so that the transponder is located in the near field of the transmitter antenna.

When a resonant transponder (i.e. the self-resonant frequency of the transponder corresponds with the transmission frequency of the reader) is placed within the magnetic alternating field of the reader's antenna, then this draws energy from the magnetic field. This additional power consumption can be measured as voltage drop at the internal resistance in the reader antennae through the supply current to the reader's antenna. The switching on and off of a load resistance at the transponder's antenna therefore effects voltage changes at the reader's antenna and thus has the effect of an amplitude modulation of the antenna voltage by the remote transponder. If the switching on and off of the load resistor is controlled by data, then this data can be transferred from the transponder to the reader. This type of data transfer is called load modulation.

The data in the reader can be reclaimed by rectifying the voltage measured at the reader's antenna. This represents the demodulation of an amplitude modulated signal.


If the additional load resistor in the transponder is switched on and off at a very high elementary frequency fH(High Frequency), then two spectral lines are created at a distance of ±fH around the transmission frequency of the reader, and these can be easily detected (however fH must be less than fREADER). In the terminology of radio technology the new elementary frequency is called a sub carrier. Data transfer is by the ASK (Amplitude Shift Keying), FSK (Frequency Shift Keying) or PSK (Phase Shift Keying) modulation of the sub carrier in time with the data flow. This represents an amplitude modulation of the sub carrier.

Backscatter Coupling

It is known that from the field of RADAR technology that electromagnetic waves are reflected by objects with dimensions greater than around half the wavelength of the wave. The efficiency with which an object reflects electromagnetic waves is described by its reflection cross-section. Objects that are in resonance with the wave front that hits them, as is the case for antenna at the appropriate frequency for example, have a particularly large reflection cross-section. The operating principle of a backscatter transponder as shown in fig.1.3.

FIG.1.3. OPERATION PRINCIPLE OF A BACKSCATTER TRANSPONDER

Power P1 is emitted from the reader's antenna, a small proportion of which (free space attenuation) reaches the transponder's antenna. The power P1' is supplied to the antenna connections as High Frequency(HF) voltage and after rectification by the diodes D1 and D2 this can be used as turn on voltage for the deactivation or activation of the power saving "power-down" mode. The diodes used here are low barrier Schottky diodes, which have a particularly low threshold voltage. The voltage obtained may also be sufficient to serve as a power supply for short ranges.

A proportion of the incoming power P1' is reflected by the antenna and returned as power P2. The reflection characteristics (= reflection cross-section) of the antenna can be influenced by altering the load connected to the antenna. In order to transmit data from the transponder to the reader, a load resistor RL connected in parallel with the antenna is switched on and off in time with the data stream to be transmitted. The


amplitude of the power P2 reflected from the transponder can thus be modulated (à modulated backscatter).

The power P2 reflected from the transponder is radiated into free space. A small proportion of this (free space attenuation) is picked up by the reader's antenna. The reflected signal therefore travels into the antenna connection of the reader in the "backwards direction" and can be decoupled using a directional coupler and transferred to the receiver input of a reader. The "forward" signal of the transmitter, which is stronger by powers of ten, is to a large degree suppressed by the directional coupler.

The ratio of power transmitted by the reader and power returning from the transponder (P1 / P2) can be estimated using the radar equation.

RFID vs. BAR CODE

RFID’s (Radio Frequency Identification) benefits this blog compares its capabilities to an existing industry standard, the Bar Code. Pundits for the technology claim that RFID will eventually replace the bar code. By understanding how RFID compares to bar codes you will gain an appreciation for its potential while learning more about how it works.

Physical Size

Tags range in size from a postage stamp to a book. The aspect ratio of a Tag's length vs. width is very flexible and not a significant factor for the Reader. Bar codes are larger than the smallest tag and very sensitive to the aspect ratio for presentation to a scanner. The ratio of a bar code's length vs. width is critical to its operation.

Lifespan

Tags have no moving parts and are embedded in protective material for an indestructible case and multi-year lifespan. Bar Codes have unlimited self life but are subject to degradation with handling.

Harsh Environments

Tags may be placed in extreme environments and perform to specification. They are very robust to handling, sensitive to environment, and generally degrade once used, stored or handled in a non-office environment.

Product Code

Digital data is stored on the Tag and provides for a significant capability to encode:

1) Tag originator

2) User data as needed by the segment or application


3) Serial number as needed by the segment/application

Major vertical markets like Retail have standards which are excellent at coding product type and manufacturer. Additional information beyond these basic parameters is not feasible because the size of the Bar Code (BC) becomes too large.

Counterfeiting

Tags are produced with a Unique Identity Code (UIC) or serial number from the manufacturer. This is embedded digitally on the microchip and may not be changed, therefore, making them extremely resistant to counterfeiting. Bar Codes may easily be duplicated and attached to products and are, therefore, easily counterfeited.

Dynamic Updates

Tags may be written to and offer on board memory to retain information. This feature may be used to store a product calibration history, preventive maintenance, etc. Updates may be made within the blink of an eye and automatically without human intervention. Once a Bar Code is printed it remains frozen. The Code and the process of attaching the BC are not supportive of real time updates. It is a labor intensive process to update any information on a Bar Code (BC) once printed.

Traceable

The combination of UIC (Unique Identification Code), user data, serial number and on-board memory makes it possible to track, recall, or document the life span of a single item. For example, with livestock this means that the birthplace of the animal, its vaccine history, feed lots, slaughter house, processor, etc may all be tracked. This kind of information supports a complete pedigree for an item attached to the Tag. BC is limited to an entire class of products and unable to drill down to a unique item. It is not feasible to recall, track or document a single item.

Scanning

RFID (Radio Frequency Identification) offers a range from inches to hundreds of feet and does not require line of sight. This means that individual Tags placed within a carton, packed in a box and stored on a pallet may be read. You do not have to open each box and present the individual item.

BC (Bar Code) - Offers a range over inches and requires line of sight to read the code. The Bar Code must be presented to the scanner in an orientation and distance that is very limited. Individual reading requires that each box on a pallet be opened and the item pulled for presentation to the scanner.

Simultaneous Scanning

RFID (Radio Frequency Identification) - Standards have algorithms to support simultaneous reading of Tags at one time.


BC (Bar Code) - Limited to one bar code at a time. Unable to support simultaneous reads.

Reusable

RFID - Yes

BC - No

From this comparison it is clear that RFID is capable to greatly amplify the benefits received from traditional bar coding. By eliminating the manual task of reading a bar code, RFID automates data entry. This permits new ways of processing items, events or transactions.


Introduction

The high performance of the PICmicro devices can be attributed to a number of architectural features commonly found in RISC microprocessors. These include:

• Harvard architecture

• Long Word Instructions

• Single Word Instructions

• Single Cycle Instructions

• Instruction Pipelining

• Reduced Instruction Set

• Register File Architecture

• Orthogonal (Symmetric) Instructions

Figure shows a simple core memory bus arrangement for Mid-Range MCU devices.

Harvard Architecture:

Harvard architecture has the program memory and data memory as separate memories and is accessed from separate buses. This improves bandwidth over traditional von Neumann architecture in which program and data are fetched from the same memory using the same bus. To execute an instruction, a von Neumann machine must make one or more (generally more) accesses across the 8-bit bus to fetch the instruction. Then data may need to be fetched, operated on, and possibly written. As can be seen from this description, that bus can be extremely congested. While with Harvard architecture, the instruction is fetched in a single instruction cycle (all 14-bits).While the program memory is being accessed, the data memory is on an independent bus and can be read and written. These separated buses allow one instruction to execute while the next instruction is fetched. A comparison of Harvard vs. von-Neumann architectures is shown in Figure.

Harvard vs. von Neumann Block Architectures


Long Word Instructions:

Long word instructions have a wider (more bits) instruction bus than the 8-bit Data Memory Bus.This is possible because the two buses are separate. This further allows instructions to be sized differently than the 8-bit wide data word which allows a more efficient use of the program memory,since the program memory width is optimized to the architectural requirements.

Single Word Instructions:

Single Word instruction opcodes are 14-bits wide making it possible to have all single word instructions. A 14-bit wide program memory access bus fetches a 14-bit instruction in a single cycle. With single word instructions, the number of words of program memory locations equals the number of instructions for the device. This means that all locations are valid instructions.Typically in the von Neumann architecture, most instructions are multi-byte. In general, a device with 4-KBytes of program memory would allow approximately 2K of instructions. This 2:1 ratio is generalized and dependent on the application code. Since each instruction may take multiple bytes, there is no assurance that each location is a valid instruction.

Long Word Instructions:

Long word instructions have a wider (more bits) instruction bus than the 8-bit Data Memory Bus.This is possible because the two buses are separate. This further allows instructions to be sized differently than the 8-bit wide data word which allows a more efficient use of the program memory, since the program memory width is optimized to the architectural requirements.

Single Word Instructions:


Single Word instruction opcodes are 14-bits wide making it possible to have all single word instructions. A 14-bit wide program memory access bus fetches a 14-bit instruction in a single cycle. With single word instructions, the number of words of program memory locations equals the number of instructions for the device. This means that all locations are valid instructions.Typically in the von Neumann architecture, most instructions are multi-byte. In general, a device with 4-KBytes of program memory would allow approximately 2K of instructions. This 2:1 ratio is generalized and dependent on the application code. Since each instruction may take multiple bytes, there is no assurance that each location is a valid instruction.

neral Mid-range PICmicro Block Diagram


Instruction Flow/Pipelining

An “Instruction Cycle” consists of four Q cycles (Q1, Q2, Q3, and Q4). Fetch takes one instruction cycle while decode and execute takes another instruction cycle. However, due to Pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g.GOTO) then an extra cycle is required to complete the instruction .

The instruction fetch begins with the program counter incrementing in Q1.

In the Execution cycle, the fetched instruction is latched into the “Instruction Register (IR)” in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destinations write).

Example shows the operation of the two stage pipeline for the instruction sequence shown. At time T CY 0, the first instruction is fetched from program memory. During T CY 1, the


first instruction executes while the second instruction is fetched. During T CY 2, the second instruction executes while the third instruction is fetched. During T CY 3, the fourth instruction is fetched while the third instruction (CALL SUB_1) is executed. When the third instruction completes execution, the CPU forces the address of instruction four onto the Stack and then changes the Program Counter(PC) to the address of SUB_1. This means that the instruction that was fetched during T CY 3 needs to be “flushed” from the pipeline. During T CY 4, instruction four is flushed (executed as a NOP ) and the instruction at address SUB_1 is fetched. Finally during T CY 5, instruction five is executed and the instruction at address SUB_1 + 1 is fetched.

Instruction Pipeline Flow

Input output lines

INTRODUCTION

General purpose I/O pins can be considered the simplest of peripherals. They allow the PICmicro to monitor and control other devices. To add flexibility and functionality to a device, some pins are multiplexed with an alternate function(s). These functions depend on which peripheral features are on the device. In general, when a peripheral is functioning, that pin may not be used as a general purpose I/O pin.

The direction of the I/O pins (input or output) is controlled by the data direction register, called the TRIS register. TRIS<x> controls the direction of PORT<x>. A ‘1’ in the TRIS bit corresponds to that pin being an input, while a ‘0’ corresponds to that pin being an output.

The PORT register is the latch for the data to be output. When the PORT is read, the device reads the levels present on the I/O pins (not the latch). This means that care should be taken with read-modify-write commands on the ports and changing the direction of a pin from an input to an output.

Figure shows a typical I/O port. This does not take into account peripheral functions that maybe multiplexed onto the I/O pin. Reading the PORT register reads the status of the pins whereas writing to it will write to the port latch. All write operations (such as BSF and BCF instructions)


are read-modify-write operations. Therefore a write to a port implies that the port pins are read; this value is modified, and then written to the port data latch.

When peripheral functions are multiplexed onto general I/O pins, the functionality of the I/O pins may change to accommodate the requirements of the peripheral module. Examples of this are the Analog-to-Digital (A/D) converter and LCD driver modules, which force the I/O pin to the peripheral function when the device is reset. In the case of the A/D, this prevents the device from consuming excess current if any analog levels were on the A/D pins after a reset occurred.

With some peripherals, the TRIS bit is overridden while the peripheral is enabled. Therefore, read-modify-write instructions (BSF, BCF, and XORWF) with TRIS as destination should be avoided. The user should refer to the corresponding peripheral section for the correct TRIS bit settings.

PORT pins may be multiplexed with analog inputs and analog VREF input. The operation of each of these pins is selected, to be an analog input or digital I/O, by clearing/setting the control bits in the ADCON1 register (A/D Control Register1). When selected as an analog input, these pins will read as ‘0’s.The TRIS registers control the direction of the port pins, even when they are being used as analog inputs. The user must ensure the TRIS bits are maintained set when using the pins as analog inputs.

Note 1:

If pins are multiplexed with Analog inputs, then on a Power-on Reset these pins are configured as analog inputs, as controlled by the ADCON1 register. Reading port pins configured as analog inputs read a ‘0’.

Note 2:

If pins are multiplexed with comparator inputs, then on a Power-on Reset these pins are


configured as analog inputs, as controlled by the CMCON register. Reading port

pins configured as analog inputs read a ‘0’.

Note 3:

If pins are multiplexed with LCD driver segments, then on a Power-on Reset these pins are configured as LCD driver segments, as controlled by the LCDSE register. To configure the pins as a digital port, the corresponding bits in the LCDSE register must be cleared. Any bit set in the LCDSE register overrides any bit settings in the corresponding TRIS register.

Note 4:

Pins may be multiplexed with the Parallel Slave Port (PSP). For the PSP to function the I/O pins must be configured as digital inputs and the PSPMODE bit must be set.

Note 5:

At present the Parallel Slave Port (PSP) is only multiplexed onto PORTD and PORTE. The microprocessor port becomes enabled when the PSPMODE bit is set. In this mode, the user must make sure that the TRISE bits are set (pins are configured as digital inputs) and that PORTE is configured for digital I/O. PORTD will override the values in the TRISD register. In this mode the PORTD and PORTE input buffers are TTL. The control bits for the PSP operation are located in TRISE.

PORTA and the TRISA Register

The RA4 pin is a Schmitt Trigger input and an open drain output. All other RA port pins have TTL input levels and full CMOS output drivers. All pins have data direction bits TRIS registers) which can configure these pins as output or input. Setting a TRISA register bit puts the corresponding output driver in a hi-impedance mode. Clearing bit in the TRISA register puts the contents of the output latch on the selected pin(s).

Example 1: Initializing PORTA

CLRF STATUS ; Bank0

CLRF PORTA ; Initialize PORTA by clearing output

; data latches

BSF STATUS, RP0 ; Select Bank1

MOVLW 0xCF ; Value used to initialize data direction

MOVWF TRISA ; PORTA<3:0> = inputs PORTA<5:4> = outputs

; TRISA<7:6> always read as '0'


PORTB and the TRISB Register

PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is TRISB. Setting a bit in the TRISB register puts the corresponding output driver in a high-impedance input mode. Clearing a bit in the TRISB register puts the contents of the output latch on the selected pin(s).

Example: Initializing PORTB

Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (OPTION<7>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset.

CLRF STATUS ; Bank0

CLRF PORTB ; Initialize PORTB by clearing output

; data latches



MOVWF TRISB ; PORTB<3:0> = inputs, PORTB<5:4> = outputs

; PORTB<7:6> = inputs

Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (OPTION<7>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset.

PORTC and the TRISC Register

PORTC is an 8-bit bi-directional port. Each pin is individually configurable as an input or output through the TRISC register. PORTC pins have Schmitt Trigger input buffers.

When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTC pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input.

Example: Initializing PORTC


CLRF STATUS ; Bank0

CLRF PORTC ; Initialize PORTC by clearing output

; data latches



MOVWF TRISC ; PORTC<3:0> = inputs, PORTC<5:4> = outputs

; PORTC<7:6> = inputs

Introduction

The Central Processing Unit (CPU) is responsible for using the information in the program memory (instructions) to control the operation of the device. Many of these instructions operate on data memory. To operate on data memory, the Arithmetic Logical Unit (ALU) is required. In addition to performing arithmetical and logical operations, the ALU controls status bits (which are found in the STATUS register). The results of some instructions force status bits to a value depending on the state of the result.

The machine codes that the CPU recognizes are show in Table.


Mid-Range MCU Instruction Set

CPU

General Instruction Format

The Mid-Range MCU instructions can be broken down into four general formats as shown in Figure. As can be seen the opcode for the instruction varies from 3-bits to 6-bits. This variable opcode size is what allows 35 instructions to be implemented.


General Format for Instructions

Central Processing Unit (CPU)

The CPU can be thought of as the “brains” of the device. It is responsible for fetching the correct instruction for execution, decoding that instruction, and then executing that instruction.

The CPU sometimes works in conjunction with the ALU to complete the execution of the instruction (in arithmetic and logical operations).

The CPU controls the program memory address bus, the data memory address bus, and accesses to the stack.

Instruction Clock

Each instruction cycle (TCY) is comprised of four Q cycles (Q1-Q4). The Q cycle time is the same as the device oscillator cycle time (TOSC). The Q cycles provide the timing/designation for the Decode, Read, Process Data, Write, etc., of each instruction cycle. The following diagram shows the relationship of the Q cycles to the instruction cycle.

The four Q cycles that make up an instruction cycle (TCY) can be generalized as:

Q1: Instruction Decode Cycle or forced No operation

Q2: Instruction Read Data Cycle or No operation

Q3: Process the Data


Q4: Instruction Write Data Cycle or No operation

Each instruction will show a detailed Q cycle operation for the instruction.

Q Cycle Activity

Arithmetic Logical Unit (ALU)

PIC micro MCUs contain an 8-bit ALU and an 8-bit working register. The ALU is a general purpose arithmetic and logical unit. It performs arithmetic and Boolean functions between the data in the working register and any register file.

Operation of the ALU and W Register

The ALU is 8-bits wide and is capable of addition, subtraction, shift and logical operations. Unless otherwise mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, typically one operand is the working register (W register). The other operand is a file register or an immediate constant. In single operand instructions, the operand is either the W register or a file register.

The W register is an 8-bit working register used for ALU operations. It is not an addressable register.

Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC), and Zero (Z) bits in the STATUS register. The C and DC bits operate as a borrow bit and a digit borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.


STATUS Register

The STATUS register, shown in Figure, contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory. Since the selection of the Data Memory banks is controlled by this register, it is required to be present in every bank. Also, this register is in the same relative position (offset) in each bank

The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended.

For example, CLRF STATUS will clear the upper-three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged).

It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register because these instructions do not affect the Z, C or DC bits from the STATUS register. For other instructions, not affecting any status bits, see Table.

Note 1:

Some devices do not require the IRP and RP1 (STATUS<7:6>) bits. These bits are not used by the Section 5. CPU and ALU and should be maintained clear. Use of these bits as general purpose R/W bits is NOT recommended, since this may affect upward code compatibility with future products.

Note 2:

The C and DC bits operate as a borrow and digit borrow bit, respectively, in subtraction.

STATUS Register

Bit 7 IRP: Register Bank Select bit (used for indirect addressing)


1 = Bank 2, 3 (100h - 1FFh)

0 = Bank 0, 1 (00h - FFh)

For devices with only Bank0 and Bank1 the IRP bit is reserved, always maintain this bit clear.

Bit 6:5 RP1:RP0: Register Bank Select bits (used for direct addressing)

11 = Bank 3 (180h - 1FFh)

10 = Bank 2 (100h - 17Fh)

01 = Bank 1 (80h - FFh)

00 = Bank 0 (00h - 7Fh)

Each bank is 128 bytes. For devices with only Bank0 and Bank1 the IRP bit is reserved, always maintain this bit clear.

Bit 4 TO: Time-out bit

1 = After power-up, CLRWDT instruction, or SLEEP instruction

0 = A WDT time-out occurred

Bit 3 PD: Power-down bit

1 = After power-up or by the CLRWDT instruction

0 = By execution of the SLEEP instruction

Bit2 Z: Zero bit

1 = The result of an arithmetic or logic operation is zero

0 = The result of an arithmetic or logic operation is not zero

Bit 1 DC: Digit carry/borrow bit (ADDWF ADDLW, SUBLW, SUBWF instructions) (for borrow the polarity sreversed)

1 = A carry-out from the 4th low order bit of the result occurred

0 = No carry-out from the 4th low order bit of the result


Bit 0 C: Carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)

1 = A carry-out from the most significant bit of the result occurred

0 = No carry-out from the most significant bit of the result occurred

Note:

For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF,RLF ) instructions, this bit is loaded with either the high or low order bit of the source register.

OPTION_REG Register

The OPTION_REG register is a readable and writable register which contains various control bits to configure the TMR0/WDT prescaler, the external INT Interrupt, TMR0, and the weak pull-ups on PORTB.

OPTION_REG Register

Bit 7 RBPU: PORTB Pull-up Enable bit

1 = PORTB pull-ups are disabled

0 = PORTB pull-ups are enabled by individual port latch values

Bit 6 INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of INT pin

0 = Interrupt on falling edge of INT pin

Bit 5 T0CS: TMR0 Clock Source Select bit

1 = Transition on T0CKI pin

0 = Internal instruction cycle clock (CLKOUT)


Bit 4 T0SE: TMR0 Source Edge Select bit

1 = Increment on high-to-low transition on T0CKI pin

0 = Increment on low-to-high transition on T0CKI pin

Bit 3 PSA: Prescaler Assignment bit

1 = Prescaler is assigned to the WDT

0 = Prescaler is assigned to the Timer0 module

bit 2-0 PS2:PS0 : Prescaler Rate Select bits

PCON Register

The Power Control (PCON) register contains flag bit(s), that together with the TO and PD bits, allows the user to differentiate between the device resets.

Note 1:

BOR is unknown on Power-on Reset. It must then be set by the user and checked on subsequent resets to see if BOR is clear, indicating a brown-out has occurred. The BOR status bit is a don't care and is not necessarily predictable if the brown-out circuit is disabled (by clearing the BODEN bit in the Configuration word).

Note 2:

It is recommended that the POR bit be cleared after a power-on reset has been

Detected, so that subsequent power-on resets may be detected.


PCON Register

Bit 7 MPEEN: Memory Parity Error Circuitry Status bit

This bit reflects the value of the MPEEN configuration bit.

Bit 6:3 Unimplemented: Read as '0'

Bit 2 PER: Memory Parity Error Reset Status bit

1 = No error occurred

0 = A program memory fetch parity error occurred

(must be set in software after a Power-on Reset occurs)

Bit 1 POR: Power-on Reset Status bit

1 = No Power-on Reset occurred

0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

Bit 0 BOR: Brown-out Reset Status bit

1 = No Brown-out Reset occurred

0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

Introduction

The analog-to-digital (A/D) converter module can have up to eight analog inputs for a device. The analog input charges a sample and hold capacitor. The output of the sample and hold capacitor is the input into the converter. The converter then generates a digital result of this analog level via successive approximation. This A/D conversion of the analog input signal, results in a corresponding 10-bit digital number.


The analog reference voltages (positive and negative supply) are software selectable to either the device’s supply voltages (AVDD, AVss) or the voltage level on the AN3/VREF+ and AN2/VREF-pins. The A/D converter has a unique feature of being able to operate while the device is in SLEEP mode.

The A/D module has four registers. These registers are:

• A/D Result High Register (ADRESH)

• A/D Result Low Register (ADRESL)

• A/D Control Register0 (ADCON0)

• A/D Control Register1 (ADCON1)

The ADCON0 register, shown in Figure 1, controls the operation of the A/D module. The ADCON1 register, shown in Figure 2, configures the functions of the port pins. The port pins can be configured as analog inputs (AN3 and AN2 can also be the voltage references) or as digital I/O.

10-bit A/D Block Diagram


Control Register


Register 1: ADCON0 Register

Bit 7:6 - ADCS1:ADCS0: A/D Conversion Clock Select bits

00= FOSC/2

01= FOSC/8

10= FOSC/32

11= FRC(clock derived from the internal A/D RC oscillator)

Bit 5:3 - CHS2:CHS0: Analog Channel Select bits

000= channel 0, (AN0)








Note:

For devices that do not implement the full 8 A/D channels, the unimplemented selections are reserved. Do not select any unimplemented channel.

Bit 2 - GO/DONE: A/D Conversion Status bit


When ADON = 1

1 = A/D conversion in progress (setting this bit starts the A/D conversion which is

automatically cleared by hardware when the A/D conversion is complete)

0 = A/D conversion not in progress

Bit 1 - Unimplemented:

Read as '0'

Bit 0 - ADON: A/D On bit

1 = A/D converter module is powered up

0 = A/D converter module is shut off and consumes no operating current

ADCON1 Register

Bit 7:6 Unimplemented: Read as '0'

Bit 5 - ADFM : A/D Result format select

1 = Right justified. 6 Most Significant bits of ADRESH are read as ’0’.

0 = Left justified. 6 Least Significant bits of ADRESL are read as ’0’.

Bit 4 Unimplemented: Read as '0'

Bit 3:0 PCFG3:PCFG0: A/D Port Configuration Control bits


Operation

The ADRESH: ADRESL registers contains the 10-bit result of the A/D conversion. When the A/D conversion is complete, the result is loaded into this A/D result register pair, the GO/DONE bit (ADCON0<2>) is cleared, and A/D interrupt flag bit, ADIF, is set. The block diagrams of the A/D module are shown in Figure. After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as inputs.

A/D Acquisition Requirements.

After this acquisition time has elapsed the A/D conversion can be started. The following steps should be followed for doing an A/D conversion:

1. Configure the A/D module:

• Configure analog pins / voltage reference/ and digital I/O (ADCON1)

• Select A/D input channel (ADCON0)

• Select A/D conversion clock (ADCON0)

• Turn on A/D module (ADCON0)

2. Configure A/D interrupt (if desired):

• Clear the ADIF bit

• Set the ADIE bit

• Set the GIE bit


3. Wait the required acquisition time.

4. Start conversion:

• Set the GO/DONE bit (ADCON0)

5. Wait for A/D conversion to complete, by either:

• Polling for the GO/DONE bit to be cleared or ADIF bit to be set

OR

• Waiting for the A/D interrupt

6. Read A/D Result register pair (ADRESH:ADRESL), clear the ADIF bit, if required.

7. For next conversion, go to step 1 or step 2 as required.

The Figure shown below shows the conversion sequence, and the terms that are used. Acquisition time is the time that the A/D module’s holding capacitor is connected to the external voltage level. Then there is the conversion time of 12 TAD, which is started when the GO bit is set. The sum of these two times is the sampling time. There is a minimum acquisition time to ensure that the holding capacitor is charged to a level that will give the desired accuracy for the A/D conversion.

A/D Conversion Sequence


Configuring Analog Port Pins

The ADCON1 and TRIS registers control the operation of the A/D port pins. The port pins that are desired as analog inputs must have their corresponding TRIS bits set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted.The A/D operation is independent of the state of the CHS2:CHS0 bits and the TRIS bits.

A/D Conversions

The Example shown below shows how to perform an A/D conversion for the PIC17C756. The PORTF and lower four PORTG pins are configured as analog inputs. The analog references (VREF+ and VREF-) are the device AVDD and AVSS. The A/D interrupt is enabled, and the A/D conversion clock is FRC. The conversion is performed on the AN0 pin (channel 0).Clearing the GO/DONE bit during a conversion will abort the current conversion. The A/D result register pair will NOT be updated with the partially completed A/D conversion sample. That is, the ADRESH:ADRESL registers will continue to contain the value of the last completed conversion (or the last value written to the ADRESH:ADRESL registers). After the A/D conversion is aborted, a 2TAD wait is required before the next acquisition is started. After this 2TAD wait, acquisition on the selected channel is automatically started.

A/D Conversion

A/D Result Registers

The ADRESH: ADRESL register pair is the location where the 10-bit A/D result is loaded at the completion of the A/D conversion. This register pair is 16-bits wide. The A/D module gives the flexibility to left or right justify the 10-bit result in the 16-bit result register. The A/D Format Select bit (ADFM) controls this justification. Figure below shows the operation of the A/D result justification.The extra bits are loaded with ‘0’s’. When an A/D result will not overwrite these locations (A/D disable), these registers may be used as two general purpose 8-bit registers.


A/D Result Justification

Operation During Sleep

The A/D module can operate during SLEEP mode. This requires that the A/D clock source be set to RC (ADCS1:ADCS0 = 11). When the RC clock source is selected, the A/D module waits one instruction cycle before starting the conversion. This allows the SLEEP instruction to be executed, which eliminates all internal digital switching noise from the conversion. When the conversion is completed the GO/DONE bit will be cleared, and the result is loaded into the ADRES register. If the A/D interrupt is enabled, the device will wake-up from SLEEP. If the A/D interrupt is not enabled, the A/D module will then be turned off, although the ADON bit will remain set. When the A/D clock source is another clock option (not RC), a SLEEP instruction will cause the present conversion to be aborted and the A/D module to be turned off (to conserve power),though the ADON bit will remain set.Turning off the A/D places the A/D module in its lowest current consumption state.

Effects of a Reset

A device reset forces all registers to their reset state. This forces the A/D module to be turned off, and any conversion is aborted.The value that is in the ADRESH:ADRESL registers is not modified for a Power-on Reset. TheADRESH:ADRESL registers will contain unknown data after a Power-on Reset.

A/D Initialization


Oscillator

The internal oscillator circuit is used to generate the device clock. The device clock is required for the device to execute instructions and for the peripherals to function. Four device clock periods generate one internal instruction clock (TCY) cycle.

There are up to eight different modes which the oscillator may have. There are two modes which allow the selection of the internal RC oscillator clock out (CLKOUT) to be driven on an I/O pin, or allow that I/O pin to be used for a general purpose function. The oscillator mode is selected by the device configuration bits. The device configuration bits are nonvolatile memory locations and the operating mode is determined by the value written during device programming. The oscillator modes are:

• LP Low Frequency (Power) Crystal

• XT Crystal/Resonator

• HS High Speed Crystal/Resonator

• RC External Resistor/Capacitor (same as EXTRC with CLKOUT)

• EXTRC External Resistor/Capacitor

• EXTRC External Resistor/Capacitor with CLKOUT

• INTRC Internal 4 MHz Resistor/Capacitor

• INTRC Internal 4 MHz Resistor/Capacitor with CLKOUT

These oscillator options are made available to allow a single device type the flexibility to fit applications with different oscillator requirements. The RC oscillator option saves system cost while the LP crystal option saves power. Configuration bits are used to select the various options.


Oscillator Configurations

Oscillator Types

Mid-Range devices can have up to eight different oscillator modes. The user can program up to three device configuration bits (FOSC2, FOSC1 and FOSC0) to select one of these eight modes:

• LP Low Frequency (Power) Crystal

• XT Crystal/Resonator

• HS High Speed Crystal/Resonator

• RC External Resistor/Capacitor (same as EXTRC with CLKOUT)

• EXTRC External Resistor/Capacitor

• EXTRC External Resistor/Capacitor with CLKOUT

• INTRC Internal 4 MHz Resistor/Capacitor

• INTRC Internal 4 MHz Resistor/Capacitor with CLKOUT

The main difference between the LP, XT, and HS modes is the gain of the internal inverter of the oscillator circuit which allows the different frequency ranges. Tables give information to aid in selecting an oscillator mode. In general, use the oscillator option with the lowest possible gain which still meets specifications. This will result in lower dynamic currents (IDD).

The frequency range of each oscillator mode is the recommended (tested) frequency cutoffs, but the selection of a different gain mode is acceptable as long as a thorough validation is performed (voltage, temperature, component variations (Resistor, Capacitor, and internal microcontroller oscillator circuitry)).

The RC mode and the EXTRC with CLKOUT mode have the same functionality. They are named like this to help describe their operation vs. the other oscillator modes.

Selecting the Oscillator Mode for Devices with FOSC1:FOSC0



CONCLUSION

The project titled “WIRELESS BASED POWER LINE BREAKAGE MONITORING" is successfully working. I believe it’s satisfied to all.

I hope this project is very useful for vehicles. And also I gain more knowledge about this field work.

This project is based with microcontroller so it is very helpful in all section. Being a microcontroller based system; it has got the following features.

(1) High Accuracy and Precision(2) Economic & Less Power consumption.

The major advantage of using microcontroller is the resulting flexibility and speed of operation.

The software developed is sufficiently simple with a few peripheral chips. Moreover the hardware supported by the software is simpler and therefore inexpensive.

Thus the all above details regarding this project is user friendly device.


BIBLIOGRAPHY

1. Let Us C – Yashwanth Kanetkar

2. Op-Amps & Linear Ic’s – Ramakant A. Gayakwad

3 Wayne Wolf, Computers as Components: Principles of Embedded Computer SystemDesign, San Francisco: Morgan Kaufman, 2000.

4 Giovanni De Micheli and Rajesh Gupta, "Hardware-software co-design," Proceedings of the IEEE, 85(3), March, 1997, pp. 349-365.

5 Rolf Ernst, "Codesign of embedded systems: status and trends," IEEE Design and Test of Computers, 15(2), April/May/June 1998, pp. 45-54.

6 Chang Yun Park and Alan C. Shaw, “Experiments with a program timing tool based on source-level timing scheme,” IEEE Computer, 24(5), May, 1991, pp. 48-57.

7 Integrated Circuits – K.R.Botkar

Websites Addresses

www.national.com www.analog.com www.microchip.com www.sparktech.org

http://www.Microchip.com/

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