Project GoalsProject Goals

1.1. Get to knowGet to know • Quartus • SoPC builder environment

2.2. Stream Stream Video

3.3. Build Build foundation for part B- Tracking system

Project StagesProject Stages

1.1. ConfigureConfigure the system using SoPC builder

2.2. Create Create embedded software

3.3. GenerateGenerate system input using USB

4.4. Display Display video

USB BasicsUSB Basics

HostHost

1.1. Detect Detect Attachment/RemovalAttachment/Removal

2.2. Manage Manage Control flowControl flow

3.3. Manage Manage Data FlowData Flow

DeviceDevice

1.1. Respond Respond to Requeststo Requests• StatusStatus• DataData

Isochronous TransferIsochronous Transfer

1.1.High priorityHigh priority

2.2.Low latencyLow latency

3.3.No Resend on ErrorNo Resend on Error

System System ArchitectureArchitecture

Referenced ArchitectureReferenced Architecture

1.1. Tal Rath and Eyal Enav Tal Rath and Eyal Enav

• Configuration:Configuration: NIOS II USBNIOS II USB Jungo configurationJungo configuration

2.2. DE2 demonstrationsDE2 demonstrations

Our DesignOur Design

• Data flow Data flow inside the System inside the System • InputInput from file from file• StreamingStreaming format format

Video StreamerVideo Streamer

12...

10221

Packet Number Packet Data

USB

38 Packets per frame

Packet ArrivalPacket Arrival

SoftwareSoftware

TIMELINETIMELINE

TIM

TIMEE

Why DMAWhy DMA??

• CPU can perform data transfers…CPU can perform data transfers…

… … but then it won’t be available for anything but then it won’t be available for anything else…else…

• The DMA allows us to transfer data from one The DMA allows us to transfer data from one place to another without making use of the place to another without making use of the CPU.CPU.

Direct Memory AccessDirect Memory Access

• DMA receives:DMA receives:– SourceSource– DestinationDestination– Amount of data to transferAmount of data to transfer

DMA USB INTERFACEDMA USB INTERFACE

USBDATAPORT

PC sends a packet

System receives INT

DMA starts transfer

System awaits next INT

Transfer finishes

SRAM VGA INTERFACESRAM VGA INTERFACE

Access CollisionAccess Collision

System with fifoSystem with fifo

Transmission Transmission donedone

Reception doneReception doneDMA streaming DMA streaming FIFOFIFO

Selected DesignSelected Design

Pixel FormatPixel Format

•Data Bytes per packet = 1022Data Bytes per packet = 1022•Bytes per pixel = 2Bytes per pixel = 2•Pixel per packet = 1022/2 = 511Pixel per packet = 1022/2 = 511

2424 vs 16 bit RGBvs 16 bit RGB

24 bit RGB 16 bit RGB

Tools and DebugTools and Debug

1.1. Quartus II Quartus II – Signal tap.

2.2. Model Sim Model Sim – for design verification

3.3. Logic analyserLogic analyser

4.4. Nios II IDENios II IDE

5.5. Hex EditorHex Editor

6.6. Microsoft Visual StudioMicrosoft Visual Studio

TroubleshootingTroubleshooting

1.1. Quartus Quartus • Version related issues• USB Drivers

2.2. Model SimModel Sim

3.3. Nios II IDE Nios II IDE • SoPC builder environment

VGA signals in SignalVGA signals in Signal taptap

VGA signals in ModelSimVGA signals in ModelSim

LogicLogic AnalizerAnalizer

• Digital Scope• Memory

Hex Editor NeoHex Editor Neo

Nios II IDE Memory viewNios II IDE Memory view

Microsoft Visual studio 2005Microsoft Visual studio 2005

Memory considerationsMemory considerations

• 0.5 MB SRAM is not enough for possible extended image resolution (640x480).

• 8 MB of SDRAM will be enough for:160x120x3x3 = 172,800 Bytes which is the current plan.

SummerySummery

MilestoneStatus

Learn SOPC environment (Quartus,Nios II IDE,SOPC builder ect.)

Done

Evaluate different VGA architecturesDone

Evaluate different DMA configurationsDone

Ramp up on USB 1.1 protocolDone

Create interrupt driven software architectureDone

Create internal protocol for streaming videoDone

Integration of different projects and platformsDone

Evaluate alternative architectures for Steaming video system

Done

2.Algorithm

•Motion image computation•Mass center computation•Prediction of next mass center (Kalman filter or more simple algorithm)