EGG GOBBLER for t-PadGuide: Dr. Hameed Mahmoodi
Team members: Phaneendra Korrapati (912037976) Saran Srivatsas tenneti (911455927)
In the modern day, embedded systems find a lot of applications in cell phones, computers and other electronic gadgets. With the advent of smart phones which can perform multiple and brilliant operations using touch interfacing the need of more faster and more-memoryholding embedded systems are being researched on. In that point of view DE2-115 with its specifications, touch interfacing ability and larger memory holding capacity than its predecessor is worth being researched on. Taking that into considerations, we intend to demonstrate the game EGG GOBBLER programmable on a DE2-115 FPGA and implement it on the t-Pad of this FPGA. We create the required layout of the game using C programming and realize the game on tPad using hardware assembly language, in this case Verilog coding.
INTRODUCTIONWe basically got the idea of our game from an already developed and popular game called PACMAN. We create a map using c programming and include some walls randomly in the game. There are a number of dots (eggs) designed all around the map. The Gobbler is supposed to move around map trying to eat the eggs scoring a point for eating each egg. The controls to move gobbler within the map are located on the screen just below the map. This controls system uses the touch interface function of the FPGA. When all the eggs available in the map are eaten then the game is WON. In a game usually there is also a losing criterion. In the actual PACMAN there is a ghost that chases after the PACMAN and PACMAN should constantly evade the ghost. When the ghost catches up with PACMAN, the game is lost. But in this version, the egg gobbler, we used different criteria for losing. We used the walls in the map and programmed them such a way that, whenever the gobbler hits a wall the game is over/lost. We also added a reset button and the score update in one of the corners of the t-Pad.
We used Quartus II tool provided by the Altera to design and implement the hardware for our project. We used the different IP`s provided by Altera in SOPC building and using hardware assembly language we generated a Verilog code to run the hardware for our project. The following is the block diagram of our hardware.
The block diagram gives an idea of the different IPs we used in building the SOPC for our project. A phase locked loop (pll) is used to generate the required clock function for the wholse system. In this system a 100Mhz clock for the Nios-II/f have been used, another 100Mhz with -65 phase shift is used to clock the SDRAM in addition to the required 40Mhz clock for the VGA controller. In the above block diagram we can see the bus flow for the output. The important hardware aspect of this project is the touch interface we used.
The three core functions that we used in the SOPC building are3
1) Touch_panel_spi 2) Touch_panel_busy 3) Touch_panel_penirq_n
SOFTWARE LAYOUT The software layout for our project is very simple. Initially we created map, then created the walls raondomly placed inside the map and created dots all along the map. Then the gobbler is created and we then constructed the programme such that the gobbler moves in the map controlled by the control commands placed in the bottom corner of the t-Pad user interface. The below figure shows the layout of the game on the t-Pad.
As you can see from the picture, the map and walls are created then the gobbler, then the controls to move the gobbler then the reset button to set the game to the starting point. And the score update is also placed at the bottom left of the t-Pad.
The above picture shows how it looks on the t-Pad when the gobller is being navigated within the map. With each egg the gobbler eats the score updates by one point. At any point of time, when you press the reset button the game is set back to the starting point. The display when the game is won (when all the eggs are gobbled up) and when the game is lost (when the gobbler hits any wall) are shown in the next two pictures.
The function flowchart of the software is shown in the below diagram.
The HAL (Hybrid Abstract language) we used in the SOPC are: 1) Alt_touchscreen_get_pen 2) Alt_video_display_clearscreen 3) Alt_vid_print_string_alpha 4) vid_draw_circle 5) Alt_video_display_regsiter_written_buffer
CONCLUSION Thus, with all the specifications successfully installed and after a successful demonstration we conclude our project. Through this project we were introduced to the FPGA and we are now well educated on working on this DE2-115 t-Pad. ACKNOWLEDGEMENTS We would like to thank out professor who have been very supportive troughout the project and encouraged with new ideas all the time. We would also like to extend our thanks to our classmate and good friend Gibin G Thallapillil who has been very supportive and helpful throughout the project.
HARDWARE ASSEMBLY CODE
References:1) ftp://ftp.altera.com/up/pub/Altera_Material/11.0/Tutorials/Schematic/Quartus_II_ Introduction.pdf 2) http://www.altera.com/education/univ/software/quartus2/unv-quartus2.html? GSA_pos=3&WT.oss_r=1&WT.oss=DE2-115 3) ftp://ftp.altera.com/up/pub/Altera_Material/11.0/Tutorials/Nios2_introduction.pdf 4) ftp://ftp.altera.com/up/pub/Altera_Material/11.0/Tutorials/Altera_Monitor_Progra m.pdf
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