HOME SECURITY SYSTEM

ByMonika Dudek and Norbert Glod

ECE 345

T.A. Ajaj Patel

May 1, 1999

Project Number 33

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ABSTRACT

The goal of this project was to build a home security system. The system was designed to

protect small residential areas, such as apartments and houses. The unit features two separate safety

arrangements. The doors and windows are protected using standard normally closed sensors. Valuable

items are secured by a wire loop system similar to that used in the computer labs. This part of the design

uses a cable that is threaded through the items to be protected, and the alarm triggers if the wire becomes

open-circuited. The loop system can be used independently from the entry/exit system. The design

features four NE555 timers that provide the warning entry and exit delays, the main alarm timing, and

the oscillation signal. The alarm states are indicated by the status LED that flashes during entry/exit

delay periods and remains on after the alarm has been triggered.

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TABLE OF CONTENTS

PAGE

INTRODUCTION…………………………………………………………. 1

DESIGN PROCEDURE AND DETAILS…………………………………. 5

DESIGN VERIFICATION………………………………………………… 10

COSTS……………………………………………………………………... 11

REFERENCE………………………………………………………………. 14

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INTRODUCTION

The alarm system is designed as a basic security system for small residential areas, such as

condominiums and houses. It may be installed without drilling or attaching it to the building, which

could be an advantage in rented accommodation. The unit features two separate protection arrangements.

The entry and exit to the apartment are protected using standard normally closed sensors such as

magnetic switches, but this design features wire contact. Entry and exit delays are independently set to

15 s, during which time a warning sounder operates and a status LED flashes.

Monolithic timers [1] (NE555) serve an important function in the design (Fig. 1.). Monostable

timers produce accurate time delays.

Fig. 1. Monostable timer circuit.

In the monostable mode, a capacitor and a single resistor are used for the timing network. Both the

threshold terminal and the discharge terminal are connected together in this mode. When the input

voltage to the trigger comparator falls below 1/3Vcc, the comparator output triggers the flip-flop so that

its output sets low. This turns the capacitor discharge transistor “off” and drives the digital output to the

high state. This condition allows the capacitor to charge at an exponential rate, which is set by the RC

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time constant. When the capacitor voltage reaches 2/3 Vcc, the threshold comparator resets the flip-flop.

This action discharges the timing capacitor and returns the digital output to the low state. Once the flip-

flop has been triggered by an input signal, it can not be retriggered until the present timing period has

been completed. The time that the output is high is given by the equation:

Various combinations of R and C and their associated times are shown in Fig. 2 [1].

Fig. 2. Time delay.

A reset pin is provided to discharge the capacitor, thus interrupting the timing cycle. As long as

the reset pin is low, the capacitor discharge transistor is turned on and prevents the capacitor from

charging. While the reset voltage is applied the digital output will remain the same.

An astable mode of the timer is used to create an oscillating signal. In the astable mode the timer

is connected so that it will retrigger itself and cause the capacitor voltage to oscillate between 1/3Vcc and

2/3Vcc (Fig. 3) [1].

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Fig. 3. Astable circuit.

The external capacitor charges to 2/3 Vcc through RA and RB and discharges to 1/3 Vcc through RB. By

varying the ratio of these resistors the duty cycle can be varied. The charge and discharge times are

independent of the supply voltage. The frequency of oscillation and the duty cycle are given by the

following equations:

The frequency of oscillation can be easily found from Fig. 4 [1].

Fig. 4. Free running frequency.

The second part of the design is a wire loop system, similar to that used in shops and computer

labs, that protects the valuable items. A wire is threaded through the items to be protected, and the alarm

is triggered immediately if either connection becomes an open circuit. The loop system can be used

independently from the entry and exit system. This can be useful if a computer lab needs to be accessible

to students, while still providing protection for valuable equipment.

The main alarm sounding period is limited to about 12 min, but the status LED remains on after

this period to indicate that the alarm has been triggered. An optional relay output could be connected to

an external sounder or alarm system.

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Referring to the block diagram (Fig. 5), the loop input and entry/exit input are both followed by

latches that hold the alarm state even if the input reverts to normal. Setting the toggle switch to the loop

only position disables the entry/exit latch. The loop latch operates the alarm timer immediately. The

entry/exit latch triggers the entry timer which drives the warning sounder. If the unit is not switched off

by the end of the entry timer period, the alarm timer is operated. When the unit is switched on, the

power-on reset circuit triggers the exit timer. During this period the two latches are cleared and the

warning sounder operates. If the loop is not connected correctly the exit timer will not operate. The

status LED flashes while the warning sounder is operating, and is lit steadily when the alarm is or has

been sounding.

Fig. 5. Block diagram.

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DESIGN PROCEDURE AND DETAILS

The project is divided into five different sub-circuits: power-on/exit timer circuit, loop input

circuit, entry input/timer circuit, alarm timer/switch and the warning sounder/LED.

The loop input and latch are shown in Fig. 6.

Fig. 6. Loop input and latch.

The far end of the loop is terminated by resistor R5 which, when the loop is connected forms a potential

divider with R4 to give a voltage equal to half the power supply voltage on pins 2 and 6 of the op-amp

(U1:A and U1:B). C1 removes any noise that may be picked up along the loop wire. U1:A and U1:B

form a window comparator [2]. R1, R2 and R3 set the top and bottom ends of the acceptance range.

With the 12V-power supply the voltage on pin 3 of U1:A is about 6.5V and that on pin 6 of U1:B is

about 5.5V. If the voltage from the loop potential divider should become outside this range, the

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appropriate output of U1 goes low, giving a high level on pin 4 of U2:B. U3:C and U3:D form an SR

(Set-Reset) latch. The SR latch operations are shown in Fig. 7 [3].

Fig. 7. SR latch.

The exit delay timer clears the latch when the unit is switched on. If the output of U2:B goes high, even

momentarily, the latch will change state, triggering the alarm.

The power on reset circuit and exit timer is shown in Fig. 8.

Fig. 8. Power on and exit timer.

When the unit is switched on C15 will be discharged, holding the inputs of U6:A high. C15 will charge

through R19 within half a second. The output of U6:A will therefore be low for a brief period when the

unit is switched on, giving a suitable signal to trigger the exit timer-Timer 1, and reset the entry and

alarm timers. The device used for U6:A has Schmitt trigger inputs to give reliable operation with an

input signal that does not conform to digital levels. U6:D inverts the signal from the loop input, so that

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the exit timer is held reset and therefore disabled, if the loop is not connected. R16 and C11 set the exit

period to 15 s.

The entry/exit input is shown in Fig. 9.

Fig. 9. Entry/exit timer.

In the normal state, pin 1 and pin 2 of U2:A are held high by the normally closed sensors. If one of the

sensors on the normally closed circuit operate, pin 1 or pin 2 is taken low by either R13 or R12

respectively. Either of the sensors is able to trigger the alarm. C6 and C7 remove any noise, which may

be picked up along these connections. U3:A and U3:B form a latch, which operates in the same manner

as that used for the loop input. The active-low loop only signal on pin 12 of U2:D comes from the

toggle switch. When the line is low it prevents the signal from the latch from reaching the entry timer-

Timer2. The timer is triggered by the negative going output of U2:D. R3 and C10 set the entry delay

period to 15 s. The output on pin 3 of the timer is high during the entry delay period. U7:B gates the

signal from U2:D and the timer to give an output that is high when the entry latch has operated and the

entry timer has timed out. R20 and C12 provide a very short delay to compensate for propagation delay

of U5:A.

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The alarm timer and output are shown in Fig. 10.

Fig. 10. Alarm timer.

When either the entry alarm or loop alarm line goes high, the output of U7:A goes low, triggering the

alarm timer-Timer3. The value of R7 and C3 give a calculated time period of 12 min., although in

practice this may be a minute or two longer due to the small leakage current in C3. Even in this case the

alarm period will be less than 15 min. During the alarm period, Q1 is turned on, driving the alarm

sounder. D1 protects the transistor from the back-EMF. The 12V-power supply is connected to the

toggle switch. When the toggle switch is set to the loop-entry/exit setting power is connected to circuit

through D2 and the active low loop only line is taken high through D3. When the toggle switch is set to

the loop only setting the active low loop only line is low.

The warning sounder circuit is shown in Fig. 11.

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Fig. 11. Warning sounder oscillator.

During the entry and exit periods the output of U7:C will be low. This is inverted by U6:C giving a high

level to the reset of the oscillating timer-Timer4. The external capacitor C13 charges through R15 and

R17 and discharges through R17 only. Thus the duty cycle may be precisely set by the ratio of these two

resistors. In the oscillatory mode of operation, C13 charges and discharges between 1/3Vcc and 2/3 Vcc.

The charge and discharge times and therefore frequency are independent of the supply voltage. The

output of the oscillating timer and the alarm timer signals enter U7:D Fig. 12.

Fig. 12. LED

An LED [4] is a semiconductor diode designed to emit light when forward biased. Since it is a diode,

voltage polarity must be observed in its use. The LED flashes during the exit and entry period, and lights

steadily when the alarm is (or has been) triggered. In the normal operating state it remains off.

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DESIGN VERIFICATIONS

The testing involves checking the various functions of the unit. Setting the switch to the loop

and entry/exit position the LED should flash and the warning sounder should beep in time with it, for

about 15 s. After this time the sounder should be quiet and the LED should be off. At this point the unit

is armed. When either of the normally closed sensors is activated the warning sounder and LED should

operate for 15 s. After this time the main alarm sounder starts and the LED remains on. When the

system is reset and the same function is chosen, but instead of activating the entry/exit sensors the loop is

open circuited, the alarm sounder operates immediately. At this point if the exit/entry and loop function

is chosen again without reconnecting the loop cable the exit delay operates, but the LED remains on

(doesn’t flash) indicating that something is wrong. Switching the unit to loop only, the exit delay

operates. Activating the normally closed sensors has no affect on the main alarm. By unplugging the

loop wire the main alarm timer is triggered.

Besides functionality testing the following timer specification tests were performed: time delay,

frequency of oscillation, and the duty cycle of the astable mode of operation. The theoretical time delay

for the exit and entry timers is:

Time delay=1.1RC=1.1*300kΩ*47uF=15.51 s.

The experimental value obtained was 16 s, which resulted in an error of 3%. The theoretical length of

operation for the alarm timer, obtained using the above equation, is 12.1 min. The experimental value

measured was 12.5 min., which resulted in an error of 3%. The theoretical frequency of operation of the

astable mode timer is given by the following equation:

frequency=1.44/((R1+2R2)C1)=1.44/((100 kΩ+2*22 kΩ)4.7uF)=2.13 Hz.

The observed frequency was 1.9 Hz, which resulted in an error of 10%. The duty cycle is given by:

D=R2/(R1+2*R2)=22 kΩ/(100 kΩ+2*22 kΩ)=0.15.

The measured duty cycle was 0.17 and the resulting error was 13%.

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COSTS

The parts list:

PART NUMBER DESCRIPTION QUANTITY TOTAL COST

R1,3-5,12,13,15,18 100kΩ Resistor 8 $1.15

R2,10,17 22kΩ Resistor 3 $0.45

R6,14,20,22 10kΩ Resistor 3 $0.45

R7 3MΩ Resistor 1 $0.15

R8 4kΩ Resistor 1 $0.15

R9 220kΩ Resistor 1 $0.15

R19 1MΩ Resistor 1 $0.15

R20 1kΩ Resistor 1 $0.15

R16,21 330kΩ Resistor 2 $0.30

C1,2,4,6-9,14,16 Ceramic Plate

Capacitor

8 $3.20

C3 220uF Radial Capacitor 1 $0.50

C5 10uF Radial Capacitor 1 $0.50

C10,11 47uF Radial Capacitor 2 $0.80

C12 100pF Ceramic Plate

Capacitor

1 $0.40

C13 4.7uF Radial Capacitor 1 $0.40

C15 100nF Disc Ceramic

Capacitor

1 $0.50

U1 LM747CN Dual Op- 1 $1.50

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Amp

U2,6 4093 Quad NAND 2 $1.00

U3,7 4001 Quad NOR 2 $1.50

U4 NE555 Timer 4 $12.00

Q1 TIP31 Transistor 1 $1.40

D1,2 IN4001 Diode 2 $0.50

D3,5-7 IN4003 Diode 4 $1.20

D4 Red LED 1 $0.25

Toggle Switch 1 $2.50

Piezo Siren 2 $6.00

House Model $20.00

Table 1. Cost analysis.

The total cost of parts was calculated to be $57.25. The total hours worked on the project amounted to

50 hrs per person. The estimated salary was $25 per h. The following formula was used to calculate the

labor cost:

Labor cost=hourly rate*actual hours spent*2.5=$6,250.

The grand total was $6,307.25.

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CONCLUSION

The design was completed successfully and all the functions worked properly. However, no

alarm system is 100% secure and completely resistant to any attempt to defeat it, and this unit is

certainly no exception. The alarm system however, should be adequate in most cases. The main

concern is to prevent the unit from being triggered and normally this would involve trying to bypass the

loop, close to the alarm unit, so that it may be disconnected. The system operates by sensing the

resistance of the terminating resistance through the loop. This resistance need not be a single

component at the far end; it could be made up of a number of resistors along the loop.

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REFERANCE

1. “General purpose bipolar timers,” July 1998, http://www.natioanal.com/ds/LM/LM555.pdf.

2. D. A. Neamen, Electronic Circuit Analysis and Design. New York: McGraw-Hill, 1996, pp. 890-

892.

3. M. M. Moris, Computer Engineering Hardware Design. New Jersey: Prentice Hall, 1990,

pp.214-217.

4. R. B. Uribe, ECE 249 Laboratory. Urbana-Champaign, 1998, pp.37-38.

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