12

First StageDesign of CTAT & PTATSoftware used: Virtuoso Technology used: cadence umc13mmrf

CTAT (Complimentary to absolute temperature):When we apply a constant current to a diode then as temperature vary voltage across diode change that can be derived from below equation:As diode equation: ; ; ; ;Derivative of with respect to temperatureGives follow:;;;But ideal slope for diode is -1.6mV/k where derived slope is different because of various different Vd values. So we can understand, feeding constant current to diode it behaves like CTAT.Schematic for simulation of CTAT-1:

Figure-1

Results of CTAT:Figure-2

PTAT (Proportional to absolute temperature):Next target to design PTAT:As we know can be used for PTAT; ;But From this equation, we have to cancel ln(Id/Is) to make PTAT. How can we make this we have to use more diode in parallel feed same current as we do CTAT. ; ; ;Vd is the voltage across parallel connected diode. ; ; ; It is PTAT. Here ln (n) is constant.Schematic of PTAT-2:Figure-3R0R1

Now we have to make vd1 & vd2 same; for same, we have add R0. We know current from ctat schematic there we have feed a constant current source of 5 uA & n=2;So we Ro=4.98K ohmsTo make vd2 and vd1 equal I have used current mirror shown in above figureHere I have put w/l ratio same of both stages. As per properties of current the voltage vd1 and vd2 will be equal. The Result for Vd1 and Vd2:Figure-4

Result PTAT with respect to temperature:

Figure-5

As per result the slope of ctat and ptat:CTAT:Slope =-1.75mV/K,PTAT:Positive = +82 uV/k, To get constant reference voltage, I have to add them both CTAT & PTAT. for we have to connect in series as designed in second stage. But both slope are different to nullify the effect of temperature variation we have increase PTAT slope value.;From this, we have calculated R1=150 Kohm;

Second StageDesign of BGVR with current mirrorSpecification:R05.2K ohm

R1150K ohm

N.MOS W20 u M

N.MOS L5 u M

P.MOS,W20 u M

P.MOS L5 u M

Vdc3.3V

I have chosen same ration of (W/L) of both P.MOS and N.MOS because of current mirror. We have to feed same current to PTAT and CTAT branch so we get same vd1 and vd2. R0R1Figure-6

Here both CTAT & PTAT are connected in series to cancel any variation. Schematic-3:

Result with respect to temperature:As per DC analysis, I have chosen temperature range from -40 to 125 degree Celsius. Output is VD3. We can see variation in Vd3 (output) 5mV for temperature variation from-40 to 125 degree in below figure of simulation.

Figure-7

Result with respect to supply voltage variation:Here Vd3 output, Vdc (net15) variation from 0 to 4 V. After 1.3 V of Vdc all P-Mos and N-mos get entered to saturation region and Vd3 became constant .

Supply variation from 0 to 4V-net 15(plot)After this region all P mos and N mos enter saturation regionVd3 (output)-Vd3 (plot)Figure-8

Third StageDesign of BGVR with cascode current mirrorR05.2K ohm

R1150K ohm

N.MOS W20 u M

N.MOS L5 u M

P.MOS,W20 u M

P.MOS L5 u M

Vdc3.3V

Specification: As per our above result, we need little improvement. We have to feed same current to CTAT and PTAT. For same, we have used cascode current mirror. So we can expect good result from this circuit.Schematic -4:Figure-9

Result with respect to temperature (-40 to 125 degree):Figure-10

As per above figure, we get variation (between maxima-minima) in Vd3 (output) 3 mV much better than the previous current mirror result.Figure-11

Result with respect to supply voltage variation:

Figure-12

Supply variation from 0 to 4V-net 15(plot)Vd3 (output)-Vd3(plot)

Conclusion:As we can see from above results the cascode current mirror provide the better result compare to simple current mirror. But in cascode structure we have low output voltage but we got 5mV variation in simple current mirror & 3mV in cascode. So cascode is more suitable for BGVR.References:1. AIC class notes & Razavi (design of analog CMOS integrated Circuits).2. http://aries.ucsd.edu/NAJMABADI/CLASS/ECE102/12-F/NOTES/ECE102_F12-LecSet-6.pdf3. http://www.google.co.in/patents/US5053640