CY8C24223A, CY8C24423A PSoC ® Programmable System-on-Chip™ Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document Number: 3-12029 Rev. *E Revised December 11, 2008 Features ■ Powerful Harvard Architecture Processor ❐ M8C Processor Speeds to 12 MHz ❐ 8x8 Multiply, 32-Bit Accumulate ❐ Low Power at High Speed ❐ 4.75V to 5.25V Operating Voltage ❐ Extended Temperature Range: -40°C to +125°C ■ Advanced Peripherals (PSoC Blocks) ❐ Six Rail-to-Rail Analog PSoC Blocks Provide: • Up to 14-Bit ADCs • Up to 9-Bit DACs • Programmable Gain Amplifiers • Programmable Filters and Comparators ❐ Four Digital PSoC Blocks Provide: • 8 to 32-Bit Timers, Counters, and PWMs • CRC and PRS Modules • Full-Duplex UART • Multiple SPI™ Masters or Slaves • Connectable to all GPIO Pins ❐ Complex Peripherals by Combining Blocks ■ Precision, Programmable Clocking ❐ Internal ± 4% 24 MHz Oscillator ❐ High Accuracy 24 MHz with Optional 32 kHz Crystal and PLL ❐ Optional External Oscillator, up to 24 MHz ❐ Internal Oscillator for Watchdog and Sleep ■ Flexible On-Chip Memory ❐ 4K Bytes Flash Program Storage 100 Erase/Write Cycles ❐ 256 Bytes SRAM Data Storage ❐ In-System Serial Programming (ISSP) ❐ Partial Flash Updates ❐ Flexible Protection Modes ■ Programmable Pin Configurations ❐ 25 mA Sink on All GPIO ❐ Pull Up, Pull Down, High Z, Strong, or Open Drain Drive Modes on All GPIO ❐ Up to Ten Analog Inputs on GPIO ❐ Two 30 mA Analog Outputs on GPIO ❐ Configurable Interrupt on All GPIO ■ Additional System Resources ❐ I 2 C™ Slave, Master, and Multi-Master to 400 kHz ❐ Watchdog and Sleep Timers ❐ User-Configurable Low Voltage Detection ❐ Integrated Supervisory Circuit ❐ On-Chip Precision Voltage Reference ■ Complete Development Tools ❐ Free Development Software (PSoC Designer™) ❐ Full-Featured, In-Circuit Emulator and Programmer ❐ Full Speed Emulation ❐ Complex Breakpoint Structure ❐ 128K Bytes Trace Memory DIGITAL SYSTEM SRAM 256 Bytes Interrupt Controller Sleep and Watchdog Multiple Clock Sources (Includes IMO, ILO, PLL, and ECO) Global Digital Interconnect Global Analog Interconnect PSoC CORE CPUCore (M8C) SROM Flash 4K Digital Block Array Multiply Accum. Internal Voltage Ref. Digital Clocks POR and LVD System Resets Decimator SYSTEM RESOURCES ANALOG SYSTEM Analog Ref Analog Input Muxing I 2 C (1 Row, 4 Blocks) Port 2 Port 1 Port 0 Analog Drivers System Bus Analog Block Array (2 Columns, 6 Blocks) Logic Block Diagram [+] Feedback
Transcript
CY8C24223A, CY8C24423A
PSoC® Programmable System-on-Chip™
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600Document Number: 3-12029 Rev. *E Revised December 11, 2008
Features■ Powerful Harvard Architecture Processor
❐ M8C Processor Speeds to 12 MHz❐ 8x8 Multiply, 32-Bit Accumulate❐ Low Power at High Speed❐ 4.75V to 5.25V Operating Voltage❐ Extended Temperature Range: -40°C to +125°C
■ Advanced Peripherals (PSoC Blocks)❐ Six Rail-to-Rail Analog PSoC Blocks Provide:
• Up to 14-Bit ADCs• Up to 9-Bit DACs• Programmable Gain Amplifiers• Programmable Filters and Comparators
❐ Four Digital PSoC Blocks Provide:• 8 to 32-Bit Timers, Counters, and PWMs• CRC and PRS Modules• Full-Duplex UART• Multiple SPI™ Masters or Slaves• Connectable to all GPIO Pins
❐ Complex Peripherals by Combining Blocks
■ Precision, Programmable Clocking❐ Internal ± 4% 24 MHz Oscillator❐ High Accuracy 24 MHz with Optional 32 kHz Crystal and PLL❐ Optional External Oscillator, up to 24 MHz❐ Internal Oscillator for Watchdog and Sleep
■ Flexible On-Chip Memory❐ 4K Bytes Flash Program Storage 100 Erase/Write Cycles❐ 256 Bytes SRAM Data Storage❐ In-System Serial Programming (ISSP)❐ Partial Flash Updates❐ Flexible Protection Modes
■ Programmable Pin Configurations❐ 25 mA Sink on All GPIO❐ Pull Up, Pull Down, High Z, Strong, or Open Drain Drive
Modes on All GPIO❐ Up to Ten Analog Inputs on GPIO❐ Two 30 mA Analog Outputs on GPIO❐ Configurable Interrupt on All GPIO
■ Additional System Resources❐ I2C™ Slave, Master, and Multi-Master to 400 kHz❐ Watchdog and Sleep Timers❐ User-Configurable Low Voltage Detection❐ Integrated Supervisory Circuit❐ On-Chip Precision Voltage Reference
■ Complete Development Tools❐ Free Development Software (PSoC Designer™)❐ Full-Featured, In-Circuit Emulator and Programmer❐ Full Speed Emulation❐ Complex Breakpoint Structure❐ 128K Bytes Trace Memory
DIGITAL SYSTEM
SRAM256 Bytes
InterruptController
Sleep andWatchdog
Multiple Clock Sources(Includes IMO, ILO, PLL, and ECO)
Global Digital InterconnectGlobal Analog Interconnect
PSoC® Functional OverviewThe PSoC® family consists of many Mixed-Signal Array withOn-Chip Controller devices. These devices are designed toreplace multiple traditional MCU-based system components withone, low cost single-chip programmable device. PSoC devicesinclude configurable blocks of analog and digital logic, andprogrammable interconnects. This architecture allows the userto create customized peripheral configurations that match therequirements of each individual application. Additionally, a fastCPU, Flash program memory, SRAM data memory, andconfigurable IO are included in a range of convenient pinouts andpackages.The PSoC architecture, as shown in the Logic Block Diagram onpage 1, is comprised of four main areas: PSoC Core, DigitalSystem, Analog System, and System Resources. Configurableglobal busing allows all the device resources to be combined intoa complete custom system. The PSoC automotive CY8C24x23Agroup can have up to three IO ports that connect to the globaldigital and analog interconnects, providing access to 4 digitalblocks and 6 analog blocks.
PSoC CoreThe PSoC Core is a powerful engine that supports a rich featureset. The core includes a CPU, memory, clocks, and configurableGPIO (General Purpose IO).The M8C CPU core is a powerful processor with speeds up to 12 MHz, providing a two MIPS 8-bit Harvard architecturemicroprocessor. The CPU uses an interrupt controller with 11vectors, to simplify programming of real time embedded events.Program execution is timed and protected using the includedSleep and Watch Dog Timers (WDT).Memory includes 4 KB of Flash for program storage and 256bytes of SRAM for data storage. Program Flash uses fourprotection levels on blocks of 64 bytes, allowing customizedsoftware IP protection.The PSoC device incorporates flexible internal clock generators,including a 24 MHz IMO (internal main oscillator) accurate to 4%over temperature and voltage. A low power 32 kHz ILO (internallow speed oscillator) is provided for the Sleep timer and WDT. Ifcrystal accuracy is desired, the ECO (32.768 kHz external crystaloscillator) is available for use as a Real Time Clock (RTC) andcan optionally generate a crystal-accurate 24 MHz system clockusing a PLL. The clocks, together with programmable clockdividers (as a System Resource), provide the flexibility tointegrate almost any timing requirement into the PSoC device.PSoC GPIOs provide connection to the CPU, digital and analogresources of the device. Each pin’s drive mode may be selectedfrom eight options, allowing great flexibility in external inter-facing. Every pin also has the capability to generate a systeminterrupt on high level, low level, and change from last read.
Digital SystemThe Digital System is composed of four digital PSoC blocks.Each block is an 8-bit resource that can be used alone orcombined with other blocks to form 8, 16, 24, and 32-bitperipherals, which are called user module references.
Figure 1. Digital System Block Diagram
Digital peripheral configurations include:
■ PWMs (8 to 32 bit)
■ PWMs with Dead Band (8 to 32 bit)
■ Counters (8 to 32 bit)
■ Timers (8 to 32 bit)
■ UART 8 bit with selectable parity
■ SPI Master and Slave
■ I2C Slave and Multi-Master (one available as a System Resource)
■ Cyclical Redundancy Checker/Generator (8 to 32 bit)
■ IrDA
■ Pseudo Random Sequence Generators (8 to 32 bit)The digital blocks can be connected to any GPIO through aseries of global buses that can route any signal to any pin. Thebuses also allow for signal multiplexing and for performing logicoperations. This configurability frees your designs from theconstraints of a fixed peripheral controller.Digital blocks are provided in rows of four, where the number ofblocks varies by PSoC device family. This allows the optimumchoice of system resources for your application. Familyresources are shown in the table PSoC Device Characteristicson page 4.
Analog SystemThe Analog System is composed of six configurable blocks, eachcomprised of an opamp circuit allowing the creation of complexanalog signal flows. Analog peripherals are very flexible and canbe customized to support specific application requirements.Some of the more common PSoC analog functions (mostavailable as user modules) are:
■ Analog-to-digital converters (up to two, with 6 to 14-bit resolution, selectable as Incremental, Delta Sigma, and SAR)
■ Filters (two and four pole band-pass, low-pass, and notch)
■ Amplifiers (up to two, with selectable gain to 48x)
■ Instrumentation amplifiers (one with selectable gain to 93x)
■ Comparators (up to two, with 16 selectable thresholds)
■ DACs (up to two, with 6 to 9-bit resolution)
■ Multiplying DACs (up to two, with 6 to 9-bit resolution)
■ High current output drivers (two with 30 mA drive as a PSoC Core resource)
■ 1.3V reference (as a System Resource)
■ DTMF Dialer
■ Modulators
■ Correlators
■ Peak Detectors
■ Many other topologies possibleAnalog blocks are arranged in a column of three, which includesone CT (Continuous Time) and two SC (Switched Capacitor)blocks, as shown in Figure 2.
Additional System ResourcesSystem Resources, some of which have been previously listed,provide additional capability useful to complete systems.Additional resources include a multiplier, decimator, switch modepump, low voltage detection, and power on reset. Briefstatements describing the merits of each system resource follow:
■ Digital clock dividers provide three customizable clock frequencies for use in applications. The clocks can be routed to both the digital and analog systems. Additional clocks can be generated using digital PSoC blocks as clock dividers.
■ A multiply accumulate (MAC) provides a fast 8-bit multiplier with 32-bit accumulate, to assist in both general math as well as digital filters.
■ The decimator provides a custom hardware filter for digital signal processing applications including the creation of Delta Sigma ADCs.
■ The I2C module provides 100 and 400 kHz communication over two wires. Slave, master, and multi-master modes are all supported.
■ Low Voltage Detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced POR (Power On Reset) circuit eliminates the need for a system supervisor.
■ An internal 1.3V reference provides an absolute reference for the analog system, including ADCs and DACs.
PSoC Device CharacteristicsDepending on your PSoC device characteristics, the digital andanalog systems can have 16, 8, or 4 digital blocks and 12, 6, or4 analog blocks. The following table lists the resources availablefor specific PSoC device groups. The PSoC device covered bythis data sheet is highlighted.
Getting StartedThe quickest path to understanding the PSoC silicon is byreading this data sheet and using the PSoC Designer IntegratedDevelopment Environment (IDE). This data sheet is an overviewof the PSoC integrated circuit and presents specific pin, register,and electrical specifications. For in-depth information, along withdetailed programming information, refer the PSoC Program-mable Sytem-on-Chip Technical Reference Manual.For up-to-date Ordering, Packaging, and Electrical Specificationinformation, refer the latest PSoC device data sheets on the webat http://www.cypress.com/psoc.
Development KitsDevelopment Kits are available from the following distributors:Digi-Key, Avnet, Arrow, and Future. The Cypress Online Storecontains development kits, C compilers, and all accessories forPSoC development. Go to the Cypress Online Store web site athttp://www.cypress.com, click the Online Store shopping carticon at the bottom of the web page, and click PSoC (Program-mable System-on-Chip) to view a current list of available items.
Technical TrainingFree PSoC technical training is available for beginners and istaught by a marketing or application engineer over the phone.PSoC training classes cover designing, debugging, advancedanalog, and application-specific classes covering topics, such asPSoC and the LIN bus. Go to http://www.cypress.com, click onDesign Support located on the left side of the web page, andselect Technical Training for more details.
ConsultantsCertified PSoC Consultants offer everything from technicalassistance to completed PSoC designs. To contact or become aPSoC Consultant go to http://www.cypress.com, click on DesignSupport located on the left side of the web page, and selectCYPros Consultants.
Technical SupportPSoC application engineers take pride in fast and accurateresponse. They can be reached with a four-hour guaranteedresponse at http://www.cypress.com/support.
Application NotesA long list of application notes can assist you in every aspect ofyour design effort. To view the PSoC application notes, go to thehttp://www.cypress.com web site and select Application Notesunder the Design Resources list located in the center of the webpage. Application notes are listed by date as default.
Development ToolsPSoC Designer is a Microsoft® Windows-based, integrateddevelopment environment for the ProgrammableSystem-on-Chip (PSoC) devices. The PSoC Designer IDE andapplication runs on Windows NT 4.0, Windows 2000, WindowsMillennium (Me), or Windows XP (refer Figure 3).PSoC Designer helps the customer to select an operatingconfiguration for the PSoC, write application code that uses thePSoC, and debug the application. This system provides designdatabase management by project, an integrated debugger withIn-Circuit Emulator, in-system programming support, and theCYASM macro assembler for the CPUs. PSoC Designer also supports a high-level C language compilerdeveloped specifically for the devices in the family.
Figure 3. PSoC Designer Subsystems
PSoC Designer Software Subsystems
Device EditorThe Device Editor subsystem allows the user to select differentonboard analog and digital components called user modulesusing the PSoC blocks. Examples of user modules are ADCs,DACs, Amplifiers, and Filters.The device editor also supports easy development of multipleconfigurations and dynamic reconfiguration. Dynamicconfiguration allows for changing configurations at run time.PSoC Designer sets up power on initialization tables for selectedPSoC block configurations and creates source code for anapplication framework. The framework contains software tooperate the selected components and, if the project uses morethan one operating configuration, contains routines to switchbetween different sets of PSoC block configurations at run time.PSoC Designer can print out a configuration sheet for a givenproject configuration for use during application programming inconjunction with the Device Data Sheet. After the framework isgenerated, the user can add application-specific code to fleshout the framework. It is also possible to change the selectedcomponents and regenerate the framework.
Design BrowserThe Design Browser allows users to select and importpreconfigured designs into the user’s project. Users can easilybrowse a catalog of preconfigured designs to facilitatetime-to-design. Examples provided in the tools include a300-baud modem, LIN Bus master and slave, fan controller, andmagnetic card reader.
Application EditorIn the Application Editor you can edit your C language andAssembly language source code. You can also assemble,compile, link, and build.Assembler. The macro assembler allows the assembly code tobe merged seamlessly with C code. The link libraries automati-cally use absolute addressing or can be compiled in relativemode, and linked with other software modules to get absoluteaddressing.C Language Compiler. A C language compiler is available thatsupports Cypress MicroSystems’ PSoC family devices. Even ifyou have never worked in the C language before, the productquickly allows you to create complete C programs for the PSoCfamily devices.The embedded, optimizing C compiler provides all the featuresof C tailored to the PSoC architecture. It comes complete withembedded libraries providing port and bus operations, standardkeypad and display support, and extended math functionality.
DebuggerThe PSoC Designer Debugger subsystem provides hardwarein-circuit emulation, allowing the designer to test the program ina physical system while providing an internal view of the PSoCdevice. Debugger commands allow the designer to read andprogram and read and write data memory, read and write IOregisters, read and write CPU registers, set and clear break-points, and provide program run, halt, and step control. Thedebugger also allows the designer to create a trace buffer ofregisters and memory locations of interest.
Online Help SystemThe online help system displays online, context-sensitive helpfor the user. Designed for procedural and quick reference, eachfunctional subsystem has its own context-sensitive help. Thissystem also provides tutorials and links to FAQs and an OnlineSupport Forum to aid the designer in getting started.
Hardware Tools
In-Circuit EmulatorA low cost, high functionality ICE (In-Circuit Emulator) isavailable for development support. This hardware has thecapability to program single devices.The emulator consists of a base unit that connects to the PC byway of the parallel or USB port. The base unit is universal andoperates with all PSoC devices. Emulation pods for each devicefamily are available separately. The emulation pod takes theplace of the PSoC device in the target board and performs fullspeed (12 MHz) operation.
Designing with User ModulesThe development process for the PSoC device differs from thatof a traditional fixed function microprocessor. The configurableanalog and digital hardware blocks give the PSoC architecture aunique flexibility that pays dividends in managing specificationchange during development and by lowering inventory costs.These configurable resources, called PSoC Blocks, have theability to implement a wide variety of user-selectable functions.Each block has several registers that determine its function andconnectivity to other blocks, multiplexers, buses and to the IOpins. Iterative development cycles permit you to adapt thehardware as well as the software. This substantially lowers therisk of having to select a different part to meet the final designrequirements.To speed the development process, the PSoC DesignerIntegrated Development Environment (IDE) provides a library ofpre-built, pre-tested hardware peripheral functions, called “UserModules.” User modules make selecting and implementingperipheral devices simple, and come in analog, digital, andmixed signal varieties. The standard User Module librarycontains over 50 common peripherals such as ADCs, DACsTimers, Counters, UARTs, and other not-so common peripheralssuch as DTMF Generators and Bi-Quad analog filter sections.Each user module establishes the basic register settings thatimplement the selected function. It also provides parameters thatallow you to tailor its precise configuration to your particularapplication. For example, a Pulse Width Modulator User Moduleconfigures one or more digital PSoC blocks, one for each 8 bits
of resolution. The user module parameters permit you toestablish the pulse width and duty cycle. User modules alsoprovide tested software to cut your development time. The usermodule application programming interface (API) provideshigh-level functions to control and respond to hardware eventsat run-time. The API also provides optional interrupt serviceroutines that you can adapt as needed.The API functions are documented in user module data sheetsthat are viewed directly in the PSoC Designer IDE. These datasheets explain the internal operation of the user module andprovide performance specifications. Each data sheet describesthe use of each user module parameter and documents thesetting of each register controlled by the user module. The development process starts when you open a new projectand bring up the Device Editor, a graphical user interface (GUI)for configuring the hardware. You pick the user modules youneed for your project and map them onto the PSoC blocks withpoint-and-click simplicity. Next, you build signal chains byinterconnecting user modules to each other and the IO pins. Atthis stage, you also configure the clock source connections andenter parameter values directly or by selecting values fromdrop-down menus. When you are ready to test the hardwareconfiguration or move on to developing code for the project, youperform the “Generate Application” step. This causes PSoCDesigner to generate source code that automatically configuresthe device to your specification and provides the high-level usermodule API functions.
Figure 4. User Module and Source Code Development Flows
The next step is to write your main program, and anysub-routines using PSoC Designer’s Application Editorsubsystem. The Application Editor includes a Project Managerthat allows you to open the project source code files (includingall generated code files) from a hierarchal view. The source codeeditor provides syntax coloring and advanced edit features forboth C and assembly language. File search capabilities includesimple string searches and recursive “grep-style” patterns. Asingle mouse click invokes the Build Manager. It employs aprofessional-strength “makefile” system to automatically analyzeall file dependencies and run the compiler and assembler asnecessary. Project-level options control optimization strategiesused by the compiler and linker. Syntax errors are displayed in aconsole window. Double clicking the error message takes youdirectly to the offending line of source code. When all is correct,the linker builds a HEX file image suitable for programming.The last step in the development process takes place inside thePSoC Designer’s Debugger subsystem. The Debuggerdownloads the HEX image to the In-Circuit Emulator (ICE) whereit runs at full speed. Debugger capabilities rival those of systemscosting many times more. In addition to traditional single-step,run-to-breakpoint and watch-variable features, the Debuggerprovides a large trace buffer and allows you define complexbreakpoint events that include monitoring address and data busvalues, memory locations and external signals.
Document ConventionsAcronyms UsedThe following table lists the acronyms that are used in thisdocument.
Units of MeasureA units of measure table is located in the Electrical Specificationssection. Table 5 on page 10 lists all the abbreviations used tomeasure the PSoC devices.
Numeric NamingHexadecimal numbers are represented with all letters inuppercase with an appended lowercase ‘h’ (for example, ‘14h’ or‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’prefix, the C coding convention. Binary numbers have anappended lowercase ‘b’ (for example, 01010100b’ or‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimal.
memoryFSR full scale rangeGPIO general purpose IOGUI graphical user interfaceHBM human body modelICE in-circuit emulatorILO internal low speed oscillatorIMO internal main oscillatorIO input/outputIPOR imprecise power on reset
LSb least-significant bitLVD low voltage detectMSb most-significant bitPC program counterPLL phase-locked loopPOR power on resetPPOR precision power on reset
PinoutsThe CY8C24x23A automotive PSoC device is available in a variety of packages which are listed and illustrated in the following tables.Every port pin (labeled with a “P”) is capable of Digital IO. However, Vss, Vdd, and XRES are not capable of Digital IO.
20-Pin Part Pinout
Table 3. 20-Pin Part Pinout (SSOP)
Pin No.
Type Pin Name Description
Figure 5. CY8C24223A 20-Pin PSoC Device Digital Analog
1 IO I P0[7] Analog column mux input2 IO IO P0[5] Analog column mux input and column
output3 IO IO P0[3] Analog column mux input and column
output4 IO I P0[1] Analog column mux input5 Power Vss Ground connection6 IO P1[7] I2C Serial Clock (SCL)7 IO P1[5] I2C Serial Data (SDA)8 IO P1[3]9 IO P1[1] Crystal Input (XTALin), I2C Serial Clock
(SCL), ISSP-SCLK*10 Power Vss Ground connection11 IO P1[0] Crystal Output (XTALout), I2C Serial Data
(SDA), ISSP-SDATA*12 IO P1[2]13 IO P1[4] Optional External Clock Input (EXTCLK)14 IO P1[6]15 Input XRES Active high external reset with internal pull
down16 IO I P0[0] Analog column mux input17 IO I P0[2] Analog column mux input18 IO I P0[4] Analog column mux input19 IO I P0[6] Analog column mux input20 Power Vdd Supply voltage
LEGEND: A = Analog, I = Input, and O = Output.* These are the ISSP pins, which are not High Z at POR (Power On Reset).See the PSoC Programmable System-on-Chip Technical Reference Manual for details.
A, I, P0[7] A, IO, P0[5] A, IO, P0[3]
A, I, P0[1]
I2C SCL, P1[7]I2C SDA, P1[5]
P1[3]I2C SCL, XTALin, P1[1]
Vss
SSOP
20191817161514131211
123456789
10
VddP0[6], A, IP0[4], A, IP0[2], A, IP0[0], A, IXRESP1[6]P1[4], EXTCLKP1[2]P1[0], XTALout, I2C SDA
Name DescriptionFigure 6. CY8C24423A 28-Pin PSoC Device
Digi-tal
Ana-log
1 IO I P0[7] Analog column mux input2 IO IO P0[5] Analog column mux input and column
output3 IO IO P0[3] Analog column mux input and column
output4 IO I P0[1] Analog column mux input5 IO P2[7]6 IO P2[5]7 IO I P2[3] Direct switched capacitor block input8 IO I P2[1] Direct switched capacitor block input9 Power Vss Ground connection10 IO P1[7] I2C Serial Clock (SCL)11 IO P1[5] I2C Serial Data (SDA)12 IO P1[3]13 IO P1[1] Crystal Input (XTALin), I2C Serial Clock
(SCL), ISSP-SCLK*14 Power Vss Ground connection15 IO P1[0] Crystal Output (XTALout), I2C Serial Data
(SDA), ISSP-SDATA*16 IO P1[2]17 IO P1[4] Optional External Clock Input (EXTCLK)18 IO P1[6] 19 Input XRES Active high external reset with internal pull
down20 IO I P2[0] Direct switched capacitor block input21 IO I P2[2] Direct switched capacitor block input22 IO P2[4] External Analog Ground (AGND)23 IO P2[6] External Voltage Reference (VRef)24 IO I P0[0] Analog column mux input25 IO I P0[2] Analog column mux input26 IO I P0[4] Analog column mux input27 IO I P0[6] Analog column mux input28 Power Vdd Supply voltage
LEGEND: A = Analog, I = Input, and O = Output.* These are the ISSP pins, which are not High Z at POR (Power On Reset).See the PSoC Programmable System-on-Chip Technical Reference Manual for details.
A, I, P0[7] A, IO, P0[5] A, IO, P0[3]
A, I, P0[1]P2[7]P2[5]
A, I, P2[3]A, I, P2[1]
I2C SCL, P1[7]I2C SDA, P1[5]
P1[3]I2C SCL, XTALin, P1[1]
Vss
VddP0[6], A, IP0[4], A, IP0[2], A, IP0[0], A, IP2[6], External VRefP2[4], External AGNDP2[2], A, IP2[0], A, IXRESP1[6]P1[4], EXTCLKP1[2]P1[0], XTALout, I2C SDA
Register ReferenceThis section lists the registers of the CY8C24x23A automotivePSoC device. For detailed register information, refer the PSoCProgrammable System-on-Chip Technical Reference Manual.
Register Conventions
Abbreviations UsedThe register conventions specific to this section are listed in thefollowing table.
Register Mapping TablesThe PSoC device has a total register address space of 512bytes. The register space is referred to as IO space and isdivided into two banks. The XOI bit in the Flag register (CPU_F)determines which bank the user is currently in. When the XOI bitis set the user is in Bank 1.Note In the following register mapping tables, blank fields areReserved and must not be accessed.
Table 5. Abbreviations
Convention DescriptionR Read register or bit(s)W Write register or bit(s)L Logical register or bit(s)C Clearable register or bit(s)# Access is bit specific
Electrical SpecificationsThis section presents the DC and AC electrical specifications of the CY8C24x23A automotive PSoC device. For the latest electricalspecifications, visit http://www.cypress.com/psoc.Specifications are valid for -40oC ≤ TA ≤ 125oC and TJ ≤ 135oC, except where noted.
Figure 7. Voltage versus CPU Frequency
The following table lists the units of measure that are used in this section.
Table 8. Units of Measure
Symbol Unit of Measure Symbol Unit of MeasureoC degree Celsius μW microwattsdB decibels mA milli-amperefF femto farad ms milli-secondHz hertz mV milli-voltsKB 1024 bytes nA nanoampereKbit 1024 bits ns nanosecondkHz kilohertz nV nanovoltskΩ kilohm W ohmMHz megahertz pA picoampereMΩ megaohm pF picofaradμA microampere pp peak-to-peakμF microfarad ppm parts per millionμH microhenry ps picosecondμs microsecond sps samples per secondμV microvolts s sigma: one standard deviationμVrms microvolts root-mean-square V volts
Symbol Description Min Typ Max Units NotesTSTG Storage Temperature -55 +25 +125 oC Higher storage temperatures
reduce data retention time. Recommended storage temper-ature is +25°C ± 25°C. Storage temperatures above 65oC degrades reliability. Maximum combined storage and operational time at +125°C is 7000 hours.
TA Ambient Temperature with Power Applied -40 – +125 oCVdd Supply Voltage on Vdd Relative to Vss -0.5 – +5.75 VVIO DC Input Voltage Vss - 0.5 – Vdd + 0.5 VVIOZ DC Voltage Applied to Tri-state Vss - 0.5 – Vdd + 0.5 VIMIO Maximum Current into any Port Pin -25 – +25 mAESD Electro Static Discharge Voltage 2000 – – V Human Body Model ESD.LU Latch-up Current – – 200 mA
Table 10. Operating Temperature
Symbol Description Min Typ Max Units NotesTA Ambient Temperature -40 – +125 oCTJ Junction Temperature -40 – +135 oC The temperature rise from ambient
to junction is package specific. See Thermal Impedances per Package on page 29. The user must limit the power consumption to comply with this requirement.
DC Electrical Characteristics DC Chip-Level SpecificationsThe following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25Vand -40°C ≤ TA ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
DC General Purpose IO SpecificationsThe following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25Vand -40°C ≤ TA ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance.
Table 11. DC Chip-Level Specifications
Symbol Description Min Typ Max Units NotesVdd Supply Voltage 4.75 – 5.25 VIDD Supply Current – 5 8 mA Conditions are Vdd = 5.25V, -40 oC ≤ TA
≤ 125 oC, CPU = 3 MHz, SYSCLK doubler disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz, analog power = off.
ISB Sleep (Mode) Current with POR, LVD, Sleep Timer, and WDT.a
a. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This must be compared with devices that have similar functions enabled.
– 4 13 μA Conditions are with internal slow speed oscillator, Vdd = 5.25V, -40 oC ≤ TA ≤ 55 oC. Analog power = off.
ISBH Sleep (Mode) Current with POR, LVD, Sleep Timer, and WDT at high temperature.a
– 4 100 μA Conditions are with internal slow speed oscillator, Vdd = 5.25V, 55 oC < TA ≤ 125 oC. Analog power = off.
ISBXTL Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and external crystal.a
– 6 15 μA Conditions are with properly loaded, 1 μW max, 32.768 kHz crystal. Vdd = 5.25V, -40 oC ≤ TA ≤ 55 oC. Analog power = off.
ISBXTLH Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and external crystal at high temper-ature.a
– 6 100 μA Conditions are with properly loaded, 1μW max, 32.768 kHz crystal. Vdd = 5.25V, 55 oC < TA ≤ 125oC. Analog power = off.
VREF Reference Voltage (Bandgap) 1.25 1.3 1.35 V Trimmed for appropriate Vdd.
Table 12. DC GPIO Specifications
Symbol Description Min Typ Max Units NotesRPU Pull up Resistor 4 5.6 8 kΩ
RPD Pull down Resistor 4 5.6 8 kΩ
VOH High Output Level 3.5 – – V IOH = 10 mA, Vdd = 4.75 to 5.25V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])).
VOL Low Output Level – – 0.75 V IOL = 25 mA, Vdd = 4.75 to 5.25V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). Total IOL budget of 150 mA.
VIL Input Low Level – – 0.8 V Vdd = 4.75 to 5.25VIH Input High Level 2.2 – V Vdd = 4.75 to 5.25VH Input Hysterisis – 60 – mVIIL Input Leakage (Absolute Value) – 1 – nA Gross tested to 1 μACIN Capacitive Load on Pins as Input – 3.5 10 pF Package and pin dependent.
Temp = 25oCCOUT Capacitive Load on Pins as Output – 3.5 10 pF Package and pin dependent.
DC Operational Amplifier SpecificationsThe following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25Vand -40°C ≤ TA ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Cap PSoCblocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block.
Table 13. DC Operational Amplifier SpecificationsSymbol Description Min Typ Max Units Notes
VOSOA Input Offset Voltage (absolute value) Low Power Input Offset Voltage (absolute value) Mid PowerInput Offset Voltage (absolute value) High Power
– 1.6 1.3 1.2
1199
mV mV mV
––
TCVOSOA Input Offset Voltage Drift – 7.0 35.0 μV/oCIEBOA Input Leakage Current (Port 0 Analog Pins) – 200 – pA Gross tested to 1 μACINOA Input Capacitance (Port 0 Analog Pins) – 4.5 10 pF Package and pin
dependent. Temp = 25oC. VCMOA Common Mode Voltage Range
Common Mode Voltage Range (high power or high opamp bias)
0.0 – VddVdd - 0.5
V The common-mode input voltage range is measured through an analog output buffer. The specification includes the limitations imposed by the characteristics of the analog output buffer.
0.5 –
GOLOA Open Loop GainPower = LowPower = MediumPower = High
–––
808080
dBdBdB
Specification is applicable at high power. For all other bias modes (except high power, high opamp bias), minimum is 60 dB.
VOHIGHOA High Output Voltage Swing (worst case internal load)Power = LowPower = MediumPower = High
Vdd - 0.2Vdd - 0.2Vdd - 0.5
–––
–––
VVV
VOLOWOA Low Output Voltage Swing (worst case internal load)Power = LowPower = MediumPower = High
DC Low Power Comparator SpecificationsThe following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25Vand -40°C ≤ TA ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
DC Analog Output Buffer SpecificationsThe following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25Vand -40°C ≤ TA ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
Table 14. DC Low Power Comparator SpecificationsSymbol Description Min Typ Max Units
VREFLPC Low power comparator (LPC) reference voltage range 0.2 – Vdd - 1 VISLPC LPC supply current – 10 40 μAVOSLPC LPC voltage offset – 2.5 30 mV
Table 15. DC Analog Output Buffer Specifications
Symbol Description Min Typ Max UnitsVOSOB Input Offset Voltage (Absolute Value) – 3 18 mVTCVOSOB Input Offset Voltage Drift – +6 – μV/°CVCMOB Common-Mode Input Voltage Range 0.5 – Vdd - 1.0 VROUTOB Output Resistance – 1 – WVOHIGHOB High Output Voltage Swing (Load = 32 ohms to Vdd/2) 0.5 x Vdd + 1.1 – – VVOLOWOB Low Output Voltage Swing (Load = 32 ohms to Vdd/2) – – 0.5 x Vdd - 1.3 VISOB Supply Current Including Bias Cell (No Load)
DC Analog Reference SpecificationsThe following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25Vand -40°C ≤ TA ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer tothe power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Controlregister. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block.Note Avoid using P2[4] for digital signaling when using an analog resource that depends on the Analog Reference. Some couplingof the digital signal may appear on the AGND.
Table 16. DC Analog Reference Specifications
Symbol Description Min Typ Max UnitsBG Bandgap Voltage Reference 1.25 1.30 1.35 V– AGND = Vdd/2a
CT Block Power = High
a. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V ± 0.05V.
DC Analog PSoC Block SpecificationsThe following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25Vand -40°C ≤ TA ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
DC POR and LVD SpecificationsThe following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25Vand -40°C ≤ TA ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.Note The bits PORLEV and VM in the following table refer to bits in the VLT_CR register. See the PSoC ProgrammableSystem-on-Chip Technical Reference Manual for more information on the VLT_CR register.
DC Programming SpecificationsThe following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25Vand -40°C ≤ TA ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
Table 17. DC Analog PSoC Block Specifications
Symbol Description Min Typ Max UnitsRCT Resistor Unit Value (Continuous Time) – 12.24 – kΩ
CSC Capacitor Unit Value (Switch Cap) – 80 – fF
Table 18. DC POR and LVD Specifications
Symbol Description Min Typ Max Units
VPPOR2R
Vdd Value for PPOR Trip (positive ramp)PORLEV[1:0] = 10b 4.55 4.70 V
VPPOR2
Vdd Value for PPOR Trip (negative ramp)PORLEV[1:0] = 10b 4.55 V
VPH2
PPOR HysteresisPORLEV[1:0] = 10b – 0 – mV
VLVD6VLVD7
Vdd Value for LVD TripVM[2:0] = 110bVM[2:0] = 111b
4.624.710
4.734.814
4.834.950
VV
Table 19. DC Programming Specifications
Symbol Description Min Typ Max Units NotesVddIWRITE Supply Voltage for Flash Write Operations 4.75 – – VIDDP Supply Current During Programming or Verify – 10 25 mAVILP Input Low Voltage During Programming or Verify – – 0.8 VVIHP Input High Voltage During Programming or Verify 2.2 – – VIILP Input Current when Applying Vilp to P1[0] or P1[1] During
Programming or Verify– – 0.2 mA Driving internal
pull down resistor.IIHP Input Current when Applying Vihp to P1[0] or P1[1] During
Programming or Verify– – 1.5 mA Driving internal
pull down resistor.VOLV Output Low Voltage During Programming or Verify – – Vss + 0.75 VVOHV Output High Voltage During Programming or Verify 3.5 – Vdd VFlashENPB Flash Endurance (per block)a
a. For the full temperature range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writ-ing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.
100 – – – Erase/write cycles per block.
FlashENT Flash Endurance (total)a,b
b. A maximum of 64 x 100 block endurance cycles is allowed.
6,400 – – – Erase/write cycles.
FlashDR Flash Data Retentionc
c. Flash data retention based on the use condition of ≤ 7000 hours at TA ≤ 125°C and the remaining time at TA ≤ 65°C.
AC Chip-Level SpecificationsThe following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25Vand -40°C ≤ TA ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
Table 20. AC Chip-Level Specifications
Symbol Description Min Typ Max Units NotesFIMO24 Internal Main Oscillator Frequency for 24 MHz 22.95 24 24.96 MHz Trimmed. Using factory trim
values.FCPU1 CPU Frequency (5V Nominal) 0.09 12 12.48 MHzF48M Digital PSoC Block Frequency – – – MHz Not allowed.F24M Digital PSoC Block Frequency 0 24 24.96a
a. See the individual user module data sheets for information on maximum frequencies for user modules.
MHzF32K1 Internal Low Speed Oscillator Frequency 15 32 64 kHzF32K2 External Crystal Oscillator – 32.768 – kHz Accuracy is capacitor and
crystal dependent. 50% duty cycle.
FPLL PLL Frequency – 23.986 – MHz A multiple (x732) of crystal frequency.
Jitter24M2 24 MHz Period Jitter (PLL) – – 800 psTPLLSLEW PLL Lock Time 0.5 – 10 msTPLLSLEWSLOW PLL Lock Time for Low Gain Setting 0.5 – 50 msTOS External Crystal Oscillator Startup to 1% – 1700 2620 msTOSACC External Crystal Oscillator Startup to 100 ppm – 2800 3800 msJitter32k 32 kHz Period Jitter – 100 nsTXRST External Reset Pulse Width 10 – – μsDC24M 24 MHz Duty Cycle 40 50 60 %Step24M 24 MHz Trim Step Size – 50 – kHzJitter24M1P 24 MHz Period Jitter (IMO) Peak-to-Peak – 300 psJitter24M1R 24 MHz Period Jitter (IMO) Root Mean
Squared– – 600 ps
FMAX Maximum frequency of signal on row input or row output.
AC General Purpose IO SpecificationsThe following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25Vand -40°C ≤ TA ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
Figure 13. GPIO Timing Diagram
AC Operational Amplifier SpecificationsThe following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25Vand -40°C ≤ TA ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.Note Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block.
Table 21. AC GPIO SpecificationsSymbol Description Min Typ Max Units Notes
FGPIO GPIO Operating Frequency 0 – 12.48 MHz Normal Strong ModeTRiseF Rise Time, Normal Strong Mode, Cload = 50 pF 2 – 22 ns Vdd = 4.75 to 5.25V, 10% - 90%TFallF Fall Time, Normal Strong Mode, Cload = 50 pF 2 – 22 ns Vdd = 4.75 to 5.25V, 10% - 90%TRiseS Rise Time, Slow Strong Mode, Cload = 50 pF 9 27 – ns Vdd = 4.75 to 5.25V, 10% - 90%TFallS Fall Time, Slow Strong Mode, Cload = 50 pF 9 22 – ns Vdd = 4.75 to 5.25V, 10% - 90%
TFallFTFallS
TRiseFTRiseS
90%
10%
GPIOPin
OutputVoltage
Table 22. AC Operational Amplifier SpecificationsSymbol Description Min Typ Max Units
AC Low Power Comparator SpecificationsThe following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25Vand -40°C ≤ TA ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of upto 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor.
Figure 14. Typical AGND Noise with P2[4] Bypass
At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At highfrequencies, increased power level reduces the noise spectrum level.
Figure 15. Typical Opamp Noise
Table 23. AC Low Power Comparator SpecificationsSymbol Description Min Typ Max Units Notes
TRLPC LPC response time – – 50 μs ≥ 50 mV overdrive comparator reference set within VREFLPC.
AC Digital Block SpecificationsThe following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25Vand -40°C ≤ TA ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
Table 24. AC Digital Block Specifications
Function Description Min Typ Max Units NotesAll Functions Maximum Block Clocking Frequency 24.96 MHzTimer Capture Pulse Width 50a
a. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
AC Analog Output Buffer SpecificationsThe following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25Vand -40°C ≤ TA ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
AC External Clock SpecificationsThe following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25Vand -40°C ≤ TA ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
AC Programming SpecificationsThe following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25Vand -40°C ≤ TA ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
Table 25. AC Analog Output Buffer Specifications
Symbol Description Min Typ Max UnitsTROB Rising Settling Time to 0.1%, 1V Step, 100 pF Load
Power = Low Power = High
––
––
33
μsμs
TSOB Falling Settling Time to 0.1%, 1V Step, 100 pF Load Power = Low Power = High
––
––
33
μsμs
SRROB Rising Slew Rate (20% to 80%), 1V Step, 100 pF Load Power = Low Power = High
0.60.6
––
––
V/μsV/μs
SRFOB Falling Slew Rate (80% to 20%), 1V Step, 100 pF Load Power = Low Power = High
0.60.6
––
––
V/μsV/μs
BWOB Small Signal Bandwidth, 20mVpp, 3dB BW, 100 pF Load Power = Low Power = High
0.80.8
––
––
MHzMHz
BWOB Large Signal Bandwidth, 1Vpp, 3dB BW, 100 pF Load Power = Low Power = High
300300
––
––
kHzkHz
Table 26. AC External Clock Specifications
Symbol Description Min Typ Max UnitsFOSCEXT Frequency 0 – 24.24 MHz– High Period 20.6 – – ns– Low Period 20.6 – – ns– Power Up IMO to Switch 150 – – μs
Table 27. AC Programming Specifications
Symbol Description Min Typ Max UnitsTRSCLK Rise Time of SCLK 1 – 20 nsTFSCLK Fall Time of SCLK 1 – 20 nsTSSCLK Data Set up Time to Falling Edge of SCLK 40 – – nsTHSCLK Data Hold Time from Falling Edge of SCLK 40 – – nsFSCLK Frequency of SCLK 0 – 8 MHzTERASEB Flash Erase Time (Block) – 15 – msTWRITE Flash Block Write Time – 30 – msTDSCLK Data Out Delay from Falling Edge of SCLK – – 45 ns
AC I2C SpecificationsThe following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25Vand -40°C ≤ TA ≤ 125°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
Figure 16. Definition for Timing for Fast/Standard Mode on the I2C Bus
Table 28. AC Characteristics of the I2C SDA and SCL Pins
Symbol DescriptionStandard Mode Fast Mode
UnitsMin Max Min Max
FSCLI2C SCL Clock Frequency 0 100 0 400 kHzTHDSTAI2C Hold Time (repeated) START Condition. After this period, the first
clock pulse is generated.4.0 – 0.6 – μs
TLOWI2C LOW Period of the SCL Clock 4.7 – 1.3 – μsTHIGHI2C HIGH Period of the SCL Clock 4.0 – 0.6 – μsTSUSTAI2C Setup Time for a Repeated START Condition 4.7 – 0.6 – μsTHDDATI2C Data Hold Time 0 – 0 – μsTSUDATI2C Data Setup Time 250 – 100a
a. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT ≥ 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
– nsTSUSTOI2C Setup Time for STOP Condition 4.0 – 0.6 – μsTBUFI2C Bus Free Time Between a STOP and START Condition 4.7 – 1.3 – μsTSPI2C Pulse Width of spikes are suppressed by the input filter. – – 0 50 ns
Packaging InformationThis section illustrates the packaging specifications for the CY8C24x23A automotive PSoC device, along with the thermal impedancesfor each package and the typical package capacitance on crystal pins.Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description ofthe emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at http://www.cypress.com/design/MR10161.
Package Minimum Peak Temperature* Maximum Peak Temperature
20 SSOP 240oC 260oC
28 SSOP 240oC 260oC
*Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5oC with Sn-Pb or 245 ± 5oC with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications.
Document Number: 3-12029 Rev. *E Revised December 11, 2008 Page 31 of 31
PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registeredtrademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under thePhilips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company namesmentioned in this document may be the trademarks of their respective holders.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypressintegrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited withoutthe express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIESOF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does notassume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems wherea malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturerassumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document History Page
Sales, Solutions, and Legal InformationWorldwide Sales and Design SupportCypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the officeclosest to you, visit us at cypress.com/sales.
** 238268 SFV See ECN First release of CY8C24x23A Automotive Preliminary Data Sheet.*A 271471 HMT See ECN Update per SFV memo. Input MWR changes, including removing SMP. Change
to Final.*B 286089 HMT See ECN Update characterization data. Fine tune pinouts. Add Reflow Peak Temp. table.*C 512475 HMT See ECN Add Low Power Comparator (LPC) AC/DC electrical spec. tables. Add ISSP note
to pinout tables. Update typical and recommended Storage Temperature per extended temp. specs. Update CY branding and QFN convention. Update copyright and trademarks.
*D 2101387 AESA See ECN Post to www.cypress.com*E 2619935 OGNE/AESA 12/11/2008 Changed title to “CY8C24223A, CY8C24423A PSoC® Programmable
System-on-Chip™”Added note on digital signaling in DC Analog Reference Specifications on page 19.Added Die Sales information note to Ordering Information on page 30.Updated data sheet template.
