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Course No: EEE 210 Group No: 09

Experiment No: 05

Name of The Experiment:

Part-A: STUDY OF JFET SMALL SIGNAL

AMPLIFIER

Part-B: STUDY OF THE BIASING AND

FREQUENCY RESPONSE OF AN

INTEGRATED CIRCUIT MOS AMPLIFIER

Date of Performance: 05.06.2012

Date of Submission: 26.06.2012

Name: Kazi Mahmudur RahmanRoll: 1006033Department:EEELevel-2; Term-1

Partner's Name:Asif Ahmed KhanPartner's Student No: 1006032

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PART-A

EXERCISE #1

FIG: Simulated circuit diagram with VSIN source

FIG: Circuit for AC sweep

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FIG: Voltage gain vs Frequency

FIG: Voltage gain vs Frequency without capacitor Cs

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FIG: Voltage gain vs Frequency with Cs removed and 100k added in series with source

FIG: Voltage gain vs frequency with Cs and RL=1 Meg

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EXERCISE #2

FIG: Simulated circuit diagram for JFET as CD amplifier

FIG: Circuit for AC sweep

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FIG: Voltage gain vs Frequency curve

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PART-B

EXERCISE #3

FIG: Simulated circuit diagram with p-MOSFET and Rbreak= 10k

FIG: Simulated circuit diagram with p-MOSFET and Rbreak= 30k

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FIG: Simulated circuit diagram with n-MOSFET and Rbreak= 10k

FIG: Simulated circuit diagram with n-MOSFET and Rbreak= 30k

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EXERCISE #4

FIG: Circuit diagram

FIG: IR2 vs Rbreak

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FIG: Simulated circuit diagram with R3=(R*10k)

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EXERCISE #5

FIG: Circuit diagram

FIG: Id vs Vgs curve

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FIG: Circuit diagram with VAC source

FIG: Output current vs Frequency curve

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FIG: Normalized Voltage gain vs Frequency curve