PULSE AND DIGITAL CIRCUITS (AEC006)...A Multivibrator is an electronic circuit that generates...

PULSE AND DIGITAL CIRCUITS(AEC006)

B.Tech IV- Sem-ECE(R16- Regulation)

Prepared by

Ms. J Swetha, Ms. N Anusha,

Mr. B Naresh, Mr. S Laxmana CharyAssistant Professor

UNIT-I

WAVE SHAPING CIRCUITS

linear wave shaping

linear wave shaping

•A linear network is a network made up of linear elements only. Alinear network can be described by linear differential equations.

•The principle of superposition and the principle of homogeneityhold good for linear networks. In pulse circuitry, there are anumber of waveforms, which appear very frequently.

•The most important of these are sinusoidal, step, pulse, squarewave, ramp, and exponential waveforms.

•The process whereby the form of a non-sinusoidal signal isaltered by transmission through a linear network is called linearwave shaping.

Responses of RC high pass for pulse input.

linear wave shaping

linear wave shaping

•for the pulse input is the same as that for a step input and is given by v0(t) = Ve-t/ RC.

At t = tp, vo(t) = V = Ve-t/RC .

•At t = tp, since the input falls by V volts suddenly and since the voltage across the

capacitor cannot change instantaneously, the output also falls suddenly by V volts to

Vp - V. Hence at t = t + ,

va(t) = Ve-tp/RC - V .

• Since Vp< V, Vp- V is negative. So there is an undershoot at t = tp and hence for t >

tp, the output is negative.

•For t > tp, the output rises exponentially towards zero with a time constant RC

according to the expression (Ve-tp/RC - V)e-(t-t

p)/RC

•The output waveforms for RC » tp, RC comparable to tp and RC « tp

linear wave shaping

Response of RC high pass for square I/P

Response of RC high pass for square I/P

Response of RC high pass for square Input

Responses of RC high pass for square input

Fig.1: High-Pass RC Circuit with square wave input

The fig.1 shows the high-pass RC circuit with square wave input and

output measured across the resistance.



The shape of the output depends on the time constant of the circuit

shown below.

Fig.3: Output when RC is arbitrarily large.

When the time constant is arbitrarily large (i.e. RC/T1 and RC/T2 are very

very large in comparison to unity) the output is same as the input but

with zero dc level.



Fig.4: Output when RC > T

When RC > T, the output is in the form of a tilt.

Fig.5: Output when RC = TWhen RC is comparable to T, the output rises and falls exponentially.



Fig.6: Output when RC<<T.

When RC << T (i.e. RC/T1 and RC/T2 are very small in comparison to

unity), the output consists of alternate positive and negative spikes. In

this case the peak-to-peak amplitude of the output is twice the peak-to-

peak value of the input.

Tilt Calculation

Tilt Calculation

'2-V='

1V

2

T=T2=T1

i.e.

V1 = -V2

The output waveform for RC>>T , here,

100×

2

V

'1-V1V

=Pti lt,200×

T/2RC-e+1

T/2RC-e-1

=%

%

When the tome constant is very large P2RC

T100×=

Differentiator

Differentiator

When the time constant of the high-pass RC circuit is very very small, the

capacitor charges very quickly, so almost all the input v appears across the

capacitor and the voltage across the resistor will be negligible compared

to the voltage across the capacitor. Hence the current is determined

entirely by the capacitance. Then the current

dt

(t)idvC=i(t)

and the output signal across the R is

dt

(t)i

dvRC=(t)

0V

Response of low pass RC circuit with pulse and square input

linear wave shaping

linear wave shaping

Pulse Input:

A pulse shape will be preserved if the 3-dB frequency is approximately equal to the reciprocal of the pulse width.Thus to pass a 0.25 μ.s pulse reasonably well requires a circuit with an upper cut-off frequency of the order of 4 MHz.

linear wave shaping

Square-Wave Input:

linear wave shaping

Switching Characteristics Of Diode

Diode as a switch:

A PN junction diode can be used as a switch, when the diode is forward

bias condition the switch is said to be in ON state, when the diode is

reverse bias condition the switch is said to be in OFF state.

The diode current is given by the relation

1)-ηKTDqV

(e0

I=I

Where I is the current flowing through the diode, I0 is the dark

saturation current q is the charge on the electron V is the voltage

applied across the diode η is the (exponential) ideality factor, K is the

Boltzmann constant T is the absolute temperature in Kelvin.

Junction diode switching times

Forward recovery time:

The time required for the diode current to reverse and attain a steady

value, when a forward bias is applied to a diode operating in reverse bias

mode.

Storage time:

If reverse voltage is applied, with this result that instantaneously the

current simply reverse making IR=IF. Certain time is needed for these

minority charge carriers to move into the other region of the p-n junction

and become majority charge carriers. This time interval is called as storage

time (ts).

Reverse recovery time: It is the sum of storage time and transition time.

Positive peak clippers

Fig2: Positive peak clippers with output waveform

During the positive half cycle of the sinusoidal input waveform, diode

becomes forward biased, it must have the input voltage magnitude greater

than +0.7 volts (0.3 volts for a germanium diode). When this happens the

diodes begins to conduct and holds the voltage across itself constant at

0.7V until the sinusoidal waveform falls below this value. Thus the output

voltage which is taken across the diode can never exceed 0.7 volts during

the positive half cycle.

Positive peak clippers

Fig2: Positive peak clippers with output waveform

During the negative half cycle, the diode is reverse biased (cathode more

positive than anode) blocking current flow through itself and as a result has

no effect on the negative half of the sinusoidal voltage which passes to the

load unaltered. Thus the diode limits the positive half of the input

waveform and is known as a positive clipper circuit.

Clampers

When a signal is transmitted through a capacitive coupling network (RC

high-pass circuit), it loses its dc component, and a clamping circuit may

be used to introduce a dc component by fixing the positive or negative

extremity of that waveform to some reference level. For this reason, the

clamping circuit is often referred to as dc restorer or dc reinserter. In

fact, it should be called a dc inserter, because the dc component

introduced may be different from the dc component lost during

transmission. The clamping circuit only changes the dc level of the input

signal. It does not affect its shape.

Clampers

Positive Clamper

Fig: Positive Clamper

Let the input voltage be Vi = Vmsinωt as shown in Fig1. When Vi, goes

negative, the diode gets forward biased and conducts and in a few cycles

the capacitor gets charged to Vm with the polarity shown in fig2. Under

steady-state conditions, the capacitor acts as a constant voltage source

and the output is V0 = Vi-(-Vm) = Vi+Vm

Clampers

Positive Clamper

Based on the above relation between VO and Vi, the output voltage

waveform is plotted. As seen in Fig2 the negative peaks of the input signal

are clamped to zero level. Peak-to-peak value of output voltage = peak-to-

peak value of input voltage = 2Vm. There is no distortion of waveform.

Fig: Positive Clamper output waveform with input signal

Clampers

Negative Clamper

Fig: Negative Clamper

During the first quarter cycle, the input signal rises from zero to the

maximum value. The diode conducts during this time and since we have

assumed an ideal diode, the voltage across it is zero. The capacitor C is

charged through the series combination of the signal source and the

diode and the voltage across C rises sinusoidally. At the end of the first

quarter cycle, the voltage across the capacitor, Vc = Vm.

Clampers

Negative Clamper

When, after the first quarter cycle, the peak has been passed and the

input signal begins to fall, the voltage Vc across the capacitor is no longer

able to follow the input, because there is no path for the capacitor to

discharge. Hence, the voltage across the capacitor remains constant at Vc =

Vm, and the charged capacitor acts as a voltage source of V volts and after

the first quarter cycle, the output is given by V0 = Vi-Vm . During the

succeeding cycles, the positive extremity of the signal will be clamped or

restored to zero and the output.

Clampers

Negative Clamper

For Vi = 0, V0 = -Vm

Vi = Vm, V0 = 0Vi = -Vm, V0 = -2Vm

Fig: Negative Clamper output waveform with input signal

Shunt clippers, problems

Non linear wave shaping

Nonlinear wave shaping

Shunt ClippersClipping above reference level

Figure (a) v-i characteristic of an ideal diode, (b) diode clipping circuit, which removes that part of the waveform that is more positive than VR, (c) the piece-wise linear transmission characteristic of the circuit, a sinusoidal input and the clipped output, (d) equivalent circuit for v( < VR, and (e) equivalent circuit for v, > VR


Clipping below reference level

Figure (a) A diode clipping circuit, which transmits that part of the sine wave that is more positive than VR, (b) the piece-wise linear transmission characteristic, a sinusoidal input and the clipped output, (c) equivalent circuit for v( < VR, and (d) equivalent circuit for v,- > VR.

Clamping circuit theorem

Non linear wave shaping


Clamping Circuit Theorem

Under steady-state conditions, for any input waveform, the shape of the

output waveform of a clamping circuit is fixed and also the area in the

forward direction (when the diode conducts) and the area in the reverse

direction (when the diode does not conduct) are related.

The clamping circuit theorem states that, for any input waveform under

steady-state conditions, the ratio of the area Af under the output voltage

curve in the forward direction to that in the reverse direction Ar is equal to

the ratio R//R-

This theorem applies quite generally independent of the input waveform

and the magnitude of the source resistance.


Under steady-state conditions, the net charge acquired by thecapacitor over one cycle must be equal to zero. Therefore, the chargegained in the interval 0 < t < T, will be equal to the charge lost in theinterval T1 < t < T1 + T2, i.e. Qg = Ql

UNIT-II

MULTIVIBRATORS

Introduction to Multivibrators

Introduction to Multivibrators:

A Multivibrator is an electronic circuit that generates square, rectangular,

pulse waveforms, also called nonlinear oscillators or function generators.

Multivibrator is basically a two amplifier circuits arranged with

regenerative feedback.

There are three types of Multivibrators

1. Astable Multivibrator

2. Monostable Multivibrator

3. Bistable Multivibrator

Fixed bias BiStable Multivibrator


Fig1: Fixed bias Bistable MultivibratorIn a bistable multivibrator both the coupling elements are resistors (dccoupling). The bistable multivibrator is also called a multi, Eccles-Jordancircuit (after its inventors), trigger circuit, scale-of-two toggle circuit, flip-flop, and binary.


Fixed bias BiStable Multivibrator Operation

Fig1 shows the circuit diagram of a fixed-bias bistable multivibrator using

transistors (inverters). Note, that the output of each amplifier is direct

coupled to the input of the other amplifier.

In one of the stable states, transistor Q1 is ON (i.e. in saturation) and Q2

is OFF (i.e. in cut-off), and in the other stable state Q1 is OFF and Q2 is ON.

Even though the circuit is symmetrical, it is not possible for the circuit to

remain in a stable state with both the transistors conducting (i.e. both

operating in the active region) simultaneously and carrying equal currents.


Fixed bias BiStable Multivibrator Operation

The reason is that if we assume that both the transistors are biasedequally and are carrying equal currents I1 and I2 and suppose there is aminute fluctuation in the current I, let us say it increases by a smallamount, then the voltage at the collector of Q1 decreases.

This will result in a decrease in voltage at the base of Q2. So Q2 conductsless and I2 decreases and hence the potential at the collector of Q2

increases. This results in an increase in the base potential of Q1. So, Q1

conducts still more and I1 is further increased and the potential at thecollector of Q1 is further reduced, and so on. So, the current I1 keeps onincreasing and the current I2 keeps on decreasing till Q1 goes intosaturation and Q2 goes into cut-off.

This action takes place because of the regenerative feedbackincorporated into the circuit and will occur only if the loop gain is greaterthan one.

Design of Bistable multivibrator

Design of fixed bias Bistable multivibrator


The transition time may be reduced by compensating this att'.nuatorby introducing a small capacitor in parallel with the coupling resistorsR and R\ of the binary . Since these capacitors are introduced toincrease the speed of operation of the device, they are called speed-upcapacitors. They are also called transpose or commutating capacitors.So, commutating capacitors are small capacitors connected in parallelwith the coupling resistors in order to increase the speed of operation.The commutating capacitors hasten the removal of charge stored atthe base of the ON transistor due to minority carriers. If thecommutating capacitors are arbitrarily large, the /?]-/?2 network actsas an overcompensated attenuator and the signal at the collector willbe transmitted to the base of the other transistor very rapidly, butlarge values of capacitors have some disadvantages.


Methods of improving resolutionThe resolution of a binary can be improved by taking the following steps:• By reducing all stray , capacitances. Reductions in the values of stray capacitances reduce their charging time, resulting in a reduction in the time taken by the transistors to go to the opposite state.•By reducing the resistors R^, R2, and Rc. Reductions in the values of /?j and /?2 result in a reduction in the charging time of the commutating capacitors with a consequent improvement in transition speed. Reducing resistors also reduces the recovery time.

•By not allowing the transistors to go into saturation. When the transistors do not saturate, the storage time will be reduced resulting in fast change from ON to OFF.

Design of self bias binary



Fig1: self bias binary


i) Potential at point A

VA=VD-i2'R1

Since VD=VE then VA = VE/2

ii) To find RC2

From fig1,

VCC-i2RC2-VD=0

From that

C2

DCC

i

V-V=RC1=RC2


iii) To find Re

From fig1, VE=iE2Re

VE = ic2Re

iv. To find R1, R2

let R1=R2=R

Given iB2 = 2iB2(min)

i1= iB2+i4

2

B

2(min)

11

BCC

R

V+iB×2=

R+RC

V-V

From the above equation find R

Triggering of Bistable multivibrator



We know that a bistable multivibrator has got two stable states and thatit can remain in any one of the states indefinitely. The process ofapplying an external signal to induce a transition from one state to theother is called triggering. The triggering signal, which is usuallyemployed is either a pulse of short duration or a step voltage. There aretwo methods of triggering—unsymmetrical triggering and symmetricaltriggering.

at the collectors


at the bases


Problems on bistable multi.


For a fixed-bias bistable multivibrator using n–p–n Ge transistor VCC = 10 V,RC = 1 kΩ, R1 =10 kΩ, R2 = 20 kΩ, hFE(min) = 40, VBB = 10 V. Calculate: (a)Stable-state currents andvoltages assuming Q1is OFF and Q2is ON and insaturation. Verify whether Q1is OFF and Q2is ON or not. (b) the maximumload current.


Calculation of UTP and LTP in Schmitt trigger



Fig: Schmitt trigger


i) To find UTP (V1)

When Q1 OFF and Q2 ON

V1 = VBE1+VE

V1 = VBE1+iC2RE

Determine equivalent voltage and resistance, then apply KVL loop

Vth-iB2Rth-VBE (act)-(iB2+iC2) RE = 0

In active region

iC2 = hfeiB2

Then V1 = Vγ+iC2RE


ii) To find LTP (V2)

When Q1 ON and Q2 OFF

V2 = VBE (act) + iC1RE

But

V2=VB

VB=i1'R2B11C

+V'Ri=V

B1

2

B

C+VR

R

V=V

m×V=VBC



From equivalent circuit

]R

V-

R

mV-V[R+V=V

2

B

C1

BCC

EBE(act)B

By using above equation to solve the LTP (V2)

2

E

C1

E

C1

E

CCBE(act)

B

R

R+

R

mR+1

R

RV+V

=V=V2



From equivalent circuit

]R

V-

R

mV-V[R+V=V

2

B

C1

BCC

EBE(act)B

By using above equation to solve the LTP (V2)

2

E

C1

E

C1

E

CCBE(act)

B

R

R+

R

mR+1

R

RV+V

=V=V2

Monostable multivibrator



MONOSTABLE MULTIVIBRATORAs the name indicates, a monostable multivibrator has got only onepermanent stable state, the other state being quasi stable. Underquiescent conditions, the monostable multivibrator will be in its stablestate only. A triggering signal is required to induce a transition fromthe stable state to the quasi stable state.


For t < 0, Q2 is ON and so vB2 =VBE(sat). At t = 0, a negative signalapplied brings Q2 to OFF state and Q[into saturation. A current /| flowsthrough Rc of Qt and hence vci dropsabruptly by /|7?c volts and so vB2 alsodrops by I\RC instantaneously. So at t -0, vB2 = VBE(sat) - IRC. For t > 0, thecapacitor charges with a time constantRC, and hence the base voltage of Q2

rises exponentially towards VCc withthe same time constant. At t = T, whenthis base voltage rises to the cut-involtage level Vy of the transistor, Q2

goes to ON state, and Qj to OFF stateand the pulse ends.

Applications of monostable multivibrator



Monostable multivibrator as a voltage-to-time converter

Fig.1shows the circuit diagram of a Monostable multivibrator as a voltage-

to-time converter. By varying the auxiliary supply voltage V, the pulse

width can be changed. The waveform of the voltage vB2 at the base of Q2 is

shown in Fig.2.

Fig.: Monostable multivibrator as a voltage-to-time converter


Monostable multivibrator as a voltage-to-time converter

The waveform of the voltage vB2 at the base of Q2 is shown in Fig.2.

Fig.: waveform of the voltage vB2 at the base of Q2


To identify the voltage across base of Q2

In the interval 0 < t < T, VB2 is given by

T/ τ-)e

CCV+(V=V

T/ τ-)e

CCV+(V-V=0

t/ τ-)e

CCV+(V-V=

B2V

t/ τ-)e

CC(-V-(V-V=

B2V

t/ τ-)e

inV-

f(V-

fV=

B2V

At t = T, VB2 = Vγ=0


)V

V+log(1 RC=T

)V

V+log(1 τ=T

)V

V+log(1=T/ τ

CC

CC

CC

Where τ=RC, then

VCC, R & C being fixed, it is seen from the above relationship that as V

changes, T also Changes.

Thus, the pulse width is a function of the auxiliary voltage v. For this

reason, the monostable multi is called as voltage to time converter.

Astable multivibrator, voltage to frequency converter



Fig.: Collector Coupled Astable multivibrator


Fig.shows the circuit diagram of a collector-coupled astable multivibrator

using n-p-n transistors. The collectors of both the transistors Q1 and Q2

are connected to the bases of the other transistors through the coupling

capacitors Cs and C2. Since both are ac couplings, neither transistor can

remain permanently at cut-off. Instead, the circuit has two quasi-stable

states, and it makes periodic transitions between these states. Hence it is

used as a master oscillator. No triggering signal is required for this

multivibrator.


Fig.: waveforms at the bases and collectors of astable Multi


Expression for T: t/ τ-)e

inV-

f(V-

fV=

BV

Let Vin = -VCC , Vf = VCC

Substitute and calculate T1 & T2, From the above analysis

T1= 0.69R1C1

T2= 0.69R2C2

Hence the total time period is represented by

T=T1+T2

T=0.69R1C1+0.69R2C2

T= 0.69(R1C1+ R2C2)


Voltage-to-Frequency Converter

Fig.: Voltage-to-Frequency ConverterFig.3 shows the circuit diagram of an Astable multivibrator used as avoltage-to-frequency converter. The frequency can be varied by varyingthe magnitude of the auxiliary voltage source V.For 0 < t < T1, Q1 is OFF and Q2 is ON.Initial value of VB = VIN = -VCC

Final Value of VB = Vf = VThe exponentially rising voltage VB is expressed as


2C2t/R-

inffB)eV-(V-V=V

2C

2t/R-

)eCC

V+(V-V=

At t= T2, we have VB=Vγ=0.

2C

2T2/R-

e)CC

V+(V-V=0

)V

CCV

+1log(2

C2

R=2T

Similarly

)V

CCV

+1log(1

C1

R=1T

)V

CCV

+1log(RC2

1=f

UNIT-III

SAMPLING GATES AND TIME BASE GENERATORS

SAMPLING GATES

A sampling gate is a transmission circuit that faithfully transmits an

input signal to the output for a finite time duration which is decided

by an external signal, called a gating signal.

SAMPLING GATES

Figure : Sampling gate

•The input appears without a distortion at the output, but is available for a

time duration T and after wards the signal is zero.

•They can transmit more number of signals.

•Applications :

Multiplexers, choppers, D/A converter, sample and hold circuits, etc.

Earlier, we had seen logic gates in which the output, depending on the input

conditions, is either a 1 level or a 0 level. That is, the inputs and outputs are

discrete in nature. In a sampling gate, however, the output is a faithful

replica of the input. Hence, sampling gates are also called linear gates,

transmission gates or time selection circuits.

SAMPLING GATES

SAMPLING GATES

Basic Principle of sampling gates

Fig.: Series switch

only when the switch closes, the input signal is transmitted to the output.

Fig.: Shunt Switch

only when the switch is open

the input is transmitted to the

output.

Classification of sampling gates:

Sampling gates can be of two types:

Unidirectional gates: These gates transmit the signals of only one

polarity.

Bidirectional gates: These gates transmit bidirectional signals (i.e.,

positive and negative signals).

SAMPLING GATES

UNIDIRECTIONAL SAMPLING GATE



Unidirectional Gate

unidirectional sampling gates are those which transmit signals ofonly one polarity(i.e,. either positive or negative).

The gating signal is also known as control pulse, selector pulse or anenabling pulse. It is a negative signal, the magnitude of whichchanges abruptly between –V2 and –V1.

Figure : Unidirectional sampling gate


Unidirectional Sampling Gate

Consider the instant at which the gate signal is –V1 which is a reasonably

large negative voltage. Even if an input pulse is present at this time instant,

the diode remains OFF as the input pulse amplitude may not be

sufficiently large so as to forward bias it. Hence there is no output.

Figure : Unidirectional sampling gate


When the control signal shifted toupward.

Fig. Output waveform


Pedestal

When the control signal is shifted to positive value ,so it will be

superimposed on input and control signals,so the pedestal occurs.

Fig. : Pedestal


Advantages:

The circuitry is simple.

Time delay between input and output is too low.

It can be extended to more number of inputs.

No current is drawn during non-transmission period. Hence under

quiescent condition, no power dissipation is present


Disadvantages:

There is interaction between control and input signals (VC and VS).

As the number of inputs increase, the loading on control inputincreases.

Output is sensitive to control input voltage V1 (upper level of VC).

Only one input should be applied at one instant of time.

Because of slow rise time of the control signal, the output may get

distorted, if the input signal is applied before reaching the steadystate.

Modified Unidirectional Sampling gate



Two input unidirectional sampling gate

Two input unidirectional sampling gate is shown in below fig 1.

Fig.1: Two input unidirectional sampling gate



Let Vs1 and Vs2 be the pulses of amplitude 5 V. When both

these signals appear at the input simultaneously, having the same

duration, the output is shown in Fig. 2, when −V1 = −25 V and −V2 = 0.

Fig.2: The waveforms of a two-input unidirectional gate.



When the control signal is at −V2 (= 0 V), and if both

the inputs are 0 the output is zero. When the inputs are above 0, the

output is 5 V. However, when the control input is at −V1 (−25 V), no

output is available. This negative control signal inhibits the gate.

Hence, this circuit is a two-input OR gate with −V1 (−25 V) and

inhibiting the gate operation.

Bidirectional Sampling gate

Bidirectional Sampling gate:

Bidirectional sampling gates are those which transmit signals of both

the polarities

Fig.: Bidirectional sampling gate using transistors


Bidirectional Sampling gate:

The control input VC applied here is a pulse waveform with

two levels V1 and V2 and pulse width tp. This pulse width decides the

desired transmission interval. The gating signal allows the input to get

transmitted. When the gating signal is at its lower level V2, the

transistor goes into active region. So, until the gating input is

maintained at its upper level, signals of either polarity, which appear at

the base of the transistor will be sampled and appear amplified at the

output.


Two-transistor Bidirectional Sampling Gates:

Fig.: Two-transistor Bidirectional Sampling Gates with waveforms

Two Diode Bidirectional Sampling gate



Two Diode Sampling gate

Fig.: two diode sampling gate


Analysis

When the gate voltage levels are such that the voltage at point A is –

ve (-Vc) and at point B is +ve (+Vc), then the both diodes are reverse

biased and hence there is no transmission of signals. when the gate

voltages are such that ythe voltage at point A is +ve (+Vc) and the

voltage at point B is –ve(-Vc) the both diodes D1 and d2 are ON, As a

result there is a transmission of input signal for the duration of gate

pulses.

The equivalent circuit to calculate voltage at node A due to Vs source.


Analysis

The equivalent circuit to calculate voltage at node A due VC source

Vsα=Vs2R+1R

2R=v

1Ath

( )Vcα1=Vc2R+1R

2R1=Vc

2R+1R

1R=v

2th

We have Rth1 = Rth2.

Similarly, considering the circuit when a negative signal is transmitted

to the output when D2is ON and combining the equivalent circuits of

the two halves, we finally have the circuit shown in Fig.2.


Final equivalent circuit

Fig.: Equivalent Circuit


Analysis

The open circuit voltage between P and the ground is α Vs and the

Thevenin resistance is R3/2

Fig.:The circuit that enables the calculation of gain A

2

3R+Rl

RlVsα=0V

2

3R+Rl

Rlα=

Vs

0V=A

2

3R+Rl

Rl

2R+1R

2R=

Vs

0V=A

Determination Of Control Voltages.

Determination of Control Voltages.


Calculation Of Minimum Positive Control Voltage

Fig.: voltage Vo when D2 is OFF Fig.:voltage Vo when D1 is ON


Calculation Of Minimum Positive Control Voltage

From the Fig.1

V0 = αVs – (1-α)Vc

From the fig.2

3R+Rl

RlV)α1(+Vsα=0V C-

By using above two equations

VsRl2+3R

3R×

1R

2R=vcp

min


Calculation of input Resistances:

Fig.: when D1 and D2 are OFF Fig.: when D1 and D2 are ON

Ri = (R1+R2)/22

1R×

Rl+2R

Rl2RRi =

Reduction of pedestal




While going through different types of sampling gates and the

outputs they produce, we have come across an extra voltage level in

the output waveforms called as Pedestal.

This is unwanted and creates some noise. The difference in the

output signals during transmission period and non-transmission

period though the input signals is not applied, is called as Pedestal.

It can be a positive or a negative pedestal.


=

4 Diode Bidirectional Gate

Bidirectional sampling gate circuit is made using diodes also. A two

diode bidirectional sampling gate is the basic one in this model. But it

has few disadvantages such as

• It has low gain

• It is sensitive to the imbalances of control voltage

• Vn (min) may be excessive

• Diode capacitance leakage is present



• During transmission, the diodes D3 and D4 are OFF. The gain A of the

circuit is given by

A=RCRC+R2×RLRL+(Rs/2)

• Hence the choice of application of control voltages enables or

disables the transmission. The signals of either polarities are

transmitted depending upon the gating inputs.

Introduction to sweep circuits



The waveforms of the type shown in Figures (a) and (b) are

generally called sweep waveforms even when they are used in

applications not involving the deflection of an electron beam.

In fact, precisely linear sweep signals are difficult to generate by

time-base generators and moreover nominally linear sweep signals

may be distorted when transmitted through a coupling

network.

Methods Of Generating A Time-base Waveform

METHODS OF GENERATING A TIME-BASE

WAVEFORM

In time-base circuits, sweep linearity is achieved by one of the

following methods.

Exponential charging.

Constant current charging.

The Miller circuit.

The bootstrap circuit.

CALCULATION OF SWEEP ERRORS


Slope or sweep speed error, es

We know that for an exponential sweep circuit


Rate of change of output or slope is


The transmission error, et:





Displacement error (ed): It is defined as the ratio of maximum

deviation of the actual sweep from the linear sweep to the

amplitude of the sweep voltage.

ed = maximum deviation / sweep amplitude

=

Vs = V (1-e-t/RC) =

Vs

max'VsVs

RC

t

Rc

vt

RC

vt

RC

t

RC

vtvvdeviation

tRc

vtv

RC

t

RC

vt

ss

s

2

21'

'

21


Taking only the amplitudeThe deviation is maximum at t=Ts/2 is

We have V’s = αt =

Vs =

ed = Ts / 8RC

max' sVVs

Putting t = Ts/2

RC

vt

RC

VTs

RC

ts

Rc

tsv

VVss

2

22'

max


Relationship Between ed, es, & etWe have ed =

es=

then ed =

et =

and ed =

then ed =

then ed =

RC

Ts

8

RC

Ts

se

8

1

RC

Ts

2

RC

Ts

8

te

4

1

te

4

1=

se

8

1

Methods of generating time base waveforms

In time-base circuits, sweep linearity is achieved by one of the followingmethods.

1. Exponential charging. In this method a capacitor is charged from

a supply voltage through a resistor to a voltage which is small comparedwith the supply voltage.

2. Constant current charging. In this method a capacitor is charged

linearly from a constant current source. Since the charging current isconstant the voltage across the capacitor increases linearly.

3. Miller circuit. In this method an operational integrator is used to

convert an input step voltage into a ramp waveform.

4. Bootstrap circuit. In this method a capacitor is charged linearly by

a constant current which is obtained by maintaining a constant voltageacross a fixed resistor in series with the capacitor.

UNI JUNCTION TRANSISTOR.

SWEEP CIRCUIT USING UNI JUNCTION

TRANSISTOR.

UNI JUNCTION TRANSISTOR

a) Construction of UJT (b) equivalent circuit of UJT, and (c) circuit when iE = 0.


SYMBOL AND INPUT CHARATERSTICTS



EXPRESSION FOR SWEEP INTERVAL

Miller Sweep Generator




• OPERATION

• When the output of Schmitt trigger generator is a negative pulse, thetransistor Q4 turns ON and the emitter current flows through R1. Theemitter is at negative potential and the same is applied at the cathodeof the diode D, which makes it forward biased. As the capacitor C isbypassed here, it is not charged.

• The application of a trigger pulse, makes the Schmitt gate output high,which in turn, turns the transistor Q4 OFF. Now, a voltage of 10v isapplied at the emitter of Q4 that makes the current flow through R1

which also makes the diode D reverse biased. As the transistor Q4 is incutoff, the capacitor C gets charged from VBB through R and provides arundown sweep output at the emitter of Q3. The capacitor Cdischarges through D and transistor Q4 at the end of the sweep.


Applications

Miller sweep circuits are the most commonly used integrator circuit

in many devices. It is a widely used saw tooth generator.

Bootstrap time base generator

Transistor bootstrap time base generator


A transistor bootstrap time-base generator. The input to

transistor Q1 is the gating waveform from a monostable

multivibrator.

Circuit Diagram

Fig.1: Bootstrap sweep circuit


Input and output waveforms


Formation of sweep

When the negative-going gating waveform is applied at t - 0, the

transistor Q] is driven OFF.

The current/Ci now flows into the capacitor C and so the voltage

across the capacitor rises according to the equation


Retrace interval:

At t = Tg, when the gate terminates, the transistor Qi goes into

conduction and a current r'Bi = VCC/R-Q flows into the base of Qi.

Hence a current/ci =/IFE*BI flows into the collector of Qj. This

current remains constant till the transistor goes into saturation.

Since Q] is ON the capacitor C discharges through Qi.

The recovery process:

During the entire the capacitor C discharges at a constant rate

because the Current through it has remained constant. So it

would have lost a charge.

Hence at the time T when the voltage across C and at the base of

Q2 returns to its value for t< 0, the voltage across Ci is smaller than

it was at the beginning of the sweep. The diode D starts conducting

at t -


COMPARISION OF SWEEP CIRCUITS

Comparison of bootstrap and miller circuits

Comparison of sweep circuits

MILLER SWEEP CIRCUIT

It employs negative feedback

In miller sweep circuit the polarity of sweep voltage is negative.

The inverting amplifier is used in this circuit.

The open circuit gain of the amplifier is A = – ∞

The linearity of the sweep voltage is better than that of the

bootstrap sweep circuit.

A voltage source V is simulated like that V is always equal to the

instantaneous capacitor voltage VC.

BOOOTSTRAP SWEEP CIRCUIT

Bootstrap sweep circuit

It employs positive feedback

In bootstrap sweep circuit the polarity of sweep voltage is positive.

The non inverting amplifier is used in this circuit.

The open circuit gain of the amplifier is A = + 1

The linearity of the sweep voltage is poor than that of the miller

sweep circuit.

A voltage source V is suggested like that V is forever equal to the

immediate capacitor voltage VC.

Comparison of sweep circuits

Problems on Time base Generators



Problem 1:Calculate component values of a UJT sweep generator required togenerate an output sweep frequency of 10KHz, with sweep amplitudeof 10V. The UJT available has ƞ =0.75, Vv = 1.2V, RBB = 6Kohms, Iv =3mA, Ip=10µA and DC supply is 18V.

Ans:

given Data

f = 10 KHz,

Vs = 10V,

Vv = 1.2V,

Iv =3mA,

Ip = 10 µA


Let VBB = 18V

Vp= Vv+Vs

= 1.2+10=11.2V

Ts = 0.9045RC

To Evaluate R & C

R should be between Rmax & Rmin

4706.2log

log

e

e

RCTs

VpV

VvVRCTs

Ip

VpVR

max


Iv

VvVR

min

MR 68.0

1010

2.1118

6max

KR 6.5

103

2.118

3min

R Must be lie between Rmax & Rmin = 100 KΩ.

Period = T = .1.01010

11

3ms

f

We have T = Ts+TrIn practice Tr should be quite small, as compared to Ts.Let Tr be 1µs.Ts = 100 µs -1 µs = 99 µs.


Ts = 0.9045RC

99 µs = CK 1009045.0

3

6

101009045.0

1099

C

nFC 1

Return this Tr is given Tr = R1 C

R1 = KnC

Tr1

1

1

But R1 should be few tens of ohms then R1 = 50 Ω.R2 must be larger than R1 and it should be few hundred ohms.Let R2 = 300 Ω.


Problem 2:For the given specifications of bootstrap sweep generator, estimate i)sweep error, ii) sweep amplitude. Hfe(min) = 20, hfe = 100, hie = 2 KΩ and alljunction voltages to be zero. The input is a 1 kHz symmetrical squarewave. VCC = 10v, VEE = 10V, RC1 =10KΩ, Cs = 0.05 µF, RB = 10 kΩ and Re =5 KΩ.Ans:

Period T = 1/f = 1 msec.Gating signal width Tg = T/2 = 0.5 msec.

We have maximum value of ramp voltage given as

sC

cccc

CR

TgV

RC

TgVVs

1

UNIT-IVSYNCHRONIZATION AND FREQUENCY

DIVISION

Synchronization & Frequency Division

Introduction to Synchronization and Frequency Division:

A pulse or digital system may involve several different basic

waveform generators and the system may require that all these generators

be operated synchronously

In any system, having different waveform generators, all of them are

required to be operated in synchronism. Synchronization is the process of

making two or more waveform generators arrive at some reference point in

the cycle exactly at the same time.


Types of Synchronization:

It can be divided in to two types.

1. Synchronization with One-to-one basis.

2. Synchronization with frequency division.


Synchronization with One-to-one basis:

Fig.1: Synchronization with one to one basis

All the generators are operated at a same frequency.

All of them arrive at some reference point in the cycle exactly at the

same time.


Synchronization with frequency division:

Generators operate at different frequencies which are integral

multiples of each other.

All of them arrive at some reference point in the cycle exactly at the

same time.

Fig.2: Synchronization with frequency division


Principle of synchronization:

These are the circuits in which the timing interval is established

through the gradual charging of a capacitor, the timing interval being

terminated by the sudden discharge (relaxation) of a capacitor.


63

3

1005.01010

105.010

V10

For an emitter follower, the current gain is given as

eoe

feI

Rh

h

A

1

1

78.89

40

51

1100

Input resistance eiie RAhRi

K9.450578.892


Open circuit voltage gain A = 0.9956

Sweep error

A

R

R

AV

Vse

i

ci

ccs 1

9956.01

9.450

10

109956.0

10

%67.20267.0 or

Pulse synchronization

Pulse synchronization of relaxation devices


Pulse synchronization of relaxation devices


Fig (a) : shows synchronization results for ) Tp < T0

.

Fig (b) : shows no synchronization results for ) Tp > T0

Fig (c) shows even if Tp < T0 but amplitude of synch pulse is small, hence no synchronization results.



FREQUENCY DIVISION IN SWEEP CIRCUITS

FREQUENCY DIVISION

• 1)Synchronization occur only when tp<to and amplitude is sufficient

to terminate at every cycle.

• 2) The sweep cycles- are terminated only by alternate pulses marked

"2". the pulses marked "1" would be required to have an amplitude

at least equal to vl if they were to be effective.

• 3) The sweep generator now acts as a divider, the division factor

being 2, since exactly one sweep cycle occurs for every two

synchronizing pulses. if ts is the sweep generator period after

synchronization, t/tp = 2.

FREQUENCY DIVISION IN SWEEP CIRCUIT

FREQUENCY DIVISION IN SWEEP CIRCUIT

The basic principle of synchronization and use for counting

purposes of other relaxation devices is same as the basic principle

of synchronization of the sweep generator.

ASTABLE RELAXATION CIRCUITS

OTHER RELAXATION CIRCUITS


•The astable multivibrator shown in Figure 6.6 may be synchronizedor used as a divider by applying either positive or negativetriggering pulses to either transistor or to both the transistorssimultaneously..


•These pulses may be applied to the collector, base, or emitter. If for

example, positive pulses are applied to Bt or C2 or negative pulses to E\,

these triggers may produce synchronization by establishing the exact

instant at which Qj comes out of cut- off. If negative pulses are applied

to B2 or Q or positive pulses to E2, then when Q2 conducts, these pulses

will be amplified and inverted and appear as positive pulses at B].

•Hence again the pulses may establish the instant when Qt comes out

of cut-off.

•The negative pulses will not be effective unless they succeed in moving

the transistor at least slightly into the active region.


Monostable Relaxation Circuits

Monostable Relaxation Circuits

Monostable Relaxation Circuit

Fig. : Monostable Multivibrator circuit

The figure 1 used as a monostable relaxation device, a monostablemultivibrator for frequency division. The input pulses may be applied atBf or Cj depending on the polarity.

Monostable as frequency divider



Fig. : Monostable Multivibrator circuit

The figure 1 used as a monostable relaxation device, a monostablemultivibrator for frequency division. The input pulses may be applied atBf or Cj depending on the polarity.


Fig. : waveform at B2 with no pulse overshoot

The waveforms of Figure 2 shows the voltage at BI and B2- Each fourthpulse causes a transition of the multivibrator, the remaining pulsesoccurring at a time when they are ineffective.


Fig.: waveform at B2 with pulse overshoot

In this case, the two portions of the multivibrator waveform would besynchronized. Also, the counting ratio will change with increasingamplitude of pulse input.

UNIt-V

DIGITAL LOGIC FAMILIES

SPECIFICATIONS OF LOGIC FAMILIES

The main characteristics of Logic families include

1)Speed 2)Fan-in 3)Fan-out

4)Noise Immunity 5)Power Dissipation

Bipolar logic families RTL

Bipolar logic families


. RTL NOR gate ND TRUTH TABLE

Case I: When A = B = 0.Both T1 and T2 transistors are in cut off state because the voltage isinsufficient to drive the transistors i.e. VBE < 0.6 V: Thus, output Y will behigh, approximately equal to supply voltage Vcc. As no current flows throughRc and drop across Rc is also zero.Thus, Y = 1, when A = B = 0.


Case II : When A = 0 and B = 1 or A = 1 and B = 0.The transistor whose input is high goes into saturation where as otherwill goes to off cut state. This positive input to transistor increases thevoltage drop across the collector resistor and decreasing the positiveoutput voltage.Thus, Y = 0,when A= 0 and B = 1 or A = 1 and B = 0.

Case III : When A = B = 1. Both the transistors T1 and T2 goes into saturation and output voltage is equal to saturation voltage.Thus, Y = 0,when A = B = 1

Bipolar logic families. DCTL, HTL



DCTL NAND Gate


High Threshold Logic(HTL):

Tristate Logic, Interfacing



Tristate Logic

INPUT OUTPUT

A B C

0

1

0

1 1

X 0 Z (high impedance)


• Interfacing :To achieve optimum performance in a digital system,

devices from more than one logic family can be used, taking

advantages of the superior characteristics of each family for

different parts of the system. For example, CMOS logic ICs can be

used in those parts of the system where low power dissipation is

required, whereas TTL can be used for those portions of the system

which require high speed of operation. Also, some function may be

easily available in TTL and others may be available in CMOS.

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