QoS profiling usingNoC Adaptive Design Information System
MPSOC August 14th 2006
Alain FANET
Founder & CTO
Arteris confidential - Sep 2005 2
Agenda• SoC complexity and cost constraints challenge on-
chip communication system architecture.• On-chip Data flows Quality (QoS) drive new
taxonomy, language and new implementation techniques
• ARTERIS proposes an Adaptive Information Systemenvironment to solve this designer’s challenge
• Let’s work on an example: Multimedia consumer SoC
• Next
Arteris confidential - Sep 2005 3
System Determinism
• By construction:– Time Division Multiplexing or Circuit switched
Network guarantees determinism by construction.
• By Cognition:– Adaptive Network Information System guarantees
determinism by traffic simulation & scheduling techniques
Arteris confidential - Sep 2005 4
NoC - Separate traffic classes
CPUCPU
Latency critical NoC
Latency critical NoC
Memory scheduler
Memory scheduler
Initiator Initiator Initiator Initiator Initiator
High throughput NoCHigh throughput NoC
TargetTarget Target Target Target Target
Low cost Control NoCLow cost Control NoC
Low cost Control NoCLow cost Control NoC
Arteris confidential - Sep 2005 5
NoC - Clustered DesignCPU DSP DMA
SRAM SRAM
Local NoCLocal NoC
Memory Scheduler
Peripheral SubSystem
CPU DSP DMA
SRAM SRAM
Local NoCLocal NoC
CPU DSP DMA
SRAM SRAM
Local NoCLocal NoC
CPU DSP DMA
SRAM SRAM
Local NoCLocal NoC
Top levelNoC
Arteris confidential - Sep 2005 6
NoC - 2D meshDSPDSP DMADMA
SRAMSRAM
XX
SRAMSRAM
DSPDSP DMADMA
SRAMSRAM
XX
SRAMSRAM
DSPDSP DMADMA
SRAMSRAM
XX
SRAMSRAM
DSPDSP DMADMA
SRAMSRAM
XX
SRAMSRAM
DSPDSP DMADMA
SRAMSRAM
XX
SRAMSRAM
DSPDSP DMADMA
SRAMSRAM
XX
SRAMSRAM
DSPDSP DMADMA
SRAMSRAM
XX
SRAMSRAM
DSPDSP DMADMA
SRAMSRAM
XX
SRAMSRAM
DSPDSP DMADMA
SRAMSRAM
XX
SRAMSRAM
DSPDSP DMADMA
SRAMSRAM
XX
SRAMSRAM
DSPDSP DMADMA
SRAMSRAM
XX
SRAMSRAM
DSPDSP DMADMA
SRAMSRAM
XX
SRAMSRAM
DSPDSP DMADMA
SRAMSRAM
XX
SRAMSRAM
DSPDSP DMADMA
SRAMSRAM
XX
SRAMSRAM
DSPDSP DMADMA
SRAMSRAM
XX
SRAMSRAM
DSPDSP DMADMA
SRAMSRAM
XX
SRAMSRAM
Arteris confidential - Sep 2005 7
SoC Application (*)initiatorsinitiators
targetstargets
(*) Authorized by STMicroelectronics Wireless Infrastructure Division
Arteris confidential - Sep 2005 8
Designer Challenges
• Different Application domains• Cost Of Design full determinism Networks• Information flows are asynchronous• QoS formal analysis is not applicable
Arteris confidential - Sep 2005 9
ARTERIS Approach
• Few data flows required “hard” determinism
• ARTERIS communication system is based on:– Highly flexible & structured Network On Chip architecture– An adaptive Network system information environment to
reach completeness in designing QoS.
Arteris confidential - Sep 2005 10
Structured NoC
Network Interface Unit
Physical implementation
Transport Protocol
Net
wor
k Fl
ows
Con
trol
Services Managem
entAXI, AHB, OCP, STBus, ….
Any technology process Any technology process
End-to-end flow control
Link control
Power mngt, SW support
Security
Perf monitoring
Power
Opt.
BW regulation
( point-to-point, GALS, multiple clock domains, …)
( packet transport, routing, network scheduling )
( IP Protocol converters)
Arteris confidential - Sep 2005 11
RTL environm
entPrototyping Application environment
ESL environment
QoS Dimensions
Completeness
QoS Dimensions
Completeness
StatisticsCollectionStatisticsCollection
Spe
cific
atio
ns
RTLemulation
RTLemulation
Adaptive Information System
Run-timeRun-time
SiliconSilicon
RealApplication
RealApplication
FPGAprototyping
FPGAprototyping
SoCPerformance
Profiling
SoCPerformance
Profiling
RTL simulation
RTL simulation
TargetedApplicationTargeted
Application
QoSDimensionsDescription
Per flow
QoSDimensionsDescription
Per flow
Critical flowFormal proofCritical flowFormal proof
NoCArchitectureExploration
NoCArchitectureExploration
Data flowssimulation
Data flowssimulation
NoC InstantiationGeneration
NoC InstantiationGeneration
StatisticsCollectionStatisticsCollection
TLMsimulation
TLMsimulation
ArchitectureExploration
time
ArchitectureExploration
time
Arteris confidential - Sep 2005 12
Models• Interface models
– IP sockets, connectivity map & memory map
• Data flow models– QoS dimensions / metrics (Throughput, latency, security
level) – Policies (level of service, tolerances, interdependency,
scheduling policies)
• Architectural models– Devices & network components
Arteris confidential - Sep 2005 13
Methods• Exploration time
– Data flow modeling• Modified Khan computing model• Very efficient data flow abstraction level• Communication modeling (scheduling, efficiency)• Target modeling
– Architectural modeling• Network architecture implementation & abstraction level
views (TLM, RTL) fully independent to data flow modeling • ARTERIS NoC Specific (topology, buffering, arbitration)
• Run-time– Selective NoC specific flow probing
Arteris confidential - Sep 2005 14
ARTERIS Tools
1
HW Acc.HW Acc.
OCPOCP
ARMARM
AXIAXI
MemoryCtrl
MemoryCtrl
STBSTB
I/OI/O
AHBAHB
NoC RTL ModelsNoC RTL Models
Application RequirementsApplication Requirements
ARTERIS
NoC
library
Customers’ IP
x x
xx x
Customer’s SoC
ARTERIS Generated NoC
x x
xx x
NIUNIU NIUNIU NIUNIU NIUNIU
ARTERIS NoCexplorer
ARTERIS NoCcompiler
Statistics collectorStatistics
collector
ARTERIS NoCprofiler
Arteris confidential - Sep 2005 15
Spe
cific
atio
nsQoS dimensions & Architectural models
TargetedApplicationTargeted
Application
QoSDimensionsDescription
Per flow
QoSDimensionsDescription
Per flow
Critical flowFormal proofCritical flowFormal proofArchitecture
Explorationtime
ArchitectureExploration
time
Arteris confidential - Sep 2005 16
Efficiency / Tolerance
Bandwidth / Tolerance
Latency
Bit rate
Security (addr. mapping)
Metrics
CPULatency guaranteed until a given throughput
C
Security, fault tolerant, firewall,
Guaranteed Data integrityA
CPU when not latency guaranteed
Best EffortE
MPEG or CDMA processingGuaranteed IP task throughput on long period within a given MTBF
D
Video In/Out, Sonet, Audio…Constant guaranteed throughput on short period
B
ExampleDefinitionClass
Quality taxonomy
Arteris confidential - Sep 2005 17
Data flow Policies
• Store• Load • Stress • Flows dependencies• Scheduling (random,…) • Flows synchronization • Flows Decoupling
Arteris confidential - Sep 2005 18
Architectural models
• IP Initiators: – IP sockets (AXI, OCP, AHB,..)
• IP Targets:– IP sockets (AXI, OCP, AHB,..)– DRAM device and scheduler– SRAM
• Network components– Switches (), Links (), FIFO()– Rate adapters (), Size converters ()– QoS components (end-to-end FC, arbiter, Bandwidth
regulator, multiclock domain..)– Chip-to-chip link
Arteris confidential - Sep 2005 19
QoS Components
< 45 nm65/45 nm130/90 nmTechnology
- New arbitration schemes (weightedfair queuing, scheduling, .. )
- Bandwidth Regulator- Events: DmaReq and Interrupts
- Application Pressure- Fixed Priority- Multiple Arbitration scheme
NoC Scheduling
- End-to-End NoC Flow control
- Threaded IP- Virtual Channel link
- Sparse packet crossbarNoC Predictability
> 100 I.P.< 100 I.P.< 30 I.P.Complexity / NoC Features
Arteris confidential - Sep 2005 20
End-to-end flow control components
InitiatorInitiator NIUNIU
TCRTCR NIUNIUTARGET
IPTARGET
IPNoC
Load/Store
Data/Ack
TCXTCX
InitiatorInitiator NIUNIU TCXTCX
Arteris confidential - Sep 2005 21
A
BC
NoC Scheduling - Arbitration
• Dynamic packet priority scheme– Per-output arbitration
• Priority propagates ahead of packets (pressure)
• When pressure is equal– Fixed Priority (reprogrammable)– Round-robin– Aging
• Pressure generation– By the IP: FIFO Threshold– By the NIU: Guaranteed bandwidth
Arteris confidential - Sep 2005 22
NoC Scheduling - Signalisation
DMADMA NIUNIUNIUNIU
TARGETIP
TARGETIP
TEventTEvent
NoC
TEventTEvent
Store/load
Ack/Data
Alarm signalAlarm signalNTTP event NTTP event
Arteris confidential - Sep 2005 23ESL environment
StatisticsCollectionStatisticsCollection
Spe
cific
atio
nsArchitecture Exploration
TargetedApplicationTargeted
Application
QoSDimensionsDescription
Per flow
QoSDimensionsDescription
Per flow
Critical flowFormal proofCritical flowFormal proof
NoCArchitectureExploration
NoCArchitectureExploration
Data flowssimulation
Data flowssimulation
TLMsimulation
TLMsimulation
ArchitectureExploration
time
ArchitectureExploration
time
Arteris confidential - Sep 2005 24
Wireless Multimedia Application Processor
On
Chi
p–
1 50
wire
sm
axd a
tapa
th
ProcessorAXI64@400MHz
DSPsAXI64@200MHz
DMAsAHB32@133MHz
BasebandAXI64@200MHz
DisplayAHB32@133MHz
CameraAHB32@100 Mhz
3D EngineAXI64@400MHzAHB32@133MHz
VideoAXI64@400 MhzAHB32@133MHzAHB64@133MHzAHB64@133MHz
DDR@266 Mhz
On Chip SRAM@133MHz
Flashperiph
Periph BusAHB32
@133MHz
Periph BusAHB32
@133 MHz
Netw
ork
On
C hipミ
150
wire
sm
axd a
tap a
t h
4 Processors and HW accelerators4 Processors and HW accelerators
DDR, On-chip SRAM & peripheral BusDDR, On-chip SRAM & peripheral Bus
Multi-use scenarios: game, comm, camera,..Multi-use scenarios: game, comm, camera,..
Multisocket AHB, AXI,..Multisocket AHB, AXI,..
Arteris confidential - Sep 2005 25
NoC Interfaces Modeling • Create your socket classes• Use them when defining your interface
– Socket have mandatory attributs• Width (aData)• Operating frequency (frequency)
– And optional ones• For initiators
– maxPendingTransaction– maxPendingTarget– maxPendingVolume
• For targets:– bankDelay– rwDelay– wrDelay
AXI SocketAXI Socket AHB SocketAHB Socket AXI SocketAXI Socket
SRAM SocketSRAM Socket DRAM SocketDRAM Socket
class myAxiSocket(AxiInitiator) :aData = 64frequency = 200e6
Classs myDramSocket(DramTarget) :aData = 64frequency = 200e6bankDelay = 50e-9turnDelay = 10e-9
class myIfce(NocInterface):class AXI_Socket(myAxiSocket) : passclass DRAM_Socket(myDramSocket): pass
…
Target model
Arteris confidential - Sep 2005 26
NoC explorer view
Arteris confidential - Sep 2005 27
Critical almost guaranteed and best effort
(E)
DMAUSB
Critical almost guaranteed and best effort
(E)
DMAUSB
Latency guaranteed until a given throughput
(C)
PROCESSORDSP
Latency guaranteed until a given throughput
(C)
PROCESSORDSP
Variable Guaranteed throughput on long period
(D)
3D EngineVIDEO
Variable Guaranteed throughput on long period
(D)
3D EngineVIDEO
Constant Guaranteed throughput on short period
( B)
CAMERA DISPLAY
BASEBAND
Constant Guaranteed throughput on short period
( B)
CAMERA DISPLAY
BASEBAND
BW in MB/s CAM DISP USB
frequency (MHz) 400 400 400 400 400 133 200 200 400 133 133 133 100 133 133 133 133 200 200
socket / Width AXI64 AXI64 AXI64 AXI64 AXI64 AHB32 AXI64 AXI64 AXI64 AHB32 AHB64 AHB64 AHB32 AHB32 AHB32 AHB32 AHB32 AXI64 AXI64
Port name D T I P #1 #2 #1 #2 VID3 VID4 VID1 VID2 #1 #2 #1 #2
Scenario 1 70 15 100 100 30 30 60 50 50 150 45 40 10 750 70.5%Scenario 2 70 15 100 100 30 30 120 140 140 45 40 10 840 78.9%Scenario 3 70 15 100 200 30 30 150 45 40 10 690 64.8%
SRAM 10 130Per1 20Per2 3 5 10Per3 3
Scenario1: Audio - Video - Telecom - StorageScenario 2: Video (encode only) - preview picture - audio - telecomScenario 3: Audio - Game - Telecom - storage
DSP
InitiatorTarget
DRAM
Processor 3D Engine VIDEO DMA BaseB Total(DRAM)
QoS Dimensions
Arteris confidential - Sep 2005 28
SoC traffic modeling
Arteris confidential - Sep 2005 29
Data Flow modeling
• Flows have the following attributes– initiator (initiator socket they are attached to)– target (target socket they access)– stress (the traffic they play– depth (size of the internal FIFO they model)– efficiency (percentage of the time they are not blocked)
• First, attach the Flow to an initiator socket• Then, define the destination of the flow
class myIfce(NocInterface):class AXI_Socket(myAxiSocket) : passclass DRAM_Socket(myDramSocket): pass
…
Class myFlow(Flow):initiator = target =stress =depth =efficiency =
myIfce.AXI_SocketmyIfce.DRAM_Socket
Target model
AXI SocketAXI Socket AHB SocketAHB Socket AXI SocketAXI Socket
SRAM SocketSRAM Socket DRAM SocketDRAM Socket
Arteris confidential - Sep 2005 30
• IP traffic are modelized at transaction level.• Uses store, load, posted store.
– A set of multiple transactions will create a trafic pattern wich is repeated until the simulation ended
Time (s)
Payload(Bytes)
4e-9 4e-9 6e-9 4e-9 4e-9
Ex:Store(32)
6e-9
/6e-9 + Load(16) /4e-9 * 2
6e-9
repeat
Data Flow Stress
Arteris confidential - Sep 2005 31
NoCexplorer view
• Stress definition for a 1600x1200 video flow– Doing 48 bytes stores (16 pixels) every 64ns– A line is composed of 100 accesses (1600 pixels)– Line frequency is 75kHz (every 13us)– A Frame is composed of 1200 lines– Frame frequency is 60Hz (every 16ms)
Stress = ()Stress = ()
( Store(48) / 64e-9 ) * 100 / 13e-6 * 1200 / 16e-3
class myIfce(NocInterface):class AXI_Socket(myAxiSocket) : passclass DRAM_Socket(myDramSocket): pass
…
Class myFlow(Flow):initiator = target =stress =depth =efficiency =
myIfce.AXI_SocketmyIfce.DRAM_Socket((Store(48)/64e-9*100/13e-
Target model
AXI SocketAXI Socket AHB SocketAHB Socket AXI SocketAXI Socket
SRAM SocketSRAM Socket DRAM SocketDRAM Socket
Arteris confidential - Sep 2005 32
myFlowmyFlow
Data flow Efficiency modeling
• Depth is the size of the IP FIFO modeled• What if the FIFO is full?
– Then, the stress gets stall• A 100% efficiency targeted for a flow means that it will be
never stalled.• If a stress which has 70% of efficiency means that it was
stalled 30% of the simulation time.• Comparison between simulated and targeted efficiency
will constitute information on the quality of QoS Dimensions
class myIfce(NocInterface):class AXI_Socket(myAxiSocket) : passclass DRAM_Socket(myDramSocket): pass
…
Class myFlow(Flow):initiator = target =stress =depth =efficiency =
myIfce.AXI_SocketmyIfce.DRAM_Socket((Store(48)/64e-9*100/13e-6*120
stress
depth
socket
The stress deposits the transaction in the FIFO
The socket sends/receives packets to/from the NoC
2560.7
Target model
AXI SocketAXI Socket AHB SocketAHB Socket AXI SocketAXI Socket
SRAM SocketSRAM Socket DRAM SocketDRAM Socket
Arteris confidential - Sep 2005 33
NoC topology modeling
ProcessorAXI64@400MHz
DSPsAXI64@200MHz
DMAsAHB32@133MHz
BasebandAXI64@200MHz
DisplayAHB32@133MHz
CameraAHB32@100Mhz
3D EngineAXI64@400MHzAHB32@133MHz
VideoAXI64@400Mhz
AHB32@133MHzAHB64@133MHzAHB64@133MHz
DDR@266Mhz
NIU
NIU
NIU
NIU
NIU
NIU
NIU
NIU
NIU
NIU
NIU
NIU
NIU
NIU
NIU
NIU
NIU
NIU
NIU
X
X
X
On Chip SRAM@133MHz
Flashperiph
Periph BusAHB32
@133MHz
Periph BusAHB32
@133MHz
X
NIU
NIU
NIU
NIU
Clock changer
Width changer
X
X
X
On
Ch
i p–
150
wir
esm
axd
a ta p
ath
ProcessorAXI64 @400MHz
DSPsAXI64 @200MHz
DMAsAHB32@133MHz
BasebandAXI64 @200MHz
DisplayAHB32@133MHz
CameraAHB32 @100 Mhz
3D EngineAXI64 @400MHz
AHB32@133MHz
VideoAXI64@400 Mhz
AHB32@133MHzAHB64@133MHzAHB64@133MHz
DDR@266 Mhz
On Chip SRAM@133MHz
Flashperiph
Periph BusAHB32
@133MHz
Periph BusAHB32
@133 MHz
Ne t
wo r
kO
nC
h ipミ
150
wir e
sm
axda
tap
ath
Arteris confidential - Sep 2005 34
Architecture exploration - no QoS
Arteris confidential - Sep 2005 35
QoS added - CPU Latency
ProcessorAXI64@400MHz
DSPsAXI64@200MHz
DMAsAHB32@133MHz
BasebandAXI64@200MHz
DisplayAHB32@133MHz
CameraAHB32@100Mhz
3D EngineAXI64@400MHzAHB32@133MHz
VideoAXI64@400Mhz
AHB32@133MHzAHB64@133MHzAHB64@133MHz
DDR@266Mhz
NIU
NIU
NIU
NIU
NIU
NIU
NIU
NIU
NIU
NIU
NIU
NIU
NIU
NIU
NIU
NIU
NIU
NIU
NIU
X
X
X
X Clock changer
Width changer
X
X
On Chip SRAM@133MHz
Flashperiph
Periph BusAHB32
@133MHz
Periph BusAHB32
@133MHz
X
NIU
NIU
NIU
NIU
ARBITER
Interface.SDC : [BankArb(40e-9), PrioArb([rx1]) , TurnArb(4e-9,20e-9)]
ARBITER
Interface.SDC : [BankArb(40e-9), PrioArb([rx1]) , TurnArb(4e-9,20e-9)]
Arteris confidential - Sep 2005 36
Architecture exploration cont’s
Arteris confidential - Sep 2005 37
Latency First results
Arteris confidential - Sep 2005 38
Bandwidth First Results
Arteris confidential - Sep 2005 39
Adding QoS component
ProcessorAXI64@400MHz
DSPsAXI64@200MHz
DMAsAHB32@133MHz
BasebandAXI64@200MHz
DisplayAHB32@133MHz
CameraAHB32@100Mhz
3D EngineAXI64@400MHzAHB32@133MHz
VideoAXI64@400Mhz
AHB32@133MHzAHB64@133MHzAHB64@133MHz
DDR@266Mhz
NIU
NIU
NIU
NIU
NIU
NIU
NIU
NIU
NIU
NIU
NIU
NIU
NIU
NIU
NIU
NIU
NIU
NIU
NIU
X
X
X
X Clock changer
Width changer
X
X
IP Fifo threshold directlydrives NIU.
Set pressure to level 2 when threshold is reached
On Chip SRAM@133MHz
Flashperiph
Periph BusAHB32
@133MHz
Periph BusAHB32
@133MHz
X
NIU
NIU
NIU
NIU
Bandwidth regulator,Increase pressure of 1 level when BW is under threshold
Bandwidth regulator,Increase pressure of 1 level when BW is under threshold
Arteris confidential - Sep 2005 40
Architecture exploration completeness
Arteris confidential - Sep 2005 41
NoC views Exportation to ESL world
QuickTime™ and aTIFF (Uncompressed) decompressor
are needed to see this picture.
QuickTime™ and aTIFF (Uncompressed) decompressor
are needed to see this picture.
SoC DesignerNoC
ESL views export
Arteris confidential - Sep 2005 42
RTL environm
entPrototyping Application environment
ESL environment
QoS Dimensions
Completeness
QoS Dimensions
Completeness
StatisticsCollectionStatisticsCollection
Spe
cific
atio
ns
RTLemulation
RTLemulation
NoC generation & performance monitoring
Run-timeRun-time
SiliconSilicon
RealApplication
RealApplication
FPGAprototyping
FPGAprototyping
SoCPerformance
Profiling
SoCPerformance
Profiling
RTL simulation
RTL simulation
TargetedApplicationTargeted
Application
QoSDimensionsDescription
Per flow
QoSDimensionsDescription
Per flow
Critical flowFormal proofCritical flowFormal proof
NoCArchitectureExploration
NoCArchitectureExploration
Data flowssimulation
Data flowssimulation
NoC InstantiationGeneration
NoC InstantiationGeneration
StatisticsCollectionStatisticsCollection
TLMsimulation
TLMsimulation
ArchitectureExploration
time
ArchitectureExploration
time
Arteris confidential - Sep 2005 43
NoC RTL views generation
ProcessorAXI64@400MHz
DSPsAXI64@200MHz
DMAsAHB32@133MHz
BasebandAXI64@200MHz
DisplayAHB32@133MHz
CameraAHB32@100Mhz
3D EngineAXI64@400MHzAHB32@133MHz
VideoAXI64@400Mhz
AHB32@133MHzAHB64@133MHzAHB64@133MHz
DDR@266Mhz
On Chip SRAM@133MHz
Flashperiph
Periph BusAHB32
@133MHz
Periph BusAHB32
@133MHz
Net
wor
k O
n C
hip
–15
0 w
ires
max
dat
apat
h
ProcessorAXI64@400MHz
DSPsAXI64@200MHz
DMAsAHB32@133MHz
BasebandAXI64@200MHz
DisplayAHB32@133MHz
CameraAHB32@100Mhz
3D EngineAXI64@400MHzAHB32@133MHz
VideoAXI64@400Mhz
AHB32@133MHzAHB64@133MHzAHB64@133MHz
DDR@266Mhz
On Chip SRAM@133MHz
Flashperiph
Periph BusAHB32
@133MHz
Periph BusAHB32
@133MHz
Net
wor
k O
n C
hip
–15
0 w
ires
max
dat
apat
h
ProcessorAXI64@400MHz
DSPsAXI64@200MHz
DMAsAHB32@133MHz
BasebandAXI64@200MHz
DisplayAHB32@133MHz
CameraAHB32@100Mhz
3D EngineAXI64@400MHzAHB32@133MHz
VideoAXI64@400Mhz
AHB32@133MHzAHB64@133MHzAHB64@133MHz
DDR@266Mhz
On Chip SRAM@133MHz
Flashperiph
Periph BusAHB32
@133MHz
Periph BusAHB32
@133MHz
NIU
NIU
NIU
NIU
NIU
NIU
NIU
NIU
NIU
NIU
NIU
NIU
NIU
NIU
NIU
NIU
NIU
NIU
NIUX
X
X
X
X
X
X
X
NIU
NIU
NIU
NIU
…. Generate NoC with NoCcompiler
Arteris confidential - Sep 2005 44
QoS Dimensions Monitoring
ProcessorAXI64@400MHz
DSPsAXI64@200MHz
DMAsAHB32@133MHz
BasebandAXI64@200MHz
DisplayAHB32@133MHz
CameraAHB32@100Mhz
3D EngineAXI64@400MHzAHB32@133MHz
VideoMhzMHzMHz
AHB64@133MHz
DDR@266Mhz
NIU
NIU
NIU
NIU
NIU
NIU
NIU
NIU
NIU
NIU
NIU
NIU
NIU
NIU
NIU
NIU
NIU
NIU
NIU
X
X
X
X
On Chip SRAM@133MHz
Flashperiph
Periph BusAHB32
@133MHz
Periph BusAHB32
@133MHz
X
NIU
NIU
NIU
NIU
X
X
JTagJTag
… using NoCprofiler
FS2API
StatisticsCollector
StatisticsCollector
Arteris confidential - Sep 2005 45
Optimized architecture
Aggregate throughput can be increase by 25% still meeting QoS requirements
Aggregate throughput can be increase by 25% still meeting QoS requirements
Reference worst-case simulation.
Reference worst-case simulation.
Strict Real Time
Loose Real Time
Arteris confidential - Sep 2005 46
SoC Results
• Improve Wire efficiency by x4 (40% wires saving)
• Reduce gates count by 2 (180Kgates)• Scale with performance roadmap• Improve Design Productivity• Improve Product Quality• Improve Power management
Arteris confidential - Sep 2005 47
Next
• Improve Description language Productivity• Increase implementation views
– Architectural models, floor-planning, Gates & Powerestimates
• Performance Monitoring directly coupled to architecture exploration tools
• Support methodology for NoC Benchmarking
Arteris confidential - Sep 2005 48
NoC Benchmarking QoS script….
…..…..…..
Scenario 1
QoS script….…..…..…..
Scenario 1
languageArchitectureExplorationArchitectureExploration
BFM
BFM
.h
QoS script….…..…..…..
Scenario 1
QoS script….…..…..…..
Scenario 1
QoS script….…..…..…..
Scenario 1
QoS script….…..…..…..
Scenario 1
QoS script….…..…..…..
Scenario 1
QoS script….…..…..…..
Scenario 1
QoS script….…..…..…..
Scenario 1
QoS script….…..…..…..
Scenario 1
RTLB
FMB
FM
ModelSystemCTLM
(self checking)
TT
TT
TT
Applications Suite
KgatesWires,Power
KgatesWires,Power
Arteris confidential - Sep 2005 49
Conclusion
• Adaptive network communication system is the solution to scale
• QoS dimensions profiling at architecture exploration time and run time
• ARTERIS provides an innovative Adaptive Network Information System environment to solve this designer’s challenge