QUARTUS II INTRODUCTION USING VERILOG DESIGN

A TYPICAL FPGA CAD FLOWDesign Entry

QUARTUS II DEVELOPMENT SYSTEM Fully-integrated Design Tool

Multiple Design Entry Methods Logic Synthesis Place and Route Simulation (functional and timing) Timing and Power Analysis Device Programming and Configuration

Design Entry (1 of 2)The desired circuit is specified by:A schematic diagramA hardware description language, such as:VerilogVHDL AHDL

Design Entry (2 of 2)

Design Entry by a schematic diagram

Design Entry by a hardware description language

SynthesisThe entered design is synthesized into a circuit that consists of the logic elements (LEs) provided in the FPGA chip.LE is the smallest unit of logic of Alteras FPGA. Its compact and provides advanced features with efficient logic ultilization.This course doesnt cover the architecture of Alteras FPGA

LE logic element

Fitting (placement and routing)The placement of the LEs defined in the netlist into the LEs in an actual FPGA chip, also choose routing wires in the chip to make the required connections between specific LEs

Timing AnalysisAnalyze the propagation delays along the various paths in the fitted circuit

Timing SimulationThe fitted circuit is tested to verify both its functional correctness and timing

Programming and ConfigurationThe design circuit is implemented in a physical FPGA chip by programming the configuration switches that configure the LEs and establish the required wiring connections

Quartus II Project ManagementWhat is a Project ? - A logic circuit or subcircuit - A project is: + checked for design entry errors + compiled + simulated (functional or timing) + analyzed for timing + used to generate programming fileQuartus II works on one project at a time and keeps all information for that project in a single directory (folder).

Quartus II Project New ProjectSelect File > New Project WizardNew Project Wizard help us create a new project and preliminary project settings, including the following:Project name and directoryName of the top-level design entityProject files and librariesTarget device family and deviceEDA tool settingsYou can change or add the settings of the project with the Settings command (Assignment menu)

Quartus II Project Directory, Name, Top-Level Entity

Quartus II Project Add FilesTo specify existing files should be included in the project.

Quartus II Project Family and Device SettingsTo specify the type of device in which the designed circuit will be implemented. In case of DE2 board, we choose: The device is EP2C35F672C6 which is the FPGA used on DE2 board

Quartus II Project EDA Tools SettingsTo specify any third-party tools that should be used. EDA is means Electronic Design Automation, a commonly used term for CAD software for electronic circuits.

Quartus II - Summary

Design Entry using Verilog An examplemodule light(x1,x2,f);inputx1,x2;outputf;assignf = (x1&~x2)|(~x1&x2);endmodule

Design Entry using Verilog Quartus II Text Editor (1 of 6)Select File > New to get the right figure, then choose Verilog HDL File, and click OK

Design Entry using Verilog Quartus II Text Editor (2 of 6)Quartus II open the Text Window Editor. The default name of design file is Verilog1.v. The first step is to specify a name for the file that will be created. Select File > Save As

Design Entry using Verilog Quartus II Text Editor (3 of 6)

Design Entry using Verilog Quartus II Text Editor (4 of 6)Type the Verilog code of our design into Text Editor.Save the file light.v by choose File > Save.

Design Entry using Verilog Quartus Text Editor (5 of 6)

Design Entry using Verilog Quartus II Text Editor (6 of 6)We can change the options of Text Editor of Quartus II by the settings in Tools > Options > Text Editor

Design Entry using Verilog Adding Design FilesIf light.v is not a part of the project, this file must be added to the project. For example: if you did not use the Quartus II Text Editor, then you place a copy of the file light.v, which you created using some other text editor, into the directory introductorial. To add this file to the project, click on the light.v file and click Open

Compilation (1 of 2)Verilog code in the design file light.v is processed by the application program called the Compiler.The Compiler : Analyze the code Synthesize the circuit Generate an implementation of the circuit for the target chip.Selecting Processing > Start Compilation

Compilation (2 of 2)

Simulating Analysis & Synthesis1

Simulating Analysis & Synthesis

Simulating Start EDA Nestlist Writer2

Simulating Start EDA Nestlist Writer

Simulating Create VWF file3

Simulating

Simulating Set End Time45

Simulating Insert Node or Bus67

Simulating89

Simulating10

SimulatingUncompleted Waveform

Simulating Editing waveformEdit waveform

Simulating Choose Simulator1112

Simulating RunRun Functional Simulation

Simulating Done!Completed Waveform

Some references"Altera's QuartusII software is such a superior development environment that I am quickly forgetting about any other PLD (programmable logic device) design tool."Can Nguyen, Principal Staff Engineer, BroadbandCommunications Sector, Motorola

"QuartusII software is superior compared to other programmable logic tool offerings, which allows us to focus our time on meeting customer needs, rather than laboring over tool usage.Dr. Greg Caso, VP Engineering, Escape Communications