QUESTIONBANK - drnnce.ac.in NEW.pdf · QUESTIONBANK SubjectCode/Subject: EC2354 / VLSI DESIGN ......

Department of ECE VLSI DESIGN

Dr. NAVALAR NEDUNCHEZHIYAN COLLEGE OF

ENGINEERING

Tholudur, Cuddalore (Dt) –606 303.

DEPARTMENTOFELECTRONICSANDCOMMUNICATIONENGINEERING

QUESTIONBANK

SubjectCode/Subject: EC2354 / VLSI DESIGN

Name : K.SENTHILNATHAN Designation : ASSISTANT PROFESSOR

Dept : ECE Semester : VIII

UNIT I CMOS TECHNOLOGY

A brief History-MOS transistor, Ideal I-V characteristics, C-V characteristics, Non ideal IV

effects, DC transfer characteristics - CMOS technologies, Layout design Rules, CMOS process

enhancements, Technology related CAD issues, Manufacturing issues

PART-A (1 Mark)

1. A unit of logic in an FPGA that is made up of multiple smaller logic modules and a local programmer

interconnect that is used to connect internal logic modules is called a ________.

A.bed-of-nails B.boundary scan C.CLB D.CPLD

2. The ________ is the most popular standard logic device family today.

A.TTL B.CMOS C.ECLD .None of the above

3. Most FPGA logic modules utilize a(n) ________ approach to create the desired logic functions.

A.AND array B.Look-up table C.OR array D.AND and OR array

4. A macrocell is ________.

A.part of a PAL or GAL B.a type of one-time programmable SPLD

C.an example of intellectual property D.a logic array block

5. The final step in a design flow in which the logic design is implemented in the target device is called

________.

A.design entry B.simulation C.downloading D.compiling

6. Using a hardware solution for a digital system is always ________ than a software solution.

A.slower B.harder C.easier D.faster

7. The programming technologies that are used in FPGA devices include SRAM, flash, and antifuse, with

________ being the most common.

A.SRAM B.flash C.antifuse D.SRAM and flash

8. Full custom ICs can operate at ________ and require the ________.

A.lowest speed, largest die area B.lowest speed, smallest die area

C.highest speed, largest die area D.highest speed, smallest die area

9. complex programmable logic device that consists of multiple SPLD arrays with programmable

interconnections is called a ________.


A.bed-of-nails B.boundary scan C.CLB D.CPLD

10. Design costs for standard cell ASICs are ________ those for MPGAs.

a. lower than b. about the same as c. higher than d. none of the above

11. Gated arrays are ________ circuits that offer hundreds of thousands of gates.

A. VLSI B.full custom C.LSI D.ULSI

12. The field programmable logic array was the first ________ programmable logic device.

A.understandable B.logic array C.multifunction D.nonmemory

13. The ________ has a physical channel between the drain and source.

A.D-MOSFET B.E-MOSFET C.V-MOSFET D.[NIL]

14. Which of the following statements is incorrect?

a) CMOS circuitry is more difficult to fabricate than NMOS or PMOS as it required devices of both polarities.

b) CMOS gates have very good noise immunity that is typically 10% of the supply voltage.

c) When a CMOS gate is static it has negligible power consumption.

d) CMOS gates have logic levels close to the supply rails.

15. The cells in a FPGA may contain registers, look-up tables and memory.

a) True b) False

16. Which of the following is preferred while placing macros ___?

a. Macros placed center of the die

b. Macros placed left and right side of die

c. Macros placed bottom and top sides of die

d. Macros placed based on connectivity of the I/O

17. The value of VGS that makes ID approximately zero is the

A. pinch-off voltage. B. cutoff voltage. C. breakdown voltage. D. ohmic voltage.

18. The JFET is always operated with the gate-source pn junction ________ -biased.

A. forward B. reverse

19. High input resistance for a JFET is due to

A. a metal oxide layer. B. a large input resistor to the device.

C. an intrinsic layer. D. the gate-source junction being reverse-biased.

Answers:

1 2 3 4 5 6 7 8 9 10

c b b a c d a d d d

11 12 13 14 15 16 17 18 19

c d a b a d b b d

PART-B (2 MARKS)

20. What are four generations of Integration Circuits? [APRIL-2009]

1)SSI (Small Scale Integration) 2)MSI (Medium Scale Integration)

3)LSI (Large Scale Integration) 4) VLSI (Very Large Scale Integration)

21. Give the advantages of IC[APRIL-2008]?

1)Size is less 2)High Speed 3)Less Power Dissipation

22. Give the variety of Integrated Circuits? [Nov-2004]

1)More Specialized Circuits 2) Application Specific Integrated Circuits(ASICs) Systems-On-Chips


23. Give the basic process for IC fabrication [Nov-2005]

1.Silicon wafer Preparation, 2. Epitaxial Growth, 3. Oxidation, 4. Photolithography,

5.Diffusion,6.Ion Implantation, 7.Isolation technique, 8.Metallization, 9.Assembly processing & Packaging

24. What are the various Silicon wafer Preparation? [APRIL-2007]

1.Crystal growth & doping, 2. Ingot trimming & grinding, 3.Ingot slicing, 4.Wafer polishing & etching, 5.

Wafer cleaning.

25. Different types of oxidation? [APRIL-2008]

Dry & Wet Oxidation

26. What is the transistors CMOS technology provides?

N-type transistors & p-type transistors.

27. What are the different layers in MOS transistors?

Drain , Source & Gate

28. What is Enhancement mode transistor? [APRIL-2009]

The device that is normally cut-off with zero gate bias.

29. What is Depletion mode Device?

The Device that conduct with zero gate bias.

30. When the channel is said to be pinched –off? [APRIL-2008]

If a large Vds is applied this voltage with deplete the Inversion layer .This Voltage effectively pinches off the

channel near the drain.

31. Give the different types of CMOS process? [APRIL-2009]

p-well process, n-well process, Silicon-On-Insulator Process, Twin- tub Process

32. What are the steps involved in twin-tub process?[ Nov-2006]

Tub Formation, Thin-oxide Construction, Source & Drain Implantation, Contact cut definition,

Metallization.

33. What are the advantages of Silicon-on-Insulator process? [APRIL-2009]

No Latch-up, Due to absence of bulks transistor structures are denser than bulk silicon.

34. Define Short Channel devices?

Transistors with Channel length less than 3- 5 microns are termed as Short channel devices. With short

channel devices the ratio between the lateral & vertical dimensions are reduced. Non- Saturated Region

Saturated Region

35. Define Threshold voltage in CMOS?[ Nov-2005]

The Threshold voltage, VT for a MOS transistor can be defined as the voltage applied between the gate

and the source of the MOS transistor below which the drain to source current, IDS effectively drops to zero.

36. What is Body effect?

The threshold voltage VT is not a constant w. r. to the voltage difference between the substrate and the

source of MOS transistor. This effect is called substrate-bias effect or body effect.

PART-C (16 MARKS)

37. Derive the CMOS inverter DC characteristics and obtain the relationship for output voltage at

different region in the transfer characteristics. [ Nov-2004]

38. Explain with neat diagrams the various CMOS fabrication technology [APRIL-2009]

39. Explain the operation of PMOS Enhancement transistor [APRIL-2008]

40. Explain the threshold voltage equation [Nov-2006]

41. Explain the silicon semiconductor fabrication process. [APRIL-2006]

42. Derive and explain the. [APRIL-2007]

(i) Threshold voltage equation, (ii) MOS DC equation.


UNIT II CIRCUIT CHARACTERIZATION AND SIMULATION

Delay estimation, Logical effort and Transistor sizing, Power dissipation, Interconnect, Design

margin, Reliability, Scaling- SPICE tutorial, Device models, Device characterization, Circuit

characterization, Interconnect simulation

PART-A (1 MARK)

43. Propagation delay is important because ________.

A. the logic gates must be given a short break during each clock cycle or else they will overheat

B. it limits the maximum operating frequency of a gate

C. it is a measure of how long the clock must be applied to the gate before it will make the required decision

D. all the gates in a system must have the same propagation times in order to be compatible

44. The output current for a LOW output is called a(n) ________.

A.sink current B.ground current C.exit current D.fan-out

45. The proliferation of small handheld consumer equipment such as digital video cameras, cellular

phones, handheld computers (________), portable audio systems, and other devices has created a need for

logic circuits in very small packages.

A. HDLs B. GDAs C. PDAs D. TTLs

46.The lower transistor of a totem-pole output is saturated when the gate output is ________.

A. overdriven B. HIGH C. LOW D. malfunctioning

47.The time it takes for an input signal to pass through internal circuitry and generate the appropriate

output effect is known as ________.

A. fan-out B. propagation delay C. rise time D. fall time

48.________ is about twice as fast as P-MOS.

A. CMOS B. DMOS C. MOD D. N-MOS

49.P-MOS and N-MOS ________.

A.represent MOSFET devices utilizing either P-channel or N-channel devices exclusively within a given gate

B.are enhancement-type CMOS devices used to produce a series of high-speed logic known as 74HC

C.represent positive and negative MOS-type devices that can be operated from differential power supplies and are

compatible with operational amplifiers

D.None of the above are.

50.________ is ideally suited for applications using battery power or battery backup power.

A. MOS B. P-MOS C. N-MOS D. CMOS

51.A logic probe is placed on the input of a digital circuit and the probe lamp blinks slowly, indicating

________.

A. that an open or bad logic level exists B. a high level output

C. a high-frequency pulse train D. that the supply voltage is low

52.The HIGH logic level for a standard TTL output must be at least ________.

A. 2.4 V B. 2 V C. 0.8 V D. 5 V

53. The term "hex inverter" refers to:

A. an inverter that has six inputs B. six inverters in a single package

C. a six-input symbolic logic device D. an inverter that has a history of failure

54. The basic logic gate whose output is the complement of the input is the:

A. OR gate B. AND gate C. inverter D. comparator


55.What is the name of a digital circuit that produces several repetitive digital waveforms?

A. an inverter B. an OR gate C. a Johnson shift counterD. an AND gate

56. The logic gate that will have HIGH or "1" at its output when any one (or more) of its inputs is HIGH is

a(n):

A. OR gate B. AND gate C. NOR gate D. NOT operation

57.CMOS IC packages are available in ________.

A. DIP configuration B. SOIC configuration C. DIP and SOIC configurations

D. neither DIP nor SOIC configuration

58.How many entries would a truth table for a four-input NAND gate have?

A. 2 B. 8 C. 16 D. 32

59.Filler cells are added ___.

a. Before Placement of std cells b. After Placement of Std Cells

c. Before Floor planning d. Before Detail Routing

60.More IR drop is due to ___.

a. Increase in metal width b. Increase in metal length

c. Decrease in metal length d. Lot of metal layers

61.PLAs, CPLDs, and FPGAs are all which type of device?

A. SLD B. PLD C. EPROM D. SRAM

62.A FPGA is an array of programmable logic blocks that are interconnected by OR gates.

A. True B. False

63.A ripple counter's speed is limited by the propagation delay of:

A. each flip-flop B. all flip-flops and gates C. the flip-flops only with gates

D. only circuit gates

64.Which type of device may be used to interface a parallel data format with external equipment's serial

format?

A. key matrix B. UART C. memory chip D. serial-in, parallel-out

65.A digital logic device used as a buffer should have what input/output characteristics?

A. high input impedance and high output impedance

B. low input impedance and high output impedance

C. low input impedance and low output impedance

D. high input impedance and low output impedance

66. CMOS logic is probably the best all-around circuitry because of its:

A. packing density B. low power consumptionC. very high noise immunity

D. low power consumption and very high noise immunity

67. The time needed for an output to change as the result of an input change is known as:

A. noise immunity B. fanout C. propagation delay D. rise time

68. Low power consumption achieved by CMOS circuits is due to which construction characteristic?

A. complementary pairs B. connecting pads C. DIP packages

D. small-scale integration

Answers:

49 50 51 52 53 54 55 56 57 58

a a c c a b d a d b

59 60 61 62 63 64 65 66 67 68

c c c d b b b a b d


PART-B (2 MARKS)

69. What are the different MOS layers? [APRIL-2009]

n-diffusion, p-diffusion, Polysilicon, Metal

70. What is pull down device?[ Nov-2008]

A device connected so as to pull the output voltage to the lower supply voltage usually 0V is called pull

down device.

71. What is pull up device?[ Nov-2006]

A device connected so as to pull the output voltage to the upper supply voltage usually VDD is called pull

up device.

72. Why NMOS technology is preferred more than PMOS technology?

N- channel transistors has greater switching speed when compared tp PMOS transistors.

73. What are the different operating regions for an MOS transistor?

Cutoff region

74. What is Stick Diagram? [APRIL-2008]

It is used to convey information through the use of color code. Also it is the cartoon of a chip layout.

75. What are the uses of Stick diagram?

It can be drawn much easier and faster than a complex layout. These are especially important tools for layout

built from large cells.

76. Give the various color coding used in stick diagram? [APRIL-2009]

Green – n-diffusion, Red- polysilicon, Blue –metal, Yellow- implant Black-contact areas.

77. Compare between CMOS and bipolar technologies [Nov-2004]

CMOS Technology Bipolar technology

Low static power dissipation

High input impedance (low drive

current)

Scalable threshold voltage

High noise margin

High packing density

High delay sensitivity to load (fanout

limitations)

Low output drive current

Bidirectional capability

A near ideal switching device

High power dissipation

Low input impedance (high drive

current)

Low voltage swing logic

Low packing density

High output drive current

Essentially unidirectional

78. Define Rise time

Rise time,tr is the time taken for a waveform to rise from 10% to 90% of its steady- state value.

79. Define Fall time [Nov-2005]

Fall time, tf is the time taken for a waveform to fall from 90% to 10% of its steady-state value.

80. Define Delay time

Delay time, td is the time difference between input transition (50%) and the 50% output level. This is the time

taken for a logic transition to pass from input to output.


82. Give the different symbols for transmission gate. [APRIL-2008]

83. What is Channel-length modulation?

The current between drain and source terminals is constant and independent of the applied voltage over the

terminals. This is not entirely correct. The effective length of the conductive channel is actually modulated by the

applied VDS, increasing VDS causes the depletion region at the drain junction to grow, reducing the length of the

effective channel.

84. What is Latch – up? [Nov-2006]

Latch up is a condition in which the parasitic components give rise to the establishment of low resistance

conducting paths between VDD and VSS with disastrous results. Careful control during fabrication is necessary

to avoid this problem.

85. What is BiCMOS Technology?

It is the combination of Bipolar technology & CMOS technology.

86. What are the basic processing steps involved in BiCMOS process?

Additional masks defining P base region, N Collector area, Buried Sub collector (SCCD)

Processing steps in CMOS process

87. What are the advantages of CMOS process? [Nov-2005]

Low power Dissipation, High Packing density, Bi directional capability

88. What are the advantages of CMOS process? [APRIL-2007]

Low Input Impedance, Low delay Sensitivity to load.

89. What is the fundamental goal in Device modeling? [APRIL-2009]

To obtain the functional relationship among the terminal electrical variables of the device that is to be modeled.

PART-C (16 MARKS)

90. Explain the Transmission gate and the tristate inverter briefly. [Nov-2005]

92. Explain about the various non ideal conditions in MOS device model. [APRIL-2008]

93. Explain with neat diagrams the Multiplexer and latches using transmission Gate.

94. Explain that how the MOS transistor is to be analysed by the small scale models.

95. Explain the complimentary CMOS inverter DC characteristics.[Nov-2004]

96. Write short notes on [APRIL-2009]

(i) Noise Margin, (ii) Rise Time, (iii) Fall Time.


UNIT III COMBINATIONAL AND SEQUENTIAL CIRCUIT DESIGN

Circuit families –Low power logic design – comparison of circuit families – Sequencing static

circuits, circuit design of latches and flip flops, Static sequencing element methodology-

sequencing dynamic circuits – synchronizers.

PART-A (1Mark)

97. What is meant by the rise time of a waveform?

a) The time taken for the waveform to increase from 10% to 90% of the height of a step.

b) The time taken for the waveform to increase from 0% to 90% of the height of a step.

c) The time delay from when the input step changes by 50% to when the output step changes by 50%.

d) The time taken for the waveform to decrease from 90% to 10% of the height of a step.

98. What is the cause of storage time in a bipolar transistor?

a) The inertia of the minority charge carriers.

b) The time taken to remove excess charge stored in the base region as a result of saturation.

c) The inertia of the majority charge carriers.

d) The 'memory effect' of the device.

99.What is meant by the fan-out of a logic gate?

a) The physical distance between the output pins on the device.

b) The number of other gates that can be connected to one of the gate's inputs.

c) The number of other gates that can be connected to the gate's output.

d) The amount of cooling required by the gate.

100.Which of the following statements is incorrect?

a) CMOS circuitry is more difficult to fabricate than NMOS or PMOS as it required devices of both polarities.

b) CMOS gates have very good noise immunity that is typically 10% of the supply voltage.

c) When a CMOS gate is static it has negligible power consumption.

d) CMOS gates have logic levels close to the supply rails.


a) TTL logic normally operates from a single 5 V supply.

b) TTL devices have logic levels of about 3.4 V and 0.2 V.

c) Standard TTL devices have a propagation delay that is dominated by the storage time of the bipolar transistors

used.

d) TTL logic has very low power consumption and is therefore widely used in highly integrated components.


a) ECL is widely used in high-speed applications.

b) ECL suffers from low noise immunity.

c) ECL is one of the fastest forms of electronic logic.

d) ECL has high power consumption.

103. What should be done with an unused TTL input that is required to be at logical 1?

a) It should be connected directly to the zero volt supply rail.

b) It should be connected directly to the positive supply rail.

c) It should be tied to the positive supply rail through an appropriate resistor.

d) It should be left disconnected.


104. What distinguishes CMOS logic gates that have the letter 'T' within their part numbers (for example

74HCT00)?

a) They are constructed using a Teflon substrate.

b) They use the supply voltages and logic levels of TTL gates.

c) They are suitable for terahertz operation.

d) They are very high-speed devices.

105. Which 'law' describes the exponential growth of integrated circuit complexity?

a)Faraday's law. b)Nyquist's theorem.

c)Moore's law. d)Lenz's law.

106.The cells in a FPGA may contain registers, look-up tables and memory.

a) True b) False


a) Some PLDs are programmed using electrically operated switches.

b) Some PLDs are programmed using anti-fuses that are selectively joined.

c) Some PLDs are programmed using mechanical switches.

d) Some PLDs are programmed using fuses that are selectively blown.

108. Communications within a microprocessor take place over a number of serial buses.

a) True b) False

109.What name is given to the common microcomputer architecture that uses a single block of memory to

store both programs and data?

a) Contemporary architecture. b) Harvard architecture.

c) RISC architecture. d) Von Neumann architecture.

110. A microcomputer stack is a form of memory structure. What mnemonic describes the operation of

this structure?

a)FILO. b)LIFO. c)FIFO. d)LILO.


a) Dynamic RAM stores information by charging or discharging capacitors.

b) RAM is volatile.

c) Static RAM stores information by energizing or de-energising inductors.

d) RAM is memory that can be written and read quickly.


a) EPROMs can be erased using an ultraviolet light source.

b) ROM devices must be programmed by the chip manufacturer.

c) EEPROMs can be written to (programmed) as well as read from.

d) ROM devices are non-volatile.

113.How many address lines would be found on a 128-kbyte memory device (assuming that this is arranged

as an array of 8-bit registers)?

a)13 b)15 c)17 d)19

114.Which of the following materials is not a semiconductor?

a) Silicone. b) Germanium.

c) Gallium arsenide. d) Gallium nitride.


a) At room temperatures, pure semiconductors make excellent conductors.

b) Doping pure semiconductor material with small amounts of donar impurities produces an n-type

semiconductor.

c) The dominant charge carriers within a doped semiconductor are called majority charge carriers.

d) Conduction within pure semiconductors is termed intrinsic conduction.


116. What is a typical conduction voltage for a silicon diode?

a) 0.25 V. b) 0.5 V. c) 0.7 V. d) 1.1 V.

117. While design normally follows a 'top-down' approach, testing is normally performed 'bottom-up'.

a) True b) False

118. What implementation method would be appropriate for an application having a complexity equivalent

to about 20 standard logic gates?

a) A series of standard CMOS or TTL gate devices. b) A simple PLD.

c) A complex PLD or FPGA. d) A PLC.

119. High volume applications will tend to suggest the use of ready-made systems to reduce development

cost.

a) True b) False

120. What name is given to a file produced by a schematic capture program that defines the

interconnections between the components of a circuit?

a) A parts count. b) A development file.

c) A circuit file. d) A net list.

121. SPICE is one of the most widely used simulation programs. What does SPICE stand for?

a) Simulation Program with Integrated Circuit Emphasis.

b) Self-Projecting Implementation of Circuit Examples.

c) Simulation Protocol for Internal Circuit Exploration

d) Simulation Program with In-Circuit Emulation.

122. SPICE can be used to simulate both analogue and digital circuitry.

a) True b) False

123. Which of the following statements relating to PLD design and programming packages is incorrect?

a) PLD design packages often produce a fuse map that can be loaded into a programmer to define the connectivity

within the component.

b) The process of programming and verifying a PLD generally takes a few minutes.

c) After programming the PLD is usually automatically tested.

d) PLD design packages often define a set of test vectors that will be used to test the programmed component.

124.Which of the following languages is not appropriate for specifying an electronic system? a)Z.

b)VDM. c)VHDL. d)C++.

125.Which of the following handles the interconnection between most of the devices and the CPU?

A) Northbridge B) RAM C) ROM D) Southbridge

126.Which chip acts as a clock to keep the current date and the time?

A) CMOS B) DVRAM C) RAM D) ROM

127.Which chip is used to store information that describes specific device parameters?

A) BIOS B) CMOS C) ROM D) system BIOS

128.How can you easily clear the CMOS, including clearing the password?

A) Unplug the PC B) Unplug the PC and remove the CMOS battery.

C) Issue a ClearCMOS command from the command line. D) This can’t be done.

129.From where can the boot option be selected?

A) Advanced BIOS Features B) Advanced Chipset Features

C) CPU Soft menu D) Power management Setup

130.Intrinsic semiconductor material is characterized by a valence shell of how many electrons?

A. 1 B. 2

C. 4 D. 6

131.Which material may also be considered a semiconductor element?

A. carbon B. ceramic C. mica D. argon


Answers:

97 98 99 100 101 102 103 104 105 106

a b c b d a c b c a

107 108 109 110 111 112 113 114 115 116

c b d a c b c a a a

117 118 119 120 121 122 123 124 125 126

a b d a a b d d d b

127 128 129 130 131

b a a a c

PART-B (2 MARKS)

132. What are four generations of Integration Circuits? [APRIL-2009]

1)SSI (Small Scale Integration) 2)MSI (Medium Scale Integration)

3)LSI (Large Scale Integration) 4) VLSI (Very Large Scale Integration)

133. Give the advantages of IC[APRIL-2008]?

1)Size is less 2)High Speed 3)Less Power Dissipation

134. Give the variety of Integrated Circuits? [Nov-2004]

1)More Specialized Circuits 2) Application Specific Integrated Circuits(ASICs) Systems-On-Chips

135. Give the basic process for IC fabrication [Nov-2005]

Silicon wafer Preparation, Epitaxial Growth, Oxidation, Photolithography, Diffusion

Ion Implantation, Isolation technique, Metallization, Assembly processing & Packaging

136. What are the various Silicon wafer Preparation? [APRIL-2007]

Crystal growth & doping, Ingot trimming & grinding, Ingot slicing, Wafer polishing & etching, Wafer

cleaning.

137. Different types of oxidation? [APRIL-2008]

Dry & Wet Oxidation

138. What is the transistors CMOS technology provides?

n-type transistors & p-type transistors.

139. What are the different layers in MOS transistors?

Drain , Source & Gate

140. What is Enhancement mode transistor? [APRIL-2009]

The device that is normally cut-off with zero gate bias.

141. What is Depletion mode Device?

The Device that conduct with zero gate bias.

142. When the channel is said to be pinched –off? [APRIL-2008]

If a large Vds is applied this voltage with deplete the Inversion layer .This Voltage

effectively pinches off the channel near the drain.

143. Give the different types of CMOS process? [APRIL-2009]

p-well process, n-well process, Silicon-On-Insulator Process, Twin- tub Process

144. What are the steps involved in twin-tub process?[ Nov-2006]

Tub Formation, Thin-oxide Construction, Source & Drain Implantation, Contact cut definition,

Metallization.

145. What are the advantages of Silicon-on-Insulator process? [APRIL-2009]

No Latch-up, Due to absence of bulks transistor structures are denser than bulk silicon.


146. Define Short Channel devices?

Transistors with Channel length less than 3- 5 microns are termed as Short channel

devices. With short channel devices the ratio between the lateral & vertical dimensions

are reduced. Non- Saturated Region Saturated Region

147. Define Threshold voltage in CMOS?[ Nov-2005]

The Threshold voltage, VT for a MOS transistor can be defined as the voltage applied

between the gate and the source of the MOS transistor below which the drain to source

current, IDS effectively drops to zero.

148. What is Body effect?

The threshold voltage VT is not a constant w. r. to the voltage difference between the

substrate and the source of MOS transistor. This effect is called substrate-bias effect or

body effect.

PART-C (16 MARKS)

149. Derive the CMOS inverter DC characteristics and obtain the relationship for output voltage at

different region in the transfer characteristics.[ Nov-2004]

150. Explain with neat diagrams the various CMOS fabrication technology [APRIL-2009]

151. Explain the operation of PMOS Enhancement transistor [APRIL-2008]

152. Explain the threshold voltage equation [Nov-2006]

153. Explain the silicon semiconductor fabrication process. [APRIL-2006]

154. Derive and explain the. [APRIL-2007]

(i) Threshold voltage equation,

(ii) MOS DC equation.

UNIT IV

CMOS TESTING

Need for testing- Testers, Text fixtures and test programs- Logic verification- Silicon debug

principles- Manufacturing test – Design for testability – Boundary scan

PART-A (1 MARK)

155. How many data select lines are required for selecting eight inputs?

A.1 B.2 C.3 D.4

156. The implementation of simplified sum-of-products expressions may be easily implemented into actual

logic circuits using all universal ________ gates with little or no increase in circuit complexity. (Select the

response for the blank space that will BEST make the statement true.)

A.AND/OR B.NAND C.NOR D.OR/AND

157.As a technician you are confronted with a TTL circuit board containing dozens of IC chips. You have

taken several readings at numerous IC chips, but the readings are inconclusive because of their erratic

nature. Of the possible faults listed, select the one that most probably is causing the problem.

A.A defective IC chip that is drawing excessive current from the power supply

B.A solar bridge between the inputs on the first IC chip on the board

C.An open input on the first IC chip on the board

D.A defective output IC chip that has an internal open to Vcc


158.Which gate is best used as a basic comparator?

A.NOR B.OR C.Exclusive-OR D.AND

159.In VHDL, macrofunctions is/are:

A.digital circuits. B.analog circuits. C.a set of bit vectors.D.preprogrammed TTL device

160A logic probe is placed on the output of a gate and the display indicator is dim. A pulser is used on each

of the input terminals, but the output indication does not change. What is wrong?

A.The output of the gate appears to be open.

B.The dim indication on the logic probe indicates that the supply voltage is probably low.

C.The dim indication is a result of a bad ground connection on the logic probe.

D.The gate may be a tristate device.

161.What will a design engineer do after he/she is satisfied that the design will work?

A.Put it in a flow chart B.Program a chip and test it

C.Give the design to a technician to verify the design D.Perform a vector test

162.What is the indiction of short on the input of load gate.

A.Only the output of deflective gte is affected.B.There is a signal loss to all gtes on the node.

C.The affected node wil be sck in the low statte.D.There is a signal loss to all gates on the node.

163.In HDL, LITERALS is/are:

A.digital systems. B. scalars. C. scalars. D. numbering system

164.The carry propagation can be expressed as ________.

A.Cp = AB B.Cp = A + B C. cp=A~b

165.A decoder can be used as a demultiplexer by ________.

A.tying all enable pins LOW B.tying all data-select lines LOW

C.tying all data-select lines HIGH

D.using the input lines for data selection and an enable line for data input

166.How many 4-bit parallel adders would be required to add two binary numbers each representing

decimal numbers up through 30010?

A.1 B.2 C.3 D.4

167.A full-adder has a Cin = 0. What are the sum ( ) and the carry (Cout) when A = 1 and B = 1?

A. = 0, Cout = 0 B. = 0, Cout = 1 C. = 1, Cout = 0 D. = 1, Cout = 1

168.How many outputs would two 8-line-to-3-line encoders, expanded to a 16-line-to-4-line encoder, have?

A.3 B.4 C.5 D.6

169What is the indication of a short to ground in the output of a driving gate?

A.Only the output of the defective gate is affected.

B.There is a signal loss to all load gates.

C.The node may be stuck in either the HIGH or the LOW state.

D.The affected node will be stuck in the HIGH state.

170 Clock tree doesn't contain following cell ___.

a. Clock buffer b. Clock Inverter c. AOI cell d. None of the above

Answers:

155 156 157 158 159 160 161 162

c b c c d a b d

163 164 165 166 167 168 169 170

b b b c b b b c


PART-B (2 MARKS)

171. Mention the levels at which testing of a chip can be done? [APRIL-2009]

a) At the wafer level, b) At the packaged-chip level c) At the board level

d) At the system level, e) In the field

172. What are the categories of testing? [Nov-2004]

a) Functionality tests b) Manufacturing tests

173. Write notes on functionality tests? [APRIL-2009]

Functionality tests verify that the chip performs its intended function. These tests assert that all the gates in the

chip, acting in concert, achieve a desired function. These tests are usually used early in the design cycle to verify

the functionality of the circuit.

174. Write notes on manufacturing tests [APRIL-2009]

Manufacturing tests verify that every gate and register in the chip functions correctly. These tests are used after

the chip is manufactured to verify that the silicon is intact.

175. Mention the defects that occur in a chip? [Nov-2004]

a) layer-to-layer shorts b) discontinous wires c) thin-oxide shorts to substrate or well

176. Give some circuit maladies to overcome the defects?

i)nodes shorted to power or ground ii)nodes shorted to each other iii)inputs floating/outputs disconnected

177. What are the tests for I/O integrity? [APRIL-2009]

i). I/O level test ii). Speed test iii). IDD test

178. What is meant by fault models?

Fault model is a model for how faults occur and their impact on circuits.

179. Give some examples of fault models?

i). Stuck-At Faults ii). Short-Circuit and Open-Circuit Faults

180. What is stuck – at fault?

With this model, a faulty gate input is modeled as a “stuck at zero” or “stuck at one”. These faults most frequently

occur due to thin-oxide shorts or metal-to-metal shorts.

181. What is meant by observability? [APRIL-2009]

The observability of a particular internal circuit node is the degree to which one can observe that node at the

outputs of an integrated circuit.

182. What is meant by controllability?

The controllability of an internal circuit node within a chip is a measure of the ease of setting the node to a 1 or 0

state.

183. What is known as percentage-fault coverage?[APRIL-2009]

The total number of nodes that, when set to 1 or 0, do result in the detection of the fault, divided by the total

number of nodes in the circuit, is called the percentage-fault coverage.

184. What is fault grading?[ Nov-2004]

Fault grading consists of two steps. First, the node to be faulted is selected. A simulation is run with no faults

inserted, and the results of this simulation are saved. Each node or line to be faulted is set to 0 and then 1 and the

test vector set is applied. If and when a discrepancy is detected between the faulted circuit response and the good

circuit response, the fault is said to be detected and the simulation is stopped.

185. Mention the ideas to increase the speed of fault simulation?

a. parallel simulation b. concurrent simulation

186. What is fault sampling?

An approach to fault analysis is known as fault sampling. This is used in circuits where it is impossible to fault

every node in the circuit. Nodes are randomly selected and faulted. The resulting fault detection rate may be


statistically inferred from the number of faults that are detected in the fault set and the size of the set. The

randomly selected faults are unbiased. It will determine whether the fault coverage exceeds a desired level.

187. What are the approaches in design for testability? [Nov-2004]

a). ad hoc testing b). scan-based approaches c). self-test and built-in testing

188. Mention the common techniques involved in ad hoc testing? [APRIL-2009]

a). partitioning large sequential circuits b). adding test points c). adding multiplexers

d). providing for easy state reset

189. What are the scan-based test techniques?

a) Level sensitive scan design b) Serial scan c) Partial serial scan d) Parallel scan

190. The circuit is level-sensitive.

Each register may be converted to a serial shift register.

191. What are the self-test techniques?

a). Signature analysis and BILBO b). Memory self-testB c). Iterative logic array testing

192. What is known as BILBO? [APRIL-2009]

Signature analysis can be merged with the scan technique to create a structure known as BILBO- for Built

In Logic Block Observation.

193. What is known as IDDQ testing?

A popular method of testing for bridging faults is called IDDQ or current supply monitoring. This relies

on the fact that when a complementary CMOS logic gate is not switching, it draws no DC current. When a

bridging fault occurs, for some combination of input conditions a measurable DC IDD will flow.

194. What are the applications of chip level test techniques?

a). Regular logic arrays b). Memories c). Random logic

195. What is boundary scan? [Nov-2004]

The increasing complexity of boards and the movement to technologies like multichip modules and

surface-mount technologies resulted in system designers agreeing on a unified scan-based methodology for

testing chips at the board. This is called boundary scan.

196. What is the test access port? [APRIL-2009]

The Test Access Port (TAP) is a definition of the interface that needs to be included in an IC to make it

capable of being included in a boundary-scan architecture. The port has four or five single bit connections, as

follows:1)TCK(The Test Clock Input) 2)TMS(The Test Mode Select)3)TDI(The Test Data Input)4)TDO(The

Test Data Output) 5) It also has an optional signal

TRST*(The Test Reset Signal)

197. What are the contents of the test architecture?

-data registers, An instruction register, A

TAP controller

198. What is the TAP controller? [APRIL-2009]

The TAP controller is a 16-state FSM that proceeds from state to state based on the TCK and TMS signals. It

provides signals that control the test data registers, and the instruction register. These include serial-shift clocks

and update clocks.

199. What is known as test data register?

The test-data registers are used to set the inputs of modules to be tested, and to collect the results of running tests.

200. What is known as boundary scan register? [APRIL-2009]

The boundary scan register is a special case of a data register. It allows circuit-board interconnections to be tested,

external components tested, and the state of chip digital I/Os to be sampled.


PART-C (16 MARKS)

201. Briefly explain [APRIL-2009]

A) Fault grading & fault simulation b) Fault grading & Fault simulation

202. Explain scan-based test techniques.[ Nov-2004]

i) Level sensitive scan design (ii) Serial scan (iii) Partial serial scan (iv) Parallel scan

203. Explain Ad-Hoc testing and chip level test techniques.

204. Explain the VLSI design flow with a neat diagram

UNIT V SPECIFICATION USING VERILOG HDL

Basic concepts- identifiers- gate primitives, gate delays, operators, timing controls, procedural

assignments conditional statements, Data flow and RTL, structural gate level switch level

modeling, Design hierarchies, Behavioral and RTL modeling, Test benches, Structural gate

level description of decoder, equality detector, comparator, priority encoder, half adder, full

adder, Ripple carry adder, D latch and D flip flop.

PART-A (1MARKS) 205. After the final routing the violations in the design ___.

a. There can be no setup, no hold violations

b. There can be only setup violation but no hold

c. There can be only hold violation not Setup violation

d. There can be both violations.

206Utilisation of the chip after placement optimisation will be ___.

a. Constant b. Decrease c. Increase . None of the above

207. What is routing congestion in the design?

a. Ratio of required routing tracks to available routing tracks

b. Ratio of available routing tracks to required routing tracks

c. Depends on the routing layers available

d. None of the above

208. What are preroutes in your design?

a. Power routing b. Signal routing c. Power and Signal routing d. None of the above.

209. Clock tree doesn't contain following cell ___.

a. Clock buffer b. Clock Inverter c. AOI cell d. None of the above

210.In VHDL,V tnds for

A.Verilog B.VLSI C. VHSI D.Very Efficient

211.In VHDL always the ------------------- file should be included

a. Library B. Header C. assembly D.target

212.Todeclare the inputs and outputs of the circuit --------------------- statement is used

A.Architecture B.Component C.Process D.entity

213.IN bit is used to declare

A. 1 bit output B.1 bit input C. 2 bit output D. 2 bit input

214.For don’t cases -------------symbol is used

A.1 B.0 C.X D.U


215.Begin statement is not used in

A.Data Flow B. Behavorial C. Structural D.None of the above

216.OR function is described in VHDL as--------------

A..OR B. ~OR~ C.OR D.|

217.IF multiplexer is implemented in behavorial modeling the following is used

A.Expression B. Function C. if else D.for

218.For describing circuits like flip flops------------------ statements is used

A.Always B.entity C.Component D. Process

219.IN VHDL,the binary vlue is movd from one variable to another using------------------

A.>= B.<= C.= D.==

220. For getting delay output ,e use

A. Delay B. after C.end D. begin

221.The VHDL is bsed on the ---------------------library

A. IEE B.OWRK C.IEEE D.Standard

222.The inputs are declared in verilog using-------------

A.Always B. Input C.output D.module

223.If we give expression ,the ype of modeling is called as----------------

A.General B.Dataflow C.Behavorial D.Structural

224.Conditional statements like if else,cse can be used only in---------------

A.Data Flow B. Behavorial C. Structural D.none

Answers:

205 206 207 208 209 210 211 212 213 214

d c a a c c a d b c

215 216 217 218 219 220 221 222 223 224

a c c d b b c d b c

PART-B (2 MARKS)

225.What is Verilog? [Nov-2004]

Verilog is a general purpose hardware descriptor language. It is similar in syntaxto the C programming language.

It can be used to model a digital system at manylevels of abstraction ranging from the algorithmic level to the

switch level.

226. What are the various modeling used in Verilog? [APRIL-2009]

1. Gate-level modeling 2. Data-flow modeling 3. Switch-level modeling 4. Behavioral modeling

227. What is the structural gate-level modeling?[ Nov-2004]

Structural modeling describes a digital logic networks in terms of the components that make up the system. Gate-

level modeling is based on using primitive logic gates and specifying how they are wired together.

228.What is Switch-level modeling?

Verilog allows switch-level modeling that is based on the behavior of MOSFETs.Digital circuits at the MOS-

transistor level are described using the MOSFET switches.

229. What are identifiers? [APRIL-2009]

Identifiers are names of modules, variables and other objects that we can reference in the design. Identifiers

consists of upper and lower case letters, digits 0 through 9, the underscore character(_) and the dollar sign($). It

must be a single group of characters.

Examples: A014, a ,b, in_o, s_out


230. What are the value sets in Verilog?[ Nov-2004]

Verilog supports four levels for the values needed to describe hardware referred to as value sets.

Value levelsCondition in hardware circuits

0 Logic zero, false condition

1 Logic one, true condition

X Unknown logic value

Z High impedance, floating state

231. What are the types of gate arrays in ASIC?

1) Channeled gate arrays 2) Channel less gate arrays 3) Structured gate arrays

232. Give the classifications of timing control? [APRIL-2009]

Methods of timing control:

1. Delay-based timing control 2. Event-based timing control 3. Level-sensitive timing control Types of

delay-based timing control: 1. Regular delay control 2. Intra-assignment delay control 3. Zero delay

control Types of event-based timing control: 1. Regular event control 2. Named event control 3. Event

OR control 4. Level-sensitive timing control

233 Give the different arithmetic operators?

Operator symbol Operation performed Number of operands

* Multiply Two , / Divide Two, + Add Two, - Subtract Two,

% Modulus Two ** Power (exponent) Two

234. Give the different bitwise operators. [APRIL-2009]

Operator symbol Operation performed Number of operands

~ Bitwise negation One , & Bitwise and Two, | Bitwise or Two, ^ Bitwise xor Two

^~ or ~^ Bitwise xnor Two, ~& Bitwise nand Two, ~| Bitwise nor Two

235. What are gate primitives?

Verilog supports basic logic gates as predefined primitives. Primitive logic function keyword provide the basics

for structural modeling at gate level. These primitives are instantiated like modules except that they are

predefined in verilog and do not need a module definition. The important operations are and, nand, or,xor, xnor,

and buf(non-inverting drive buffer).

236. Give the two blocks in behavioral modeling.

1. An initial block executes once in the simulation and is used to set up initial conditions and step-by-step

data flow 2. An always block executes in a loop and repeats during the simulation.

237. What are the types of conditional statements? [APRIL-2009]

1. No else statement Syntax : if ( [expression] ) true – statement; 2. One else statement

Syntax : if ( [expression] ) true – statement; else false-statement; 3. Nested if-else-if

Syntax : if ( [expression1] ) true statement 1; else if ( [expression2] ) true-statement 2;

else if ( [expression3] ) true-statement 3; else default-statement;The [expression] is luated. If it is true (1 or

a non-zero value) true-statement is executed. If it is false (zero) or ambiguous (x), the false-statement is executed.

238. Name the types of ports in Verilog[APRIL-2009]

Types of port Keyword

Input port Input

Output port Output

Bidirectional port inout

239. What are the types of procedural assignments? [APRIL-2009]

1. Blocking assignment 2. Non-blocking assignment


PART-C (16 MARKS)

240. Explain the concept of gate delay in VERILOG with example [APRIL-2009]

241. Explain the concept involved in structural gate level modeling and also give the

description for Half adder and Full adder.

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