R-F Type Low Voltage 8-bit Mask MCU HT47C07L/HT47C08L...R-F Type Low Voltage 8-bit Mask MCU...

R-F Type Low Voltage 8-bit Mask MCU

HT47C07L/HT47C08L

Revision: V1.10 Date: Deee 01Deee 01

Rev. 1.10 Deee 01 Rev. 1.10 Deee 01

HT47C07L/HT47C08LR-F Type Low Voltage 8-bit Mask MCU


Table of Contents

Features ............................................................................................................ 4General Description ......................................................................................... 4Selection Table ................................................................................................. 5Block Diagram .................................................................................................. 5Pin Assignment ................................................................................................ 6Pin Descriptions .............................................................................................. 7

HT7C07L ............................................................................................................................... 7HT7C08L ............................................................................................................................... 8

Absolute Maximum Ratings ............................................................................ 9D.C. Characteristics ......................................................................................... 9A.C. Characteristics ....................................................................................... 10Power-on Reset Electrical Characteristics .................................................. 10System Architecture .......................................................................................11

Cloking and Pipelining ..........................................................................................................11Poga Counte – PC ...........................................................................................................11Stak ..................................................................................................................................... 1Aitheti and Logi Unit – ALU ........................................................................................... 1

Program Memory – ROM ............................................................................... 13Data Memory – RAM ...................................................................................... 14Special Function Register Description ........................................................ 16

Indiet Addessing Registes – IAR0 IAR1 ........................................................................ 16Auulato – ACC .............................................................................................................. 16Status Registe – STATUS .................................................................................................... 16

Oscillator Configuration ................................................................................ 18Watchdog Timer ............................................................................................. 18Multi-function Timer ...................................................................................... 18Time Base ....................................................................................................... 19

TBC Registe ......................................................................................................................... 19

Reset and Initialisation .................................................................................. 20Input/Output Ports ......................................................................................... 23Timer/Event Counter ..................................................................................... 26RC Type A/D Converter ................................................................................. 29Power Down Operation – HALT .................................................................... 37Interrupts ........................................................................................................ 38LCD Display Memory ..................................................................................... 39

LCD Dive Output ................................................................................................................. 0




Low Voltage Detector – LVD ......................................................................... 43Mask Options ................................................................................................. 43Application Circuits ....................................................................................... 44

HT7C07L ............................................................................................................................. HT7C08L .............................................................................................................................

Instruction Set ................................................................................................ 45Intodution ........................................................................................................................... 5Instution Tiing .................................................................................................................. 5Moving and Tansfeing Data ............................................................................................... 5Aitheti Opeations ............................................................................................................ 5Logial and Rotate Opeations .............................................................................................. 6Banhes and Contol Tansfe ............................................................................................. 6Bit Opeations ....................................................................................................................... 6Tale Read Opeations ......................................................................................................... 6Othe Opeations ................................................................................................................... 6

Instruction Set Summary .............................................................................. 47Tale Conventions ................................................................................................................. 7

Instruction Definition ..................................................................................... 49Package Information ..................................................................................... 58

8-pin LQFP (7×7) Outline Diensions .................................................................... 59

Rev. 1.10 Deee 01 Rev. 1.10 5 Deee 01



Features• Operatingvoltage:1.2V~2.2V

• Upto21bidirectionalI/Olines

• On-chip32kHz~128kHzInternalRCoscillator

• UptotwoRCtypeA/Dconverters

• WatchdogTimer

• Upto2K×16programmemoryROM

• Upto96×8datamemoryRAM

• TimeBaseFunction

• Onebuzzeroutput(BZ,BZ)

• OneELcarrieroutput

• OneLCDdriverwithupto21×3segments

• HALTfunctionandwake-upfeaturereducepowerconsumption

• Four-levelsubroutinenesting

• LowVoltageDetectFunction

• Bitmanipulationinstruction

• 16-bittablereadinstruction

• Upto31μsinstructioncyclewith128kHzsystemclock

• 63powerfulinstructions

• Allinstructionsinoneortwomachinecycles

• 48-pinLQFPpackagetypes

General DescriptionTheHT47C07LandHT47C08Lare8-bit,highperformanceRISCarchitecturemicrocontrollerdevicesspecificallydesignedforapplicationsthatinterfacedirectlytoanalogsignals,suchasthosefromsensors.Itssinglecycleinstructionandtwo-stagepipelinearchitecturemakeitsuitableforhighspeedapplications.

Theadvantagesoflowpowerconsumption,I/Oflexibility,timerfunctions,oscillatoroptions,RCtypeA/Dconverter,LCDdriver,HALTandwake-upfunctions,enhance theversatilityof thesedevicetosuitawiderangeofResistortoFrequencyapplicationpossibilitiessuchassensorsignalprocessing,remotemetering,andparticularlysuitableforuseasclinicalthermometerMCUdevice.

Selection TableMost featuresarecommon toalldevices.Themain featuresdistinguishing themareMemorycapacity,I/Ocount,RCTypeA/DConverterchannels,LCDDriverOutputsandpackagetypes.Thefollowingtablesummarisesthemainfeaturesofeachdevice.

Part No. Program Memory

Data Memory I/O EL Carrier

OutputRC Type A/D

Converter16-bit Timer LCD Driver Time

Base Stacks Package

HT7C07L 1K×16 8×8 18 1 1 1 19× o 0× 1 8LQFPHT7C08L K×16 96×8 1 1 1 1× 1 8LQFP

Rev. 1.10 Deee 01 Rev. 1.10 5 Deee 01



Block Diagram

8-itRISCMCUCoe

Wathdog Tie

ResetCiuitIntenal RC

Osillato

Poga Meoy

DataMeoy Stak

LCDDive

Inteupt Contolle

Low VoltageDetet

RC Type A/DConvete

Tie Base

16-it Tie

I/OPots Buzze LCD Bias

Geneato

Pin Assignment

PA0/BZPA1/BZPA/EL

PAPAPA5PA6PA7NCNCNC

VSS

SEG6SEG7SEG8PB0/SEG9PB1/SEG10PB/SEG11PB/SEG1PB/SEG1PB5/SEG1PB6/SEG15PB7/SEG16PC0/SEG17

PC

1/SEG

18N

CN

CC

OM

/SEG

19C

OM

1C

OM

0N

CN

CN

CR

CIN

RSE

NR

RE

F

SE

G5

SE

G

SE

G

SE

G

SE

G1

SE

G0

NCVAC

C1

RES

VD

D

HT47C07L48 LQFP-A

15678910111

1 1 15 16 17 18 19 0 1 567890156

5678 78901

PA0/BZPA1/BZPA/EL

PAPAPA5PA6PA7PCPCPCVSS

SEG6SEG7SEG8PB0/SEG9PB1/SEG10PB/SEG11PB/SEG1PB/SEG1PB5/SEG1PB6/SEG15PB7/SEG16PC0/SEG17

PC

1/SEG

18S

EG19

SEG

0C

OM

C

OM

1C

OM

0R

CIN

1R

SE

N1

RR

EF1

RC

IN0

RS

EN

0R

RE

F0

SE

G5

SE

G

SE

G

SE

G

SE

G1

SE

G0

VCVAC

C1

RES

VD

D

HT47C08L48 LQFP-A

15678910111

1 1 15 16 17 18 19 0 1 567890156

5678 78901

Rev. 1.10 6 Deee 01 Rev. 1.10 7 Deee 01



Pin Descriptions

HT47C07L

Pin Name I/O Option Pin-Shared MappingRES I — Shitt tigge eset input. Ative low.

PA0/BZPA1/BZ

I/OI/O

Wake-up Pull-high o NoneBZ o BZ

Bidietional -it input/output pot. Eah it an e a wake-up input. The PA0 and PA1 ae pin-shaed with the BZ and BZ espetively. One the PA0 and PA1 ae seleted as uzze diving outputs the output signals oe fo an intenal uzze lok geneato. Softwae instutions deteine the CMOS output o Shitt tigge input with pull-high esisto (ask option).

PA/EL I/OWake-up Pull-high o NoneEL

Bidietional 1-it input/output pot. This it an e a wake-up input. The PA is pin-shaed with the EL aie output. One the PA is seleted as EL aie output the output signal oes fo an intenal EL aie lok geneato. Softwae instutions deteine the CMOS output o Shitt tigge input with pull-high esisto (ask option).

PA~PA7 I/O Wake-up Pull-high o None

Bidietional 5-it input/output pot. Eah it an e a wake-up input. Softwae instutions deteine the CMOS output o Shitt tigge input with pull-high esisto (ask option).

PB0/SEG9~ PB7/SEG16 I/O I/O o SEG

Bidietional 8-it input/output pot. Softwae instutions deteine the CMOS output or Schmitt trigger input with pull-high resistor (configuration option). These pins ae used as the LCD dive outputs fo LCD panel segments. Configuration options can select each pin to be used as either an I/O pin o a segent dive output.

PC0/SEG17~ PC1/SEG18 I/O I/O o SEG

Bidietional -it input/output pot. Softwae instutions deteine the CMOS output or Schmitt trigger input with pull-high resistor (configuration option). These pins ae used as the LCD dive outputs fo LCD panel segments. Configuration options can select each pin to be used as either an I/O pin o a segent dive output.

SEG0~SEG8 O — LCD dive output fo LCD panel segents.

COM0~COM1 COM/SEG19 O 1/ o 1/ Duty

COM0~COM1 ae the LCD oon outputs.The 1/ LCD duty yle ask option will deteine whethe pin COM/SEG19 is onfigued as a SEG19 segent output dive o as a COM oon output dive fo the LCD panel.

VA C1 C — — VA: LCD powe supply voltage onnet a apaito etween VA and VSS.C1 C: Swithing pins fo VA. Connet a apaito etween C1 and C.

RCIN I — RC type A/D onvete input pin fo RC osillation.

RREF O — RC type A/D onvete output pin fo efeene esisto osillation.

RSEN O — RC type A/D onvete output pin fo senso esisto osillation.

VDD P — Positive powe supply.

VSS P — Negative powe supply gound.

Rev. 1.10 6 Deee 01 Rev. 1.10 7 Deee 01



HT47C08L

Pin Name I/O Option Pin-Shared Mapping

RES I — Shitt tigge eset input. Ative low.

PA0/BZPA1/BZ

I/OI/O

Wake-up Pull-high o None BZ o BZ

Bidietional -it input/output pot. Eah it an e a wake-up input. The PA0 and PA1 ae pin-shaed with the BZ and BZ espetively. One the PA0 and PA1 ae seleted as uzze diving outputs the output signals oe fo an intenal uzze lok geneato. Softwae instutions deteine the CMOS output o Shitt tigge input with pull-high esisto (ask option).

PA/EL I/OWake-up Pull-high o None EL

Bidietional 1-it input/output pot. This it an e a wake-up input. The PA is pin-shaed with the EL aie output. One the PA is seleted as EL aie output the output signal oes fo an intenal EL aie lok geneato. Softwae instutions deteine the CMOS output o Shitt tigge input with pull-high esisto (ask option).

PA~PA7 I/O Wake-up Pull-high o None

Bidietional 5-it input/output pot. Eah it an e a wake-up input. Softwae instutions deteine the CMOS output o Shitt tigge input with pull-high esisto (ask option).

PC~PC I/O — Bidietional -it input/output pot. Softwae instutions deteine the CMOS output o Shitt tigge input with pull-high esisto (ask option).

PB0/SEG9~ PB7/SEG16 I/O I/O o SEG

Bidietional 8-it input/output pot. Softwae instutions deteine the CMOS output or Schmitt trigger input with pull-high resistor (configuration option). These pins ae used as the LCD dive outputs fo LCD panel segments. Configuration options can select each pin to be used as either an I/O pin o a segent dive output.

PC0/SEG17~ PC1/SEG18 I/O I/O o SEG

Bidietional -it input/output pot. Softwae instutions deteine the CMOS output or Schmitt trigger input with pull-high resistor (configuration option). These pins ae used as the LCD dive outputs fo LCD panel segments. Configuration options can select each pin to be used as either an I/O pin o a segent dive output.

SEG0~SEG8 SEG19~0 O — LCD dive output fo LCD panel segents.

COM0~COM O — COM0~COM ae the LCD oon outputs.

VA VCC1 C — —

VA VC: LCD powe supply voltage onnet a apaito etween VA and VSS and etween VC and VSS espetively.

C1 C: Swithing pins fo VA and VC. Connet a apaito etween C1 and C.

RCIN0 I — RC type A/D onvete input pin0 fo RC osillation.

RREF0 O — RC type A/D onvete output pin0 fo efeene esisto osillation.

RSEN0 O — RC type A/D onvete output pin0 fo senso esisto osillation.

RCIN1 I — RC type A/D onvete input pin1 fo RC osillation.

RREF1 O — RC type A/D onvete output pin1 fo efeene esisto osillation.

RSEN1 O — RC type A/D onvete output pin1 fo senso esisto osillation.

VDD P — Positive powe supply.

VSS P — Negative powe supply gound.

Rev. 1.10 8 Deee 01 Rev. 1.10 9 Deee 01



Absolute Maximum RatingsSupplyVoltage....................................................................................................... VSS−0.3Vto2.5VInputVoltage..................................................................................................VSS−0.3VtoVDD+0.3VStorageTemperature....................................................................................................-50˚Cto125˚COperatingTemperature..................................................................................................-10˚Cto50˚C

Note:Thesearestressratingsonly.Stressesexceeding therangespecifiedunder"AbsoluteMaximumRatings"maycausesubstantialdamagetothesedevices.Functionaloperationofthesedevicesatotherconditionsbeyondthoselistedinthespecificationisnotimpliedandprolongedexposuretoextremeconditionsmayaffectdevicesreliability.

D.C. CharacteristicsTa=5°C

Symbol ParameterTest Conditions

Min. Typ. Max. UnitVDD Conditions

VDD Opeating Voltage — — 1. — . V

VA LCD Voltage — 1/ ias — VDD× — V

VB LCD Voltage — 1/ ias — VDD — V

VLVD1 Low Voltage Deteto Voltage — Mask Option 1.5 1. 1.5 V

VLVD Low Voltage Deteto Voltage — Mask Option 1. 1.7 1. V

VLVD Low Voltage Deteto Voltage — Mask Option 1.0 1.5 1.0 V

IDD1 Opeating Cuent 1.5V No load fSYS=kHz A/D off LVD disaled — — 5 μA

IDD Opeating Cuent 1.5VNo load fSYS=kHz A/D on LVD disaled*R=30kΩ, *C=2200pF

— — 5 μA

IDD Opeating Cuent 1.5V No load fSYS=18kHz A/D off LVD disaled — — 0 μA

IDD Opeating Cuent 1.5VNo load fSYS=18kHz A/D on LVD disaled*R=30kΩ, *C=2200pF

— — 60 μA

ILVD LVD Cuent 1.5V LVD enaled — 50 100 μA

ISTB1Standy Cuent (LVD Disaled LCD Off Syste OSC off) 1.5V No load syste HALT

A/D Off LVD disaled — 0.1 1 μA

ISTBStandy Cuent(LCD On) 1.5V

No load syste HALT fSYS=kHz A/D Off LVD disaled

— — μA

ISTBStandy Cuent(LCD On) 1.5V

No load syste HALT fSYS=18kHz A/D Off LVD disaled

— — 1 μA

VIL1 Input Low Voltage fo I/O Pots — — 0 — 0.VDD V

VIH1 Input High Voltage fo I/O Pots — — 0.8VDD — VDD V

VIL Input Low Voltage (RES) — — 0 — 0.VDD V

VIH Input High Voltage (RES) — — 0.9VDD — VDD V

IOL1I/O Pot Sink Cuent(PA PB PC) 1.5V VOL=0.1VDD 0.5 0.8 — A

IOH1I/O Pot Soue Cuent(PA PB PC) 1.5V VOH=0.9VDD -0. -0.6 — A

Rev. 1.10 8 Deee 01 Rev. 1.10 9 Deee 01





IOLI/O Pot Sink Cuent(RREFn RSENn) 1.5V VOL=0.1VDD 7 — A

IOHI/O Pot Soue Cuent(RREFn RSENn) 1.5V VOH=0.9VDD - -5 — A

IOL LCD oon and segent Sink Cuent 1.5V VOL=0.1VDD 50 100 — μA

IOH LCD oon and segent Soue Cuent 1.5V VOH=0.9VDD -50 -100 — μA

RPH Pull-high Resistane of I/O Pots 1.5V — 75 150 00 kΩ

Note:*RstandsfortheRCtypeA/Dconverterresistance*CstandsfortheRCtypeA/Dconvertercapacitance

A.C. CharacteristicsTa=5°C



fLIRC LIRC Osillato Clok 1.5V — 10. 18.0 15.6 kHz

tONLIRC Stale Tie fo LIRC Osillato 1.5V — — — 1 s

fSYS Syste Clok 1.5V — 5 — 15 kHz

tRES Extenal Reset Low Pulse Width 1.5V — 100 — — μs

fAD A/D type RC osillation fequeny 1.5V — — — 50 kHz

fLCD LCD Dive Clok Fequeny — User select by configuration option — — kHz

Power-on Reset Electrical CharacteristicsTa=5°C



VPOR VDD Stat Voltage to Ensue Powe-on Reset 100 V

RRVDD VDD Rising Rate to Ensue Powe-on Reset 0.05 V/s

tPORMiniu Tie fo VDD Stays at VPOR to Ensue Powe-on Reset 1 s

Rev. 1.10 10 Deee 01 Rev. 1.10 11 Deee 01



System Architecture

Clocking and PipeliningThesystemclock isderived froman internalRCoscillatorand is internallydivided into fournon-overlappingclocks(T1,T2,T3andT4).Oneinstructioncycleconsistsoffoursystemclockcycles.

Instructionfetchingandexecutionarepipelinedinsuchawaythatafetchtakesoneinstructioncyclewhiledecodingandexecutiontakesthenextinstructioncycle.Thispipeliningschemeensuresthatinstructionsareeffectivelyexecutedinonecycle.Exceptionstothisareinstructionsthatchangethecontentsoftheprogramcounter,suchassubroutinecallsorjumps,inwhichcase,twocyclesarerequiredtocompletetheinstruction.

Execution Flow

Program Counter – PCThe10-bitand11-bitprogramcounter(PC)controlsthesequenceinwhichtheinstructionsstoredin theprogramROMareexecutedand itscontentsspecifyamaximumof1024addresses forHT47C07Land2048addressesforHT47C08Lrespectively.

Afteraccessingaprogrammemorywordtofetchaninstructioncode,thecontentsoftheprogramcounterareincrementedbyone.Theprogramcounterthenpointstothememorywordcontainingthenextinstructioncode.

Whenexecutingajumpinstruction,conditionalskipexecution,loadingPCLregister,subroutinecall,initialreset,internalinterrupt,externalinterruptorreturnfromsubroutine,etc.,themicrocontrollermanagesprogramcontrolbyloadingtheaddresscorrespondingtoeachinstruction.

Forconditionalskipinstructions,oncetheconditionhasbeenmet,thenextinstruction,whichhasalreadybeenfetchedduring thecurrent instructionexecution, isdiscardedandadummycyclereplacesitwhiletheproperinstructionisobtained.Otherwiseproceedwiththenextinstruction.

Thelowerbyteoftheprogramcounter(PCL)isavailableforprogramcontrolandisareadableandwriteableregister(06H).MovingdataintothePCLperformsashortjump.Thedestinationwillbewithin256locations.

Whenacontroltransfertakesplace,anadditionaldummycycleisrequired.

Rev. 1.10 10 Deee 01 Rev. 1.10 11 Deee 01



ModeProgram Counter

*10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0Initial Reset 0 0 0 0 0 0 0 0 0 0 0Tie/event Counte Inteupt 0 0 0 0 0 0 0 0 1 0 0Tie Base Inteupt 0 0 0 0 0 0 0 1 0 0 0Skip Poga Counte+Loading PCL *10 *9 *8 @7 @6 @5 @ @ @ @1 @0Jup Call Banh #10 #9 #8 #7 #6 #5 # # # #1 #0Retun fo Suoutine S10 S9 S8 S7 S6 S5 S S S S1 S0

Program Counter

Note:*10~*0:Programcounterbits #10~#0:Instructioncodebits

S10~S0:Stackregisterbits @7~@0:PCLbits

ForHT47C07L,theprogramcounteris10bits,i.e.bit9~bit0.

ForHT47C08L,theprogramcounteris11bits,i.e.bit10~bit0.

StackThisisaspecialpartofthememorywhichisusedtosavethecontentsoftheprogramcounter(PC)only.Thestackisorganizedintofourlevelsandisneitherpartofthedatanorpartoftheprogramspace,andisneitherreadablenorwriteable.Theactivated level is indexedbythestackpointer(SP)andisneitherreadablenorwriteable.Atasubroutinecallorinterruptacknowledgesignal,thecontentsoftheprogramcounterarepushedontothestack.Attheendofasubroutineoraninterruptroutine,signaledbya return instruction(RETorRETI), theprogramcounter is restored to itspreviousvaluefromthestack.Afterachipreset,thestackpointerwillpointtothetopofthestack.

Ifthestackisfullandanon-maskedinterrupttakesplace,theinterruptrequestflagwillberecordedbutacknowledgesignalwillbeinhibited.Whenthestackpointerisdecremented(byRETorRETI),the interruptwillbeserviced.Thisfeaturepreventsstackoverflowallowingtheprogrammer tousethestructuremoreeasily.Inasimilarcase, if thestackisfullanda"CALL"issubsequentlyexecuted,stackoverflowoccursandthefirstentrywillbelost(onlythemostrecentfourreturnaddressesisstored).

Arithmetic and Logic Unit – ALUThiscircuitperforms8-bit arithmeticand logicoperation.TheALUprovides the followingfunctions:

• Arithmeticoperations:ADD,ADDM,ADC,ADCM,SUB,SUBM,SBC,SBCM,DAA

• Logicoperations:AND,OR,XOR,ANDM,ORM,XORM,CPL,CPLA

• RotationRRA,RR,RRCA,RRC,RLA,RL,RLCA,RLC

• IncrementandDecrementINCA,INC,DECA,DEC

• Branchdecision,JMP,SZ,SZA,SNZ,SIZ,SDZ,SIZA,SDZA,CALL,RET,RETI

TheALUnotonlysavestheresultsofadataoperationbutcanalsochangethestatusregister.

Rev. 1.10 1 Deee 01 Rev. 1.10 1 Deee 01



Program Memory – ROMTheprogrammemoryisusedtostoretheprograminstructions,whicharetobeexecuted.Italsocontainsdata, table informationand interruptentries, and isorganized into1024×16bits forHT47C07Lor2048×16bitsforHT47C08L,addressedbytheprogramcounterandtablepointerregisters.

Certainlocationswithintheprogrammemoryarereservedforspecialusage:

• Location000HThisareaisreservedforusebythechipresetforprograminitialization.Afterachipreset isinitiated,theprogramwilljumptothislocationandbeginexecution.

• Location004HThisarea is reservedfor the timer/eventcounter interruptserviceprogram.If timer interruptresultsfromatimer/eventcounterAorBoverflow,andiftheinterruptisenabledandthestackisnotfull,theprogramwilljumptothislocationandbeginexecution.

• Location008HThisareaisreservedforthetimebaseinterruptserviceprogram.Ifatimebaseinterruptoccurs,andiftheinterruptisenabledandthestackisnotfull,theprogramwilljumptothislocationandbeginexecution.

• TablelocationAnylocationwithintheprogrammemorycanbeusedasa look-uptablewhereprogrammerscanstorefixeddata.TheinstructionsTABRDC[m](thecurrentpage,1page=256words)andTABRDL[m](thelastpage)transferthecontentsofthelower-orderbytetothespecifieddatamemory,and thehigher-orderbyte toTBLH(08H).Only thedestinationof the lower-orderbyteinthetableiswell-defined, thehigher-orderbyteof thetablewordaretransferredtotheTBLH.Thetablehigher-orderbyte(TBLH)isareadonlyregister.Thetablepointer(TBLP)isaread/writeregister(07H),whichindicatesthetablelocation.Beforeaccessingthetable, thelocationmustbeplacedintheTBLP.TheTBLHisreadonlyandcannotberestored.IfthemainroutineandtheISR(interruptserviceroutine)bothemploythetablereadinstruction,thecontentsoftheTBLHinthemainroutinearelikelytobechangedbythetablereadinstructionusedintheISR.Errorscanoccur.Inotherwordsusingthetablereadinstructionin themainroutineandtheISRsimultaneouslyshouldbeavoided.However,ifthetablereadinstructionhastobeappliedinboththemainroutineandtheISR,theinterruptissupposedtobedisabledpriortothetablereadinstruction.ItwillnotbeenableduntiltheTBLHhasbeenbackedup.Alltablerelatedinstructionsneed twocycles tocomplete theoperation.Theseareasmayfunctionasnormalprogrammemorydependingupontherequirements.

Rev. 1.10 1 Deee 01 Rev. 1.10 1 Deee 01



Note:nisupto3forHT47C07Lwhilenisupto7forHT47C08L

Program Memory

Instruction(s)Table Location

*10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0TABRDC [] P10 P9 P8 @7 @6 @5 @ @ @ @1 @0TABRDL [] 1 1 1 @7 @6 @5 @ @ @ @1 @0

Table Location

Note:*10~*0:Bitsoftablelocation @7~@0:Bitsoftablepointer

P10~P0:Bitsofcurrentprogramcounter

ForHT47C07L,thebitsoftablelocationare10bits.

ForHT47C08L,thebitsoftablelocationare11bits.

Data Memory – RAMThedatamemoryisdividedintotwofunctionalgroups:specialfunctionregistersandgeneral-purposedatamemory.Mostareread/write,butsomearereadonly.

Thespecialfunctionregistersincludetheindirectaddressingregister0(IAR0),thememorypointerregister0(MP0),theindirectaddressingregister1(IAR1),thememorypointerregister1(MP1),thebankpointer(BP), theaccumulator(ACC), theprogramcounterlower-orderbyteregister(PCL),thetablepointer(TBLP),thetablehigher-orderbyteregister(TBLH),thetimebasecontrolregister(TBC), thestatusregister(STATUS), theinterruptcontrolregister(INTC), theI/Oregisters(PA;PB;PC),I/Oportcontrolregister(PAC;PBC;PCC),thetimer/eventcounterAhigher-orderbyteregister(TMRAH),thetimer/eventcounterAlower-orderbyteregister(TMRAL),thetimer/eventcountercontrolregister(TMRC),thetimer/eventcounterBhigher-orderbyteregister(TMRBH),thetimer/eventcounterBlower-orderbyteregister(TMRBL),theRCoscillatortypeA/Dconvertercontrolregister(ADCR).

Theremainingspacebefore the80Harereservedfor futureexpandedusageandreading theselocationswillreturntheresult00H.Thegeneral-purposedatamemory,addressedfrom80HtoAFHforHT47C07Lorfrom80HtoDFHforHT47C08L,isusedfordataandcontrolinformationunderinstructioncommand.

Alldatamemoryareascanhandlearithmetic, logic, increment,decrementandrotateoperations.Exceptforsomededicatedbits,eachbitinthedatamemorycanbesetandresetbythe"SET[m].i"and"CLR[m].i" instruction, respectively.Theyarealso indirectlyaccessible throughmemorypointerregisters(MP0;01H,MP1;03H).

Rev. 1.10 1 Deee 01 Rev. 1.10 15 Deee 01



RAM Mapping

Rev. 1.10 1 Deee 01 Rev. 1.10 15 Deee 01



Special Function Register DescriptionMostoftheSpecialFunctionRegisterdetailswillbedescribedintherelevantfunctionalsection,howeverseveralregistersrequireaseparatedescriptioninthissection.

Indirect Addressing Registers – IAR0, IAR1 Location00Hand02Hareindirectaddressingregistersthatarenotphysicallyimplemented.Anyread/writeoperationto[00H]and[02H]accessdatamemorypointedtobyMP0(01H)andMP1(03H)respectively.Readinglocation00Hor02Hindirectlywill returnaresultof00H.Writingindirectlyresultsinnooperation.

Thefunctionofdatamovementbetweentwoindirectaddressingregistersarenotsupported.Thememorypointerregisters,MP0andMP1,areboth8-bitregisterswhichcanbeusedtoaccessthedatamemorybycombiningcorrespondingindirectaddressingregisters.

MP0onlycanbeappliedtodatamemory,whileMP1canbeappliedtothedatamemoryandtheLCDdisplaymemory.

Accumulator – ACC TheaccumulatoriscloselyrelatedwithoperationscarriedoutbytheALU.Itismappedtolocation05HofthedatamemoryandistheplacewhereallimmediateresultsfromtheALUarestored.Datamovementbetweentwodatamemorylocationsmustpassthroughtheaccumulator.

Status Register – STATUSThis8-bit register (0AH)contains thezero flag (Z),carry flag (C),auxiliarycarry flag (AC),overflowflag(OV),powerdownflag(PDF)andwatchdogtime-outflag(TO).Italsorecordsthestatusinformationandcontrolstheoperationsequence.

WiththeexceptionoftheTOandPDFflags,bitsinthestatusregistercanbealteredbyinstructionslikemostotherregisters.AnydatawrittenintothestatusregisterwillnotchangetheTOorPDFflags.Inadditionitshouldbenotedthatoperationsrelatedtothestatusregistermaygivedifferentresultsfromthoseintended.TheTOandPDFflagscanonlybechangedbythewatchdogtimeroverflow,systempower-up,clearingthewatchdogtimerandexecutingtheHALTinstruction.

TheZ,OV,ACandCflagsgenerallyreflectthestatusofthelatestoperations.

• Cissetifanoperationresultsinacarryduringanadditionoperationorifaborrowdoesnottakeplaceduringasubtractionoperation;otherwiseCiscleared.Cisalsoaffectedbyarotatethroughcarryinstruction.

• ACissetifanoperationresultsinacarryoutofthelownibblesinaddition,ornoborrowfromthehighnibbleintothelownibbleinsubtraction;otherwiseACiscleared.

• Zissetiftheresultofanarithmeticorlogicaloperationiszero;otherwiseZiscleared.

• OV isset ifanoperationresultsinacarryintothehighest-orderbitbutnotacarryoutofthehighest-orderbit,orviceversa;otherwiseOViscleared.

• PDF isclearedbyasystempower-uporexecutingthe“CLRWDT”instruction.PDFissetbyexecutingthe“HALT”instruction.

• TOisclearedbyasystempower-uporexecutingthe“CLRWDT”or“HALT”instruction.TOissetbyaWDTtime-out.

Inaddition,onenteringthe interruptsequenceorexecutingasubroutinecall, thestatusregisterwillnotbeautomaticallypushedontothestack.If thecontentsofstatusareimportantandif thesubroutinecancorruptthestatusregister,precautionsmustbetakentosaveitproperly.

Rev. 1.10 16 Deee 01 Rev. 1.10 17 Deee 01



STATUS Register

Bit 7 6 5 4 3 2 1 0Nae — — TO PDF OV Z AC CR/W — — R R R/W R/W R/W R/WPOR — — 0 0 x x x x

"x" unknownBit7,6 Unimplemented,readas“0”Bit5 TO:WatchdogTime-Outflag

0:Afterpoweruporexecutingthe“CLRWDT”or“HALT”instruction1:Awatchdogtime-outoccurred.

Bit4 PDF:Powerdownflag0:Afterpoweruporexecutingthe“CLRWDT”instruction1:Byexecutingthe“HALT”instruction

Bit3 OV:Overflowflag0:Nooverflow1:Anoperationresultsinacarryintothehighest-orderbitbutnotacarryoutofthehighest-orderbitorviceversa.

Bit2 Z:Zeroflag0:Theresultofanarithmeticorlogicaloperationisnotzero1:Theresultofanarithmeticorlogicaloperationiszero

Bit1 AC:Auxiliaryflag0:Noauxiliarycarry1:Anoperationresultsinacarryoutofthelownibblesinaddition,ornoborrowfromthehighnibbleintothelownibbleinsubtraction

Bit0 C:Carryflag0:Nocarry-out1:Anoperationresultsinacarryduringanadditionoperationorifaborrowdoesnottakeplaceduringasubtractionoperation

Cisalsoaffectedbyarotatethroughcarryinstruction.

Rev. 1.10 16 Deee 01 Rev. 1.10 17 Deee 01



Oscillator ConfigurationTheinternalRCoscillatorisafullyintegratedsystemoscillatorrequiringnoexternalcomponents.TheinternalRCoscillatorhasafrequencyof32kHz,64kHzor128kHzdeterminedbythemaskoptions.Theoscillationfrequencymayvarywiththepowersupplyvoltage,temperatureandprocessvariations.

Watchdog TimerTheWDTclocksource (fS) is fSYS.The timer isdesigned topreventsoftwaremalfunctionsorsequencesfromjumpingtounknownlocationswithunpredictableresults.TheWatchdogTimercanbedisabledbymaskoption.IftheWatchdogTimerisdisabled,alltheexecutionsrelatedtotheWDTresultinnooperation.

IftheWatchdogTimerfunctionisenabled,andthedevicesenterthepowerdownmodebyexecutingtheHALT instruction, theWatchdogTimerwillkeepcountingand thenwakeup thedevicesfromthepowerdownmodeduetotheWatchdogTimertime-outastheoscillatorisselectedtobeswitchedoninthepowerdownmode.

TheWDToverflowundernormaloperationwillinitializea“chipreset”andsetthestatusbitTO.Whereas in thepowerdownmode, theoverflowwill initializea“warmreset”whereinonlytheprogramcounterandstackpointerareresettozero.ToclearthecontentsoftheWDT,threemethodsareadopted.Thefirstisanexternalhardwarereset(alowlevelontheRESpin),thesecondisviasoftwareinstructions,andthethirdisviaa“HALT”instruction.ThesoftwareinstructionisCLRWDT.AnyexecutionoftheCLRWDTinstructionwillcleartheWDT.TheWDTmayresetthechipduetotime-out.

TheWDTtime-outperiodrangesfromfS/215~fS/216.The“CLRWDT”instructiononlyclearsthelasttwo-stageoftheWDT.

Multi-function TimerThedevicesprovideamulti-functiontimerfortheWDTandtimebasebutwithdifferenttime-outperiods.Themulti-functiontimerconsistsofan8-stagedivideranda7-bitprescaler,withtheclocksourcecomingfromfSYS.Themulti-functiontimeralsoprovidesaselectablefrequencysignal(rangesfromfS/23tofS/26)forLCDdrivercircuits,andaselectablefrequencysignal(rangesfromfS/22tofS/25)forthebuzzeroutputbyoptions.Itisrecommendedtoselectanear4kHzsignaltoLCDdrivercircuitsforproperdisplay.

Multi-function Timer

Rev. 1.10 18 Deee 01 Rev. 1.10 19 Deee 01



Time BaseThetimebaseisusedtosupplyaregularinternalinterrupt.Itstime-outfrequencyrangesfromfS/28tofS/215bysoftwareprogramming.WritingdatatoRT2,RT1andRT0(bits2,1,0ofTBC;09H)yieldsvarioustime-outfrequency.Ifatimebasetime-outoccurs, therelatedinterruptrequestflag(TBF;bit5ofINTC)isset.Butiftheinterruptisenabled,andthestackisnotfull,asubroutinecalltolocation08Hoccurs.WhentheHALTinstructionisexecuted,thetimebasestillworksandcanwake-upfromHALTmodeiffOSCison.IftheTBFissetto“1”beforeenteringtheHALTmode,thewake-upfunctionwillbedisabled.

TBC Register

Register Name

Bit

7 6 5 4 3 2 1 0Nae — — — — — RT RT1 RT0R/W — — — — — R/W R/W R/WPOR — — — — — 1 1 1

Bit7~3 Unimplemented,readas"0"Bit2~0 RT2~RT0:TimeBaseDividedFactor

000:28001:29010:210011:211100:212101:213110:214111:215

Rev. 1.10 18 Deee 01 Rev. 1.10 19 Deee 01



Reset and InitialisationTherearethreewaysinwhicharesetmayoccur.

• RESresetduringnormaloperation

• RESresetduringpowerdownmode

• WDTtime-outresetduringnormaloperation

TheWDTtime-outresetduringpowerdownmodeisdifferentfromotherchipresetconditions,sinceitcanperformawarmresetthatjustresetstheprogramcounterandstackpointerleavingtheothercircuitsintheiroriginalstate.Someregistersremainunchangedduringotherresetconditions.Mostregistersareresettotheinitialconditionwhentheresetconditionsaremet.ByexaminingthePDFandTOflags,theprogramcandistinguishbetweendifferent“chipresets”.

TO PDF RESET Conditions0 0 Syste powe-upu u RES eset duing noal opeation0 1 RES eset wake-up fo powe down ode1 u WDT tie-out duing noal opeation1 1 WDT wake-up fo powe down ode

Note: "u" stands fo unhangedThefollowingtableindicatesthewayinwhichthevariousfunctionalunitsareaffectedafteraresetoccurs.

Item Condition After ResetPoga Counte Reset to 000HInteupts All inteupts will e disaledPesale Divide All tie ounte pesale divide will e leaedWDT Tie Base Clea afte aste eset WDT egins ountingTie/event Counte All tie ountes will e tuned offInput/output Pots All I/O pots will e setup as inputsStak Pointe Stak pointe will point to the top of the stak

Reset Configuration

Rev. 1.10 0 Deee 01 Rev. 1.10 1 Deee 01



Reset Circuit

Reset Timing Chart

Thestatesoftheregistersaresummarizedinthefollowingtable:

HT47C07L

Register Reset(Power On)

WDT Time-out(Normal Operation)

RES Reset(Normal Operation)

RES Reset(HALT)

WDT Time-out(HALT)

MP0 x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u


BP - - - - - - - 0 - - - - - - - 0 - - - - - - - 0 - - - - - - - 0 - - - - - - - 0

ACC x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u

PCL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TBLP x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u

TBLH x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u

TBC - - - - - 1 1 1 - - - - - 1 1 1 - - - - - 1 1 1 - - - - - 1 1 1 - - - - - u u u

STATUS - - 0 0 x x x x - - 1 u u u u u - - u u u u u u - - 0 1 u u u u - - 1 1 u u u u

INTC - - 0 0 - 0 0 0 - - 0 0 - 0 0 0 - - 0 0 - 0 0 0 - - 0 0 - 0 0 0 - - u u - u u u

PA 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u u

PAC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u u

PB 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u u

PBC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u u

PC - - - - - - 1 1 - - - - - - 1 1 - - - - - - 1 1 - - - - - - 1 1 - - - - - - u u

PCC - - - - - - 1 1 - - - - - - 1 1 - - - - - - 1 1 - - - - - - 1 1 - - - - - - u u

TMRAH x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u u

TMRAL x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u u

TMRC - 0 0 0 1 - - - - 0 0 0 1 - - - - 0 0 0 1 - - - - 0 0 0 1 - - - - u u u u - - -

TMRBH x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u u

TMRBL x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u u

ADCR - 0 0 x 0 0 0 0 - 0 0 x 0 0 0 0 - 0 0 x 0 0 0 0 - 0 0 x 0 0 0 0 - u u u u u u u

Note:“u”standsforunchanged“x”standsfor“unknown”“-”standsforunimplemented

Rev. 1.10 0 Deee 01 Rev. 1.10 1 Deee 01



HT47C08L

Register Reset(Power On)

WDT Time-out(Normal Operation)

RES Reset(Normal Operation)

RES Reset(HALT)

WDT Time-out(HALT)



BP - - - - - - - 0 - - - - - - - 0 - - - - - - - 0 - - - - - - - 0 - - - - - - - 0

ACC x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u

PCL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TBLP x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u

TBLH x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u

TBC - - - - - 1 1 1 - - - - - 1 1 1 - - - - - 1 1 1 - - - - - 1 1 1 - - - - - u u u

STATUS - - 0 0 x x x x - - 1 u u u u u - - u u u u u u - - 0 1 u u u u - - 1 1 u u u u

INTC - - 0 0 - 0 0 0 - - 0 0 - 0 0 0 - - 0 0 - 0 0 0 - - 0 0 - 0 0 0 - - u u - u u u

PA 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u u

PAC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u u

PB 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u u

PBC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u u

PC - - - 1 1 1 1 1 - - - 1 1 1 1 1 - - - 1 1 1 1 1 - - - 1 1 1 1 1 - - - u u u u u

PCC - - - 1 1 1 1 1 - - - 1 1 1 1 1 - - - 1 1 1 1 1 - - - 1 1 1 1 1 - - - u u u u u

TMRAH x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u u

TMRAL x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u u

TMRC - 0 0 0 1 - - - - 0 0 0 1 - - - - 0 0 0 1 - - - - 0 0 0 1 - - - - u u u u - - -

TMRBH x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u u

TMRBL x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u u

ADCR 0 0 0 x 0 0 0 0 0 0 0 x 0 0 0 0 0 0 0 x 0 0 0 0 0 0 0 x 0 0 0 0 u u u u u u u u

Note:“u”standsforunchanged“x”standsfor“unknown”“-”standsforunimplemented




Input/Output PortsTherearebidirectional input/outputports in themicrocontroller, labeledPA,PBandPC,whicharemappedtothedatamemory[12H],[14H]and[16H]respectively.AlloftheseI/Olinescanbeusedasinputandoutputoperations.Fortheinputoperation,theselinesarenon-latching,thatis,theinputsmustbereadyattheT2risingedgeofinstruction“MOVA,[m]”(m=12H,14Hor16H).Foroutputoperation,allthedataislatchedandremainunchangeduntiltheoutputlatchisrewritten.

Each I/O linehas itsowncontrol register (PAC,PBCandPCC) tocontrol the input/outputconfiguration.With thiscontrol register,CMOSoutputorSchmitt trigger inputwithpull-highresistor structurescanbe reconfigureddynamicallyunder softwarecontrol.To functionasaninput,thecorrespondinglatchofthecontrolregisterhastobesetas"1".Thepull-highresistorwillbeexhibitedautomatically.The inputsourcesalsodependon thecontrol register. If thecontrolregisterbit is"1", theinputwillreadthepadstate("MOV"andread-modify-write instructions).Ifthecontrolregisterbitis"0",thecontentsofthelatcheswillmovetointernaldatabus("MOV"andread-modify-write instructions).The inputpaths(padstateor latches)ofread-modify-writeinstructionsaredependenton thecontrol registerbits.Foroutput function,CMOSis theonlyconfiguration.Thecontrolregistersaremappedtolocations13H,15Hand17Hrespectively.

Afterachipreset, these input/output linesremainathighlevels(pull-high),exceptPC0/PC1asfloating.Eachbitoftheseinput/outputlatchescanbesetorclearedby“SET[m].i”(m=12H,14Hor16H)instructions.Someinstructionsfirstinputdataandthenfollowtheoutputoperations.Forexample,"SET[m].i","CPLA[m]",readtheentireportstates intotheCPU,executethedefinedoperations(bit-operation),andthenwritetheresultsbacktothelatchesortotheaccumulator.

EachbitoftheportAhasthecapabilityofwaking-upthedevices.

ThePA0andPA1arepin-sharedwithBZandBZ,respectively.If theBZmodeisselected, theoutputsignalinoutputmodeofPA0(orPA1)willbeBZ(orBZ)signal.Theinputmodealwaysretainitsoriginalfunctions.The4kHzbuzzeroutputsignals(inoutputmode)arecontrolledbythePA0andPA1dataregisters.ThetruthtableofPA0/BZandPA1/BZarelistedbelow.

PA1 Data Register PA0 Data Register PA1, PA0 Pad Function

0 (CLR PA.1) 0 (CLR PA.0) PA0=BZ PA1=BZ1 (SET PA.1) 0 (CLR PA.0) PA0=BZ PA1=0

X 1 (SET PA.0) PA0=0 PA1=0

Mask Option

Note:BZandELmodefunctionsarenotshowninthisdiagram




ThePA2ispin-sharedwithELcarriersignals.IftheELcarrieroutputisselected,theoutputsignalinoutputmodeofPA2willbetheELcarriersignal.Theinputmodealwaysremainsitsoriginalfunctions.TheELcarrieroutputsignal(inoutputmode)iscontrolledbythePA2dataregister.ThetruthtableofPA2/ELislistedbelow.

PA2 Data Register PA2 Pad Function0 (CLR PA.) PA=01 (SET PA.) PA=EL aie output

EL Timing (fOSC=128kHz)

I/O Register Lists• HT47C07L

Register Name

Bit

7 6 5 4 3 2 1 0PA D7 D6 D5 D D D D1 D0

PAC D7 D6 D5 D D D D1 D0PB D7 D6 D5 D D D D1 D0

PBC D7 D6 D5 D D D D1 D0PC — — — — — — D1 D0

PCC — — — — — — D1 D0

• HT47C08L

Register Name

Bit

7 6 5 4 3 2 1 0PA D7 D6 D5 D D D D1 D0

PAC D7 D6 D5 D D D D1 D0PB D7 D6 D5 D D D D1 D0

PBC D7 D6 D5 D D D D1 D0PC — — — D D D D1 D0

PCC — — — D D D D1 D0

PAC Register

Register Name

Bit

7 6 5 4 3 2 1 0Nae D7 D6 D5 D D D D1 D0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 1 1 1 1 1 1 1 1

Bit7~0 I/OPortAbit7~bit0Input/OutputControl0:Output1:Input

Rev. 1.10 Deee 01 Rev. 1.10 5 Deee 01



PBC Register

Register Name

Bit

7 6 5 4 3 2 1 0Nae D7 D6 D5 D D D D1 D0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 1 1 1 1 1 1 1 1

Bit7~0 I/OPortBbit7~bit0Input/OutputControl0:Output1:Input

PCC Register• HT47C07L

Register Name

Bit

7 6 5 4 3 2 1 0Nae — — — — — — D1 D0R/W — — — — — — R/W R/WPOR — — — — — — 1 1

Bit7~2 Unimplemented,readas"0"Bit1~0 I/OPortCbit1~bit0Input/OutputControl

0:Output1:Input

• HT47C08L

Register Name

Bit

7 6 5 4 3 2 1 0Nae — — — D D D D1 D0R/W — — — R/W R/W R/W R/W R/WPOR — — — 1 1 1 1 1

Bit7~5 Unimplemented,readas"0"Bit4~0 I/OPortCbit4~bit0Input/OutputControl

0:Output1:Input

Rev. 1.10 Deee 01 Rev. 1.10 5 Deee 01



Timer/Event CounterOne16-bit timer/eventcounterorRC typeA/Dconverter is implemented in thedevices.TheADC_TMbit(bit1ofADCRregister)determineswhethertimerAandtimerBarecomposedofone16-bittimer/eventcounterorcomposedofanRCtypeA/Dconverter.

TheTMRAL,TMRAH,TMRBLandTMRBHcomposedofone16-bittimer/eventcounter,whenADC_TMbit is “0”.TheTMRBLandTMRBHare timer/eventcounterpreload registers forlower-orderbyteandhigher-orderbyterespectively.

The timer/eventcounterclocksourcecomes fromsystemclock (fSYS)orexternal source.Theexternalclockinputallowstheuser tocountexternalevents,countexternalRCtypeA/Dclock,measuretimeintervalsorpulsewidths,orgenerateanaccuratetimebase.

Therearesixregistersrelatedtothetimer/eventcounteroperatingmode.TMRAH([20H]),TMRAL([21H]),TMRC([22H]),TMRBH([23H]),TMRBL([24H])andADCR([25H]).WritingtoTMRBLonlywrites thedata intoa lowbytebuffer,andwriting toTMRBHwillwrite thedataand thecontentsofthelowbytebufferintothetime/eventcounterpreloadregister(16-bit)simultaneously.Thetimer/eventcounterpreloadregisterischangedbywritingtoTMRBHoperationsandwritingtoTMRBLwillkeepthetimer/eventcounterpreloadregisterunchanged.

ReadingTMRAHwillalsolatchtheTMRALintothelowbytebuffertoavoidfalsetimingproblem.ReadingTMRALreturnsthecontentsofthelowbytebuffer.Inotherwords, thelowbyteofthetimer/eventcountercannotbereaddirectly.ItmustreadtheTMRAHfirst tomakethelowbytecontentsoftimer/eventcounterbelatchedintothebuffer.

TheTMRCis the timer/eventcountercontrol register,whichdefines the timer/eventcounteroptions.Thetimer/eventcountercontrolregisterdefines theoperatingmode,countingenableordisableandactiveedge.WritingtotimerBlocationputsthestartingvalueinthetimer/eventcounterpreloadregister,whilereadingtimerAyieldsthecontentsofthetimer/eventcounter.TimerBisthetimer/eventcounterpreloadregister.

TheTM0andTM1bitsdefinetheoperationmode.Theeventcountmodeisusedtocountexternalevents,whichmeansthattheclocksource(A/Dclock)comesfromanexternalpin.Thetimermodefunctionsasanormaltimerwiththeclocksourcecomingfromtheinternalclock(fSYS).Finally,thepulsewidthmeasurementmodecanbeusedtocountthehighorlowleveldurationoftheexternalsignal(A/Dclockfrompad:RCINn)(HT47C07L:RCIN;HT47C08L:RCIN0orRCIN1selectedbyCHSEL).Thecountingisbasedonthesystemclock(fSYS).

Intheeventcount,A/Dclockorinternaltimermode,oncethetimer/eventcounterstartscounting,itwillcountfromthecurrentcontentsinthetimer/eventcounter(TMRAHandTMRAL)toFFFFH.Onceoverflowoccurs,thecounterisreloadedfromthetimer/eventcounterpreloadregister(TMRBHandTMRBL)andatthesametimegeneratesthecorrespondinginterruptrequestflag(TF;bit4ofINTC).

InthepulsewidthmeasurementmodewiththeTONandTEbitsequaltoone,oncetheRCINhasreceivedatransientfromlowtohigh(orhightolowiftheTEbitis0)itwillstartcountinguntiltheA/DClockreturnstotheoriginallevelandresetstheTON.Themeasuredresultwillremaininthetimer/eventcountereveniftheactivatedtransientoccursagain.Inotherwords,onlyonecyclemeasurementcanbedone.UntilsettingtheTON,thecyclemeasurementwillfunctionagainaslongasitreceivesfurthertransientpulse.Notethatinthisoperationmode,thetimer/eventcounterstartscountingnotaccordingtothelogiclevelbutaccordingtothetransientedges.Inthecaseofcounteroverflow,thecounterisreloadedfromthetimer/eventcounterpreloadregisterandissuesinterruptrequestjustliketheothertwomodes.

Rev. 1.10 6 Deee 01 Rev. 1.10 7 Deee 01



Toenablethecountingoperation,thetimeronbit(TON;bit4ofTMRC)shouldbesetto1.Inthepulsewidthmeasurementmode,theTONwillautomaticallybeclearedafterthemeasurementcycleiscompleted.Butintheothertwomodes,theTONcanonlyberesetbyinstructions.

In thecaseof timer/eventcounteroffcondition,writingdata to the timer/eventcounterpreloadregisteralsoreloadsthatdatatothetimer/eventcounter.Butifthetimer/eventcounterturnson,datawrittentothetimer/eventcounterpreloadregister iskeptonlyinthetimer/eventcounterpreloadregister.Thetimer/eventcounterwillstilloperateuntiloverflowoccurs.

Whenthetimer/eventcounter(readingTMRAH)isread,theclockwillbeblockedtoavoiderrors.Asthismayresultsinacountingerror,thismustbetakenintoconsideration.

It isstronglyrecommendedto loadfirst thedesiredvalueintoTMRBL,TMRBH,TMRAL,andTMRAHregisters thenturnontherelatedtimer/eventcounterforproperoperation.BecausetheinitialvalueofTMRBL,TMRBH,TMRALandTMRAHareunknown.

Example for Timer/event counter mode (disable interrupt):clr tmrcclr adcr.1 ; set timer modeclr intc.4 ; clear timer/event counter interrupt request flagmov a, low (65536-1000) ; give timer initial valuemov tmrbl, a ; count 1000 time and then overflowmov a, high (65536-1000)mov tmrbh, amov a, 01010000b ; timer clock source=fSYS and timer onmov tmrc, ap10:clr wdt

TMRC Register

Register Name

Bit

7 6 5 4 3 2 1 0Nae — TM1 TM0 TON TE — — —R/W — R/W R/W R/W R/W — — —POR — 0 0 0 1 — — —

Bit7 Unimplemented,readas"0"Bit6~5 TM1,TM0:TOdefinetheoperatingmode

00:Unused01:Eventcountermode(Externalclock:A/DclockfrompadRCIN)10:Timermode(Internalclock:fSYS)11:Pulsewidthmeasurementmode(RCIN,fSYS)

Bit4 TON:Toenable/disabletimercounting0:Disabled1:Enabled

Bit3 TE:DefinestheTMRactiveedgeofthetimer/eventcounterInEventCounterMode(TM1,TM0)=(0,1)1:countonfallingedge0:countonrisingedge

InPulseWidthmeasurementmode(TM1,TM0)=(1,1)1:startcountingontherisingedge,stoponthefallingedge0:startcountingonthefallingedge,stopontherisingedge

Bit2~0 Unimplemented,readas"0"

Rev. 1.10 6 Deee 01 Rev. 1.10 7 Deee 01



Timer/Event Counter – HT47C07L

Timer/Event Counter – HT47C08L

RC Type A/D ConverterAnRCtypeA/Dconverterisimplementedinthedevices.TheA/Dconvertercontainstwo16-bitprogrammablecount-upcountersandthetimerAclocksourcecomesfromthesystemclock.ThetimerBclocksourcecomesfromtheexternalRCoscillatororinternalRCoscillatorselectedbytheTMBSELbitintheADCRregister.TheTMRAL,TMRAH,TMRBLandTMRBHarecomposedoftheA/DconverterwhenADC_TMbit(bit1ofADCRregister)isto1.

TheA/DconvertertimerBclocksourcemaycomefromR-FOscillatorortheinternalRCoscillatorforHT47C07Ldevice.ForHT47C08Ldevice,theA/DconvertertimerBclocksourcemaycomefromR-FOscillator0,R-FOscillator1ortheinternalRCoscillatorwherenisequalto0or1.ThetimerAclocksourceisthesystemclockbysetting(TM1,TM0=1,0).

Therearesix registers related to theA/Dconverter, i.e.,TMRAH,TMRAL,TMRC,TMRBH,TMRBLandADCR.TheinternaltimerclockisinputtoTMRAHandTMRAL,theA/Dclockisinput toTMRBHandTMRBL.Thebit0of theADCRregister,OVB_OVA,determineswhethertimerAor timerBoverflows, then theTFbit issetand timer interruptoccurs.When theA/Dconvertermode timerAor timerBoverflows, theTONbit is resetandstopcounting.WritingTMRAH/TMRBHmakes the startingvaluebeplaced in the timerAor timerBand readingTMRAH/TMRBHretrievesthecontentsofthetimerAortimerB.WritingTMRAL/TMRBLonlywrites thedata intoa lowbytebuffer,andwritingTMRAH/TMRBHwillwrite thedataandthecontentsofthelowbytebufferintothetimerAortimerB(16-bit)simultaneously.ThetimerAortimerBischangedbywritingTMRAH/TMRBHoperationsandwritingTMRAL/TMRBLwillkeepthetimerAortimerBunchanged.

Rev. 1.10 8 Deee 01 Rev. 1.10 9 Deee 01



ReadingTMRAH/TMRBHwillalsolatchtheTMRAL/TMRBLintothelowbytebuffertoavoidfalsetimingproblem.ReadingTMRAL/TMRBLreturnsthecontentsofthelowbytebuffer.Inotherwords,thelowbyteoftimerAortimerBcannotbereaddirectly.ItmustreadtheTMRAH/TMRBHfirsttomakethelowbytecontentsoftimerAortimerBbelatchedintothebuffer.

Thebit2ofADCRdecideswhichresistorandcapacitorcomposeanoscillationcircuitandinputtoTMRBHandTMRBL.

TheTM0andTM1bitsofTMRCdefine the timerAclocksource. It is recommended that thetimerAclocksourceusethesystemclock.

WhentheTONbit(bit4oftheTMRC)issetto"1"thetimerAandtimerBwillstartcountinguntiltimerAortimerBoverflows,thetimer/eventcountergeneratestheinterruptrequestflag(TF;bit4ofINTC)andthetimerAandtimerBstopcountingandresettheTONbitto"0"atthesametime.

IftheTONbitis"1",theTMRAH,TMRAL,TMRBHandTMRBLcannotbereadorwrittento.Onlywhenthetimer/eventcounterisoffandwhentheinstruction"MOV"isusedcanthosefourregistersbereadorwrittento.

“SystemClockOscillator”isusedtooscillatingtheclocksignaltobetheMCUsystemclock.Itcomsumesfewerpowerthanotheroscillators.Thesystemclockisalsothereferenceclocktocounttherealtimeinordertodecreasingpowerconsumption.However,thesystemclockisnotaccurateinvariantoperatingvoltageor invariantambient temperature.Hence, thesystemclockshallbecalibratedfirst.LIRC2OscillatorismoreaccuratethanSystemClockOscillatorinvariantoperatingvoltageor invariantambient temperature,soLIRC2canbeusedtocalibrate theSystemClockOscillator.TheCalibrationcanbeacheievedbyexecutingthestepsbelow.

• Step1:Select“Systemclock” to theclocksourceofTMRAandselect“LIRC2”to theclocksourceofTMRB

• Step2:AssignthevaluesofregistersTMRALandTMRAH

• Step3:SelectTMRAastheinterruptsourceoftimer/eventoverflowoccuranceandthenactivateTMRAintimermodeandTMRBsimultaneously.

• Step4:OnceTMRAoverflowoccur,stopcountingTMRAandTMRBautomaticallyandthencalculatethevarianceofTMRAandTMRB

• Step5:Systemclockcanbecalibratedbythevariancejustcalculatedintheapplicationprogram.

Inordertodecrasepowerconsumption,LIRC2isadvisedtobeturnrdonwhiledoingSystemClockpulsewidthmeasurementandturnedoffwhilefinishingSystemClockpulsewidthmeasurement.

“RtoFOscillator”isusedtooscillatetheclockwhosefrequencyisdecidedbytheexternalresistor.TakethereferencetotheBolckdiagram“RtoFOscillator”,areferenceresistor“REFResistor”issuppliedto“RtoFOscillator”toproduceanoutputclockfrequencyasareferencefrequency.TheThermistor“NIC” issupplied to“R toFOscillator” toproduceanoutputclockfrequencyandthencompare thatfrequencywith thereferencyfrequencytomeasure the temperature.Thetemperaturemeasurementcanbeachievedbyfollowingsteps.

• Step1:Select“Systemclock”totheclocksourceofTMRAandselect“RtoFOscillator”totheclocksourceofTMRB

• Step2:Select theRREFpathas the inputRCpathof“RtoFOscillator”byclearingRSELcontrolbit

• Step3:AssignthevaluesofregistersTMRALandTMRAH

• Step4:SelectTMRAastheinterruptsourceoftimer/eventoverflowoccuranceandthenactivateTMRAintimermodeandTMRB

Rev. 1.10 8 Deee 01 Rev. 1.10 9 Deee 01



• Step5:OnceTMRAoverflowoccur,stopcountingTMRAandTMRBautomaticallyandthencalculatethevarianceofTMRAandTMRB.Thevarianceissaidtobe“Variance1”

• Step6:SelecttheRSENpathastheinputRCpathof“RtoFOscillator”bysettingRSELcontrolbitandthenredotheactionsfromstep4tostep5.Furthermore,thevariancecanbeobtainedandsaidtobe“Variance2”

• Step7:Theoutputfrequencydifferenceof“RSENpath”and“RREFpath”in“RtoFOscillator”canbecalculatedbycomparisonof“Variance1”and“Variance2” inapplicationprogram.Furthermore,theNICtemperaturecanbeobtainedfromthatfrequencydifferencejustcalculated.

R-FOscillator0on/offcontrolforHT47C07LTM1 TM0 ADC/TM TON R-F OSC0 Notes

TON Off Don’t Cae Don’t Cae Don’t Cae 0 OFF —Tie Mode 1 0 0 1 OFF —

Event Counte Mode 0 1 1 1 ONThe TE it ust e set high iediately afte the TON it has een set high

PWM Mode 1 1 1 1 ON —UNUSED 0 0 Don’t Cae 1 OFF —Event Counte Mode o PWM Mode Don’t Cae 1 0 1 ON —

R-FOscillator0andR-FOscillator1on/offcontrolforHT47C08L

TM1 TM0 ADC/TM CHSEL TON R-F OSC0

R-F OSC1 Notes

TON Off Don’t Cae

Don’t Cae

Don’t Cae

Don’t Cae 0 OFF OFF —

Tie Mode 1 0 0 Don’t Cae 1 OFF OFF —

Event Counte Mode 0 1 1 0 1 ON OFFThe TE it ust e set high iediately afte the TON it has een set high

Event Counte Mode 0 1 1 1 1 OFF ONThe TE it ust e set high iediately afte the TON it has een set high

PWM Mode 1 1 1 1 1 OFF ON —PWM Mode 1 1 1 0 1 ON OFF —

UNUSED 0 0 Don’t Cae

Don’t Cae 1 OFF OFF —

Event Counte Modeo PWM Mode

Don’t Cae 1 0 0 1 ON OFF —

Event Counte Modeo PWM Mode

Don’t Cae 1 0 1 1 OFF ON —

Rev. 1.10 0 Deee 01 Rev. 1.10 1 Deee 01



RC Type A/D Converter

2200pF

RefResistor

30kΩ

NIC20kΩ~60kΩ

Q

QSET

CLR

S

R

VIL

VIH

R to F Oscillator Output

RSELRREF

RSEN

R to F Oscillator - HT47C07L

Rev. 1.10 0 Deee 01 Rev. 1.10 1 Deee 01



2200pF

RefResistor

30kΩ

NIC20kΩ~60kΩ

Q

QSET

CLR

S

R

VIL

VIHR to F Oscillator Output

RSELRREF0

RSEN0

2200pF

RefResistor

30kΩ

NIC20kΩ~60kΩ

Q

QSET

CLR

S

R

RSEL

RREF1

RSEN1

R-F Output1

CHSEL

VIL

VIH

R-F Output0

R to F Oscillator - HT47C08L

Syste Clok Output

System Clock Oscillator

Q

QSET

CLR

S

R

VIL

VIH

LIRC Output

LIRC2 Oscillator




ADCR Register• ADCR Register – HT47C07L

Bit 7 6 5 4 3 2 1 0Nae — TMBSEL LIRCON BLF BON RSEL ADC_TM OVB_OVAR/W — R/W R/W R/W R/W R/W R/W R/WPOR — 0 0 0 0 0 0 0

Bit7 Unimplemented,readas"0"Bit6 TMBSEL:TimerBclocksourceselect

0:LIRC2oscillator1:RtoFOscillator

Note that thisbit isonlyavailablewhen theRC typeA/Dconverter is enabled(ADC_TM=1).

Bit5 LIRC2ON:LIRC2oscillatorenablecontrol0:Disable1:Enable

Bit4 BLF:Lowvoltageflag0:Batterypowerisgood1:Lowbattery

Bit3 BON:Lowvoltagedetectorenablecontrol0:Disable1:Enable

Bit2 RSEL:A/DConverteroperatingmodeselect0:RREF~CREFoscillation(referenceresistorandreferencecapacitor)1:RSEN~CREFoscillation(resistorsensorandreferencecapacitor)

Bit1 ADC_TM:RCTypeA/DConverteror16-bitTimer/Eventcounterenablecontrol0:16-bitTimer/Eventcounterisenabled1:RCTypeA/DConverterisenabled

Bit0 OVB_OVA:Selecttimer/eventcounterinterruptsource0:TimerAoverflow1:TimerBoverflow

IntheRCtypeA/Dconvertermode,thisbitisusedtodefinethetimer/eventcounterinterruptwhichcomesfromtimerAorBoverflow.Intimer/eventcountermode,thisbitisnotavailable.




• ADCR Register – HT47C08L

Bit 7 6 5 4 3 2 1 0Nae CHSEL TMBSEL LIRCON BLF BON RSEL ADC_TM OVB_OVAR/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0

Bit7 CHSEL:SlecttheinputchannelofR-FOscillatorOutput0:R-FOutput01:R-FOutput1

Bit6 TMBSEL:TimerBclocksourceselect0:LIRC2oscillator1:RtoFoscillator

Note that thisbit isonlyavailablewhen theRC typeA/Dconverter is enabled(ADC_TM=1).

Bit5 LIRC2ON:LIRC2oscillatorenablecontrol0:Disable1:Enable

Bit4 BLF:Lowvoltageflag0:Batterypowerisgood1:Lowbattery

Bit3 BON:Lowvoltagedetectorenablecontrol0:Disable1:Enable

Bit2 RSEL:A/DConverteroperatingmodeselect0:RREF~CREFoscillation(referenceresistorandreferencecapacitor)1:RSEN~CREFoscillation(resistorsensorandreferencecapacitor)

Bit1 ADC_TM:RCTypeA/DConverteror16-bitTimer/Eventcounterenablecontrol0:16-bitTimer/Eventcounterisenabled1:RCTypeA/DConverterisenabled

Bit0 OVB_OVA:Selecttimer/eventcounterinterruptsource0:TimerAoverflow1:TimerBoverflow

IntheRCtypeA/Dconvertermode,thisbitisusedtodefinethetimer/eventcounterinterruptwhichcomesfromtimerAorBoverflow.Intimer/eventcountermode,thisbitisnotavailable.

Rev. 1.10 Deee 01 Rev. 1.10 5 Deee 01



Example for RC type A/D converter mode (Timer A overflow):clr tmrcclr adcr.1 ; set timer modeclr intc.4 ; clear timer/event counter interrupt request flagmov a, low (65536-1000) ; give timer A initial valuemov tmrbl, a ; count 1000 time and then overflowmov a, high (65536-1000)mov tmrbh, amov a, 00000010b ; RREF~CREF ; set RC type ADC mode ; set Timer A overflowmov adcr, a mov a, 00h ; give timer B initial valuemov tmrbl, amov a, 00hmov tmrbh, amov a, 01010000b ; timer A clock source=fSYS and timer onmov tmrc, ap10:clr wdtsnz intc.4 ; polling timer/event counter interrupt request flagjmp p10clr intc.4 ; clear timer/event counter interrupt request flag ; program continue

Example for RC type A/D converter mode (Timer B overflow):clr tmrcclr adcr.1 ; set timer modeclr intc.4 ; clear timer/event counter interrupt request flagmov a, 00h ; give timer A initial valuemov tmrbl, amov a, 00hmov tmrbh, amov a, 00000011b ; RREF~CREF ; set RC type ADC mode ; set Timer B overflowmov adcr,amov a, low (65536-1000) ; give timer B initial valuemov tmrbl, a ; count 1000 time and then overflowmov a, high (65536-1000)mov tmrbh, amov a, 00110000b ; timer A clock source=fSYS and timer onmov tmrc, ap10:clr wdtsnz intc.4 ; polling timer/event counter interrupt request flagjmp p10clr intc.4 ; clear timer/event counter interrupt request flag ; program continue

Rev. 1.10 Deee 01 Rev. 1.10 5 Deee 01



Power Down Operation – HALTTheHALTmodeisinitializedbythe“HALT”instructionandresultsinthefollowing:

• ThefOSCandfSYSwillstillworkorstopdependingontheoscillator/LCDfunctionon/offinthepowerdownmodeoption,butT1willbeturnedoff.

• Thecontentsoftheon-chipRAMandregistersremainunchanged.

• TheWDTwillbeclearedandresumecountingiftheoscillatorisswitchedoninthepowerdownmode.

• AllI/Oportsmaintaintheiroriginalstatus.

• ThePDFflagissetandtheTOflagiscleared.

• TheLCDdrivercanbeturnedofforondependinguponthat theLCDfunctionisdisabledorenabledinthepowerdownmode.

• Thetimebasewillstoporkeeprunningdependinguponthattheoscillatorisswitchedofforoninthepowerdownmode.

PortAwake-upand internal interruptwake-upmethodscanbeconsideredasacontinuationofnormalexecution.AwakeningfromanI/Oportstimulus,theprogramwillresumeexecutionatthenextinstruction.Ifawakeningfromaninternalinterrupt,twopossibilitiesmayoccur.Iftheinternalinterruptisdisabledortheinternalinterruptisenabledbutthestackisfull,theprogramwillresumeexecutionatthenextinstruction.Iftheinternalinterruptisenabledandthestackisnotfull,aregularinterruptresponsetakesplace.

Ifaninternalinterruptrequestflagissetto1beforeenteringthepowerdownmode,thewake-upfunctionoftherelatedinterruptwillbedisabled.

Ifthewake-upresultsfromaninternalinterruptacknowledgesignal,theactualinterruptsubroutineexecutionwillbedelayedbymore thanonecycle.However, if thewake-upresults in thenextinstructionexecutionfollowingtheHALTinstruction,theexecutionwillbeperformedimmediately.

Tominimizepowerconsumption,alltheI/Opinsshouldbecarefullymanagedbeforeenteringthepowerdownmode.

InterruptsThedevicesprovideaninternaltimer/eventcounterinterruptandaninternaltimebaseinterrupt.Theinterruptcontrolregister(INTC;0BH)containstheinterruptcontrolbitstosettheenable/disableandinterruptrequestflags.

Onceaninterruptsubroutineisserviced,allotherinterruptswillbeblockedbyclearingtheEMIbit.Thisschememaypreventanyfurtherinterruptnesting.Otherinterruptrequestsmayoccurduringthisinterval,butonlytheinterruptrequestflagisrecorded.Ifanotherinterruptrequiresservicingwhiletheprogramisintheinterruptserviceroutine,theprogrammershouldsettheEMIbitandthecorrespondingbitoftheINTCtoallowinterruptnesting.Ifthestackisfull,theinterruptrequestwillnotbeacknowledged,eveniftherelatedinterruptisenabled,untilthestackpointerisdecremented.Ifimmediateserviceisdesired,thestackmustbepreventedfrombecomingfull.

Asan interrupt is serviced,acontrol transferoccursbypushing theprogramcounteronto thestack,followedbyabranchtoasubroutineatspecifiedlocationsintheprogrammemory.Onlytheprogramcounterispushedontothestack.Ifthecontentsoftheregisterandstatusregister(STATUS)isalteredbytheinterruptserviceprogramwhichcorruptsthedesiredcontrolsequence,thecontentsmustbesavedfirst.

Rev. 1.10 6 Deee 01 Rev. 1.10 7 Deee 01



Theinternaltimer/eventcounterinterruptisinitializedbysettingthetimer/eventcounterinterruptrequestflag(TF;bit4ofINTC),causedbyatimerAortimerBoverflow.Whentheinterruptisenabled,andthestackisnotfullandtheTFbitisset,asubroutinecalltolocation04Hwilloccur.Therelated interrupt request flag (TF)willbe resetand theEMIbitcleared todisable furtherinterrupts.

Thetimebaseinterruptisinitializedbysettingthetimebaseinterruptrequestflag(TBF;bit5ofINTC),causedbyaregulartimebasesignal.Whentheinterruptisenabled,andthestackisnotfullandtheTBFbitisset,asubroutinecalltolocation08Hwilloccur.Therelatedinterruptrequestflag(TBF)willberesetandtheEMIbitclearedtodisablefurtherinterrupts.

Duringtheexecutionofaninterruptsubroutine,otherinterruptacknowledgmentsarehelduntiltheRETIinstructionisexecutedortheEMIbitandtherelatedinterruptcontrolbitaresetto1(ifthestackisnotfull).Toreturnfromtheinterruptsubroutine,RETorRETIinstructionmaybeinvoked.RETIwillsettheEMIbittoenableaninterruptservice,butRETdoesnot.

InterruptsoccurringintheintervalbetweentherisingedgesoftwoconsecutiveT2pulses,willbeservicedonthelatterofthetwoT2pulses,ifthecorrespondinginterruptsareenabled.Inthecaseofsimultaneousrequeststhefollowingtableshowstheprioritythatisapplied.ThesecanbemaskedbyresettingtheEMIbit.

Interrupt Source Priority VectorTie/event ounte inteupt 1 0HTie ase inteupt 08H

INTC Register

Register Name

Bit

7 6 5 4 3 2 1 0Nae — — TBF TF — ETBI ETI EMIR/W — — R/W R/W — R/W R/W R/WPOR — — 0 0 — 0 0 0

Bit7~6 Unimplemented,readas"0"Bit5 TBF:Timebaseinterruptrequestflag

0:Inactive1:Active

Bit4 TF:Timer/eventcounterinterruptrequestflag0:Inactive1:Active

Bit3 Unimplemented,readas"0"Bit2 ETBI:Controlsthetimebaseinterrupt

0:Disabled1:Enabled

Bit1 ETI:Controlsthetimer/eventcounterinterrupt0:Disabled1:Enabled

Bit0 EMI:Controlsthemasterorglobalinterrupt0:Disabled1:Enabled

Rev. 1.10 6 Deee 01 Rev. 1.10 7 Deee 01



LCD Display MemoryThedevicesprovideanareaofembeddeddatamemoryforLCDdisplay.ThisareaislocatedintheRAMatBank1.Bankpointer(BP;locatedat04HoftheRAM)istheswitchbetweentheRAMandtheLCDdisplaymemory.WhentheBPissetas01H,anydatawrittenintotheaddressfrom40Hto53Horfrom40Hto54HwillaffecttheLCDdisplay.WhentheBPisclearedto00H,anydatawrittenintotheaddressfrom40Hto53Horfrom40Hto54Hmeanstoaccessthegeneralpurposedatamemory.TheLCDdisplaycanbereadandwrittentoonlybyindirectaddressingmodeusingMP1.Whendataiswrittenintothedisplaydataarea, it isautomaticallyreadbytheLCDdriverwhichthengeneratesthecorrespondingLCDdrivingsignals.Toturnthedisplayonoroff,a"1"ora"0"iswrittentothecorrespondingbitofthedisplaymemory,respectively.ThefigureillustratesthemappingbetweenthedisplaymemoryandLCDpatternforthedevices.

LCD Display Memory (Bank 1) – HT47C07L

LCD Display Memory (Bank 1) – HT47C08L

LCD Driver OutputTheoutputnumberof theLCDdriverdevicecanbe20×2or19×3(i.e.,1/2dutyor1/3duty)forHT47C07Land21×3(i.e.,1/3duty)forHT47C08Ldeterminedbyamaskoption.TheLCDdriverbiastypecanonlybe“C”type.AcapacitormountedbetweenC1andC2pinsisneeded.AcapacitormountedbetweenVApinandgroundisrequiredif1/2biaslevelisselected.NotethatfortheHT47C08Ldeviceif the1/3dutyisselected, theLCDdriverbiaswillbesetto1/2bias.Thecapacitorswithacapacitancevalueof0.1μFaresuggestedtobeusedfortheLCDbiasgenerator.TherelationshipbetweenLCDbias type,bias levelsandcapacitorconnectionsare listed in thefollowingtable.

Bias Types Bias Levels C1/C2 VA Pin VC PinC 1/ 0.1μF 0.1μF x

Rev. 1.10 8 Deee 01 Rev. 1.10 9 Deee 01



AclocksourceisnecessarytodrivetheLCDdriverandtherecommendedclockfrequencytodrivetheLCDdriverisabout4kHz.SincetheLCDdriverclockisderivedfromthesystemclock, thesystemclockshouldbedividedbyaselectedratiodeterminedbymaskoptionstoobtainaproperLCDdriverclockfrequency.

Clock Source Frequency LCD Clock Division Ratio LCD Driver Clock Frequency18kHz 1/5 kHz6kHz 1/ kHzkHz 1/ kHz

Note:VA=VDD×2,VB=VDD

LCD Driver Output (1/2 duty, 1/2 bias)

Rev. 1.10 8 Deee 01 Rev. 1.10 9 Deee 01



Note:VA=VDD×2,VB=VDD

LCD Driver Output (1/3 duty, 1/2 bias)

Rev. 1.10 0 Deee 01 Rev. 1.10 1 Deee 01



Low Voltage Detector – LVDThedevicesprovidealowvoltagedetectorforbatterysystemapplication.IftheLVDisonandthebatteryvoltageislowerthanthespecifiedvalue,thelowvoltageflag(BLF;bit4ofADCRregister)isset.Thespecifiedvaluemaybesetas1.3V±0.05V,1.27V±0.05Vor1.25V±0.05Vbymaskoptions.Thelowvoltagedetectorcircuitcanbeturned“On”or“Off”bywritinga“1”ora“0”toBON(bit3ofADCRregister).TheBLFisinvalidwhentheBONisclearedas“0”.SetBON=0aftercheckingthevoltagetopreventfromDCcurrentconsumptionofLVD.

Mask OptionsThefollowingtableshowsmanykindsofoptionsinthedevices.Alltheseoptionsshouldbedefinedinordertoensurepropersystemfunctioning.

No. Options

1 Intenal RC osillato fequeny seletion: kHz 6kHz o 18kHz

LVD voltage seletion: 1.5V 1.7V o 1.V

WDT funtion: Enale o disale

Buzze output fequeny seletion: fSYS/ fSYS/ fSYS/ o fSYS/5

5 To define the PA0/PA1 output function: Noal I/O funtion o Buzze output (PA0: BZ; PA1: BZ)

6 To define the PA2 output function: Noal I/O funtion o EL aie output

7 Osillato/LCD ae on o off when CPU entes powe down ode: Off o on

8 PA0~PA7 pull-high funtion: Enale o disale

9 PB0~PB7 pull-high funtion: Enale o disale

10 PC0~PC1 fo HT7C07L/PC0~PC fo HT7C08L pull-high funtion: Enale o disale

11 LCD segent seletion (SEG9~SEG18): I/O funtion o LCD segent

1LCD duty seletion(*):Fo HT7C07L: 1/ duty ( oon) o 1/ duty ( oon)Fo HT7C08L: 1/ duty ( oon 1/ ias)

1 LCD dive lok seletion: fSYS/ fSYS/ fSYS/5 o fSYS/6

ForHT47C07Ldevice:

Ifthe1/2dutyisselected,theCOM2/SEG19pinisusedasaLCDsegmentoutputSEG19.

Ifthe1/3dutyisselected,theCOM2/SEG19pinisusedasaLCDcommonoutputCOM2.

Rev. 1.10 40 December 23, 2014 Rev. 1.10 41 December 23, 2014



Application Circuits

HT47C07L

HT47C08L




Instruction Set

IntroductionCentral to thesuccessfuloperationofanymicrocontroller is its instructionset,whichisasetofprograminstructioncodesthatdirectsthemicrocontrollertoperformcertainoperations.InthecaseofHoltekmicrocontrollers,acomprehensiveandflexiblesetofover60instructionsisprovidedtoenableprogrammerstoimplementtheirapplicationwiththeminimumofprogrammingoverheads.

Foreasierunderstandingofthevariousinstructioncodes, theyhavebeensubdividedintoseveralfunctionalgroupings.

Instruction TimingMostinstructionsareimplementedwithinoneinstructioncycle.Theexceptionstothisarebranch,call,or tablereadinstructionswheretwoinstructioncyclesarerequired.Oneinstructioncycleisequalto4systemclockcycles,thereforeinthecaseofan8MHzsystemoscillator,mostinstructionswouldbeimplementedwithin0.5µsandbranchorcall instructionswouldbeimplementedwithin1µs.Althoughinstructionswhichrequireonemorecycle to implementaregenerally limited totheJMP,CALL,RET,RETIandtablereadinstructions, it is important torealize thatanyotherinstructionswhichinvolvemanipulationoftheProgramCounterLowregisterorPCLwillalsotakeonemorecycletoimplement.AsinstructionswhichchangethecontentsofthePCLwill implyadirect jumptothatnewaddress,onemorecyclewillberequired.Examplesofsuchinstructionswouldbe″CLRPCL″or″MOVPCL,A″.Forthecaseofskipinstructions,itmustbenotedthatiftheresultofthecomparisoninvolvesaskipoperationthenthiswillalsotakeonemorecycle,ifnoskipisinvolvedthenonlyonecycleisrequired.

Moving and Transferring DataThe transferofdatawithin themicrocontrollerprogram isoneof themost frequentlyusedoperations.MakinguseofthreekindsofMOVinstructions,datacanbetransferredfromregisterstotheAccumulatorandvice-versaaswellasbeingabletomovespecificimmediatedatadirectlyintotheAccumulator.Oneofthemostimportantdatatransferapplicationsis toreceivedatafromtheinputportsandtransferdatatotheoutputports.

Arithmetic OperationsTheabilitytoperformcertainarithmeticoperationsanddatamanipulationisanecessaryfeatureofmostmicrocontrollerapplications.WithintheHoltekmicrocontrollerinstructionsetarearangeofaddandsubtract instructionmnemonicstoenablethenecessaryarithmetictobecarriedout.Caremustbe taken toensurecorrecthandlingofcarryandborrowdatawhenresultsexceed255foradditionandlessthan0forsubtraction.TheincrementanddecrementinstructionsINC,INCA,DECandDECAprovideasimplemeansofincreasingordecreasingbyavalueofoneofthevaluesinthedestinationspecified.




Logical and Rotate OperationsThestandardlogicaloperationssuchasAND,OR,XORandCPLallhavetheirowninstructionwithintheHoltekmicrocontroller instructionset.Aswiththecaseofmost instructionsinvolvingdatamanipulation, datamust pass through theAccumulatorwhichmay involve additionalprogrammingsteps. Inall logicaldataoperations, thezero flagmaybeset if the resultof theoperationiszero.AnotherformoflogicaldatamanipulationcomesfromtherotateinstructionssuchasRR,RL,RRCandRLCwhichprovideasimplemeansofrotatingonebitrightorleft.Differentrotateinstructionsexistdependingonprogramrequirements.Rotateinstructionsareusefulforserialportprogrammingapplicationswheredatacanberotatedfromaninternalregister intotheCarrybitfromwhereitcanbeexaminedandthenecessaryserialbitsethighorlow.Anotherapplicationwhererotatedataoperationsareusedistoimplementmultiplicationanddivisioncalculations.

Branches and Control TransferProgrambranchingtakestheformofeitherjumpstospecifiedlocationsusingtheJMPinstructionortoasubroutineusingtheCALLinstruction.Theydifferinthesensethatinthecaseofasubroutinecall, theprogrammustreturntotheinstructionimmediatelywhenthesubroutinehasbeencarriedout.ThisisdonebyplacingareturninstructionRETinthesubroutinewhichwillcausetheprogramtojumpbacktotheaddressrightaftertheCALLinstruction.InthecaseofaJMPinstruction,theprogramsimplyjumpstothedesiredlocation.Thereisnorequirementtojumpbacktotheoriginaljumpingoffpointas in thecaseof theCALLinstruction.Onespecialandextremelyusefulsetofbranch instructionsare theconditionalbranches.Hereadecision is firstmaderegarding theconditionofacertaindatamemoryorindividualbits.Dependingupontheconditions,theprogramwillcontinuewiththenextinstructionorskipoveritandjumptothefollowinginstruction.Theseinstructionsarethekeytodecisionmakingandbranchingwithintheprogramperhapsdeterminedbytheconditionofcertaininputswitchesorbytheconditionofinternaldatabits.

Bit OperationsTheabilitytoprovidesinglebitoperationsonDataMemoryisanextremelyflexiblefeatureofallHoltekmicrocontrollers.Thisfeature isespeciallyusefulforoutputportbitprogrammingwhereindividualbitsorportpinscanbedirectlysethighorlowusingeitherthe″SET[m].i″or″CLR[m].i″instructionsrespectively.Thefeatureremovestheneedforprogrammerstofirstreadthe8-bitoutputport,manipulatetheinputdatatoensurethatotherbitsarenotchangedandthenoutputtheportwiththecorrectnewdata.Thisread-modify-writeprocessistakencareofautomaticallywhenthesebitoperationinstructionsareused.

Table Read OperationsDatastorage isnormally implementedbyusing registers.However,whenworkingwith largeamountsoffixeddata, thevolumeinvolvedoftenmakesit inconvenienttostorethefixeddataintheDataMemory.Toovercomethisproblem,HoltekmicrocontrollersallowanareaofProgramMemorytobesetupasatablewheredatacanbedirectlystored.Asetofeasytouseinstructionsprovides themeansbywhich this fixeddatacanbereferencedandretrievedfromtheProgramMemory.

Other OperationsInaddition to theabovefunctional instructions,a rangeofother instructionsalsoexistsuchasthe″HALT″instructionforPower-downoperationsand instructions tocontrol theoperationoftheWatchdogTimerfor reliableprogramoperationsunderextremeelectricorelectromagneticenvironments.Fortheirrelevantoperations,refertothefunctionalrelatedsections.

Rev. 1.10 Deee 01 Rev. 1.10 5 Deee 01



Instruction Set SummaryThefollowingtabledepictsasummaryoftheinstructionsetcategorisedaccordingtofunctionandcanbeconsultedasabasicinstructionreferenceusingthefollowinglistedconventions.

Table Conventionsx:Bitsimmediatedatam:DataMemoryaddressA:Accumulatori:0~7numberofbitsaddr:Programmemoryaddress

Mnemonic Description Cycles Flag AffectedArithmeticADD A[] ADDM A[] ADD Ax ADC A[] ADCM A[] SUB Ax SUB A[] SUBM A[] SBC A[] SBCM A[] DAA []

Add Data Meoy to ACC Add ACC to Data Meoy Add iediate data to ACC Add Data Meoy to ACC with Cay Add ACC to Data eoy with Cay Sutat iediate data fo the ACC Sutat Data Meoy fo ACC Sutat Data Meoy fo ACC with esult in Data Meoy Sutat Data Meoy fo ACC with Cay Sutat Data Meoy fo ACC with Cay esult in Data Meoy Deial adjust ACC fo Addition with esult in Data Meoy

1 1Note

1 1

1Note 1 1

1Note 1

1Note 1Note

Z C AC OV Z C AC OV Z C AC OV Z C AC OV Z C AC OV Z C AC OV Z C AC OV Z C AC OV Z C AC OV Z C AC OV

CLogic Operation

AND A[] OR A[] XOR A[] ANDM A[] ORM A[] XORM A[] AND Ax OR Ax XOR Ax CPL [] CPLA []

Logial AND Data Meoy to ACC Logial OR Data Meoy to ACC Logial XOR Data Meoy to ACC Logial AND ACC to Data Meoy Logial OR ACC to Data Meoy Logial XOR ACC to Data Meoy Logial AND iediate Data to ACC Logial OR iediate Data to ACC Logial XOR iediate Data to ACC Copleent Data Meoy Copleent Data Meoy with esult in ACC

1 1 1

1Note

1Note

1Note

1

1

1

1Note

1

Z Z Z Z Z Z Z Z Z Z Z

Increment & Decrement

INCA [] INC [] DECA [] DEC []

Ineent Data Meoy with esult in ACC Ineent Data Meoy Deeent Data Meoy with esult in ACC Deeent Data Meoy

1 1Note

1

1Note

Z Z Z Z

RotateRRA [] RR [] RRCA [] RRC [] RLA [] RL [] RLCA [] RLC []

Rotate Data Meoy ight with esult in ACC Rotate Data Meoy ight Rotate Data Meoy ight though Cay with esult in ACC Rotate Data Meoy ight though Cay Rotate Data Meoy left with esult in ACC Rotate Data Meoy left Rotate Data Meoy left though Cay with esult in ACC Rotate Data Meoy left though Cay

1 1Note

1 1Note

1 1Note

1 1Note

None None

C C

None None

C C

Data MoveMOV A[] MOV []A MOV Ax

Move Data Meoy to ACC Move ACC to Data Meoy Move iediate data to ACC

1 1Note

1

None None None

Bit Operation

Rev. 1.10 Deee 01 Rev. 1.10 5 Deee 01



Mnemonic Description Cycles Flag AffectedCLR [].i SET [].i

Clea it of Data Meoy Set it of Data Meoy

1Note 1Note

None None

BranchJMP add SZ [] SZA [] SZ [].i SNZ [].i SIZ [] SDZ [] SIZA [] SDZA [] CALL add RET RET Ax RETI

Jup unonditionally Skip if Data Meoy is zeo Skip if Data Meoy is zeo with data oveent to ACC Skip if it i of Data Meoy is zeo Skip if it i of Data Meoy is not zeo Skip if ineent Data Meoy is zeo Skip if deeent Data Meoy is zeo Skip if ineent Data Meoy is zeo with esult in ACC Skip if deeent Data Meoy is zeo with esult in ACC Suoutine all Retun fo suoutine Retun fo suoutine and load iediate data to ACC Retun fo inteupt

1Note 1note 1Note

1Note 1Note 1Note 1Note 1Note

None None None None None None None None None None None None None

Table ReadTABRDC [] TABRDL []

Read tale to TBLH and Data Meoy Read tale (last page) to TBLH and Data Meoy

Note Note

None None

MiscellaneousNOP CLR [] SET [] CLR WDT CLR WDT1 CLR WDT SWAP [] SWAPA [] HALT

No opeation Clea Data Meoy Set Data Meoy Clea Wathdog Tie Pe-lea Wathdog Tie Pe-lea Wathdog Tie Swap niles of Data Meoy Swap niles of Data Meoy with esult in ACC Ente powe down ode

1 1Note 1Note

1 1 1

1Note 1 1

None None None

TO PDF TO PDF TO PDF

None None

TO PDF

Note:1.Forskipinstructions,iftheresultofthecomparisoninvolvesaskipthentwocyclesarerequired,ifnoskiptakesplaceonlyonecycleisrequired.

2.AnyinstructionwhichchangesthecontentsofthePCLwillalsorequire2cyclesforexecution.

3.Forthe″CLRWDT1″and″CLRWDT2″instructionstheTOandPDFflagsmaybeaffectedbytheexecutionstatus.TheTOandPDFflagsareclearedafterboth″CLRWDT1″and″CLRWDT2″instructionsareconsecutivelyexecuted.OtherwisetheTOandPDFflagsremainunchanged.

Rev. 1.10 6 Deee 01 Rev. 1.10 7 Deee 01



Instruction Definition

ADC A,[m] AddDataMemorytoACCwithCarryDescription ThecontentsofthespecifiedDataMemory,Accumulatorandthecarryflagareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+[m]+CAffectedflag(s) OV,Z,AC,C

ADCM A,[m] AddACCtoDataMemorywithCarryDescription ThecontentsofthespecifiedDataMemory,Accumulatorandthecarryflagareadded. TheresultisstoredinthespecifiedDataMemory.Operation [m]←ACC+[m]+CAffectedflag(s) OV,Z,AC,C

ADD A,[m] AddDataMemorytoACCDescription ThecontentsofthespecifiedDataMemoryandtheAccumulatorareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+[m]Affectedflag(s) OV,Z,AC,C

ADD A,x AddimmediatedatatoACCDescription ThecontentsoftheAccumulatorandthespecifiedimmediatedataareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+xAffectedflag(s) OV,Z,AC,C

ADDM A,[m] AddACCtoDataMemoryDescription ThecontentsofthespecifiedDataMemoryandtheAccumulatorareadded. TheresultisstoredinthespecifiedDataMemory.Operation [m]←ACC+[m]Affectedflag(s) OV,Z,AC,C

AND A,[m] LogicalANDDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalAND operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″AND″[m]Affectedflag(s) Z

AND A,x LogicalANDimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalAND operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″AND″xAffectedflag(s) Z

ANDM A,[m] LogicalANDACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalAND operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″AND″[m]Affectedflag(s) Z

Rev. 1.10 6 Deee 01 Rev. 1.10 7 Deee 01



CALL addr SubroutinecallDescription Unconditionallycallsasubroutineatthespecifiedaddress.TheProgramCounterthen incrementsby1toobtaintheaddressofthenextinstructionwhichisthenpushedontothe stack.Thespecifiedaddressisthenloadedandtheprogramcontinuesexecutionfromthis newaddress.Asthisinstructionrequiresanadditionaloperation,itisatwocycleinstruction.Operation Stack←ProgramCounter+1 ProgramCounter←addrAffectedflag(s) None

CLR [m] ClearDataMemoryDescription EachbitofthespecifiedDataMemoryisclearedto0.Operation [m]←00HAffectedflag(s) None

CLR [m].i ClearbitofDataMemoryDescription BitiofthespecifiedDataMemoryisclearedto0.Operation [m].i←0Affectedflag(s) None

CLR WDT ClearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF

CLR WDT1 Pre-clearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Notethatthisinstructionworksin conjunctionwithCLRWDT2andmustbeexecutedalternatelywithCLRWDT2tohave effect.RepetitivelyexecutingthisinstructionwithoutalternatelyexecutingCLRWDT2will havenoeffect.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF

CLR WDT2 Pre-clearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Notethatthisinstructionworksinconjunction withCLRWDT1andmustbeexecutedalternatelywithCLRWDT1tohaveeffect. RepetitivelyexecutingthisinstructionwithoutalternatelyexecutingCLRWDT1willhaveno effect.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF

CPL [m] ComplementDataMemoryDescription EachbitofthespecifiedDataMemoryislogicallycomplemented(1′scomplement).Bitswhich previouslycontaineda1arechangedto0andviceversa.Operation [m]←[m]Affectedflag(s) Z

Rev. 1.10 8 Deee 01 Rev. 1.10 9 Deee 01



CPLA [m] ComplementDataMemorywithresultinACCDescription EachbitofthespecifiedDataMemoryislogicallycomplemented(1′scomplement).Bitswhich previouslycontaineda1arechangedto0andviceversa.Thecomplementedresultisstoredin theAccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]Affectedflag(s) Z

DAA [m] Decimal-AdjustACCforadditionwithresultinDataMemoryDescription ConvertthecontentsoftheAccumulatorvaluetoaBCD(BinaryCodedDecimal)value resultingfromthepreviousadditionoftwoBCDvariables.Ifthelownibbleisgreaterthan9 orifACflagisset,thenavalueof6willbeaddedtothelownibble.Otherwisethelownibble remainsunchanged.Ifthehighnibbleisgreaterthan9oriftheCflagisset,thenavalueof6 willbeaddedtothehighnibble.Essentially,thedecimalconversionisperformedbyadding 00H,06H,60Hor66HdependingontheAccumulatorandflagconditions.OnlytheCflag maybeaffectedbythisinstructionwhichindicatesthatiftheoriginalBCDsumisgreaterthan 100,itallowsmultipleprecisiondecimaladdition.Operation [m]←ACC+00Hor [m]←ACC+06Hor [m]←ACC+60Hor [m]←ACC+66HAffectedflag(s) C

DEC [m] DecrementDataMemoryDescription DatainthespecifiedDataMemoryisdecrementedby1.Operation [m]←[m]−1Affectedflag(s) Z

DECA[m] DecrementDataMemorywithresultinACCDescription DatainthespecifiedDataMemoryisdecrementedby1.Theresultisstoredinthe Accumulator.ThecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]−1Affectedflag(s) Z

HALT EnterpowerdownmodeDescription Thisinstructionstopstheprogramexecutionandturnsoffthesystemclock.Thecontentsof theDataMemoryandregistersareretained.TheWDTandprescalerarecleared.Thepower downflagPDFissetandtheWDTtime-outflagTOiscleared.Operation TO←0 PDF←1Affectedflag(s) TO,PDF

INC [m] IncrementDataMemoryDescription DatainthespecifiedDataMemoryisincrementedby1.Operation [m]←[m]+1Affectedflag(s) Z

INCA [m] IncrementDataMemorywithresultinACCDescription DatainthespecifiedDataMemoryisincrementedby1.TheresultisstoredintheAccumulator. ThecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]+1Affectedflag(s) Z

Rev. 1.10 8 Deee 01 Rev. 1.10 9 Deee 01



JMP addr JumpunconditionallyDescription ThecontentsoftheProgramCounterarereplacedwiththespecifiedaddress.Program executionthencontinuesfromthisnewaddress.Asthisrequirestheinsertionofadummy instructionwhilethenewaddressisloaded,itisatwocycleinstruction.Operation ProgramCounter←addrAffectedflag(s) None

MOV A,[m] MoveDataMemorytoACCDescription ThecontentsofthespecifiedDataMemoryarecopiedtotheAccumulator.Operation ACC←[m]Affectedflag(s) None

MOV A,x MoveimmediatedatatoACCDescription TheimmediatedataspecifiedisloadedintotheAccumulator.Operation ACC←xAffectedflag(s) None

MOV [m],A MoveACCtoDataMemoryDescription ThecontentsoftheAccumulatorarecopiedtothespecifiedDataMemory.Operation [m]←ACCAffectedflag(s) None

NOP NooperationDescription Nooperationisperformed.Executioncontinueswiththenextinstruction.Operation NooperationAffectedflag(s) None

OR A,[m] LogicalORDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwise logicalORoperation.TheresultisstoredintheAccumulator.Operation ACC←ACC″OR″[m]Affectedflag(s) Z

OR A,x LogicalORimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″OR″xAffectedflag(s) Z

ORM A,[m] LogicalORACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalOR operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″OR″[m]Affectedflag(s) Z

RET ReturnfromsubroutineDescription TheProgramCounterisrestoredfromthestack.Programexecutioncontinuesattherestored address.Operation ProgramCounter←StackAffectedflag(s) None

Rev. 1.10 50 Deee 01 Rev. 1.10 51 Deee 01



RET A,x ReturnfromsubroutineandloadimmediatedatatoACCDescription TheProgramCounterisrestoredfromthestackandtheAccumulatorloadedwiththespecified immediatedata.Programexecutioncontinuesattherestoredaddress.Operation ProgramCounter←Stack ACC←xAffectedflag(s) None

RETI ReturnfrominterruptDescription TheProgramCounterisrestoredfromthestackandtheinterruptsarere-enabledbysettingthe EMIbit.EMIisthemasterinterruptglobalenablebit.Ifaninterruptwaspendingwhenthe RETIinstructionisexecuted,thependingInterruptroutinewillbeprocessedbeforereturning tothemainprogram.Operation ProgramCounter←Stack EMI←1Affectedflag(s) None

RL [m] RotateDataMemoryleftDescription ThecontentsofthespecifiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0.Operation [m].(i+1)←[m].i;(i=0~6) [m].0←[m].7Affectedflag(s) None

RLA [m] RotateDataMemoryleftwithresultinACCDescription ThecontentsofthespecifiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0. TherotatedresultisstoredintheAccumulatorandthecontentsoftheDataMemoryremain unchanged.Operation ACC.(i+1)←[m].i;(i=0~6) ACC.0←[m].7Affectedflag(s) None

RLC [m] RotateDataMemoryleftthroughCarryDescription ThecontentsofthespecifiedDataMemoryandthecarryflagarerotatedleftby1bit.Bit7 replacestheCarrybitandtheoriginalcarryflagisrotatedintobit0.Operation [m].(i+1)←[m].i;(i=0~6) [m].0←C C←[m].7Affectedflag(s) C

RLCA [m] RotateDataMemoryleftthroughCarrywithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedleftby1bit.Bit7replacesthe Carrybitandtheoriginalcarryflagisrotatedintothebit0.Therotatedresultisstoredinthe AccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC.(i+1)←[m].i;(i=0~6) ACC.0←C C←[m].7Affectedflag(s) C

RR [m] RotateDataMemoryrightDescription ThecontentsofthespecifiedDataMemoryarerotatedrightby1bitwithbit0rotatedintobit7.Operation [m].i←[m].(i+1);(i=0~6) [m].7←[m].0Affectedflag(s) None

Rev. 1.10 50 Deee 01 Rev. 1.10 51 Deee 01



RRA [m] RotateDataMemoryrightwithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedrightby1bitwithbit0 rotatedintobit7.TherotatedresultisstoredintheAccumulatorandthecontentsofthe DataMemoryremainunchanged.Operation ACC.i←[m].(i+1);(i=0~6) ACC.7←[m].0Affectedflag(s) None

RRC [m] RotateDataMemoryrightthroughCarryDescription ThecontentsofthespecifiedDataMemoryandthecarryflagarerotatedrightby1bit.Bit0 replacestheCarrybitandtheoriginalcarryflagisrotatedintobit7.Operation [m].i←[m].(i+1);(i=0~6) [m].7←C C←[m].0Affectedflag(s) C

RRCA [m] RotateDataMemoryrightthroughCarrywithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedrightby1bit.Bit0replaces theCarrybitandtheoriginalcarryflagisrotatedintobit7.Therotatedresultisstoredinthe AccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC.i←[m].(i+1);(i=0~6) ACC.7←C C←[m].0Affectedflag(s) C

SBC A,[m] SubtractDataMemoryfromACCwithCarryDescription ThecontentsofthespecifiedDataMemoryandthecomplementofthecarryflagare subtractedfromtheAccumulator.TheresultisstoredintheAccumulator.Notethatifthe resultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultis positiveorzero,theCflagwillbesetto1.Operation ACC←ACC−[m]−CAffectedflag(s) OV,Z,AC,C

SBCM A,[m] SubtractDataMemoryfromACCwithCarryandresultinDataMemoryDescription ThecontentsofthespecifiedDataMemoryandthecomplementofthecarryflagare subtractedfromtheAccumulator.TheresultisstoredintheDataMemory.Notethatifthe resultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultis positiveorzero,theCflagwillbesetto1.Operation [m]←ACC−[m]−CAffectedflag(s) OV,Z,AC,C

SDZ [m] SkipifdecrementDataMemoryis0Description ThecontentsofthespecifiedDataMemoryarefirstdecrementedby1.Iftheresultis0the followinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhile thenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogram proceedswiththefollowinginstruction.Operation [m]←[m]−1 Skipif[m]=0Affectedflag(s) None

Rev. 1.10 5 Deee 01 Rev. 1.10 5 Deee 01



SDZA [m] SkipifdecrementDataMemoryiszerowithresultinACCDescription ThecontentsofthespecifiedDataMemoryarefirstdecrementedby1.Iftheresultis0,the followinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespecified DataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummy instructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0, theprogramproceedswiththefollowinginstruction.Operation ACC←[m]−1 SkipifACC=0Affectedflag(s) None

SET [m] SetDataMemoryDescription EachbitofthespecifiedDataMemoryissetto1.Operation [m]←FFHAffectedflag(s) None

SET [m].i SetbitofDataMemoryDescription BitiofthespecifiedDataMemoryissetto1.Operation [m].i←1Affectedflag(s) None

SIZ [m] SkipifincrementDataMemoryis0Description ThecontentsofthespecifiedDataMemoryarefirstincrementedby1.Iftheresultis0,the followinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhile thenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogram proceedswiththefollowinginstruction.Operation [m]←[m]+1 Skipif[m]=0Affectedflag(s) None

SIZA [m] SkipifincrementDataMemoryiszerowithresultinACCDescription ThecontentsofthespecifiedDataMemoryarefirstincrementedby1.Iftheresultis0,the followinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespecified DataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummy instructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot 0theprogramproceedswiththefollowinginstruction.Operation ACC←[m]+1 SkipifACC=0Affectedflag(s) None

SNZ [m].i SkipifbitiofDataMemoryisnot0Description IfbitiofthespecifiedDataMemoryisnot0,thefollowinginstructionisskipped.Asthis requirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwo cycleinstruction.Iftheresultis0theprogramproceedswiththefollowinginstruction.Operation Skipif[m].i≠0Affectedflag(s) None

SUB A,[m] SubtractDataMemoryfromACCDescription ThespecifiedDataMemoryissubtractedfromthecontentsoftheAccumulator.Theresultis storedintheAccumulator.Notethatiftheresultofsubtractionisnegative,theCflagwillbe clearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation ACC←ACC−[m]Affectedflag(s) OV,Z,AC,C

Rev. 1.10 5 Deee 01 Rev. 1.10 5 Deee 01



SUBM A,[m] SubtractDataMemoryfromACCwithresultinDataMemoryDescription ThespecifiedDataMemoryissubtractedfromthecontentsoftheAccumulator.Theresultis storedintheDataMemory.Notethatiftheresultofsubtractionisnegative,theCflagwillbe clearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation [m]←ACC−[m]Affectedflag(s) OV,Z,AC,C

SUB A,x SubtractimmediatedatafromACCDescription TheimmediatedataspecifiedbythecodeissubtractedfromthecontentsoftheAccumulator. TheresultisstoredintheAccumulator.Notethatiftheresultofsubtractionisnegative,theC flagwillbeclearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation ACC←ACC−xAffectedflag(s) OV,Z,AC,C

SWAP [m] SwapnibblesofDataMemoryDescription Thelow-orderandhigh-ordernibblesofthespecifiedDataMemoryareinterchanged.Operation [m].3~[m].0↔[m].7~[m].4Affectedflag(s) None

SWAPA [m] SwapnibblesofDataMemorywithresultinACCDescription Thelow-orderandhigh-ordernibblesofthespecifiedDataMemoryareinterchanged.The resultisstoredintheAccumulator.ThecontentsoftheDataMemoryremainunchanged.Operation ACC.3~ACC.0←[m].7~[m].4 ACC.7~ACC.4←[m].3~[m].0Affectedflag(s) None

SZ [m] SkipifDataMemoryis0Description IfthecontentsofthespecifiedDataMemoryis0,thefollowinginstructionisskipped.Asthis requirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwo cycleinstruction.Iftheresultisnot0theprogramproceedswiththefollowinginstruction.Operation Skipif[m]=0Affectedflag(s) None

SZA [m] SkipifDataMemoryis0withdatamovementtoACCDescription ThecontentsofthespecifiedDataMemoryarecopiedtotheAccumulator.Ifthevalueiszero, thefollowinginstructionisskipped.Asthisrequirestheinsertionofadummyinstruction whilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0the programproceedswiththefollowinginstruction.Operation ACC←[m] Skipif[m]=0Affectedflag(s) None

SZ [m].i SkipifbitiofDataMemoryis0Description IfbitiofthespecifiedDataMemoryis0,thefollowinginstructionisskipped.Asthisrequires theinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwocycle instruction.Iftheresultisnot0,theprogramproceedswiththefollowinginstruction.Operation Skipif[m].i=0Affectedflag(s) None

Rev. 1.10 5 Deee 01 Rev. 1.10 55 Deee 01



TABRDC [m] Readtable(currentpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(currentpage)addressedbythetablepointer(TBLP)is movedtothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

TABRDL [m] Readtable(lastpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(lastpage)addressedbythetablepointer(TBLP)ismoved tothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

XOR A,[m] LogicalXORDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalXOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″XOR″[m]Affectedflag(s) Z

XORM A,[m] LogicalXORACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalXOR operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″XOR″[m]Affectedflag(s) Z

XOR A,x LogicalXORimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalXOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″XOR″xAffectedflag(s) Z

Rev. 1.10 5 Deee 01 Rev. 1.10 55 Deee 01



Package Information

Note that thepackage informationprovidedhere is for consultationpurposesonly.As thisinformationmaybeupdatedatregularintervalsusersareremindedtoconsulttheHoltekwebsiteforthelatestversionofthepackageinformation.

Additionalsupplementaryinformationwithregardtopackagingislistedbelow.Clickontherelevantsectiontobetransferredtotherelevantwebsitepage.

• FurtherPackageInformation(includeOutlineDimensions,ProductTapeandReelSpecifications)

• PackingMeterialsInformation

• Cartoninformation

http://www.holtek.com

http://www.holtek.com.tw/english/literature/package.pdf

http://www.holtek.com.tw/english/literature/packing-e.pdf

http://www.holtek.com.tw/english/literature/carton.pdf

Rev. 1.10 56 Deee 01 Rev. 1.10 57 Deee 01



48-pin LQFP (7mm × 7mm) Outline Dimensions

SymbolDimensions in inch

Min. Nom. Max.A — 0.5 BSC —B — 0.76 BSC —C — 0.5 BSC —D — 0.76 BSC —E — 0.00 BSC —F 0.007 0.009 0.011G 0.05 0.055 0.057H — — 0.06 I 0.00 — 0.006 J 0.018 0.0 0.00 K 0.00 — 0.008 α 0° ― 7°

SymbolDimensions in mm

Min. Nom. Max.A — 9.00 BSC —B — 7.00 BSC —C — 9.00 BSC —D — 7.00 BSC —E — 0.50 BSC —F 0.17 0. 0.7G 1.5 1.0 1.5H — — 1.60 I 0.05 — 0.15 J 0.5 0.60 0.75 K 0.09 — 0.0 α 0° ― 7°

Rev. 1.10 56 Deee 01 Rev. 1.10 57 Deee 01



Copyight© 01 y HOLTEK SEMICONDUCTOR INC.The infoation appeaing in this Data Sheet is elieved to e auate at the tie of puliation. Howeve Holtek assues no esponsiility aising fo the use of the specifications described. The applications mentioned herein are used solely fo the pupose of illustation and Holtek akes no waanty o epesentation that suh appliations will e suitale without futhe odifiation no eoends the use of its poduts fo appliation that ay pesent a isk to huan life due to alfuntion o othewise. Holtek's poduts ae not authoized fo use as itial oponents in life suppot devies o systes. Holtek eseves the ight to alte its products without prior notification. For the most up-to-date information, please visit ou we site at http://www.holtek.o.tw.

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R-F Type Low Voltage 8-bit Mask MCU HT47C07L/HT47C08L...R-F Type Low Voltage 8-bit Mask MCU...

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