R Spartan-3 1.2V FPGA Family: Functional Description€¦ · IFF2 Q SR Fixed Delay LVCMOS, LVTTL,...

IOBs

IOB OverviewThe InputOutput Block (IOB) provides a programmablebidirectional interface between an IO pin and the FPGArsquosinternal logic

A simplified diagram of the IOBrsquos internal structure appearsin Figure 1 There are three main signal paths within theIOB the output path input path and 3-state path Eachpath has its own pair of storage elements that can act aseither registers or latches For more information see theStorage Element Functions section The three main signalpaths are as follows

bull The input path carries data from the pad which isbonded to a package pin through an optionalprogrammable delay element directly to the I line Afterthe delay element there are alternate routes through apair of storage elements to the IQ1 and IQ2 lines TheIOB outputs I IQ1 and IQ2 all lead to the FPGArsquosinternal logic The delay element can be set to ensure ahold time of zero

bull The output path starting with the O1 and O2 linescarries data from the FPGArsquos internal logic through amultiplexer and then a three-state driver to the IOBpad In addition to this direct path the multiplexerprovides the option to insert a pair of storage elements

bull The 3-state path determines when the output driver ishigh impedance The T1 and T2 lines carry data from

the FPGArsquos internal logic through a multiplexer to theoutput driver In addition to this direct path themultiplexer provides the option to insert a pair ofstorage elements

bull All signal paths entering the IOB including thoseassociated with the storage elements have an inverteroption Any inverter placed on these paths isautomatically absorbed into the IOB

Storage Element FunctionsThere are three pairs of storage elements in each IOB onepair for each of the three paths It is possible to configureeach of these storage elements as an edge-triggeredD-type flip-flop (FD) or a level-sensitive latch (LD)

The storage-element-pair on either the Output path or theThree-State path can be used together with a special multi-plexer to produce Double-Data-Rate (DDR) transmissionThis is accomplished by taking data synchronized to theclock signalrsquos rising edge and converting them to bits syn-chronized on both the rising and the falling edge The com-bination of two registers and a multiplexer is referred to as aDouble-Data-Rate D-type flip-flop (FDDR)

See Double-Data-Rate Transmission page 3 for moreinformation

The signal paths associated with the storage element aredescribed in Table 1

0

Spartan-3 12V FPGA Family Functional Description

DS099-2 (v12) July 11 2003 0 0 Advance Product Specification

R

Table 1 Storage Element Signal Description

Storage Element Signal Description Function

D Data input Data at this input is stored on the active edge of CK enabled by CE For latch operation when the input is enabled data passes directly to the output Q

Q Data output The data on this output reflects the state of the storage element For operation as a latch in transparent mode Q will mirror the data at D

CK Clock input A signalrsquos active edge on this input with CE asserted loads data into the storage element

CE Clock Enable input When asserted this input enables CK If not connected CE defaults to the asserted state

SR SetReset Forces storage element into the state specified by the SRHIGHSRLOW attributes The SYNCASYNC attribute setting determines if the SR input is synchronized to the clock or not

REV Reverse Used together with SR Forces storage element into the state opposite from what SR does

DS099-2 (v12) July 11 2003 wwwxilinxcom 1Advance Product Specification 1-800-255-7778

copy 2003 Xilinx Inc All rights reserved All Xilinx trademarks registered trademarks patents and disclaimers are as listed at httpwwwxilinxcomlegalhtm All other trademarks and registered trademarks are the property of their respective owners All specifications are subject to change without notice

Spartan-3 12V FPGA Family Functional DescriptionR

Figure 1 Simplified IOB Diagram

D

CE

CK

TFF1

Three-state Path

T

T1

TCE

T2TFF2

Q

SR

DDRMUX

REV

D

CE

CK

Q

SR REV

D

CE

CK

OFF1

Output Path

O1

OCE

O2OFF2

Q

SR

DDRMUX

WeakKeeperLatch

VCCO

VREFPin

IO Pin fromAdjacentIOB

DS099_01_040703

IOPin

Program-mableOutputDriver

DCI

ESDWeakPull-Up

WeakPull-Down

ESD

REV

D

CE

CK

Q

SR REV

OTCLK1

OTCLK2

D

CE

CK

IFF1

Input Path

I

ICE

IFF2

Q

SR

FixedDelay

LVCMOS LVTTL PCI

Single-ended Standardsusing VREF

Differential Standards

REV

D

CE

CK

Q

SR REV

ICLK1

ICLK2

SR

REV

Note All IOB signals communicating with the FPGAs internal logic have the option of inverting polarity

IQ1

IQ2

2 wwwxilinxcom DS099-2 (v12) July 11 20031-800-255-7778 Advance Product Specification

According to Figure 1 the clock line OTCLK1 connects theCK inputs of the upper registers on the output andthree-state paths Similarly OTCLK2 connects the CKinputs for the lower registers on the output and three-statepaths The upper and lower registers on the input path haveindependent clock lines ICLK1 and ICLK2

The enable line OCE connects the CE inputs of the upperand lower registers on the output path Similarly TCE con-nects the CE inputs for the register pair on the three-state

path and ICE does the same for the register pair on theinput path

The SetReset (SR) line entering the IOB is common to allsix registers as is the Reverse (REV) line

Each storage element supports numerous options in addi-tion to the control over signal polarity described in the IOBOverview section These are described in Table 2

Double-Data-Rate TransmissionDouble-Data-Rate (DDR) transmission describes the tech-nique of synchronizing signals to both the rising and fallingedges of the clock signal Spartan-3 devices use regis-ter-pairs in all three IOB paths to perform DDR operations

The pair of storage elements on the IOBrsquos Output path(OFF1 and OFF2) used as registers combine with a spe-cial multiplexer to form a DDR D-type flip-flop (FDDR) Thisprimitive permits DDR transmission where output data bitsare synchronized to both the rising and falling edges of aclock It is possible to access this function by placing eitheran FDDRRSE or an FDDRCPE component or symbol intothe design DDR operation requires two clock signals (50duty cycle) one the inverted form of the other These sig-nals trigger the two registers in alternating fashion asshown in Figure 2 Commonly the Digital Clock Manager(DCM) generates the two clock signals by mirroring anincoming signal then shifting it 180 degrees This approachensures minimal skew between the two signals

The storage-element-pair on the Three-State path (TFF1and TFF2) can also be combined with a local multiplexer toform an FDDR primitive This permits synchronizing the out-put enable to both the rising and falling edges of a clockThis DDR operation is realized in the same way as for theoutput path

The storage-element-pair on the input path (IFF1 and IFF2)allows an IO to receive a DDR signal An incoming DDRclock signal triggers one register and the inverted clock sig-nal triggers the other register In this way the registers taketurns capturing bits of the incoming DDR data signal

Aside from high bandwidth data transfers DDR can also beused to reproduce or ldquomirrorrdquo a clock signal on the outputThis approach is used to transmit clock and data signalstogether A similar approach is used to reproduce a clocksignal at multiple outputs The advantage for bothapproaches is that skew across the outputs will be minimal

Table 2 Storage Element Options

Option Switch Function Specificity

FFLatch Chooses between an edge-sensitive flip-flop or a level-sensitive latch

Independent for each storage element

SYNCASYNC Determines whether SR is synchronous or asynchronous

SRHIGHSRLOW Determines whether SR acts as a Set which forces the storage element to a logic ldquo1 (SRHIGH) or a Reset which forces a logic ldquo0rdquo (SRLOW)

Independent for each storage element except when using FDDR In the latter case the selection for the upper element (OFF1 or TFF2) will apply to both elements

INIT1INIT0 In the event of a Global SetReset after configuration or upon activation of the GTS net this switch decides whether to set or reset a storage element By default choosing SRLOW also selects INIT0 choosing SRHIGH also selects INIT1

Independent for each storage element except when using FDDR In the latter case selecting INIT0 for one element applies to both elements (even though INIT1 is selected for the other)

Pull-Up and Pull-Down ResistorsThe optional pull-up and pull-down resistors are intended toestablish High and Low levels respectively at unused IOsThe weak pull-up resistor optionally connects each IOB padto VCCO A weak pull-down resistor optionally connectseach pad to GND These resistors are placed in a designusing the PULLUP and PULLDOWN symbols in a sche-matic respectively They can also be instantiated as com-ponents set as constraints or passed as attributes in HDLcode These resistors can also be selected for all unusedIO using the Bitstream Generator (BitGen) option Unused-Pin A Low logic level on HSWAP_EN activates the pull-upresistors on all IOs during configuration

Weak-Keeper CircuitEach IO has an optional weak-keeper circuit that retainsthe last logic level on a line after all drivers have been turnedoff This is useful to keep bus lines from floating when allconnected drivers are in a high-impedance state This func-tion is placed in a design using the KEEPER symbolPull-up and pull-down resistors override the weak-keepercircuit

ESD ProtectionClamp diodes protect all device pads against damage fromElectro-Static Discharge (ESD) as well as excessive voltagetransients Each IO has two clamp diodes One diodeextends P-to-N from the pad to VCCO and a second diodeextends N-to-P from the pad to GND During operationthese diodes are normally biased in the off state These

clamp diodes are always connected to the pad regardlessof the signal standard selected The presence of diodes lim-its the ability of Spartan-3 IOs to tolerate high signal volt-ages The VIN absolute maximum rating in Table 1 Module 3specifies the voltage range that IOs can tolerate

Slew Rate Control and Drive StrengthTwo options FAST and SLOW control the output slew rateThe FAST option supports output switching at a high rateThe SLOW option reduces bus transients These options areonly available when using one of the LVCMOS or LVTTLstandards which also provide up to seven different levels ofcurrent drive strength 2 4 6 8 12 16 and 24 mA Choos-ing the appropriate drive strength level is yet another meansto minimize bus transients

Table 3 shows the drive strengths that the LVCMOS andLVTTL standards support The Fast option is indicated byappending an F attribute after the output buffer symbolOBUF or the bidirectional buffer symbol IOBUF The Slowoption appends an S attribute The drive strength in milliam-peres follows the slew rate attribute For exampleOBUF_LVCMOS18_S_6 or IOBUF_LVCMOS25_F_16

Boundary-Scan CapabilityAll Spartan-3 IOBs support boundary-scan testing compat-ible with IEEE 11491 standards See Boundary-Scan(JTAG) Mode page 36 for more information

SelectIO Signal StandardsThe IOBs support 17 different single-ended signal stan-dards as listed in Table 4 Furthermore the majority ofIOBs can be used in specific pairs supporting any of six dif-ferential signal standards as shown in Table 5 The desiredstandard is selected by placing the appropriate IO librarysymbol or component into the FPGA design For examplethe symbol named IOBUF_LVCMOS15_F_8 represents abidirectional IO to which the 15V LVCMOS signal standardhas been assigned The slew rate and current drive are setto Fast and 8 mA respectively

Together with placing the appropriate IO symbol two exter-nally applied voltage levels VCCO and VREF select thedesired signal standard The VCCO lines provide current tothe output driver The voltage on these lines determines the

Figure 2 Clocking the DDR Register

D1

CLK1

DDR MUX

DCM

Q1

FDDR

D2

CLK2

Q2

180˚ 0˚

DS099-2_02_070303

Q

Table 3 Programmable Output Drive Current

Signal Standard

Current Drive (mA)

2 4 6 8 12 16 24

LVCMOS12 - - - -

LVCMOS15 - -

LVCMOS18 -

LVCMOS25

LVCMOS33

LVTTL

output voltage swing for all standards except GTL andGTLP

All single-ended standards except the LVCMOS modesrequire a Reference Voltage (VREF) to bias the input-switch-ing threshold Once a configuration data file is loaded intothe FPGA that calls for the IOs of a given bank to use sucha signal standard a few specifically reserved IO pins on thesame bank automatically convert to VREF inputs Whenusing one of the LVCMOS standards these pins remainIOs because the VCCO voltage biases the input-switchingthreshold so there is no need for VREF Select the VCCO andVREF levels to suit the desired single-ended standardaccording to Table 4

Differential standards employ a pair of signals one theopposite polarity of the other The noise canceling (egCommon-Mode Rejection) properties of these standardspermit exceptionally high data transfer rates This sectionintroduces the differential signaling capabilities of Spartan-3devices

Each device-package combination designates specific IOpairs that are specially optimized to support differentialstandards A unique ldquoL-numberrdquo part of the pin name iden-tifies the line-pairs associated with each bank (see Module4) For each pair the letters ldquoPrdquo and ldquoNrdquo designate the trueand inverted lines respectively For example the pin namesIO_L43P_7 and IO_L43N_7 indicate the true and invertedlines comprising the line pair L43 on Bank 7 The differentialOutput Voltage (VOD) parameter measures the voltage dif-ference the High and Low logic levels that a pair of differen-tial outputs drive The VOD range for each of the differentialstandards is listed in Table 5 The VCCO lines provide cur-rent to the outputs The VREF lines are not used Select theVCCO level to suit the desired differential standard accordingto Table 5

The need to supply VREF and VCCO imposes constraints onwhich standards can be used in the same bank See TheOrganization of IOBs into Banks section for additionalguidelines concerning the use of the VCCO and VREF lines

Digitally Controlled Impedance (DCI)When the round-trip delay of an output signal mdash ie fromoutput to input and back again mdash exceeds rise and falltimes it is common practice to add termination resistors tothe line carrying the signal These resistors effectivelymatch the impedance of a devicersquos IO to the characteristicimpedance of the transmission line thereby preventingreflections that adversely affect signal integrity Howeverwith the high IO counts supported by modern devices add-ing resistors requires significantly more components andboard area Furthermore for some packages mdash eg ballgrid arrays mdash it may not always be possible to place resis-tors close to pins

DCI answers these concerns by providing two kinds ofon-chip terminations Parallel terminations make use of anintegrated resistor network Series terminations result fromcontrolling the impedance of output drivers DCI activelyadjusts both parallel and series terminations to accurately

Table 4 Single-Ended IO Standards (Values in Volts)

Signal Standard

VCCO

VREF for Inputs(1)

Board Termination Voltage (VTT)

For Outputs

For Inputs

GTL Note 2 Note 2 08 12

GTLP Note 2 Note 2 1 15

HSTL_I 15 - 075 075

HSTL_III 15 - 09 15

HSTL_I_18 18 - 09 09

HSTL_II_18 18 - 09 09

HSTL_III_18 18 - 11 18

LVCMOS12 12 12 - -

LVCMOS15 15 15 - -

LVCMOS18 18 18 - -

LVCMOS25 25 25 - -

LVCMOS33 33 33 - -

LVTTL 33 33 - -

PCI33_3 30 30 - -

SSTL18_I 18 - 09 09

SSTL2_I 25 - 125 125

SSTL2_II 25 - 125 125

Notes 1 Banks 4 and 5 of any Spartan-3 device in a VQ100 package

do not support signal standards using VREF2 The VCCO level used for the GTL and GTLP standards must

be no lower than the termination voltage (VTT) nor can it be lower than the voltage at the IO pad

3 See Table 6 for a listing of the single-ended DCI standards

Table 5 Differential IO Standards

Signal Standard

VCCO (Volts) VREF for Inputs (Volts)

VOD(1) (mV)

For Outputs

For Inputs Min Max

LDT_25 25 - - 430 670

LVDS_25 25 - - 250 400

BLVDS_25 25 - - 250 450

LVDSEXT_25 25 - - 330 700

ULVDS_25 25 - - 430 670

RSDS_25 25 - - 100 400

Notes 1 Measured with a termination resistor value (RT) of 100

Ohms2 See Table 6 for a listing of the differential DCI standards

Signal Standard

VCCO

VREF for Inputs(1)

For Outputs

For Inputs

match the characteristic impedance of the transmission lineThis adjustment process compensates for differences in IOimpedance that can result from normal variation in theambient temperature the supply voltage and the manufac-turing process When the output driver turns off the seriestermination by definition approaches a very high imped-ance in contrast parallel termination resistors remain at thetargeted values

DCI is available only for certain IO standards as listed inTable 6 DCI is selected by applying the appropriate IOstandard extensions to symbols or components There arefive basic ways to configure terminations as shown inTable 7 The DCI IO standard determines which of theseterminations is put into effect

Table 6 DCI IO Standards

Category of Signal Standard Signal Standard

VCCO (V)

VREF for Inputs (V)

Termination Type

For Outputs

For Inputs At Output At Input

Single-Ended

Gunning Transceiver Logic

GTL_DCI 12 12 08 Single Single

GTLP_DCI 15 15 10

High-Speed Transceiver Logic

HSTL_I_DCI 15 15 075 None Split

HSTL_III_DCI 15 15 09 None Single

HSTL_I_DCI_18 18 18 09 None Split

HSTL_II_DCI_18 18 18 09 Split

HSTL_III_DCI_18 18 18 11 None Single

Low-Voltage CMOS LVDCI_15 15 15 - Controlled impedance driver

None

LVDCI_18 18 18 -

LVDCI_25 25 25 -

LVDCI_33 33 33 -

LVDCI_DV2_15 15 15 - Controlled driver with half-impedance

LVDCI_DV2_18 18 18 -

LVDCI_DV2_25 25 25 -

LVDCI_DV2_33 33 33 -

Stub Series Terminated Logic

SSTL18_I_DCI 18 18 09 25-Ohm driver Split

SSTL2_I_DCI 25 25 125 25-Ohm driver

SSTL2_II_DCI 25 25 125 Split with 25-Ohm driver

Differential

Low-Voltage Differential Signalling

LVDS_25_DCI 25 25 - None Split on each line

of pairLVDSEXT_25_DCI 25 25 -

Notes 1 Bank 5 of any Spartan-3 device in a VQ100 or TQ144 package does not support DCI signal standards

Table 7 DCI Terminations

Termination Schematic(1) IO Standards

Controlled impedance output driver LVDCI_15LVDCI_18LVDCI_25LVDCI_33

Controlled output driver with half impedance LVDCI_DV2_15LVDCI_DV2_18LVDCI_DV2_25LVDCI_DV2_33

Single resistor GTL_DCIGTLP_DCIHSTL_III_DCI(2)

HSTL_III_DCI_18(2)

Split resistors HSTL_I_DCI(2)

HSTL_I_DCI_18(2)

HSTL_II_DCI_18LVDS_25_DCILVDSEXT_25_DCI

Split resistors with output driver impedance fixed to 25Ω

SSTL18_I_DCI(3)

SSTL2_I_DCI(3)

SSTL2_II_DCI

Notes 1 The value of R is equivalent to the characteristic impedance of the line connected to the IO It is also equal to half the value of RREF

for the DV2 standards and RREF for all other DCI standards2 For DCI using HSTL Classes I and III terminations only go into effect at inputs (not at outputs)3 For DCI using SSTL Class I the split termination only goes into effect at inputs (not at outputs)

Z0

IOB

R

Z0

IOB

R2

R Z0

VCCOIOB

2R

2R Z0

VCCOIOB

25Ω

2R

2R Z0

VCCOIOB

The DCI feature operates independently for each of thedevicersquos eight banks Each bank has an N reference pin(VRN) and a P reference pin (VRP) to calibrate driverand termination resistance Only when using a DCI stan-dard on a given bank do these two pins function as VRNand VRP When not using a DCI standard the two pins func-tion as user IOs As shown in Figure 3 add an external ref-erence resistor to pull the VRN pin up to VCCO and anotherreference resistor to pull the VRP pin down to GND Bothresistors have the same value mdash commonly 50 Ohms mdashwith one-percent tolerance which is either the characteristicimpedance of the line or twice that depending on the DCIstandard in use Standards having a symbol name that con-tains the letters ldquoDV2rdquo use a reference resistor value that istwice the line impedance DCI adjusts the output driverimpedance to match the reference resistorsrsquo value or halfthat according to the standard DCI always adjusts theon-chip termination resistors to directly match the referenceresistorsrsquo value

The rules guiding the use of DCI standards on banks are asfollows

1 No more than one DCI IO standard with a Single Termination is allowed per bank

2 No more than one DCI IO standard with a Split Termination is allowed per bank

3 Single Termination Split Termination Controlled- Impedance Driver and Controlled-Impedance Driver with Half Impedance can co-exist in the same bank

See also The Organization of IOBs into Banks page 8

The Organization of IOBs into BanksIOBs are allocated among eight banks so that each side ofthe device has two banks as shown in Figure 4 For allpackages each bank has independent VREF lines Forexample VREF Bank 3 lines are separate from the VREFlines going to all other banks

For the Very Thin Quad Flat Pack (VQ) Plastic Quad FlatPack (PQ) Fine Pitch Thin Ball Grid Array (FT) and FinePitch Ball Grid Array (FG) packages each bank has dedi-cated VCCO lines For example the VCCO Bank 7 lines areseparate from the VCCO lines going to all other banks Thus

Spartan-3 devices in these packages support eight inde-pendent VCCO supplies

In contrast the 144-pin Thin Quad Flat Pack (TQ144) pack-age ties VCCO together internally for the pair of banks oneach side of the device For example the VCCO Bank 0 andthe VCCO Bank 1 lines are tied together The interconnectedbank-pairs are 01 23 45 and 67 As a result Spartan-3devices in the TQ144 package support four independentVCCO supplies

Spartan-3 CompatibilityWithin the Spartan-3 family all devices are pin-compatibleby package When the need for future logic resources out-grows the capacity of the Spartan-3 device in current use alarger device in the same package can serve as a directreplacement Larger devices may add extra VREF and VCCOlines to support a greater number of IOs In the largerdevice more pins can convert from user IOs to VREF linesAlso additional VCCO lines are bonded out to pins that wereldquonot connectedrdquo in the smaller device Thus it is importantto plan for future upgrades at the time of the boardrsquos initialdesign by laying out connections to the extra pins

The Spartan-3 family is not pin-compatible with any previ-ous Xilinx FPGA family

Rules Concerning BanksWhen assigning IOs to banks it is important to follow thefollowing VCCO rules

1 Leave no VCCO pins unconnected on the FPGA

2 Set all VCCO lines associated with the (interconnected) bank to the same voltage level

3 The VCCO levels used by all standards assigned to the IOs of the (interconnected) bank(s) must agree The Xilinx development software checks for this Tables 4 5 and 6 describe how different standards use the VCCO supply

Figure 3 Connection of Reference Resistors (RREF)

DS099-2_04_091602

VCCO

VRN

VRP

One of eightIO Banks

RREF (1)

Figure 4 Spartan-3 IO Banks (top view)

DS099-2_03_060102

Bank 0 Bank 1

Bank 5 Bank 4

Ban

k 7

Ban

k 6

Ban

k 2

Ban

k 3

4 If none of the standards assigned to the IOs of the (interconnected) bank(s) use VCCO tie all associated VCCO lines to 25V

5 In general apply 25V to VCCO Bank 4 from power-on to the end of configuration Apply the same voltage to VCCO Bank 5 during parallel configuration or a Readback operation For information on how to program the FPGA using 33V signals and power see the 33V-Tolerant Configuration Interface section

If any of the standards assigned to the Inputs of the bankuse VREF then observe the following additional rules

1 Leave no VREF pins unconnected on any bank

2 Set all VREF lines associated with the bank to the same voltage level

3 The VREF levels used by all standards assigned to the Inputs of the bank must agree The Xilinx development software checks for this Tables 4 and 6 describe how different standards use the VREF supply

If none of the standards assigned to the Inputs of a bankuse VREF for biasing input switching thresholds all associ-ated VREF pins function as User IOs

Exceptions to Banks Supporting IO StandardsBank 5 of any Spartan-3 device in a VQ100 or TQ144 pack-age does not support DCI signal standards In this casebank 5 has neither VRN nor VRP pins

Furthermore banks 4 and 5 of any Spartan-3 device in aVQ100 package do not support signal standards usingVREF (see Table 4) In this case the two banks do not haveany VREF pins

Supply Voltages for the IOBsThree different supplies power the IOBs

1 The VCCO supplies one for each of the FPGArsquos IO banks power the output drivers except when using the GTL and GTLP signal standards The voltage on the VCCO pins determines the voltage swing of the output signal

2 VCCINT is the main power supply for the FPGArsquos internal logic

3 The VCCAUX is an auxiliary source of power primarily to optimize the performance of various FPGA functions such as IO switching

The IOs During Power-On Configuration and User ModeWith no power applied to the FPGA all IOs are in ahigh-impedance state The VCCINT (12V) VCCAUX (25V)and VCCO supplies may be applied in any order Beforepower-on can finish VCCINT VCCO Bank 4 and VCCAUXmust have reached their respective minimum recom-mended operating levels (see Table 2 in Module 3) At thistime all IO drivers also will be in a high-impedance stateVCCO Bank 4 VCCINT and VCCAUX serve as inputs to theinternal Power-On Reset circuit (POR)

A Low level applied to HSWAP_EN input enables weakpull-up resistors on User IOs from power-on throughoutconfiguration A High level on HSWAP_EN disables thepull-up resistors allowing the IOs to float As soon aspower is applied the FPGA begins initializing its configura-tion memory At the same time the FPGA internally assertsthe Global Set-Reset (GSR) which asynchronously resetsall IOB storage elements to a Low state

Upon the completion of initialization INIT_B goes Highsampling the M0 M1 and M2 inputs to determine the con-figuration mode At this point the configuration data isloaded into the FPGA The IO drivers remain in ahigh-impedance state (with or without pull-up resistors asdetermined by the HSWAP_EN input) throughout configura-tion

The Global Three State (GTS) net is released duringStart-Up marking the end of configuration and the begin-ning of design operation in the User mode At this pointthose IOs to which signals have been assigned go activewhile all unused IOs remain in a high-impedance state Therelease of the GSR net also part of Start-up leaves the IOBregisters in a Low state by default unless the loaded designreverses the polarity of their respective RS inputs

In User mode all weak internal pull-up resistors on the IOsare disabled and HSWAP_EN becomes a ldquodonrsquot carerdquo inputIf it is desirable to have weak pull-up or pull-down resistorson IOs carrying signals the appropriate symbol mdash egPULLUP PULLDOWN mdash must be placed at the appropriatepads in the design The Bitstream Generator (Bitgen) optionUnusedPin available in the Xilinx development softwaredetermines whether unused IOs collectively have pull-upresistors pull-down resistors or no resistors in User mode

CLB OverviewThe Configurable Logic Blocks (CLBs) constitute the mainlogic resource for implementing synchronous as well ascombinatorial circuits Each CLB comprises four intercon-nected slices as shown in Figure 5 These slices aregrouped in pairs Each pair is organized as a column with anindependent carry chain

The nomenclature that the FPGA Editor mdash part of the Xilinxdevelopment software mdash uses to designate slices is as fol-lows The letter X followed by a number identifies columnsof slices The X number counts up in sequence from theleft side of the die to the right The letter Y followed by anumber identifies the position of each slice in a pair as wellas indicating the CLB row The Y number counts slicesstarting from the bottom of the die according to thesequence 0 1 0 1 (the first CLB row) 2 3 2 3 (the sec-ond CLB row) etc Figure 5 shows the CLB located in thelower left-hand corner of the die Slices X0Y0 and X0Y1make up the column-pair on the left where as slices X1Y0and X1Y1 make up the column-pair on the right For eachCLB the term ldquoleft-handrdquo (or SLICEM) is used to indicatedthe pair of slices labeled with an even X number such asX0 and the term ldquoright-handrdquo (or SLICEL) designates thepair of slices with an odd X number eg X1

Elements Within a SliceAll four slices have the following elements in common twologic function generators two storage elements wide-func-tion multiplexers carry logic and arithmetic gates asshown in Figure 6 Both the left-hand and right-hand slicepairs use these elements to provide logic arithmetic and

ROM functions Besides these the left-hand pair supportstwo additional functions storing data using Distributed RAMand shifting data with 16-bit registers Figure 6 is a diagramof the left-hand slice therefore it represents a superset ofthe elements and connections to be found in all slices SeeFunction Generator page 12 for more information

The RAM-based function generator mdash also known as aLook-Up Table or LUT mdash is the main resource for imple-menting logic functions Furthermore the LUTs in eachleft-hand slice pair can be configured as Distributed RAM ora 16-bit shift register For information on the former seeXAPP464 Using Look-Up Tables as Distributed RAM inSpartan-3 FPGAs for information on the latter refer toXAPP465 Using Look-Up Tables as Shift Registers (SRL16)in Spartan-3 FPGAs The function generators located in theupper and lower portions of the slice are referred to as theG and F respectively

The storage element which is programmable as either aD-type flip-flop or a level-sensitive latch provides a meansfor synchronizing data to a clock signal among other usesThe storage elements in the upper and lower portions of theslice are called FFY and FFX respectively

Wide-function multiplexers effectively combine LUTs inorder to permit more complex logic operations Each slicehas two of these multiplexers with F5MUX in the lower por-tion of the slice and FXMUX in the upper portion Depend-ing on the slice FXMUX takes on the name F6MUXF7MUX or F8MUX For more details on the multiplexerssee XAPP466 Using Dedicated Multiplexers in Spartan-3FPGAs

Figure 5 Arrangement of Slices within the CLB

DS099-2_05_040703

Interconnectto Neighbors

Left-Hand SLICEM(Logic or Distributed RAM

or Shift Register)

Right-Hand SLICEL(Logic Only)

CIN

SLICEX0Y1

SLICEX0Y0

SwitchMatrix

COUT

CLB

COUT

SHIFTOUTSHIFTIN

CIN

SLICEX1Y1

SLICEX1Y0

Figure 6 Simplified Diagram of the Left-Hand SLICEM

Notes 1 Options to invert signal polarity as well as other options that enable lines for various functions are not shown2 The index i can be 6 7 or 8 depending on the slice In this position the upper right-hand slice has an F8MUX

and the upper left-hand slice has an F7MUX The lower right-hand and left-hand slices both have an F6MUX

The carry chain together with various dedicated arithmeticlogic gates support fast and efficient implementations ofmath operations The carry chain enters the slice as CINand exits as COUT Five multiplexers control the chainCYINIT CY0F and CYMUXF in the lower portion as well asCY0G and CYMUXG in the upper portion The dedicatedarithmetic logic includes the exclusive-OR gates XORF andXORG (upper and lower portions of the slice respectively)as well as the AND gates GAND and FAND (upper andlower portions respectively)

Main Logic PathsCentral to the operation of each slice are two nearly identi-cal data paths distinguished using the terms top and bot-tom The description that follows uses names associatedwith the bottom path (The top path names appear in paren-theses) The basic path originates at an interconnect-switchmatrix outside the CLB Four lines F1 through F4 (or G1through G4 on the upper path) enter the slice and connectdirectly to the LUT Once inside the slice the lower 4-bitpath passes through a function generator F (or G) thatperforms logic operations The function generatorrsquos Dataoutput D offers five possible paths

1 Exit the slice via line X (or Y) and return to interconnect

2 Inside the slice X (or Y) serves as an input to the DXMUX (DYMUX) which feeds the data input D of the FFY (FFX) storage element The Q output of the storage element drives the line XQ (or YQ) which exits the slice

3 Control the CYMUXF (or CYMUXG) multiplexer on the carry chain

4 With the carry chain serve as an input to the XORF (or XORG) exclusive-OR gate that performs arithmetic operations producing a result on X (or Y)

5 Drive the multiplexer F5MUX to implement logic functions wider than four bits The D outputs of both the F-LUT and G-LUT serve as data inputs to this multiplexer

In addition to the main logic paths described above thereare two bypass paths that enter the slice as BX and BYOnce inside the FPGA BX in the bottom half of the slice (orBY in the top half) can take any of several possiblebranches

1 Bypass both the LUT and the storage element then exit the slice as BXOUT (or BYOUT) and return to interconnect

2 Bypass the LUT then pass through a storage element via the D input before exiting as XQ (or YQ)

3 Control the wide function multiplexer F5MUX (or F6MUX)

4 Via multiplexers serve as an input to the carry chain

5 Drives the DI input of the LUT See Distributed RAM section

6 BY can control the REV inputs of both the FFY and FFX storage elements See Storage Element Section

7 Finally the DIG_MUX multiplexer can switch BY onto to the DIG line which exits the slice

Other slice signals shown in Figure 6 page 11 are dis-cussed in the sections that follow

Function GeneratorEach of the two LUTs (F and G) in a slice have four logicinputs (A1-A4) and a single output (D) This permits anyfour-variable Boolean logic operation to be programmedinto them Furthermore wide function multiplexers can beused to effectively combine LUTs within the same CLB oracross different CLBs making logic functions with still moreinput variables possible

The LUTs in both the right-hand and left-hand slice-pairsnot only support the logic functions described above butalso can function as ROM that is initialized with data at thetime of configuration

The LUTs in the left-hand slice-pair (even-numbered col-umns such as X0 in Figure 5) of each CLB support twoadditional functions that the right-hand slice-pair (odd-num-bered columns such as X1) do not

First it is possible to program the ldquoleft-hand LUTsrdquo as dis-tributed RAM This type of memory affords moderateamounts of data buffering anywhere along a data path Oneleft-hand LUT stores 16 bits Multiple left-hand LUTs can becombined in various ways to store larger amounts of data Adual port option combines two LUTs so that memory accessis possible from two independent data lines A DistributedROM option permits pre-loading the memory with data dur-ing FPGA configuration For more information see the Dis-tributed RAM section

Second it is possible to program each left-hand LUT as a16-bit shift register Used in this way each LUT can delayserial data anywhere from one to 16 clock cycles The fourleft-hand LUTs of a single CLB can be combined to producedelays up to 64 clock cycles The SHIFTIN and SHIFTOUTlines cascade LUTs to form larger shift registers It is alsopossible to combine shift registers across more than oneCLB The resulting programmable delays can be used tobalance the timing of data pipelines

Block RAM OverviewAll Spartan-3 devices support block RAM which is orga-nized as configurable synchronous 18Kbit blocks BlockRAM stores relatively large amounts of data more efficientlythan the distributed RAM feature described earlier (The lat-ter is better suited for buffering small amounts of data any-where along signal paths) This section describes basicBlock RAM functions For more information see XAPP463Using Block RAM in Spartan-3 FPGAs

The aspect ratio mdash ie width vs depth mdash of each blockRAM is configurable Furthermore multiple blocks can becascaded to create still wider andor deeper memories

A choice among primitives determines whether the blockRAM functions as dual- or single-port memory A name ofthe form RAM16_S[wA]_S[wB] calls out the dual-port primi-tive where the integers wA and wB specify the total datapath width at ports wA and wB respectively Thus aRAM16_S9_S18 is a dual-port RAM with a 9-bit-wide Port Aand an 18-bit-wide Port B A name of the form RAM16_S[w]identifies the single-port primitive where the integer wspecifies the total data path width of the lone port ARAM16_S18 is a single-port RAM with an 18-bit-wide portOther memory functions mdash eg FIFOs data path widthconversion ROM etc mdash are readily available using theCORE Generatortrade system part of the Xilinx developmentsoftware

Arrangement of RAM Blocks on DieThe XC3S50 has one column of block RAM The Spartan-3devices ranging from the XC3S200 to XC3S2000 have twocolumns of block RAM The XC3S4000 and XC3S5000have four columns The position of the columns on the die isshown in Figure 1 in Module 1 For a given device the totalavailable RAM blocks are distributed equally among the col-umns Table 8 shows the number of RAM blocks the datastorage capacity and the number of columns for eachdevice

The Internal Structure of the Block RAM The block RAM has a dual port structure The two identicaldata ports called A and B permit independent access to thecommon RAM block which has a maximum capacity of18432 bits mdash or 16384 bits when no parity lines are usedEach port has its own dedicated set of data control andclock lines for synchronous read and write operationsThere are four basic data paths as shown in Figure 7 (1)write to and read from Port A (2) write to and read from PortB (3) data transfer from Port A to Port B and (4) data trans-fer from Port B to Port A

Block RAM Port Signal DefinitionsRepresentations of the dual-port primitiveRAM16_S[wA]_S[wB] and the single-port primitiveRAM16_S[w] with their associated signals are shown inFigure 8a and Figure 8b respectively These signals aredefined in Table 9

Table 8 Number of RAM Blocks by Device

DeviceTotal Number

of RAM Blocks

Total Addressable

Locations (bits)

Number of

Columns

XC3S50 4 73728 1

XC3S200 12 221184 2

XC3S400 16 294912 2

XC3S1000 24 442368 2

XC3S1500 32 589824 2

XC3S2000 40 737280 2

XC3S4000 96 1769472 4

XC3S5000 104 1916928 4

Figure 7 Block RAM Data Paths

DS099-2_12_030703

Spartan-3Dual Port

Block RAM

Read

Write

Read

Write

Read

Por

t A

Por

t B

21

4

Figure 8 Block RAM Primitives

DS099-2_13_091302

WEAENA

SSRACLKA

ADDRA[rA 10]DIA[wA 10]

DIPA[30]

DOPA[pA 10]

DOA[wA 10]

RAM16_wA_wB

(a) Dual-Port (b) Single-Port

DOPB[pB 10]

DOB[wB 10]

WEBENB

SSRBCLKB

ADDRB[rB 10]DIB[wB 10]

DIPB[30]

WEEN

SSRCLK

ADDR[r 10]DI[w 10]

DIP[p 10]

DOP[p 10]

DO[w 10]

RAM16_Sw

Notes 1 wA and wB are integers representing the total data path width (ie data bits plus parity bits) at ports A and B respectively2 pA and pB are integers that indicate the number of data path lines serving as parity bits3 rA and rB are integers representing the address bus width at ports A and B respectively4 The control signals CLK WE EN and SSR on both ports have the option of inverted polarity

Table 9 Block RAM Port Signals

Signal Description

Port A Signal Name

Port B Signal Name Direction Function

Address Bus ADDRA ADDRB Input The Address Bus selects a memory location for read or write operations The width (w) of the portrsquos associated data path determines the number of available address lines (r)

Data Input Bus DIA DIB Input Data at the DI input bus is written to the addressed memory location addressed on an enabled active CLK edge

It is possible to configure a portrsquos total data path width (w) to be 1 2 4 9 18 or 36 bits This selection applies to both the DI and DO paths of a given port Each port is independent For a port assigned a width (w) the number of addressable locations will be 16384(w-p) where p is the number of parity bits Each memory location will have a width of w (including parity bits) See the DIP signal description for more information of parity

Parity Data Input(s)

DIPA DIPB Input Parity inputs represent additional bits included in the data input path to support error detection The number of parity bits p included in the DI (same as for the DO bus) depends on a portrsquos total data path width (w) See Table 10

Port Aspect RatiosOn a given port it is possible to select a number of differentpossible widths (w ndash p) for the DIDO buses as shown inTable 10 These two buses always have the same widthThis data bus width selection is independent for each port Ifthe data bus width of Port A differs from that of Port B the

Block RAM automatically performs a bus-matching functionWhen data are written to a port with a narrow bus then readfrom a port with a wide bus the latter port will effectivelycombine ldquonarrowrdquo words to form ldquowiderdquo words Similarlywhen data are written into a port with a wide bus then readfrom a port with a narrow bus the latter port will divide

Data Output Bus

DOA DOB Output Basic data access occurs whenever WE is inactive The DO outputs mirror the data stored in the addressed memory location

Data access with WE asserted is also possible if one of the following two attributes is chosen WRITE_FIRST accesses data before the write takes place READ_FIRST accesses data after the write occurs

A third attribute NO_CHANGE latches the DO outputs upon the assertion of WE

It is possible to configure a portrsquos total data path width (w) to be 1 2 4 9 18 or 36 bits This selection applies to both the DI and DO paths See the DI signal description

Parity Data Output(s)

DOPA DOPB Output Parity inputs represent additional bits included in the data input path to support error detection The number of parity bits p included in the DI (same as for the DO bus) depends on a portrsquos total data path width (w) See Table 10

Write Enable WEA WEB Input When asserted together with EN this input enables the writing of data to the RAM In this case the data access attributes WRITE_FIRST READ_FIRST or NO_CHANGE determines if and how data is updated on the DO outputs See the DO signal description

When WE is inactive with EN asserted read operations are still possible In this case a transparent latch passes data from the addressed memory location to the DO outputs

Clock Enable ENA ENB Input When asserted this input enables the CLK signal to synchronize Block RAM functions as follows the writing of data to the DI inputs (when WE is also asserted) the updating of data at the DO outputs as well as the settingresetting of the DO output latches

When de-asserted the above functions are disabled

SetReset SSRA SSRB Input When asserted this pin forces the DO output latch to the value that the SRVAL attribute is set to A SetReset operation on one port has no effect on the other ports functioning nor does it disturb the memoryrsquos data contents It is synchronized to the CLK signal

Clock CLKA CLKB Input This input accepts the clock signal to which read and write operations are synchronized All associated port inputs are required to meet setup times with respect to the clock signalrsquos active edge The data output bus responds after a clock-to-out delay referenced to the clock signalrsquos active edge

Table 9 Block RAM Port Signals (Continued)

Signal Description

Port A Signal Name

ldquowiderdquo words to form ldquonarrowrdquo words When the data buswidth is eight bits or greater extra parity bits become avail-able The width of the total data path (w) is the sum of theDIDO bus width and any parity bits (p)

The width selection made for the DIDO bus determines thenumber of address lines according to the relationshipexpressed below

r = 14 ndash [log(wndashp)log(2)] (1)

In turn the number of address lines delimits the total num-ber (n) of addressable locations or depth according to thefollowing equation

n = 2r (2)

The product of w and n yields the total block RAM capacityEquations (1) and (2) show that as the data bus widthincreases the number of address lines along with the num-ber of addressable memory locations decreases Using thepermissible DIDO bus widths as inputs to these equationsprovides the bus width and memory capacity measuresshown in Table 10

Block RAM Data OperationsWriting data to and accessing data from the block RAM aresynchronous operations that take place independently oneach of the two ports

The waveforms for the write operation are shown in the tophalf of the Figure 9 Figure 10 and Figure 11 When the WEand EN signals enable the active edge of CLK data at theDI input bus is written to the block RAM location addressedby the ADDR lines

There are a number of different conditions under which datacan be accessed at the DO outputs Basic data accessalways occurs when the WE input is inactive Under this

condition data stored in the memory location addressed bythe ADDR lines passes through a transparent output latchto the DO outputs The timing for basic data access isshown in the portions of Figure 9 Figure 10 and Figure 11during which WE is Low

Data can also be accessed on the DO outputs when assert-ing the WE input This is accomplished using two differentattributes

Choosing the WRITE_FIRST attribute data is written to theaddressed memory location on an enabled active CLK edgeand is also passed to the DO outputs WRITE_FIRST timingis shown in the portion of Figure 9 during which WE is High

Table 10 Port Aspect Ratios for Port A or B

DIDO Bus Width(w ndash p bits)

DIPDOP Bus Width (p bits)

Total Data Path Width (w bits)

ADDR Bus Width (r bits)

No of Addressable Locations (n)

Block RAM Capacity

(bits)

1 0 1 14 16384 16384

2 0 2 13 8192 16384

4 0 4 12 4096 16384

8 1 9 11 2048 18432

16 2 18 10 1024 18432

32 4 36 9 512 18432

Choosing the READ_FIRST attribute data already stored inthe addressed location pass to the DO outputs before thatlocation is over-written with new data from the DI inputs on

an enabled active CLK edge READ_FIRST timing is shownin the portion of Figure 10 during which WE is High

Choosing a third attribute called NO_CHANGE puts the DOoutputs in a latched state when asserting WE Under thiscondition the DO outputs will retain the data driven just

before WE was asserted NO_CHANGE timing is shown inthe portion of Figure 11 during which WE is High

Figure 9 Waveforms of Block RAM Data Operations with WRITE_FIRST Selected

CLK

WE

DI

ADDR

DO

EN

DISABLED READ

XXXX 1111 2222 XXXX

aa bb cc dd

0000 MEM(aa) 1111 2222 MEM(dd)

READWRITEMEM(bb)=1111

WRITEMEM(cc)=2222

DS099-2_14_030403

Figure 10 Waveforms of Block RAM Data Operations with READ_FIRST Selected

CLK

WE

DI

ADDR

DO

EN

DISABLED READ

XXXX 1111 2222 XXXX

aa bb cc dd

0000 MEM(aa) old MEM(bb) old MEM(cc) MEM(dd)

WRITEMEM(cc)=2222

DS099-2_15_030403

Dedicated MultipliersAll Spartan-3 devices provide embedded multipliers thataccept two 18-bit words as inputs to produce a 36-bit prod-uct This section provides an introduction to multipliers Forfurther details see XAPP467 Using Embedded Multipliersin Spartan-3 FPGAs

The input buses to the multiplier accept data in tworsquos-com-plement form (either 18-bit signed or 17-bit unsigned) Onesuch multiplier is matched to each block RAM on the dieThe close physical proximity of the two ensures efficient

data handling Cascading multipliers permits multiplicandsmore than three in number as well as wider than 18-bitsThe multiplier is placed in a design using one of two primi-tives an asynchronous version called MULT18X18 and aversion with a register at the outputs called MULT18X18Sas shown in Figure 12a and Figure 12b respectively Thesignals for these primitives are defined in Table 11

The CORE Generator system produces multipliers basedon these primitives that can be configured to suit a widerange of requirements

Figure 11 Waveforms of Block RAM Data Operations with NO_CHANGE Selected

CLK

WE

DI

ADDR

DO

EN

DISABLED READ

XXXX 1111 2222 XXXX

aa bb cc dd

0000 MEM(aa) MEM(dd)

WRITEMEM(cc)=2222

DS099-2_16_030403

Figure 12 Embedded Multiplier Primitives

DS099-2_17_091302

(a) Asynchronous 18-bit Multiplier (b) 18-bit Multiplier with Register at Outputs

A[170]

B[170]

P[350]MULT18X18

A[170]

B[170]

CLK

CE

RST

P[350]MULT18X18S

Digital Clock Manager (DCM)Spartan-3 devices provide flexible complete control overclock frequency phase shift and skew through the use ofthe DCM feature To accomplish this the DCM employs aDelay-Locked Loop (DLL) a fully digital control system thatuses feedback to maintain clock signal characteristics with ahigh degree of precision despite normal variations in oper-ating temperature and voltage This section provides a fun-damental description of the DCM For further informationsee XAPP462 Using Digital Clock Managers (DCMs) inSpartan-3 FPGAs

Each member of the Spartan-3 family has four DCMsexcept the smallest the XC3S50 which has two DCMsThe DCMs are located at the ends of the outermost BlockRAM column(s) See Figure 1 in Module 1 The Digital ClockManager is placed in a design as the ldquoDCMrdquo primitive

The DCM supports three major functions

bull Clock-skew Elimination Clock skew describes the extent to which clock signals may under normal circumstances deviate from zero-phase alignment It occurs when slight differences in path delays cause the

clock signal to arrive at different points on the die at different times This clock skew can increase set-up and hold time requirements as well as clock-to-out time which may be undesirable in applications operating at a high frequency when timing is critical The DCM eliminates clock skew by aligning the output clock signal it generates with another version of the clock signal that is fed back As a result the two clock signals establish a zero-phase relationship This effectively cancels out clock distribution delays that may lie in the signal path leading from the clock output of the DCM to its feedback input

bull Frequency Synthesis Provided with an input clock signal the DCM can generate a wide range of different output clock frequencies This is accomplished by either multiplying andor dividing the frequency of the input clock signal by any of several different factors

bull Phase Shifting The DCM provides the ability to shift the phase of all its output clock signals with respect to its input clock signal

Table 11 Embedded Multiplier Primitives Descriptions

Signal Name Direction Function

A[170] Input Apply one 18-bit multiplicand to these inputs The MULT18X18S primitive requires a setup time before the enabled rising edge of CLK

B[170] Input Apply the other 18-bit multiplicand to these inputs The MULT18X18S primitive requires a setup time before the enabled rising edge of CLK

P[350] Output The output on the P bus is a 36-bit product of the multiplicands A and B In the case of the MULT18X18S primitive an enabled rising CLK edge updates the P bus

CLK Input CLK is only an input to the MULT18X18S primitive The clock signal applied to this input when enabled by CE updates the output register that drives the P bus

CE Input CE is only an input to the MULT18X18S primitive Enable for the CLK signal Asserting this input enables the CLK signal to update the P bus

RST Input RST is only an input to the MULT18X18S primitive Asserting this input resets the output register on an enabled rising CLK edge forcing the P bus to all zeroes

Notes 1 The control signals CLK CE and RST have the option of inverted polarity

The DCM has four functional components theDelay-Locked Loop (DLL) the Digital Frequency Synthe-sizer (DFS) the Phase Shifter (PS) and the Status Logic

Each component has its associated signals as shown inFigure 13

Delay-Locked Loop (DLL)The most basic function of the DLL component is to elimi-nate clock skew The main signal path of the DLL consists ofan input stage followed by a series of discrete delay ele-ments or taps which in turn leads to an output stage This

path together with logic for phase detection and controlforms a system complete with feedback as shown inFigure 14

Figure 13 DCM Functional Blocks and Associated Signals

DS099-2_07_040103

PSINCDECPSEN

PSCLK

CLKIN

CLKFB

RSTSTATUS [70]

LOCKED8

CLKFX180

CLKFX

CLK0

PSDONE

ClockDistribution

DelayCLK90CLK180CLK270CLK2XCLK2X180CLKDV

StatusLogic

DFSDLL

PhaseShifter

Del

ay T

aps

Out

put S

tage

Inpu

t Sta

ge

DCM

Figure 14 Simplified Functional Diagram of DLL

DS099-2_08_041103

CLKINDelay

n

CLKFB

RST

CLK0

CLK90

CLK180

CLK270

CLK2X

CLK2X180

CLKDV

Out

put S

ectio

n

Control

Delayn-1

PhaseDetection

LOCKED

Delay2

Delay1

The DLL component has two clock inputs CLKIN andCLKFB as well as seven clock outputs CLK0 CLK90CLK180 CLK270 CLK2X CLK2X180 and CLKDV asdescribed in Table 12 The clock outputs drive simulta-neously however the High Frequency mode only supports

a subset of the outputs available in the Low Frequencymode See DLL Frequency Modes page 23 Signals thatinitialize and report the state of the DLL are discussed inThe Status Logic Component page 28

The clock signal supplied to the CLKIN input serves as areference waveform with which the DLL seeks to align thefeedback signal at the CLKFB input When eliminating clockskew the common approach to using the DLL is as followsThe CLK0 signal is passed through the clock distributionnetwork to all the registers it synchronizes These registersare either internal or external to the FPGA After passingthrough the clock distribution network the clock signalreturns to the DLL via a feedback line called CLKFB Thecontrol block inside the DLL measures the phase errorbetween CLKFB and CLKIN This phase error is a measureof the clock skew that the clock distribution network intro-

duces The control block activates the appropriate numberof delay elements to cancel out the clock skew Once theDLL has brought the CLK0 signal in phase with the CLKINsignal it asserts the LOCKED output indicating a ldquolockrdquo onto the CLKIN signal

DLL Attributes and Related FunctionsA number of different functional options can be set for theDLL component through the use of the attributes describedin Table 13 Each attribute is described in detail in the sec-tions that follow

Table 12 DLL Signals

Signal Direction Description

Mode Support

Low Frequency

High Frequency

CLKIN Input Accepts original clock signal Yes Yes

CLKFB Input Accepts either CLK0 or CLK2X as feed back signal (Set CLK_FEEDBACK attribute accordingly)

Yes Yes

CLK0 Output Generates clock signal with same frequency and phase as CLKIN Yes Yes

CLK90 Output Generates clock signal with same frequency as CLKIN only phase-shifted 90deg

Yes No

Yes Yes

Yes No

CLK2X Output Generates clock signal with same phase as CLKIN only twice the frequency

Yes No

CLK2X180 Output Generates clock signal with twice the frequency of CLKIN phase-shifted 180deg with respect to CLKIN

Yes No

CLKDV Output Divides the CLKIN frequency by CLKDV_DIVIDE value to generate lower frequency clock signal that is phase-aligned to CLKIN

Yes Yes

DLL Clock Input Connections

An external clock source enters the FPGA using a GlobalClock Input Buffer (IBUFG) which directly accesses the glo-bal clock network or an Input Buffer (IBUF) Clock signalswithin the FPGA drive a global clock net using a GlobalClock Multiplexer Buffer (BUFGMUX) The global clock netconnects directly to the CLKIN input The internal and exter-nal connections are shown in Figure 15a and Figure 15crespectively A differential clock (eg LVDS) can serve asan input to CLKIN

DLL Clock Output and Feedback ConnectionsAs many as four of the nine DCM clock outputs can simulta-neously drive the four BUFGMUX buffers on the same dieedge (top or bottom) All DCM clock outputs can simulta-neously drive general routing resources including intercon-nect leading to OBUF buffers

The feedback loop is essential for DLL operation and isestablished by driving the CLKFB input with either the CLK0or the CLK2X signal so that any undesirable clock distribu-tion delay is included in the loop It is possible to use eitherof these two signals for synchronizing any of the seven DLLoutputs CLK0 CLK90 CLK180 CLK270 CLKDV CLK2Xor CLK2X180 The value assigned to the CLK_FEEDBACKattribute must agree with the physical feedback connectiona value of 1X for the CLK0 case 2X for the CLK2X case Ifthe DCM is used in an application that does not require theDLL mdash ie only the DFS is used mdash then there is no feed-back loop so CLK_FEEDBACK is set to NONE

There are two basic cases that determine how to connectthe DLL clock outputs and feedback connections on-chipsynchronization and off-chip synchronization which areillustrated in Figure 15a through Figure 15d

Table 13 DLL Attributes

Attribute Description Values

CLK_FEEDBACK Chooses either the CLK0 or CLK2X output to drive the CLKFB input

NONE 1X 2X

DLL_FREQUENCY_MODE Chooses between High Frequency and Low Frequency modes

LOW HIGH

CLKIN_DIVIDE_BY_2 Halves the frequency of the CLKIN signal just as it enters the DCM

TRUE FALSE

CLKDV_DIVIDE Selects constant used to divide the CLKIN input frequency to generate the CLKDV output frequency

15 2 25 3 35 4 45 5 55 60 65 70 75 8 9 10 11 12 13 14 15 and 16

DUTY_CYCLE_CORRECTION Enables 50 duty cycle correction for the CLK0 CLK90 CLK180 and CLK270 outputs

TRUE FALSE

In the on-chip synchronization case (Figure 15a andFigure 15b) it is possible to connect any of the DLLrsquos sevenoutput clock signals through general routing resources tothe FPGArsquos internal registers Either a Global Clock Buffer(BUFG) or a BUFGMUX affords access to the global clocknetwork As shown in Figure 15a the feedback loop is cre-ated by routing CLK0 (or CLK2X in Figure 15b) to a globalclock net which in turn drives the CLKFB input

In the off-chip synchronization case (Figure 15c andFigure 15d) CLK0 (or CLK2X) plus any of the DLLrsquos otheroutput clock signals exit the FPGA using output buffers(OBUF) to drive an external clock network plus registers onthe board As shown in Figure 15c the feedback loop isformed by feeding CLK0 (or CLK2X in Figure 15d) backinto the FPGA using an IBUFG which directly accesses theglobal clock network or an IBUF Then the global clock netis connected directly to the CLKFB input

DLL Frequency ModesThe DLL supports two distinct operating modes High Fre-quency and Low Frequency with each specified over a differ-ent clock frequency range The DLL_FREQUENCY_MODE

attribute chooses between the two modes When theattribute is set to LOW the Low Frequency mode permits allseven DLL clock outputs to operate over a low-to-moderatefrequency range When the attribute is set to HIGH the HighFrequency mode allows the CLK0 CLK180 and CLKDV out-puts to operate at the highest possible frequencies Theremaining DLL clock outputs are not available for use in HighFrequency mode

Accommodating High Input FrequenciesIf the frequency of the CLKIN signal is high such that itexceeds the maximum permitted divide it down to anacceptable value using the CLKIN_DIVIDE_BY_2 attributeWhen this attribute is set to TRUE the CLKIN frequency isdivided by a factor of two just as it enters the DCM

Coarse Phase Shift Outputs of the DLL Compo-nentIn addition to CLK0 for zero-phase alignment to the CLKINsignal the DLL also provides the CLK90 CLK180 andCLK270 outputs for 90deg 180deg and 270deg phase-shifted sig-nals respectively These signals are described in Table 12

Figure 15 Input Clock Output Clock and Feedback Connections for the DLL

DS099-2_09_071003

CLK90CLK180CLK270CLKDVCLK2X

CLK2X180

CLK0

ClockNet Delay

BUFGMUX

BUFG

FPGA

(a) On-Chip with CLK0 Feedback

CLKIN

DCM

CLKFB

CLK2X180

CLK0

ClockNet Delay

IBUFG

FPGA

(c) Off-Chip with CLK0 Feedback

CLKIN

DCM

CLKFB

OBUFG

CLK2X

IBUFG

FPGA

(d) Off-Chip with CLK2X Feedback

CLKIN

DCM

CLKFB

OBUFG

CLK0CLK90

CLK180CLK270CLKDV

CLK2X180

CLK2X

ClockNet Delay

BUFGMUX

BUFG

FPGA

(b) On-Chip with CLK2X Feedback

CLKIN

DCM

CLKFB

CLK0CLK90

CLK180CLK270CLKDV

CLK2X180

Notes 1 In the Low Frequency mode all seven DLL outputs are available In the High Frequency mode only the CLK0 CLK180

and CLKDV outputs are available

Their relative timing in the Low Frequency Mode is shown inFigure 16 The CLK90 CLK180 and CLK270 outputs arenot available when operating in the High Frequency mode(See the description of the DLL_FREQUENCY_MODEattribute in Table 13) For control in finer increments than90deg see the Phase Shifter (PS) page 26 section

Basic Frequency Synthesis Outputs of the DLL ComponentThe DLL component provides basic options for frequencymultiplication and division in addition to the more flexiblesynthesis capability of the DFS component described in alater section These operations result in output clock signalswith frequencies that are either a fraction (for division) or amultiple (for multiplication) of the incoming clock frequencyThe CLK2X output produces an in-phase signal that is twicethe frequency of CLKIN The CLK2X180 output also dou-bles the frequency but is 180deg out-of-phase with respect toCLKIN The CLKDIV output generates a clock frequencythat is a predetermined fraction of the CLKIN frequencyThe CLKDV_DIVIDE attribute determines the factor used todivide the CLKIN frequency The attribute can be set to var-ious values as described in Table 13 The basic frequencysynthesis outputs are described in Table 12 Their relativetiming in the Low Frequency Mode is shown in Figure 16

The CLK2X and CLK2X180 outputs are not available whenoperating in the High Frequency mode (See the descriptionof the DLL_FREQUENCY_MODE attribute in Table 14)

Duty Cycle Correction of DLL Clock OutputsThe CLK2X(1) CLK2X180 and CLKDV(2) output signalsordinarily exhibit a 50 duty cycle ndash even if the incomingCLKIN signal has a different duty cycle Fifty-percent dutycycle means that the High and Low times of each clockcycle are equal The DUTY_CYCLE_CORRECTIONattribute determines whether or not duty cycle correction isapplied to the CLK0 CLK90 CLK180 and CLK270 outputsIf DUTY_CYCLE_CORRECTION is set to TRUE then theduty cycle of these four outputs is corrected to 50 IfDUTY_CYCLE_CORRECTION is set to FALSE then theseoutputs exhibit the same duty cycle as the CLKIN signalFigure 16 compares the characteristics of the DLLrsquos outputsignals to those of the CLKIN signal

1 The CLK2X output generates a 25 duty cycle clock at the same frequency as the CLKIN signal until the DLL has achieved lock2 The duty cycle of the CLKDV outputs may differ somewhat from 50 (ie the signal will be High for less than 50 of the period) when

the CLKDV_DIVIDE attribute is set to a non-integer value and the DLL is operating in the High Frequency mode

Figure 16 Characteristics of the DLL Clock Outputs

Output Signal - Duty Cycle is Always Corrected

Output Signal - Attribute Corrects Duty Cycle

Phase

Input Signal (30 Duty Cycle)

0o 90o 180o 270o 0o 90o 180o 270o 0o

DUTY_CYCLE_CORRECTION = FALSE

DUTY_CYCLE_CORRECTION = TRUE

DS099-2_10_031303

CLK2X

CLK2X180

CLKIN

CLKDV(1)

CLK0

CLK90

CLK180

CLK270

CLK0

CLK90

CLK180

CLK270

t

Notes 1 The DLL attribute CLKDV_DIVIDE is set to 2

Digital Frequency Synthesizer (DFS)The DFS component generates clock signals the frequencyof which is a product of the clock frequency at the CLKINinput and a ratio of two user-determined integers Becauseof the wide range of possible output frequencies such a ratiopermits the DFS feature provides still further flexibility thanthe DLLrsquos basic synthesis options as described in the pre-ceding section The DFS componentrsquos two dedicated out-puts CLKFX and CLKFX180 are defined in Table 15

The signal at the CLKFX180 output is essentially an inver-sion of the CLKFX signal These two outputs always exhibita 50 duty cycle This is true even when the CLKIN signaldoes not These DFS clock outputs are driven at the sametime as the DLLrsquos seven clock outputs

The numerator of the ratio is the integer value assigned tothe attribute CLKFX_MULTIPLY and the denominator is theinteger value assigned to the attribute CLKFX_DIVIDEThese attributes are described in Table 14

The output frequency (fCLKFX) can be expressed as a func-tion of the incoming clock frequency (fCLKIN) as follows

fCLKFX = fCLKIN(CLKFX_MULTIPLYCLKFX_DIVIDE) (3)

Regarding the two attributes it is possible to assign anycombination of integer values provided that two conditionsare met

1 The two values fall within their corresponding ranges as specified in Table 14

2 The fCLKFX frequency calculated from the above expression accords with the DCMrsquos operating frequency specifications

For example if CLKFX_MULTIPLY = 5 and CLKFX_DIVIDE= 3 then the frequency of the output clock signal would be53 that of the input clock signal

DFS Frequency ModesThe DFS supports two operating modes High Frequencyand Low Frequency with each specified over a differentclock frequency range The DFS_FREQUENCY_MODEattribute chooses between the two modes When theattribute is set to LOW the Low Frequency mode permits

the two DFS outputs to operate over a low-to-moderate fre-quency range When the attribute is set to HIGH the HighFrequency mode allows both these outputs to operate at thehighest possible frequencies

DFS With or Without the DLLThe DFS component can be used with or without the DLLcomponent

Without the DLL the DFS component multiplies or dividesthe CLKIN signal frequency according to the respectiveCLKFX_MULTIPLY and CLKFX_DIVIDE values generatinga clock with the new target frequency on the CLKFX andCLKFX180 outputs Though classified as belonging to theDLL component the CLKIN input is shared with the DFScomponent This case does not employ feedback looptherefore it cannot correct for clock distribution delay

With the DLL the DFS operates as described in the preced-ing case only with the additional benefit of eliminating theclock distribution delay In this case a feedback loop fromthe CLK0 output to the CLKFB input must be present

The DLL and DFS components work together to achievethis phase correction as follows Given values for theCLKFX_MULTIPLY and CLKFX_DIVIDE attributes the DLLselects the delay element for which the output clock edgecoincides with the input clock edge whenever mathemati-cally possible For example when CLKFX_MULTIPLY = 5and CLKFX_DIVIDE = 3 the input and output clock edgeswill coincide every three input periods which is equivalent intime to five output periods

Smaller CLKFX_MULTIPLY and CLKFX_DIVIDE valuesachieve faster lock times With no factors common to thetwo attributes alignment will occur once with every numberof cycles equal to the CLKFX_DIVIDE value Therefore it isrecommended that the user reduce these values by factor-ing wherever possible For example givenCLKFX_MULTIPLY = 9 and CLKFX_DIVIDE = 6 removinga factor of three yields CLKFX_MULTIPLY = 3 andCLKFX_DIVIDE = 2 While both value-pairs will result in themultiplication of clock frequency by 32 the latter value-pairwill enable the DLL to lock more quickly

Table 14 DFS Attributes

DFS_FREQUENCY_MODE Chooses between High Frequency and Low Frequency modes Low High

CLKFX_MULTIPLY Frequency multiplier constant Integer from 2 to 32

CLKFX_DIVIDE Frequency divisor constant Integer from 1 to 32

Table 15 DFS Signals

CLKFX Output Multiplies the CLKIN frequency by the attribute-value ratio (CLKFX_MULTIPLYCLKFX_DIVIDE) to generate a clock signal with a new target frequency

CLKFX180 Output Generates a clock signal with same frequency as CLKFX only shifted 180deg out-of-phase

DFS Clock Output ConnectionsThere are two basic cases that determine how to connectthe DFS clock outputs on-chip and off-chip which are illus-trated in Figure 15a and Figure 15c respectively This issimilar to what has already been described for the DLL com-ponent See the DLL Clock Output and Feedback Con-nections page 22 section

In the on-chip case it is possible to connect either of theDFSrsquos two output clock signals through general routingresources to the FPGArsquos internal registers Either a GlobalClock Buffer (BUFG) or a BUFGMUX affords access to theglobal clock network The optional feedback loop is formedin this way routing CLK0 to a global clock net which in turndrives the CLKFB input

In the off-chip case the DFSrsquos two output clock signals plusCLK0 for an optional feedback loop can exit the FPGAusing output buffers (OBUF) to drive a clock network plusregisters on the board The feedback loop is formed byfeeding the CLK0 signal back into the FPGA using anIBUFG which directly accesses the global clock network oran IBUF Then the global clock net is connected directly tothe CLKFB input

Phase Shifter (PS)The DCM provides two approaches to controlling the phaseof a DCM clock output signal relative to the CLKIN signalFirst there are nine clock outputs that employ the DLL toachieve a desired phase relationship CLK0 CLK90CLK180 CLK270 CLK2X CLK2X180 CLKDV CLKFX andCLKFX180 These outputs afford ldquocoarserdquo phase control

The second approach uses the PS component described inthis section to provide a still finer degree of control The PScomponent accomplishes this by introducing a fine phaseshift (TPS) between the CLKFB and CLKIN signals insidethe DLL component The user can control this fine phaseshift down to a resolution of 1256 of a CLKIN cycle or onetap delay (DCM_TAP) whichever is greater When in usethe PS component shifts the phase of all nine DCM clockoutput signals together If the PS component is usedtogether with a DCM clock output such as the CLK90CLK180 CLK270 CLK2X180 and CLKFX180 then the finephase shift of the former gets added to the coarse phaseshift of the latter

PS Component Enabling and Mode SelectionThe CLKOUT_PHASE_SHIFT attribute enables the PScomponent for use in addition to selecting between twooperating modes As described in Table 16 this attributehas three possible values NONE FIXED and VARIABLEWhen CLKOUT_PHASE_SHIFT is set to NONE the PScomponent is disabled and its inputs PSEN PSCLK andPSINCDEC must be tied to GND The set of waveforms inFigure 17a shows the disabled case where the DLL main-tains a zero-phase alignment of signals CLKFB and CLKINupon which the PS component has no effect The PS com-ponent is enabled by setting the attribute to either theFIXED or VARIABLE values which select the Fixed Phasemode and the Variable Phase mode respectively Thesetwo modes are described in the sections that follow

Determining the Fine Phase ShiftThe user controls the phase shift of CLKFB relative toCLKIN by setting andor adjusting the value of thePHASE_SHIFT attribute This value must be an integerranging from ndash255 to +255 The PS component uses thisvalue to calculate the desired fine phase shift (TPS) as afraction of the CLKIN period (TCLKIN) Given values forPHASE-SHIFT and TCLKIN it is possible to calculate TPS asfollows

TPS = (PHASE_SHIFT256)TCLKIN (4)

Both the Fixed Phase and Variable Phase operating modesemploy this calculation If the PHASE_SHIFT value is zerothen CLKFB and CLKIN will be in phase the same as whenthe PS component is disabled When the PHASE_SHIFTvalue is positive the CLKFB signal will be shifted later intime with respect to CLKIN If the attribute value is negativethe CLKFB signal will be shifted earlier in time with respectto CLKIN

The Fixed Phase ModeThis mode fixes the desired fine phase shift to a fraction ofthe TCLKIN as determined by Equation (4) and itsuser-selected PHASE_SHIFT value P The set of wave-forms in Figure 17b illustrates the relationship betweenCLKFB and CLKIN in the Fixed Phase mode In the FixedPhase mode the PSEN PSCLK and PSINCDEC inputs arenot used and must be tied to GND

Table 16 PS Attributes

CLKOUT_PHASE_SHIFT Disables PS component or chooses between Fixed Phase and Variable Phase modes

NONE FIXED VARIABLE

PHASE_SHIFT Determines size and direction of initial fine phase shift Integers from ndash255 to +255(1)

Notes 1 The practical range of values will be less when TCLKIN gt FINE_SHIFT_RANGE in the Fixed Phase mode also when TCLKIN gt

(FINE_SHIFT_RANGE)2 in the Variable Phase mode the FINE_SHIFT_RANGE represents the sum total delay of all taps

Figure 17 Phase Shifter Waveforms

DS099-2_11_031303

CLKIN

CLKFB

TCLKINP

256

b CLKOUT_PHASE_SHIFT = FIXED

TCLKINP

256

Shift Range over all P Values ndash255 +255

Shift Range over all P Values 0

0

ndash255 +255

Shift Range over all N Values 0ndash255 +255

CLKIN

CLKFB beforeDecrement

c CLKOUT_PHASE_SHIFT = VARIABLE

CLKFB afterDecrement

TCLKINN

256

CLKIN

CLKFB

a CLKOUT_PHASE_SHIFT = NONE

Notes 1 P represents the integer value ranging from ndash255 to +255 to which the PHASE_SHIFT attribute is assigned2 N is an integer value ranging from ndash255 to +255 that represents the net phase shift effect from a series of increment andor

decrement operations N = Total number of increments ndash Total number of decrements

A positive value for N indicates a net increment a negative value indicates a net decrement

The Variable Phase ModeThe ldquoVariable Phaserdquo mode dynamically adjusts the finephase shift over time using three inputs to the PS compo-nent namely PSEN PSCLK and PSINCDEC as defined inTable 17

Just following device configuration the PS component ini-tially determines TPS by evaluating Equation (4) for thevalue assigned to the PHASE_SHIFT attribute Then todynamically adjust that phase shift use the three PS inputsto increase or decrease the fine phase shift

PSINCDEC is synchronized to the PSCLK clock signalwhich is enabled by asserting PSEN It is possible to drivethe PSCLK input with the CLKIN signal or any other clocksignal A request for phase adjustment is entered as followsFor each PSCLK cycle that PSINCDEC is High the PScomponent adds 1256 of a CLKIN cycle to TPS Similarlyfor each enabled PSCLK cycle that PSINCDEC is Low thePS component subtracts 1256 of a CLKIN cycle from TPSThe phase adjustment may require as many as 100 CLKINcycles plus three PSCLK cycles to take effect at which

point the output PSDONE goes High for one PSCLK cycleThis pulse indicates that the PS component has finished thepresent adjustment and is now ready for the next requestAsserting the Reset (RST) input returns TPS to its originalshift time as determined by the PHASE_SHIFT attributevalue The set of waveforms in Figure 17c illustrates therelationship between CLKFB and CLKIN in the VariablePhase mode

The Status Logic ComponentThe Status Logic component not only reports on the state ofthe DCM but also provides a means of resetting the DCM toan initial known state The signals associated with the Sta-tus Logic component are described in Table 18

As a rule the Reset (RST) input is asserted only upon con-figuring the device or changing the CLKIN frequency ADCM reset does not affect attribute values (egCLKFX_MULTIPLY and CLKFX_DIVIDE) If not used RSTmust be tied to GND

The eight bits of the STATUS bus are defined in Table 19

Table 17 Signals for Variable Phase Mode

PSEN(1) Input Enables PSCLK for variable phase adjustment

PSCLK(1) Input Clock to synchronize phase shift adjustment

PSINCDEC(1) Input Chooses between increment and decrement for phase adjustment It is synchronized to the PSCLK signal

PSDONE Output Goes High to indicate that present phase adjustment is complete and PS component is ready for next phase adjustment request It is synchronized to the PSCLK signal

Notes 1 It is possible to program this input for either a true or inverted polarity

Table 18 Status Logic Signals

RST Input A High resets the entire DCM to its initial power-on state Initializes the DLL taps for a delay of zero Sets the LOCKED output Low This input is asynchronous

STATUS[70] Output The bit values on the STATUS bus provide information regarding the state of DLL and PS operation

LOCKED Output Indicates that the CLKIN and CLKFB signals are in phase by going High The two signals are out-of-phase when Low

Stabilizing DCM Clocks Before User ModeIt is possible to delay the completion of device configurationuntil after the DLL has achieved a lock condition using theSTARTUP_WAIT attribute described in Table 20 Thisoption ensures that the FPGA does not enter user mode mdashie begin functional operation mdash until all system clocksgenerated by the DCM are stable In order to achieve thedelay it is necessary to set the attribute to TRUE as well asset the BitGen option LCK_cycle to one of the six cyclesmaking up the Startup phase of configuration The selectedcycle defines the point at which configuration will halt untilthe LOCKED output goes High

Global Clock NetworkSpartan-3 devices have eight Global Clock inputs calledGCLK0 - GCLK7 These inputs provide access to alow-capacitance low-skew network that is well-suited tocarrying high-frequency signals The Spartan-3 clock net-work is shown in Figure 18 GCLK0 through GCLK3 areplaced at the center of the diersquos bottom edge GCLK4through GCLK7 are placed at the center of the diersquos topedge It is possible to route each of the eight Global Clockinputs to any CLB on the die

Eight Global Clock Multiplexers (also called BUFGMUX ele-ments) are provided that accept signals from Global Clockinputs and route them to the internal clock network as well

as DCMs Four BUFGMUX elements are placed at the cen-ter of the diersquos bottom edge just above the GCLK0 - GCLK4inputs The remaining four BUFGMUX elements are placedat the center of the diersquos top edge just below the GCLK4 -GCLK7 inputs

Each BUFGMUX element is a 2-to-1 multiplexer that canreceive signals from any of the four following sources

1 One of the four Global Clock inputs on the same side of the die mdash top or bottom mdash as the BUFGMUX element in use

2 Any of four nearby horizontal Double lines

3 Any of four outputs from the DCM in the right-hand quadrant that is on the same side of the die as the BUFGMUX element in use

4 Any of four outputs from the DCM in the left-hand quadrant that is on the same side of the die as the BUFGMUX element in use

Sources 3 and 4 are not available on the XC3S50 die thatlacks DCMs

Each BUFGMUX can switch incoming clock signals to twopossible destinations

1 The vertical spine belonging to the same side of the die mdash top or bottom mdash as the BUFGMUX element in use The two spines mdash top and bottom mdash each comprise four vertical clock lines each running from one of the

Table 19 DCM STATUS Bus

Bit Name Description

0 Phase Shift Overflow

A value of 1 indicates a phase shift overflow when one of two conditions occur bull Incrementing (or decrementing) TPS beyond 255256 of a CLKIN cycle

bull The DLL is producing its maximum possible phase shift (ie all delay taps are active)(1)

1 CLKIN Activity A value of 1 indicates that the CLKIN signal is not toggling A value of 0 indicates toggling This bit functions only when the CLKFB input is connected(2)

2 Reserved -

3 Reserved -

4 Reserved -

5 Reserved -

6 Reserved -

7 Reserved -

Notes 1 The DLL phase shift with all delay taps active is specified as the parameter FINE_SHIFT_RANGE2 If only the DFS clock outputs are used but none of the DLL clock outputs this bit will not go High when the CLKIN signal stops

Table 20 Status Attributes

STARTUP_WAIT Delays transition from configuration to user mode until lock condition is achieved TRUE FALSE

BUFGMUX elements on the same side towards the center of the die At the center of the die clock signals reach the eight-line horizontal spine which spans the width of the die In turn the horizontal spine branches out into a subsidiary clock interconnect that accesses the CLBs

2 The clock input of either DCM on the same side of the die mdash top or bottom mdash as the BUFGMUX element in use

A Global clock input is placed in a design using either aBUFGMUX element or the BUFG (Global Clock Buffer) ele-ment For the purpose of minimizing the dynamic power dis-sipation of the clock network the Xilinx developmentsoftware automatically disables all clock line segments thata design does not use

Figure 18 Spartan-3 Clock Network (Top View)

4

8

4

88

Horizontal Spine

Top

Spi

neB

otto

m S

pine

4

DCM DCM

Array Dependent

bull

DS099-2_18_070203

4 BUFGMUX

GCLK2GCLK3

GCLK0GCLK1

4 BUFGMUX

GCLK6 GCLK4GCLK7 GCLK5

InterconnectInterconnect (or routing) passes signals among the variousfunctional elements of Spartan-3 devices There are fourkinds of interconnect Long lines Hex lines Double linesand Direct lines

Long lines connect to one out of every six CLBs (seeFigure 19a) Because of their low capacitance these linesare well-suited for carrying high-frequency signals with min-imal loading effects (eg skew) If all eight Global ClockInputs are already committed and there remain additionalclock signals to be assigned Long lines serve as a goodalternative

Hex lines connect one out of every three CLBs (seeFigure 19b) These lines fall between Long lines and Dou-

ble lines in terms of capability Hex lines approach thehigh-frequency characteristics of Long lines at the sametime offering greater connectivity

Double lines connect to every other CLB (see Figure 19c)Compared to the types of lines already discussed Doublelines provide a higher degree of flexibility when making con-nections

Direct lines afford any CLB direct access to neighboringCLBs (see Figure 19d) These lines are most often used toconduct a signal from a source CLB to a Double Hex orLong line and then from the longer interconnect back to aDirect line accessing a destination CLB

Figure 19 Types of Interconnect

bull bull bullCLB CLB bull bull bullCLB CLB bull bull bullCLB CLB

6 6 6 6 6

bull bull bullCLB CLBbull bull bullCLB CLB

DS099-2_19_040103

(a) Long Line

CLB CLB CLB CLB CLB CLBCLB

8

DS099-2_20_040103

(b) Hex Line

CLB

2

CLB CLB

DS099-2_21_040103

CLBCLB CLB

DS099-2_22_040103

(d) Direct Lines

(c) Double Line

ConfigurationSpartan-3 devices are configured by loading applicationspecific configuration data into the internal configurationmemory Configuration is carried out using a subset of thedevice pins some of which are Dedicated to one functiononly while others indicated by the term Dual-Purpose

can be re-used as general-purpose User IOs once configu-ration is complete

Depending on the system design several configurationmodes are supported selectable via mode pins The modepins M0 M1 and M2 are Dedicated pins The mode pin set-tings are shown in Table 21

An additional pin HSWAP_EN is used in conjunction withthe mode pins to select whether user IO pins have pull-upsduring configuration By default HSWAP_EN is tied High(internal pull-up) which shuts off the pull-ups on the user IOpins during configuration When HSWAP_EN is tied Lowuser IOs have pull-ups during configuration Other Dedi-cated pins are CCLK (the configuration clock pin) DONEPROG_B and the boundary-scan pins TDI TDO TMSand TCK Depending on the configuration mode chosenCCLK can be an output generated by the FPGA or an inputaccepting an externally generated clock

A persist option is available which can be used to force theconfiguration pins to retain their configuration function evenafter device configuration is complete If the persist option isnot selected then the configuration pins with the exceptionof CCLK PROG_B and DONE can be used as user IO innormal operation The persist option does not apply to theboundary-scan related pins The persist feature is valuablein applications that readback configuration data after enter-ing the User mode

Table 22 lists the total number of bits required to configureeach FPGA as well as the PROMs suitable for storing thosebits See DS123 Platform Flash In-System ProgrammableConfiguration PROMs data sheet for more information

The Standard Configuration InterfaceConfiguration signals belong to one of two different catego-ries Dedicated or Dual-Purpose Which category deter-mines which of the FPGArsquos power rails supplies the signalrsquosdriver and thus helps describe the electrical at the pin

The Dedicated configuration pins include PROG_BHSWAP_EN TDI TMS TCK TDO CCLK DONE andM0-M2 These pins use the VCCAUX lines for power

The Dual-Purpose configuration pins comprise INIT_BDOUT BUSY RDWR_B CS_B and DIND0-D7 Each ofthese pins according to its bank placement uses the VCCOlines for either Bank 4 (VCCO_4) or Bank 5 (VCCO_5) Allthe signals used in the serial configuration modes rely onVCCO_4 power Signals used in the parallel configurationmodes and Readback require from VCCO_5 as well as fromVCCO_4

Both the Dedicated and Dual-Purpose signals describedabove constitute the configuration interface In the standardcase this interface is 25V-LVCMOS-compatible Thismeans that 25V is applied to the VCCAUX VCCO_4 andVCCO_5 lines (this last in the parallel or Readback caseonly) One need only apply 25 Volts to these VCCO linesfrom power-on to the end of configuration Upon enteringthe User mode it is possible to switch to supply voltage per-mitting signal swings other than 25V

Table 21 Spartan-3 Configuration Mode Pin Settings

Configuration Mode(1) M0 M1 M2 Synchronizing Clock Data Width Serial DOUT(2)

Master Serial 0 0 0 CCLK Output 1 Yes

Slave Serial 1 1 1 CCLK Input 1 Yes

Master Parallel 1 1 0 CCLK Output 8 No

Slave Parallel 0 1 1 CCLK Input 8 No

JTAG 1 0 1 TCK Input 1 No

Notes 1 The voltage levels on the M0 M1 and M2 pins select the configuration mode2 The daisy chain is possible only in the Serial modes when DOUT is used

Table 22 Spartan-3 Configuration Data

Device File Sizes

Xilinx Platform Flash PROM

Serial Configuration

Parallel Configuration

XC3S50 439264 XCF01S XCF08P

XC3S200 1047616 XCF01S XCF08P

XC3S400 1699136 XCF02S XCF08P

XC3S1000 3223488 XCF04S XCF08P

XC3S1500 5214784 XCF08P XCF08P

XC3S2000 7673024 XCF08P XCF08P

XC3S4000 11316864 XCF16P XCF16P

XC3S5000 13271936 XCF16P XCF16P

33V-Tolerant Configuration InterfaceIt is possible to achieve 33V-tolerance at the configurationinterface simply by adding a few external resistors Thisapproach may prove useful when it is undesirable to switchthe VCCO_4 and VCCO_5 voltages from 25V to 33V afterconfiguration

The 33V-tolerance is implemented as follows (a similarapproach can be used for other supply voltage levels)

First to power the Dual-Purpose configuration pins apply33V to the VCCO_4 and (as needed) the VCCO_5 linesThis scales the output voltages and input thresholds associ-ated with these pins so that they become 33V-compatible

Second to power the Dedicated configuration pins apply25V to the VCCAUX lines (the same as for the standardinterface) In order to achieve 33V-tolerance the Dedicatedinputs will require series resistors that limit the incomingcurrent to 10mA or less The Dedicated outputs will needpull-up resistors to ensure adequate noise margin when theFPGA is driving a High logic level into another devicersquos 33Vreceiver Choose a power regulator or supply that can toler-ate reverse current on the VCCAUX lines

Configuration ModesSpartan-3 supports the following five configuration modes

bull Slave Serial modebull Master Serial mode

bull Slave Parallel mode

bull Master Parallel modebull Boundary-Scan (JTAG) mode (IEEE 1532IEEE

11491)

Slave Serial ModeIn Slave Serial mode the FPGA receives configuration datain bit-serial form from a serial PROM or other serial sourceof configuration data The FPGA on the far right of Figure 20is set for the Slave Serial mode The CCLK pin on the FPGAis an input in this mode The serial bitstream must be setupat the DIN input pin a short time before each rising edge ofthe externally generated CCLK

Multiple FPGAs can be daisy-chained for configuration froma single source After a particular FPGA has been config-ured the data for the next device is routed internally to theDOUT pin The data on the DOUT pin changes on the risingedge of CCLK

Figure 20 Connection Diagram for Master and Slave Serial Configuration

DOUTDIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Master

PROG_B

DIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Slave

PROG_B

DS099_23_041103

D0

CLK

CE

OERESET

CF

PlatformFlash PROM

XCF0xSor

XCFxxP

VCCINT

12V

VCCAUX

VCCO Bank 4

25V

47KΩAll

25V

VCCAUX VCCINT

VCCO Bank 412V

33V

VCC VCCJ

VCCO

25V

M0M1M2

GNDGNDGND

Notes 1 There are two ways to use the DONE line First one may set the BitGen option DriveDone to Yes only for the

last FPGA to be configured in the chain shown above (or for the single FPGA as may be the case) This enables the DONE pin to drive High thus no pull-up resistor is necessary DriveDone is set to No for the remaining FPGAs in the chain Second DriveDone can be set to No for all FPGAs Then all DONE lines are open-drain and require the pull-up resistor shown in grey In most cases a value between 33KΩ to 47KΩ is sufficient However when using DONE synchronously with a long chain of FPGAs cumulative capacitance may necessitate lower resistor values (eg down to 330Ω) in order to ensure a rise time within one clock cycle

2 For information on how to program the FPGA using 33V signals and power see 33V-Tolerant Configuration Interface

Slave Serial mode is selected by applying lt111gt to themode pins (M0 M1 and M2) A weak pull-up on the modepins makes slave serial the default mode if the pins are leftunconnected

Master Serial ModeIn Master Serial mode the CCLK pin is an output pin TheFPGA just to the right of the PROM in Figure 20 is set forMaster Serial mode It is the FPGA that drives the configu-ration clock on the CCLK pin to a Xilinx Serial PROM whichin turn feeds bit-serial data to the DIN input The FPGAaccepts this data on each rising CCLK edge After theFPGA has been loaded the data for the next device in adaisy-chain is presented on the DOUT pin after the risingCCLK edge

The interface is identical to slave serial except that an inter-nal oscillator is used to generate the configuration clock(CCLK) A wide range of frequencies can be selected forCCLK which always starts at a default frequency of 6 MHzConfiguration bits then switch CCLK to a higher frequencyfor the remainder of the configuration

Slave Parallel ModeThe Parallel modes support the fastest configurationByte-wide data is written into the FPGA with a BUSY flag

controlling the flow of data An external source provides8-bit-wide data CCLK an active-Low Chip Select (CS_B)signal and an active-Low Write signal (RDWR_B) If BUSYis asserted (High) by the FPGA the data must be held untilBUSY goes Low Data can also be read using the SlaveParallel mode If RDWR_B is asserted configuration data isread out of the FPGA as part of a readback operation

After configuration it is possible to use any of the Multipur-pose pins (DIND0-D7 DOUTBUSY INITB CS_B andRDWR_B) as User IOs To do this simply set the BitGenoption Persist to No and assign the desired signals to multi-purpose configuration pins using the Xilinx developmentsoftware Alternatively it is possible to continue using theconfiguration port (eg all configuration pins taken together)when operating in the User mode This is accomplished bysetting the Persist option to Yes

Multiple FPGAs can be configured using the Slave Parallelmode and can be made to start-up simultaneouslyFigure 21 shows the device connections To configure mul-tiple devices in this way wire the individual CCLK DataRDWR_B and BUSY pins of all the devices in parallel Theindividual devices are loaded separately by deasserting theCS_B pin of each device in turn and writing the appropriatedata

Figure 21 Connection Diagram for Slave Parallel Configuration

PROG_B

INIT_B

DONE

Spartan-3Slave

INIT_B

D[07]

CCLK

RDWR_B

BUSY

CS_B

PROG_B

DONE

CS_B

Spartan-3Slave

INIT_B

GND

D[07]

CCLK

RDWR_B

BUSY

CS_B

D[07]

CCLK

RDWR_B

BUSY

PROG_B

DONE

CS_B

DS099_24_041103

25V

M1M2M0

25V

M1M2M0

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

47KΩ 47KΩ

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

25V

GND

Notes 1 There are two ways to use the DONE line First one may set the BitGen option DriveDone to Yes only for the last FPGA

to be configured in the chain shown above (or for the single FPGA as may be the case) This enables the DONE pin to drive High thus no pull-up resistor is necessary DriveDone is set to No for the remaining FPGAs in the chain Second DriveDone can be set to No for all FPGAs Then all DONE lines are open-drain and require the pull-up resistor shown in grey In most cases a value between 33KΩ to 47KΩ is sufficient However when using DONE synchronously with a long chain of FPGAs cumulative capacitance may necessitate lower resistor values (eg down to 330Ω) in order to ensure a rise time within one clock cycle

2 If the FPGAs use different configuration data files configure them in sequence by first asserting the CS_B of one FPGA then asserting the CS_B of the other FPGA

Master Parallel ModeIn this mode the device is configured byte-wide on a CCLKsupplied by the FPGA Timing is similar to the Slave Parallelmode except that CCLK is supplied by the FPGA Thedevice connections are shown in Figure 22

Boundary-Scan (JTAG) ModeIn Boundary-Scan mode dedicated pins are used for con-figuring the FPGA The configuration is done entirelythrough the IEEE 11491 Test Access Port (TAP) FPGAconfiguration using the Boundary-Scan mode is compliantwith the IEEE 11491-1993 standard and the new IEEE1532 standard for In-System Configurable (ISC) devices

Configuration through the boundary-scan port is alwaysavailable independent of the mode selection Selecting theBoundary-Scan mode simply turns off the other modes

Configuration SequenceThe configuration of Spartan-3 devices is a three-stage pro-cess that occurs after Power-On Reset or the assertion ofPROG_B POR occurs after the VCCINT VCCAUX and VCCOBank 4 supplies have reached their respective maximuminput threshold levels (see Table 6 in Module 3) After PORthe three-stage process begins

First the configuration memory is cleared Next con-figuration data is loaded into the memory and finally thelogic is activated by a start-up process A flow diagram forthe configuration sequence of the Serial and Parallel modesis shown in Figure 23 The flow diagram for the Bound-ary-Scan configuration sequence appears in Figure 24

Figure 22 Connection Diagram for Master Parallel Configuration

Spartan-3Master

D[07]

CCLK

PROG_B

DONE

INIT_B

DATA[07]

CCLK

RDWR_B

CS_B

CF

CE

OERESET

Platform Flash PROM

DS099_25_041103

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

GND

33V

VCC VCCJ

VCCO

25V

XCFxxP

25V

All47KΩ

Notes 1 There are two ways to use the DONE line First one may set the BitGen option DriveDone to Yes

only for the last FPGA to be configured in the chain shown above (or for the single FPGA as may be the case) This enables the DONE pin to drive High thus no pull-up resistor is necessary DriveDone is set to No for the remaining FPGAs in the chain Second DriveDone can be set to No for all FPGAs Then all DONE lines are open-drain and require the pull-up resistor shown in grey In most cases a value between 33KΩ to 47KΩ is sufficient However when using DONE synchronously with a long chain of FPGAs cumulative capacitance may necessitate lower resistor values (eg down to 330Ω) in order to ensure a rise time within one clock cycle

Figure 23 Configuration Flow Diagram for the Serial and Parallel Modes

Sample mode pins

No

Yes

YesClear configuration memory

Power-On Set PROG_B Lowafter Power-On

Yes

NoCRCcorrect

YesNoReconfigure

Load configurationdata frames

INIT_B goes LowAbort Start-Up

Start-Upsequence

User mode

INIT_ B = High

PROG_B = Low

DS099_26_041103

VCCINT gt1Vand VCCAUX gt 2V

and VCCO Bank 4 gt 1V

Figure 24 Boundary-Scan Configuration Flow Diagram

Samplemode pins

(JTAG port becomesavailable)

Clearconfiguration

memory

No

Yes

No

Yes

Power-On

CRCcorrect

Load CFG_INinstruction

Shutdownsequence

Reconfigure

Load JSTARTinstruction

SynchronousTAP reset

(Clock five 1son TMS)

Start-Upsequence

User mode

INIT_B = High

PROG_B = Low

Load JShutdowninstruction

No

DS099_27_041103

Set PROG_B Lowafter Power-On

Configuration is automatically initiated after power-onunless it is delayed by the user INIT_B is an open-drain linethat the FPGA holds Low during the clearing of the configu-ration memory Extending the time that the pin is Lowcauses the configuration sequencer to wait Thus configu-ration is delayed by preventing entry into the phase wheredata is loaded

The configuration process can also be initiated by assertingthe PROG_B pin The end of the memory-clearing phase issignaled by the INIT_B pin going High At this point the con-figuration data is written to the FPGA The FPGA holds theGlobal SetReset (GSR) signal active throughout configura-tion keeping all flip-flops on the device in a reset state Thecompletion of the entire process is signaled by the DONEpin going High

The default start-up sequence shown in Figure 25 servesas a transition to the User mode The default start-upsequence is that one CCLK cycle after DONE goes Highthe Global Three-State signal (GTS) is released This per-mits device outputs to which signals have been assigned tobecome active One CCLK cycle later the Global WriteEnable (GWE) signal is released This permits the internalstorage elements to begin changing state in response to thedesign logic and the user clock

The relative timing of configuration events can be changedvia the BitGen options in the Xilinx development software Inaddition the GTS and GWE events can be made depen-dent on the DONE pins of multiple devices all going Highforcing the devices to start synchronously The sequencecan also be paused at any stage until lock has beenachieved on any DCM

ReadbackUsing Slave Parallel mode configuration data from the FPGA can be read back Readback is supported only in theSlave Parallel and Boundary-Scan modes

Along with the configuration data it is possible to read backthe contents of all registers distributed SelectRAM andblock RAM resources This capability is used for real-timedebugging

Figure 25 Default Start-Up Sequence

Start-Up Clock

Default Cycles

Sync-to-DONE

0 1 2 3 4 5 6 7

0 1

DONE High

2 3 4 5 6 7

Phase

Start-Up Clock

Phase

DONE

GTS

GSR

GWE

DS099_028_040803

DONE

GTS

GSR

GWE

Notes 1 The BitGen option StartupClk in the Xilinx

development software selects the CCLK input TCK input or a user-designated global clock input (the GCLK0 - GCLK7 pins) for receiving the clock signal that synchronizes Start-Up

Revision History

The Spartan-3 Family Data SheetDS099-1 Spartan-3 12V FPGA Family Introduction and Ordering Information (Module 1)

DS099-2 Spartan-3 12V FPGA Family Functional Description (Module 2)

DS099-3 Spartan-3 12V FPGA Family DC and Switching Characteristics (Module 3)

DS099-4 Spartan-3 12V FPGA Family Pinout Tables (Module 4)

Date Version No Description

041103 10 Initial Xilinx release

051903 11 Added Block RAM column DCMs and multipliers to XC3S50 descriptions

071103 12 Explained the configuration port Persist option in Slave Parallel Mode section Updated Figure 2 and Double-Data-Rate Transmission section to indicate that DDR clocking for the XC3S50 is the same as that for all other Spartan-3 devices Updated description of IO voltage tolerance in ESD Protection section In Table 6 changed input termination type for DCI version of the LVCMOS standard to None Added additional flexibility for making DLL connections in Figure 15 and accompanying text In the Configuration section inserted an explanation of how to choose power supplies for the configuration interface including guidelines for achieving 33V-tolerance

IOBs
- IOB Overview
- Storage Element Functions
- Double-Data-Rate Transmission
- Pull-Up and Pull-Down Resistors
- Weak-Keeper Circuit
- ESD Protection
- Slew Rate Control and Drive Strength
- Boundary-Scan Capability
- SelectIO Signal Standards
- Digitally Controlled Impedance (DCI)
- The Organization of IOBs into Banks
- Spartan-3 Compatibility
- Rules Concerning Banks
- Exceptions to Banks Supporting IO Standards
- Supply Voltages for the IOBs
- The IOs During Power-On Configuration and User Mode
- - CLB Overview
  - - Elements Within a Slice
    - Main Logic Paths
    - Function Generator
    - - Block RAM Overview
      - Arrangement of RAM Blocks on Die
        
        The Internal Structure of the Block RAM
        
        Block RAM Port Signal Definitions
        
        Port Aspect Ratios
        
        Block RAM Data Operations
        
        Dedicated Multipliers
        
        Digital Clock Manager (DCM)
        
        Delay-Locked Loop (DLL)
        
        DLL Attributes and Related Functions
        
        
        DLL Clock Output and Feedback Connections
        
        DLL Frequency Modes
        
        Accommodating High Input Frequencies
        
        Coarse Phase Shift Outputs of the DLL Component
        
        Basic Frequency Synthesis Outputs of the DLL Component
        
        Duty Cycle Correction of DLL Clock Outputs
        
        Digital Frequency Synthesizer (DFS)
        
        DFS Frequency Modes
        
        DFS With or Without the DLL
        
        DFS Clock Output Connections
        
        Phase Shifter (PS)
        
        PS Component Enabling and Mode Selection
        
        The Fixed Phase Mode
        
        The Variable Phase Mode
        
        The Status Logic Component
        
        Stabilizing DCM Clocks Before User Mode
        
        Global Clock Network
        
        Interconnect
        
        Configuration
        
        The Standard Configuration Interface
        
        33V-Tolerant Configuration Interface
        
        Configuration Modes
        
        Slave Serial Mode
        
        Master Serial Mode
        
        Slave Parallel Mode
        
        Master Parallel Mode
        
        Boundary-Scan (JTAG) Mode
        
        Configuration Sequence
        
        Readback
        
        Revision History
        
        The Spartan-3 Family Data Sheet

Page 2: R Spartan-3 1.2V FPGA Family: Functional Description€¦ · IFF2 Q SR Fixed Delay LVCMOS, LVTTL, PCI Single-ended Standards using V REF Differential Standards REV D CE CK Q SR REV

Figure 1 Simplified IOB Diagram

D

CE

CK

TFF1

Three-state Path

T

T1

TCE

T2TFF2

Q

SR

DDRMUX

REV

D

CE

CK

Q

SR REV

D

CE

CK

OFF1

Output Path

O1

OCE

O2OFF2

Q

SR

DDRMUX

WeakKeeperLatch

VCCO

VREFPin

IO Pin fromAdjacentIOB

DS099_01_040703

IOPin

Program-mableOutputDriver

DCI

ESDWeakPull-Up

WeakPull-Down

ESD

REV

D

CE

CK

Q

SR REV

OTCLK1

OTCLK2

D

CE

CK

IFF1

Input Path

I

ICE

IFF2

Q

SR

FixedDelay

LVCMOS LVTTL PCI

Single-ended Standardsusing VREF

Differential Standards

REV

D

CE

CK

Q

SR REV

ICLK1

ICLK2

SR

REV

Note All IOB signals communicating with the FPGAs internal logic have the option of inverting polarity

IQ1

IQ2

D1

CLK1

DDR MUX

DCM

Q1

FDDR

D2

CLK2

Q2

180˚ 0˚

DS099-2_02_070303

Q

Signal Standard

Current Drive (mA)

2 4 6 8 12 16 24

LVCMOS12 - - - -

LVCMOS15 - -

LVCMOS18 -

LVCMOS25

LVCMOS33

LVTTL

Signal Standard

VCCO

VREF for Inputs(1)

For Outputs

For Inputs

HSTL_I 15 - 075 075

HSTL_III 15 - 09 15

HSTL_I_18 18 - 09 09

HSTL_II_18 18 - 09 09

HSTL_III_18 18 - 11 18

LVCMOS12 12 12 - -

LVCMOS15 15 15 - -

LVCMOS18 18 18 - -

LVCMOS25 25 25 - -

LVCMOS33 33 33 - -

LVTTL 33 33 - -

PCI33_3 30 30 - -

SSTL18_I 18 - 09 09

SSTL2_I 25 - 125 125

SSTL2_II 25 - 125 125

Signal Standard

VOD(1) (mV)

For Outputs

For Inputs Min Max

LDT_25 25 - - 430 670

LVDS_25 25 - - 250 400

BLVDS_25 25 - - 250 450

LVDSEXT_25 25 - - 330 700

ULVDS_25 25 - - 430 670

RSDS_25 25 - - 100 400

Signal Standard

VCCO

VREF for Inputs(1)

For Outputs

For Inputs

VCCO (V)

VREF for Inputs (V)

Termination Type

For Outputs

Single-Ended

GTLP_DCI 15 15 10

None

LVDCI_18 18 18 -

LVDCI_25 25 25 -

LVDCI_33 33 33 -

LVDCI_DV2_18 18 18 -

LVDCI_DV2_25 25 25 -

LVDCI_DV2_33 33 33 -

Differential

HSTL_III_DCI_18(2)

HSTL_I_DCI_18(2)

SSTL18_I_DCI(3)

SSTL2_I_DCI(3)

SSTL2_II_DCI

Z0

IOB

R

Z0

IOB

R2

R Z0

VCCOIOB

2R

2R Z0

VCCOIOB

25Ω

2R

2R Z0

VCCOIOB

DS099-2_04_091602

VCCO

VRN

VRP

RREF (1)

DS099-2_03_060102

Bank 0 Bank 1

Bank 5 Bank 4

Ban

k 7

Ban

k 6

Ban

k 2

Ban

k 3

DS099-2_05_040703

or Shift Register)

CIN

SLICEX0Y1

SLICEX0Y0

SwitchMatrix

COUT

CLB

COUT

SHIFTOUTSHIFTIN

CIN

SLICEX1Y1

SLICEX1Y0

DeviceTotal Number

of RAM Blocks

Total Addressable

Locations (bits)

Number of

Columns

XC3S50 4 73728 1

XC3S200 12 221184 2

XC3S400 16 294912 2

XC3S1000 24 442368 2

XC3S1500 32 589824 2

XC3S2000 40 737280 2

XC3S4000 96 1769472 4

XC3S5000 104 1916928 4

DS099-2_12_030703

Spartan-3Dual Port

Block RAM

Read

Write

Read

Write

Read

Por

t A

Por

t B

21

4

DS099-2_13_091302

WEAENA

SSRACLKA

DIPA[30]

DOPA[pA 10]

DOA[wA 10]

RAM16_wA_wB

DOPB[pB 10]

DOB[wB 10]

WEBENB

SSRBCLKB

DIPB[30]

WEEN

SSRCLK

ADDR[r 10]DI[w 10]

DIP[p 10]

DOP[p 10]

DO[w 10]

RAM16_Sw

Signal Description

Port A Signal Name

Data Output Bus

Signal Description

Port A Signal Name

n = 2r (2)

Block RAM Capacity

(bits)

1 0 1 14 16384 16384

2 0 2 13 8192 16384

4 0 4 12 4096 16384

8 1 9 11 2048 18432

16 2 18 10 1024 18432

32 4 36 9 512 18432

CLK

WE

DI

ADDR

DO

EN

DISABLED READ

XXXX 1111 2222 XXXX

aa bb cc dd

0000 MEM(aa) 1111 2222 MEM(dd)

WRITEMEM(cc)=2222

DS099-2_14_030403

CLK

WE

DI

ADDR

DO

EN

DISABLED READ

XXXX 1111 2222 XXXX

aa bb cc dd

WRITEMEM(cc)=2222

DS099-2_15_030403

CLK

WE

DI

ADDR

DO

EN

DISABLED READ

XXXX 1111 2222 XXXX

aa bb cc dd

WRITEMEM(cc)=2222

DS099-2_16_030403

DS099-2_17_091302

A[170]

B[170]

P[350]MULT18X18

A[170]

B[170]

CLK

CE

RST

P[350]MULT18X18S

DS099-2_07_040103

PSINCDECPSEN

PSCLK

CLKIN

CLKFB

RSTSTATUS [70]

LOCKED8

CLKFX180

CLKFX

CLK0

PSDONE

ClockDistribution

StatusLogic

DFSDLL

PhaseShifter

Del

ay T

aps

Out

put S

tage

Inpu

t Sta

ge

DCM

DS099-2_08_041103

CLKINDelay

n

CLKFB

RST

CLK0

CLK90

CLK180

CLK270

CLK2X

CLK2X180

CLKDV

Out

put S

ectio

n

Control

Delayn-1

PhaseDetection

LOCKED

Delay2

Delay1

Mode Support

Low Frequency

High Frequency

Yes Yes

Yes No

Yes Yes

Yes No

Yes Yes

NONE 1X 2X

LOW HIGH

TRUE FALSE

15 2 25 3 35 4 45 5 55 60 65 70 75 8 9 10 11 12 13 14 15 and 16

TRUE FALSE

DS099-2_09_071003

CLK2X180

CLK0

ClockNet Delay

BUFGMUX

BUFG

FPGA

CLKIN

DCM

CLKFB

CLK2X180

CLK0

ClockNet Delay

IBUFG

FPGA

CLKIN

DCM

CLKFB

OBUFG

CLK2X

IBUFG

FPGA

CLKIN

DCM

CLKFB

OBUFG

CLK0CLK90

CLK180CLK270CLKDV

CLK2X180

CLK2X

ClockNet Delay

BUFGMUX

BUFG

FPGA

CLKIN

DCM

CLKFB

CLK0CLK90

CLK180CLK270CLKDV

CLK2X180

Phase

0o 90o 180o 270o 0o 90o 180o 270o 0o

DS099-2_10_031303

CLK2X

CLK2X180

CLKIN

CLKDV(1)

CLK0

CLK90

CLK180

CLK270

CLK0

CLK90

CLK180

CLK270

t

NONE FIXED VARIABLE

DS099-2_11_031303

CLKIN

CLKFB

TCLKINP

256

TCLKINP

256

0

ndash255 +255

CLKIN

TCLKINN

256

CLKIN

CLKFB

2 Reserved -

3 Reserved -

4 Reserved -

5 Reserved -

6 Reserved -

7 Reserved -

4

8

4

88

Horizontal Spine

Top

Spi

neB

otto

m S

pine

4

DCM DCM

Array Dependent

bull

DS099-2_18_070203

4 BUFGMUX

GCLK2GCLK3

GCLK0GCLK1

4 BUFGMUX

6 6 6 6 6

DS099-2_19_040103

(a) Long Line

8

DS099-2_20_040103

(b) Hex Line

CLB

2

CLB CLB

DS099-2_21_040103

CLBCLB CLB

DS099-2_22_040103

(d) Direct Lines

(c) Double Line

Device File Sizes

XC3S200 1047616 XCF01S XCF08P

XC3S400 1699136 XCF02S XCF08P

XC3S1000 3223488 XCF04S XCF08P

XC3S1500 5214784 XCF08P XCF08P

XC3S2000 7673024 XCF08P XCF08P

XC3S4000 11316864 XCF16P XCF16P

XC3S5000 13271936 XCF16P XCF16P

11491)

DOUTDIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Master

PROG_B

DIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Slave

PROG_B

DS099_23_041103

D0

CLK

CE

OERESET

CF

PlatformFlash PROM

XCF0xSor

XCFxxP

VCCINT

12V

VCCAUX

VCCO Bank 4

25V

47KΩAll

25V

VCCAUX VCCINT

VCCO Bank 412V

33V

VCC VCCJ

VCCO

25V

M0M1M2

GNDGNDGND

PROG_B

INIT_B

DONE

Spartan-3Slave

INIT_B

D[07]

CCLK

RDWR_B

BUSY

CS_B

PROG_B

DONE

CS_B

Spartan-3Slave

INIT_B

GND

D[07]

CCLK

RDWR_B

BUSY

CS_B

D[07]

CCLK

RDWR_B

BUSY

PROG_B

DONE

CS_B

DS099_24_041103

25V

M1M2M0

25V

M1M2M0

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

47KΩ 47KΩ

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

25V

GND

Spartan-3Master

D[07]

CCLK

PROG_B

DONE

INIT_B

DATA[07]

CCLK

RDWR_B

CS_B

CF

CE

OERESET

Platform Flash PROM

DS099_25_041103

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

GND

33V

VCC VCCJ

VCCO

25V

XCFxxP

25V

All47KΩ

Sample mode pins

No

Yes

NoCRCcorrect

YesNoReconfigure

Start-Upsequence

User mode

INIT_ B = High

PROG_B = Low

DS099_26_041103

Samplemode pins

Clearconfiguration

memory

No

Yes

No

Yes

Power-On

CRCcorrect

Shutdownsequence

Reconfigure

Start-Upsequence

User mode

INIT_B = High

PROG_B = Low

No

DS099_27_041103

Start-Up Clock

Default Cycles

Sync-to-DONE

0 1 2 3 4 5 6 7

0 1

DONE High

2 3 4 5 6 7

Phase

Start-Up Clock

Phase

DONE

GTS

GSR

GWE

DS099_028_040803

DONE

GTS

GSR

GWE

Revision History

IOBs
- IOB Overview
- ESD Protection
- - CLB Overview
    - Main Logic Paths
        
        
        
        Port Aspect Ratios
        
        
        
        
        
        
        
        
        DLL Frequency Modes
        
        
        
        
        
        
        DFS Frequency Modes
        
        
        
        Phase Shifter (PS)
        
        
        
        
        
        
        
        Interconnect
        
        Configuration
        
        
        
        Configuration Modes
        
        Slave Serial Mode
        
        Master Serial Mode
        
        Slave Parallel Mode
        
        
        
        
        Readback
        
        Revision History

Page 3: R Spartan-3 1.2V FPGA Family: Functional Description€¦ · IFF2 Q SR Fixed Delay LVCMOS, LVTTL, PCI Single-ended Standards using V REF Differential Standards REV D CE CK Q SR REV

D1

CLK1

DDR MUX

DCM

Q1

FDDR

D2

CLK2

Q2

180˚ 0˚

DS099-2_02_070303

Q

Signal Standard

Current Drive (mA)

2 4 6 8 12 16 24

LVCMOS12 - - - -

LVCMOS15 - -

LVCMOS18 -

LVCMOS25

LVCMOS33

LVTTL

Signal Standard

VCCO

VREF for Inputs(1)

For Outputs

For Inputs

HSTL_I 15 - 075 075

HSTL_III 15 - 09 15

HSTL_I_18 18 - 09 09

HSTL_II_18 18 - 09 09

HSTL_III_18 18 - 11 18

LVCMOS12 12 12 - -

LVCMOS15 15 15 - -

LVCMOS18 18 18 - -

LVCMOS25 25 25 - -

LVCMOS33 33 33 - -

LVTTL 33 33 - -

PCI33_3 30 30 - -

SSTL18_I 18 - 09 09

SSTL2_I 25 - 125 125

SSTL2_II 25 - 125 125

Signal Standard

VOD(1) (mV)

For Outputs

For Inputs Min Max

LDT_25 25 - - 430 670

LVDS_25 25 - - 250 400

BLVDS_25 25 - - 250 450

LVDSEXT_25 25 - - 330 700

ULVDS_25 25 - - 430 670

RSDS_25 25 - - 100 400

Signal Standard

VCCO

VREF for Inputs(1)

For Outputs

For Inputs

VCCO (V)

VREF for Inputs (V)

Termination Type

For Outputs

Single-Ended

GTLP_DCI 15 15 10

None

LVDCI_18 18 18 -

LVDCI_25 25 25 -

LVDCI_33 33 33 -

LVDCI_DV2_18 18 18 -

LVDCI_DV2_25 25 25 -

LVDCI_DV2_33 33 33 -

Differential

HSTL_III_DCI_18(2)

HSTL_I_DCI_18(2)

SSTL18_I_DCI(3)

SSTL2_I_DCI(3)

SSTL2_II_DCI

Z0

IOB

R

Z0

IOB

R2

R Z0

VCCOIOB

2R

2R Z0

VCCOIOB

25Ω

2R

2R Z0

VCCOIOB

DS099-2_04_091602

VCCO

VRN

VRP

RREF (1)

DS099-2_03_060102

Bank 0 Bank 1

Bank 5 Bank 4

Ban

k 7

Ban

k 6

Ban

k 2

Ban

k 3

DS099-2_05_040703

or Shift Register)

CIN

SLICEX0Y1

SLICEX0Y0

SwitchMatrix

COUT

CLB

COUT

SHIFTOUTSHIFTIN

CIN

SLICEX1Y1

SLICEX1Y0

DeviceTotal Number

of RAM Blocks

Total Addressable

Locations (bits)

Number of

Columns

XC3S50 4 73728 1

XC3S200 12 221184 2

XC3S400 16 294912 2

XC3S1000 24 442368 2

XC3S1500 32 589824 2

XC3S2000 40 737280 2

XC3S4000 96 1769472 4

XC3S5000 104 1916928 4

DS099-2_12_030703

Spartan-3Dual Port

Block RAM

Read

Write

Read

Write

Read

Por

t A

Por

t B

21

4

DS099-2_13_091302

WEAENA

SSRACLKA

DIPA[30]

DOPA[pA 10]

DOA[wA 10]

RAM16_wA_wB

DOPB[pB 10]

DOB[wB 10]

WEBENB

SSRBCLKB

DIPB[30]

WEEN

SSRCLK

ADDR[r 10]DI[w 10]

DIP[p 10]

DOP[p 10]

DO[w 10]

RAM16_Sw

Signal Description

Port A Signal Name

Data Output Bus

Signal Description

Port A Signal Name

n = 2r (2)

Block RAM Capacity

(bits)

1 0 1 14 16384 16384

2 0 2 13 8192 16384

4 0 4 12 4096 16384

8 1 9 11 2048 18432

16 2 18 10 1024 18432

32 4 36 9 512 18432

CLK

WE

DI

ADDR

DO

EN

DISABLED READ

XXXX 1111 2222 XXXX

aa bb cc dd

0000 MEM(aa) 1111 2222 MEM(dd)

WRITEMEM(cc)=2222

DS099-2_14_030403

CLK

WE

DI

ADDR

DO

EN

DISABLED READ

XXXX 1111 2222 XXXX

aa bb cc dd

WRITEMEM(cc)=2222

DS099-2_15_030403

CLK

WE

DI

ADDR

DO

EN

DISABLED READ

XXXX 1111 2222 XXXX

aa bb cc dd

WRITEMEM(cc)=2222

DS099-2_16_030403

DS099-2_17_091302

A[170]

B[170]

P[350]MULT18X18

A[170]

B[170]

CLK

CE

RST

P[350]MULT18X18S

DS099-2_07_040103

PSINCDECPSEN

PSCLK

CLKIN

CLKFB

RSTSTATUS [70]

LOCKED8

CLKFX180

CLKFX

CLK0

PSDONE

ClockDistribution

StatusLogic

DFSDLL

PhaseShifter

Del

ay T

aps

Out

put S

tage

Inpu

t Sta

ge

DCM

DS099-2_08_041103

CLKINDelay

n

CLKFB

RST

CLK0

CLK90

CLK180

CLK270

CLK2X

CLK2X180

CLKDV

Out

put S

ectio

n

Control

Delayn-1

PhaseDetection

LOCKED

Delay2

Delay1

Mode Support

Low Frequency

High Frequency

Yes Yes

Yes No

Yes Yes

Yes No

Yes Yes

NONE 1X 2X

LOW HIGH

TRUE FALSE

15 2 25 3 35 4 45 5 55 60 65 70 75 8 9 10 11 12 13 14 15 and 16

TRUE FALSE

DS099-2_09_071003

CLK2X180

CLK0

ClockNet Delay

BUFGMUX

BUFG

FPGA

CLKIN

DCM

CLKFB

CLK2X180

CLK0

ClockNet Delay

IBUFG

FPGA

CLKIN

DCM

CLKFB

OBUFG

CLK2X

IBUFG

FPGA

CLKIN

DCM

CLKFB

OBUFG

CLK0CLK90

CLK180CLK270CLKDV

CLK2X180

CLK2X

ClockNet Delay

BUFGMUX

BUFG

FPGA

CLKIN

DCM

CLKFB

CLK0CLK90

CLK180CLK270CLKDV

CLK2X180

Phase

0o 90o 180o 270o 0o 90o 180o 270o 0o

DS099-2_10_031303

CLK2X

CLK2X180

CLKIN

CLKDV(1)

CLK0

CLK90

CLK180

CLK270

CLK0

CLK90

CLK180

CLK270

t

NONE FIXED VARIABLE

DS099-2_11_031303

CLKIN

CLKFB

TCLKINP

256

TCLKINP

256

0

ndash255 +255

CLKIN

TCLKINN

256

CLKIN

CLKFB

2 Reserved -

3 Reserved -

4 Reserved -

5 Reserved -

6 Reserved -

7 Reserved -

4

8

4

88

Horizontal Spine

Top

Spi

neB

otto

m S

pine

4

DCM DCM

Array Dependent

bull

DS099-2_18_070203

4 BUFGMUX

GCLK2GCLK3

GCLK0GCLK1

4 BUFGMUX

6 6 6 6 6

DS099-2_19_040103

(a) Long Line

8

DS099-2_20_040103

(b) Hex Line

CLB

2

CLB CLB

DS099-2_21_040103

CLBCLB CLB

DS099-2_22_040103

(d) Direct Lines

(c) Double Line

Device File Sizes

XC3S200 1047616 XCF01S XCF08P

XC3S400 1699136 XCF02S XCF08P

XC3S1000 3223488 XCF04S XCF08P

XC3S1500 5214784 XCF08P XCF08P

XC3S2000 7673024 XCF08P XCF08P

XC3S4000 11316864 XCF16P XCF16P

XC3S5000 13271936 XCF16P XCF16P

11491)

DOUTDIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Master

PROG_B

DIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Slave

PROG_B

DS099_23_041103

D0

CLK

CE

OERESET

CF

PlatformFlash PROM

XCF0xSor

XCFxxP

VCCINT

12V

VCCAUX

VCCO Bank 4

25V

47KΩAll

25V

VCCAUX VCCINT

VCCO Bank 412V

33V

VCC VCCJ

VCCO

25V

M0M1M2

GNDGNDGND

PROG_B

INIT_B

DONE

Spartan-3Slave

INIT_B

D[07]

CCLK

RDWR_B

BUSY

CS_B

PROG_B

DONE

CS_B

Spartan-3Slave

INIT_B

GND

D[07]

CCLK

RDWR_B

BUSY

CS_B

D[07]

CCLK

RDWR_B

BUSY

PROG_B

DONE

CS_B

DS099_24_041103

25V

M1M2M0

25V

M1M2M0

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

47KΩ 47KΩ

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

25V

GND

Spartan-3Master

D[07]

CCLK

PROG_B

DONE

INIT_B

DATA[07]

CCLK

RDWR_B

CS_B

CF

CE

OERESET

Platform Flash PROM

DS099_25_041103

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

GND

33V

VCC VCCJ

VCCO

25V

XCFxxP

25V

All47KΩ

Sample mode pins

No

Yes

NoCRCcorrect

YesNoReconfigure

Start-Upsequence

User mode

INIT_ B = High

PROG_B = Low

DS099_26_041103

Samplemode pins

Clearconfiguration

memory

No

Yes

No

Yes

Power-On

CRCcorrect

Shutdownsequence

Reconfigure

Start-Upsequence

User mode

INIT_B = High

PROG_B = Low

No

DS099_27_041103

Start-Up Clock

Default Cycles

Sync-to-DONE

0 1 2 3 4 5 6 7

0 1

DONE High

2 3 4 5 6 7

Phase

Start-Up Clock

Phase

DONE

GTS

GSR

GWE

DS099_028_040803

DONE

GTS

GSR

GWE

Revision History

IOBs
- IOB Overview
- ESD Protection
- - CLB Overview
    - Main Logic Paths
        
        
        
        Port Aspect Ratios
        
        
        
        
        
        
        
        
        DLL Frequency Modes
        
        
        
        
        
        
        DFS Frequency Modes
        
        
        
        Phase Shifter (PS)
        
        
        
        
        
        
        
        Interconnect
        
        Configuration
        
        
        
        Configuration Modes
        
        Slave Serial Mode
        
        Master Serial Mode
        
        Slave Parallel Mode
        
        
        
        
        Readback
        
        Revision History

Page 4: R Spartan-3 1.2V FPGA Family: Functional Description€¦ · IFF2 Q SR Fixed Delay LVCMOS, LVTTL, PCI Single-ended Standards using V REF Differential Standards REV D CE CK Q SR REV

D1

CLK1

DDR MUX

DCM

Q1

FDDR

D2

CLK2

Q2

180˚ 0˚

DS099-2_02_070303

Q

Signal Standard

Current Drive (mA)

2 4 6 8 12 16 24

LVCMOS12 - - - -

LVCMOS15 - -

LVCMOS18 -

LVCMOS25

LVCMOS33

LVTTL

Signal Standard

VCCO

VREF for Inputs(1)

For Outputs

For Inputs

HSTL_I 15 - 075 075

HSTL_III 15 - 09 15

HSTL_I_18 18 - 09 09

HSTL_II_18 18 - 09 09

HSTL_III_18 18 - 11 18

LVCMOS12 12 12 - -

LVCMOS15 15 15 - -

LVCMOS18 18 18 - -

LVCMOS25 25 25 - -

LVCMOS33 33 33 - -

LVTTL 33 33 - -

PCI33_3 30 30 - -

SSTL18_I 18 - 09 09

SSTL2_I 25 - 125 125

SSTL2_II 25 - 125 125

Signal Standard

VOD(1) (mV)

For Outputs

For Inputs Min Max

LDT_25 25 - - 430 670

LVDS_25 25 - - 250 400

BLVDS_25 25 - - 250 450

LVDSEXT_25 25 - - 330 700

ULVDS_25 25 - - 430 670

RSDS_25 25 - - 100 400

Signal Standard

VCCO

VREF for Inputs(1)

For Outputs

For Inputs

VCCO (V)

VREF for Inputs (V)

Termination Type

For Outputs

Single-Ended

GTLP_DCI 15 15 10

None

LVDCI_18 18 18 -

LVDCI_25 25 25 -

LVDCI_33 33 33 -

LVDCI_DV2_18 18 18 -

LVDCI_DV2_25 25 25 -

LVDCI_DV2_33 33 33 -

Differential

HSTL_III_DCI_18(2)

HSTL_I_DCI_18(2)

SSTL18_I_DCI(3)

SSTL2_I_DCI(3)

SSTL2_II_DCI

Z0

IOB

R

Z0

IOB

R2

R Z0

VCCOIOB

2R

2R Z0

VCCOIOB

25Ω

2R

2R Z0

VCCOIOB

DS099-2_04_091602

VCCO

VRN

VRP

RREF (1)

DS099-2_03_060102

Bank 0 Bank 1

Bank 5 Bank 4

Ban

k 7

Ban

k 6

Ban

k 2

Ban

k 3

DS099-2_05_040703

or Shift Register)

CIN

SLICEX0Y1

SLICEX0Y0

SwitchMatrix

COUT

CLB

COUT

SHIFTOUTSHIFTIN

CIN

SLICEX1Y1

SLICEX1Y0

DeviceTotal Number

of RAM Blocks

Total Addressable

Locations (bits)

Number of

Columns

XC3S50 4 73728 1

XC3S200 12 221184 2

XC3S400 16 294912 2

XC3S1000 24 442368 2

XC3S1500 32 589824 2

XC3S2000 40 737280 2

XC3S4000 96 1769472 4

XC3S5000 104 1916928 4

DS099-2_12_030703

Spartan-3Dual Port

Block RAM

Read

Write

Read

Write

Read

Por

t A

Por

t B

21

4

DS099-2_13_091302

WEAENA

SSRACLKA

DIPA[30]

DOPA[pA 10]

DOA[wA 10]

RAM16_wA_wB

DOPB[pB 10]

DOB[wB 10]

WEBENB

SSRBCLKB

DIPB[30]

WEEN

SSRCLK

ADDR[r 10]DI[w 10]

DIP[p 10]

DOP[p 10]

DO[w 10]

RAM16_Sw

Signal Description

Port A Signal Name

Data Output Bus

Signal Description

Port A Signal Name

n = 2r (2)

Block RAM Capacity

(bits)

1 0 1 14 16384 16384

2 0 2 13 8192 16384

4 0 4 12 4096 16384

8 1 9 11 2048 18432

16 2 18 10 1024 18432

32 4 36 9 512 18432

CLK

WE

DI

ADDR

DO

EN

DISABLED READ

XXXX 1111 2222 XXXX

aa bb cc dd

0000 MEM(aa) 1111 2222 MEM(dd)

WRITEMEM(cc)=2222

DS099-2_14_030403

CLK

WE

DI

ADDR

DO

EN

DISABLED READ

XXXX 1111 2222 XXXX

aa bb cc dd

WRITEMEM(cc)=2222

DS099-2_15_030403

CLK

WE

DI

ADDR

DO

EN

DISABLED READ

XXXX 1111 2222 XXXX

aa bb cc dd

WRITEMEM(cc)=2222

DS099-2_16_030403

DS099-2_17_091302

A[170]

B[170]

P[350]MULT18X18

A[170]

B[170]

CLK

CE

RST

P[350]MULT18X18S

DS099-2_07_040103

PSINCDECPSEN

PSCLK

CLKIN

CLKFB

RSTSTATUS [70]

LOCKED8

CLKFX180

CLKFX

CLK0

PSDONE

ClockDistribution

StatusLogic

DFSDLL

PhaseShifter

Del

ay T

aps

Out

put S

tage

Inpu

t Sta

ge

DCM

DS099-2_08_041103

CLKINDelay

n

CLKFB

RST

CLK0

CLK90

CLK180

CLK270

CLK2X

CLK2X180

CLKDV

Out

put S

ectio

n

Control

Delayn-1

PhaseDetection

LOCKED

Delay2

Delay1

Mode Support

Low Frequency

High Frequency

Yes Yes

Yes No

Yes Yes

Yes No

Yes Yes

NONE 1X 2X

LOW HIGH

TRUE FALSE

15 2 25 3 35 4 45 5 55 60 65 70 75 8 9 10 11 12 13 14 15 and 16

TRUE FALSE

DS099-2_09_071003

CLK2X180

CLK0

ClockNet Delay

BUFGMUX

BUFG

FPGA

CLKIN

DCM

CLKFB

CLK2X180

CLK0

ClockNet Delay

IBUFG

FPGA

CLKIN

DCM

CLKFB

OBUFG

CLK2X

IBUFG

FPGA

CLKIN

DCM

CLKFB

OBUFG

CLK0CLK90

CLK180CLK270CLKDV

CLK2X180

CLK2X

ClockNet Delay

BUFGMUX

BUFG

FPGA

CLKIN

DCM

CLKFB

CLK0CLK90

CLK180CLK270CLKDV

CLK2X180

Phase

0o 90o 180o 270o 0o 90o 180o 270o 0o

DS099-2_10_031303

CLK2X

CLK2X180

CLKIN

CLKDV(1)

CLK0

CLK90

CLK180

CLK270

CLK0

CLK90

CLK180

CLK270

t

NONE FIXED VARIABLE

DS099-2_11_031303

CLKIN

CLKFB

TCLKINP

256

TCLKINP

256

0

ndash255 +255

CLKIN

TCLKINN

256

CLKIN

CLKFB

2 Reserved -

3 Reserved -

4 Reserved -

5 Reserved -

6 Reserved -

7 Reserved -

4

8

4

88

Horizontal Spine

Top

Spi

neB

otto

m S

pine

4

DCM DCM

Array Dependent

bull

DS099-2_18_070203

4 BUFGMUX

GCLK2GCLK3

GCLK0GCLK1

4 BUFGMUX

6 6 6 6 6

DS099-2_19_040103

(a) Long Line

8

DS099-2_20_040103

(b) Hex Line

CLB

2

CLB CLB

DS099-2_21_040103

CLBCLB CLB

DS099-2_22_040103

(d) Direct Lines

(c) Double Line

Device File Sizes

XC3S200 1047616 XCF01S XCF08P

XC3S400 1699136 XCF02S XCF08P

XC3S1000 3223488 XCF04S XCF08P

XC3S1500 5214784 XCF08P XCF08P

XC3S2000 7673024 XCF08P XCF08P

XC3S4000 11316864 XCF16P XCF16P

XC3S5000 13271936 XCF16P XCF16P

11491)

DOUTDIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Master

PROG_B

DIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Slave

PROG_B

DS099_23_041103

D0

CLK

CE

OERESET

CF

PlatformFlash PROM

XCF0xSor

XCFxxP

VCCINT

12V

VCCAUX

VCCO Bank 4

25V

47KΩAll

25V

VCCAUX VCCINT

VCCO Bank 412V

33V

VCC VCCJ

VCCO

25V

M0M1M2

GNDGNDGND

PROG_B

INIT_B

DONE

Spartan-3Slave

INIT_B

D[07]

CCLK

RDWR_B

BUSY

CS_B

PROG_B

DONE

CS_B

Spartan-3Slave

INIT_B

GND

D[07]

CCLK

RDWR_B

BUSY

CS_B

D[07]

CCLK

RDWR_B

BUSY

PROG_B

DONE

CS_B

DS099_24_041103

25V

M1M2M0

25V

M1M2M0

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

47KΩ 47KΩ

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

25V

GND

Spartan-3Master

D[07]

CCLK

PROG_B

DONE

INIT_B

DATA[07]

CCLK

RDWR_B

CS_B

CF

CE

OERESET

Platform Flash PROM

DS099_25_041103

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

GND

33V

VCC VCCJ

VCCO

25V

XCFxxP

25V

All47KΩ

Sample mode pins

No

Yes

NoCRCcorrect

YesNoReconfigure

Start-Upsequence

User mode

INIT_ B = High

PROG_B = Low

DS099_26_041103

Samplemode pins

Clearconfiguration

memory

No

Yes

No

Yes

Power-On

CRCcorrect

Shutdownsequence

Reconfigure

Start-Upsequence

User mode

INIT_B = High

PROG_B = Low

No

DS099_27_041103

Start-Up Clock

Default Cycles

Sync-to-DONE

0 1 2 3 4 5 6 7

0 1

DONE High

2 3 4 5 6 7

Phase

Start-Up Clock

Phase

DONE

GTS

GSR

GWE

DS099_028_040803

DONE

GTS

GSR

GWE

Revision History

IOBs
- IOB Overview
- ESD Protection
- - CLB Overview
    - Main Logic Paths
        
        
        
        Port Aspect Ratios
        
        
        
        
        
        
        
        
        DLL Frequency Modes
        
        
        
        
        
        
        DFS Frequency Modes
        
        
        
        Phase Shifter (PS)
        
        
        
        
        
        
        
        Interconnect
        
        Configuration
        
        
        
        Configuration Modes
        
        Slave Serial Mode
        
        Master Serial Mode
        
        Slave Parallel Mode
        
        
        
        
        Readback
        
        Revision History

Page 5: R Spartan-3 1.2V FPGA Family: Functional Description€¦ · IFF2 Q SR Fixed Delay LVCMOS, LVTTL, PCI Single-ended Standards using V REF Differential Standards REV D CE CK Q SR REV

Signal Standard

VCCO

VREF for Inputs(1)

For Outputs

For Inputs

HSTL_I 15 - 075 075

HSTL_III 15 - 09 15

HSTL_I_18 18 - 09 09

HSTL_II_18 18 - 09 09

HSTL_III_18 18 - 11 18

LVCMOS12 12 12 - -

LVCMOS15 15 15 - -

LVCMOS18 18 18 - -

LVCMOS25 25 25 - -

LVCMOS33 33 33 - -

LVTTL 33 33 - -

PCI33_3 30 30 - -

SSTL18_I 18 - 09 09

SSTL2_I 25 - 125 125

SSTL2_II 25 - 125 125

Signal Standard

VOD(1) (mV)

For Outputs

For Inputs Min Max

LDT_25 25 - - 430 670

LVDS_25 25 - - 250 400

BLVDS_25 25 - - 250 450

LVDSEXT_25 25 - - 330 700

ULVDS_25 25 - - 430 670

RSDS_25 25 - - 100 400

Signal Standard

VCCO

VREF for Inputs(1)

For Outputs

For Inputs

VCCO (V)

VREF for Inputs (V)

Termination Type

For Outputs

Single-Ended

GTLP_DCI 15 15 10

None

LVDCI_18 18 18 -

LVDCI_25 25 25 -

LVDCI_33 33 33 -

LVDCI_DV2_18 18 18 -

LVDCI_DV2_25 25 25 -

LVDCI_DV2_33 33 33 -

Differential

HSTL_III_DCI_18(2)

HSTL_I_DCI_18(2)

SSTL18_I_DCI(3)

SSTL2_I_DCI(3)

SSTL2_II_DCI

Z0

IOB

R

Z0

IOB

R2

R Z0

VCCOIOB

2R

2R Z0

VCCOIOB

25Ω

2R

2R Z0

VCCOIOB

DS099-2_04_091602

VCCO

VRN

VRP

RREF (1)

DS099-2_03_060102

Bank 0 Bank 1

Bank 5 Bank 4

Ban

k 7

Ban

k 6

Ban

k 2

Ban

k 3

DS099-2_05_040703

or Shift Register)

CIN

SLICEX0Y1

SLICEX0Y0

SwitchMatrix

COUT

CLB

COUT

SHIFTOUTSHIFTIN

CIN

SLICEX1Y1

SLICEX1Y0

DeviceTotal Number

of RAM Blocks

Total Addressable

Locations (bits)

Number of

Columns

XC3S50 4 73728 1

XC3S200 12 221184 2

XC3S400 16 294912 2

XC3S1000 24 442368 2

XC3S1500 32 589824 2

XC3S2000 40 737280 2

XC3S4000 96 1769472 4

XC3S5000 104 1916928 4

DS099-2_12_030703

Spartan-3Dual Port

Block RAM

Read

Write

Read

Write

Read

Por

t A

Por

t B

21

4

DS099-2_13_091302

WEAENA

SSRACLKA

DIPA[30]

DOPA[pA 10]

DOA[wA 10]

RAM16_wA_wB

DOPB[pB 10]

DOB[wB 10]

WEBENB

SSRBCLKB

DIPB[30]

WEEN

SSRCLK

ADDR[r 10]DI[w 10]

DIP[p 10]

DOP[p 10]

DO[w 10]

RAM16_Sw

Signal Description

Port A Signal Name

Data Output Bus

Signal Description

Port A Signal Name

n = 2r (2)

Block RAM Capacity

(bits)

1 0 1 14 16384 16384

2 0 2 13 8192 16384

4 0 4 12 4096 16384

8 1 9 11 2048 18432

16 2 18 10 1024 18432

32 4 36 9 512 18432

CLK

WE

DI

ADDR

DO

EN

DISABLED READ

XXXX 1111 2222 XXXX

aa bb cc dd

0000 MEM(aa) 1111 2222 MEM(dd)

WRITEMEM(cc)=2222

DS099-2_14_030403

CLK

WE

DI

ADDR

DO

EN

DISABLED READ

XXXX 1111 2222 XXXX

aa bb cc dd

WRITEMEM(cc)=2222

DS099-2_15_030403

CLK

WE

DI

ADDR

DO

EN

DISABLED READ

XXXX 1111 2222 XXXX

aa bb cc dd

WRITEMEM(cc)=2222

DS099-2_16_030403

DS099-2_17_091302

A[170]

B[170]

P[350]MULT18X18

A[170]

B[170]

CLK

CE

RST

P[350]MULT18X18S

DS099-2_07_040103

PSINCDECPSEN

PSCLK

CLKIN

CLKFB

RSTSTATUS [70]

LOCKED8

CLKFX180

CLKFX

CLK0

PSDONE

ClockDistribution

StatusLogic

DFSDLL

PhaseShifter

Del

ay T

aps

Out

put S

tage

Inpu

t Sta

ge

DCM

DS099-2_08_041103

CLKINDelay

n

CLKFB

RST

CLK0

CLK90

CLK180

CLK270

CLK2X

CLK2X180

CLKDV

Out

put S

ectio

n

Control

Delayn-1

PhaseDetection

LOCKED

Delay2

Delay1

Mode Support

Low Frequency

High Frequency

Yes Yes

Yes No

Yes Yes

Yes No

Yes Yes

NONE 1X 2X

LOW HIGH

TRUE FALSE

15 2 25 3 35 4 45 5 55 60 65 70 75 8 9 10 11 12 13 14 15 and 16

TRUE FALSE

DS099-2_09_071003

CLK2X180

CLK0

ClockNet Delay

BUFGMUX

BUFG

FPGA

CLKIN

DCM

CLKFB

CLK2X180

CLK0

ClockNet Delay

IBUFG

FPGA

CLKIN

DCM

CLKFB

OBUFG

CLK2X

IBUFG

FPGA

CLKIN

DCM

CLKFB

OBUFG

CLK0CLK90

CLK180CLK270CLKDV

CLK2X180

CLK2X

ClockNet Delay

BUFGMUX

BUFG

FPGA

CLKIN

DCM

CLKFB

CLK0CLK90

CLK180CLK270CLKDV

CLK2X180

Phase

0o 90o 180o 270o 0o 90o 180o 270o 0o

DS099-2_10_031303

CLK2X

CLK2X180

CLKIN

CLKDV(1)

CLK0

CLK90

CLK180

CLK270

CLK0

CLK90

CLK180

CLK270

t

NONE FIXED VARIABLE

DS099-2_11_031303

CLKIN

CLKFB

TCLKINP

256

TCLKINP

256

0

ndash255 +255

CLKIN

TCLKINN

256

CLKIN

CLKFB

2 Reserved -

3 Reserved -

4 Reserved -

5 Reserved -

6 Reserved -

7 Reserved -

4

8

4

88

Horizontal Spine

Top

Spi

neB

otto

m S

pine

4

DCM DCM

Array Dependent

bull

DS099-2_18_070203

4 BUFGMUX

GCLK2GCLK3

GCLK0GCLK1

4 BUFGMUX

6 6 6 6 6

DS099-2_19_040103

(a) Long Line

8

DS099-2_20_040103

(b) Hex Line

CLB

2

CLB CLB

DS099-2_21_040103

CLBCLB CLB

DS099-2_22_040103

(d) Direct Lines

(c) Double Line

Device File Sizes

XC3S200 1047616 XCF01S XCF08P

XC3S400 1699136 XCF02S XCF08P

XC3S1000 3223488 XCF04S XCF08P

XC3S1500 5214784 XCF08P XCF08P

XC3S2000 7673024 XCF08P XCF08P

XC3S4000 11316864 XCF16P XCF16P

XC3S5000 13271936 XCF16P XCF16P

11491)

DOUTDIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Master

PROG_B

DIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Slave

PROG_B

DS099_23_041103

D0

CLK

CE

OERESET

CF

PlatformFlash PROM

XCF0xSor

XCFxxP

VCCINT

12V

VCCAUX

VCCO Bank 4

25V

47KΩAll

25V

VCCAUX VCCINT

VCCO Bank 412V

33V

VCC VCCJ

VCCO

25V

M0M1M2

GNDGNDGND

PROG_B

INIT_B

DONE

Spartan-3Slave

INIT_B

D[07]

CCLK

RDWR_B

BUSY

CS_B

PROG_B

DONE

CS_B

Spartan-3Slave

INIT_B

GND

D[07]

CCLK

RDWR_B

BUSY

CS_B

D[07]

CCLK

RDWR_B

BUSY

PROG_B

DONE

CS_B

DS099_24_041103

25V

M1M2M0

25V

M1M2M0

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

47KΩ 47KΩ

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

25V

GND

Spartan-3Master

D[07]

CCLK

PROG_B

DONE

INIT_B

DATA[07]

CCLK

RDWR_B

CS_B

CF

CE

OERESET

Platform Flash PROM

DS099_25_041103

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

GND

33V

VCC VCCJ

VCCO

25V

XCFxxP

25V

All47KΩ

Sample mode pins

No

Yes

NoCRCcorrect

YesNoReconfigure

Start-Upsequence

User mode

INIT_ B = High

PROG_B = Low

DS099_26_041103

Samplemode pins

Clearconfiguration

memory

No

Yes

No

Yes

Power-On

CRCcorrect

Shutdownsequence

Reconfigure

Start-Upsequence

User mode

INIT_B = High

PROG_B = Low

No

DS099_27_041103

Start-Up Clock

Default Cycles

Sync-to-DONE

0 1 2 3 4 5 6 7

0 1

DONE High

2 3 4 5 6 7

Phase

Start-Up Clock

Phase

DONE

GTS

GSR

GWE

DS099_028_040803

DONE

GTS

GSR

GWE

Revision History

IOBs
- IOB Overview
- ESD Protection
- - CLB Overview
    - Main Logic Paths
        
        
        
        Port Aspect Ratios
        
        
        
        
        
        
        
        
        DLL Frequency Modes
        
        
        
        
        
        
        DFS Frequency Modes
        
        
        
        Phase Shifter (PS)
        
        
        
        
        
        
        
        Interconnect
        
        Configuration
        
        
        
        Configuration Modes
        
        Slave Serial Mode
        
        Master Serial Mode
        
        Slave Parallel Mode
        
        
        
        
        Readback
        
        Revision History

Page 6: R Spartan-3 1.2V FPGA Family: Functional Description€¦ · IFF2 Q SR Fixed Delay LVCMOS, LVTTL, PCI Single-ended Standards using V REF Differential Standards REV D CE CK Q SR REV

VCCO (V)

VREF for Inputs (V)

Termination Type

For Outputs

Single-Ended

GTLP_DCI 15 15 10

None

LVDCI_18 18 18 -

LVDCI_25 25 25 -

LVDCI_33 33 33 -

LVDCI_DV2_18 18 18 -

LVDCI_DV2_25 25 25 -

LVDCI_DV2_33 33 33 -

Differential

HSTL_III_DCI_18(2)

HSTL_I_DCI_18(2)

SSTL18_I_DCI(3)

SSTL2_I_DCI(3)

SSTL2_II_DCI

Z0

IOB

R

Z0

IOB

R2

R Z0

VCCOIOB

2R

2R Z0

VCCOIOB

25Ω

2R

2R Z0

VCCOIOB

DS099-2_04_091602

VCCO

VRN

VRP

RREF (1)

DS099-2_03_060102

Bank 0 Bank 1

Bank 5 Bank 4

Ban

k 7

Ban

k 6

Ban

k 2

Ban

k 3

DS099-2_05_040703

or Shift Register)

CIN

SLICEX0Y1

SLICEX0Y0

SwitchMatrix

COUT

CLB

COUT

SHIFTOUTSHIFTIN

CIN

SLICEX1Y1

SLICEX1Y0

DeviceTotal Number

of RAM Blocks

Total Addressable

Locations (bits)

Number of

Columns

XC3S50 4 73728 1

XC3S200 12 221184 2

XC3S400 16 294912 2

XC3S1000 24 442368 2

XC3S1500 32 589824 2

XC3S2000 40 737280 2

XC3S4000 96 1769472 4

XC3S5000 104 1916928 4

DS099-2_12_030703

Spartan-3Dual Port

Block RAM

Read

Write

Read

Write

Read

Por

t A

Por

t B

21

4

DS099-2_13_091302

WEAENA

SSRACLKA

DIPA[30]

DOPA[pA 10]

DOA[wA 10]

RAM16_wA_wB

DOPB[pB 10]

DOB[wB 10]

WEBENB

SSRBCLKB

DIPB[30]

WEEN

SSRCLK

ADDR[r 10]DI[w 10]

DIP[p 10]

DOP[p 10]

DO[w 10]

RAM16_Sw

Signal Description

Port A Signal Name

Data Output Bus

Signal Description

Port A Signal Name

n = 2r (2)

Block RAM Capacity

(bits)

1 0 1 14 16384 16384

2 0 2 13 8192 16384

4 0 4 12 4096 16384

8 1 9 11 2048 18432

16 2 18 10 1024 18432

32 4 36 9 512 18432

CLK

WE

DI

ADDR

DO

EN

DISABLED READ

XXXX 1111 2222 XXXX

aa bb cc dd

0000 MEM(aa) 1111 2222 MEM(dd)

WRITEMEM(cc)=2222

DS099-2_14_030403

CLK

WE

DI

ADDR

DO

EN

DISABLED READ

XXXX 1111 2222 XXXX

aa bb cc dd

WRITEMEM(cc)=2222

DS099-2_15_030403

CLK

WE

DI

ADDR

DO

EN

DISABLED READ

XXXX 1111 2222 XXXX

aa bb cc dd

WRITEMEM(cc)=2222

DS099-2_16_030403

DS099-2_17_091302

A[170]

B[170]

P[350]MULT18X18

A[170]

B[170]

CLK

CE

RST

P[350]MULT18X18S

DS099-2_07_040103

PSINCDECPSEN

PSCLK

CLKIN

CLKFB

RSTSTATUS [70]

LOCKED8

CLKFX180

CLKFX

CLK0

PSDONE

ClockDistribution

StatusLogic

DFSDLL

PhaseShifter

Del

ay T

aps

Out

put S

tage

Inpu

t Sta

ge

DCM

DS099-2_08_041103

CLKINDelay

n

CLKFB

RST

CLK0

CLK90

CLK180

CLK270

CLK2X

CLK2X180

CLKDV

Out

put S

ectio

n

Control

Delayn-1

PhaseDetection

LOCKED

Delay2

Delay1

Mode Support

Low Frequency

High Frequency

Yes Yes

Yes No

Yes Yes

Yes No

Yes Yes

NONE 1X 2X

LOW HIGH

TRUE FALSE

15 2 25 3 35 4 45 5 55 60 65 70 75 8 9 10 11 12 13 14 15 and 16

TRUE FALSE

DS099-2_09_071003

CLK2X180

CLK0

ClockNet Delay

BUFGMUX

BUFG

FPGA

CLKIN

DCM

CLKFB

CLK2X180

CLK0

ClockNet Delay

IBUFG

FPGA

CLKIN

DCM

CLKFB

OBUFG

CLK2X

IBUFG

FPGA

CLKIN

DCM

CLKFB

OBUFG

CLK0CLK90

CLK180CLK270CLKDV

CLK2X180

CLK2X

ClockNet Delay

BUFGMUX

BUFG

FPGA

CLKIN

DCM

CLKFB

CLK0CLK90

CLK180CLK270CLKDV

CLK2X180

Phase

0o 90o 180o 270o 0o 90o 180o 270o 0o

DS099-2_10_031303

CLK2X

CLK2X180

CLKIN

CLKDV(1)

CLK0

CLK90

CLK180

CLK270

CLK0

CLK90

CLK180

CLK270

t

NONE FIXED VARIABLE

DS099-2_11_031303

CLKIN

CLKFB

TCLKINP

256

TCLKINP

256

0

ndash255 +255

CLKIN

TCLKINN

256

CLKIN

CLKFB

2 Reserved -

3 Reserved -

4 Reserved -

5 Reserved -

6 Reserved -

7 Reserved -

4

8

4

88

Horizontal Spine

Top

Spi

neB

otto

m S

pine

4

DCM DCM

Array Dependent

bull

DS099-2_18_070203

4 BUFGMUX

GCLK2GCLK3

GCLK0GCLK1

4 BUFGMUX

6 6 6 6 6

DS099-2_19_040103

(a) Long Line

8

DS099-2_20_040103

(b) Hex Line

CLB

2

CLB CLB

DS099-2_21_040103

CLBCLB CLB

DS099-2_22_040103

(d) Direct Lines

(c) Double Line

Device File Sizes

XC3S200 1047616 XCF01S XCF08P

XC3S400 1699136 XCF02S XCF08P

XC3S1000 3223488 XCF04S XCF08P

XC3S1500 5214784 XCF08P XCF08P

XC3S2000 7673024 XCF08P XCF08P

XC3S4000 11316864 XCF16P XCF16P

XC3S5000 13271936 XCF16P XCF16P

11491)

DOUTDIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Master

PROG_B

DIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Slave

PROG_B

DS099_23_041103

D0

CLK

CE

OERESET

CF

PlatformFlash PROM

XCF0xSor

XCFxxP

VCCINT

12V

VCCAUX

VCCO Bank 4

25V

47KΩAll

25V

VCCAUX VCCINT

VCCO Bank 412V

33V

VCC VCCJ

VCCO

25V

M0M1M2

GNDGNDGND

PROG_B

INIT_B

DONE

Spartan-3Slave

INIT_B

D[07]

CCLK

RDWR_B

BUSY

CS_B

PROG_B

DONE

CS_B

Spartan-3Slave

INIT_B

GND

D[07]

CCLK

RDWR_B

BUSY

CS_B

D[07]

CCLK

RDWR_B

BUSY

PROG_B

DONE

CS_B

DS099_24_041103

25V

M1M2M0

25V

M1M2M0

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

47KΩ 47KΩ

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

25V

GND

Spartan-3Master

D[07]

CCLK

PROG_B

DONE

INIT_B

DATA[07]

CCLK

RDWR_B

CS_B

CF

CE

OERESET

Platform Flash PROM

DS099_25_041103

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

GND

33V

VCC VCCJ

VCCO

25V

XCFxxP

25V

All47KΩ

Sample mode pins

No

Yes

NoCRCcorrect

YesNoReconfigure

Start-Upsequence

User mode

INIT_ B = High

PROG_B = Low

DS099_26_041103

Samplemode pins

Clearconfiguration

memory

No

Yes

No

Yes

Power-On

CRCcorrect

Shutdownsequence

Reconfigure

Start-Upsequence

User mode

INIT_B = High

PROG_B = Low

No

DS099_27_041103

Start-Up Clock

Default Cycles

Sync-to-DONE

0 1 2 3 4 5 6 7

0 1

DONE High

2 3 4 5 6 7

Phase

Start-Up Clock

Phase

DONE

GTS

GSR

GWE

DS099_028_040803

DONE

GTS

GSR

GWE

Revision History

IOBs
- IOB Overview
- ESD Protection
- - CLB Overview
    - Main Logic Paths
        
        
        
        Port Aspect Ratios
        
        
        
        
        
        
        
        
        DLL Frequency Modes
        
        
        
        
        
        
        DFS Frequency Modes
        
        
        
        Phase Shifter (PS)
        
        
        
        
        
        
        
        Interconnect
        
        Configuration
        
        
        
        Configuration Modes
        
        Slave Serial Mode
        
        Master Serial Mode
        
        Slave Parallel Mode
        
        
        
        
        Readback
        
        Revision History

Page 7: R Spartan-3 1.2V FPGA Family: Functional Description€¦ · IFF2 Q SR Fixed Delay LVCMOS, LVTTL, PCI Single-ended Standards using V REF Differential Standards REV D CE CK Q SR REV

HSTL_III_DCI_18(2)

HSTL_I_DCI_18(2)

SSTL18_I_DCI(3)

SSTL2_I_DCI(3)

SSTL2_II_DCI

Z0

IOB

R

Z0

IOB

R2

R Z0

VCCOIOB

2R

2R Z0

VCCOIOB

25Ω

2R

2R Z0

VCCOIOB

DS099-2_04_091602

VCCO

VRN

VRP

RREF (1)

DS099-2_03_060102

Bank 0 Bank 1

Bank 5 Bank 4

Ban

k 7

Ban

k 6

Ban

k 2

Ban

k 3

DS099-2_05_040703

or Shift Register)

CIN

SLICEX0Y1

SLICEX0Y0

SwitchMatrix

COUT

CLB

COUT

SHIFTOUTSHIFTIN

CIN

SLICEX1Y1

SLICEX1Y0

DeviceTotal Number

of RAM Blocks

Total Addressable

Locations (bits)

Number of

Columns

XC3S50 4 73728 1

XC3S200 12 221184 2

XC3S400 16 294912 2

XC3S1000 24 442368 2

XC3S1500 32 589824 2

XC3S2000 40 737280 2

XC3S4000 96 1769472 4

XC3S5000 104 1916928 4

DS099-2_12_030703

Spartan-3Dual Port

Block RAM

Read

Write

Read

Write

Read

Por

t A

Por

t B

21

4

DS099-2_13_091302

WEAENA

SSRACLKA

DIPA[30]

DOPA[pA 10]

DOA[wA 10]

RAM16_wA_wB

DOPB[pB 10]

DOB[wB 10]

WEBENB

SSRBCLKB

DIPB[30]

WEEN

SSRCLK

ADDR[r 10]DI[w 10]

DIP[p 10]

DOP[p 10]

DO[w 10]

RAM16_Sw

Signal Description

Port A Signal Name

Data Output Bus

Signal Description

Port A Signal Name

n = 2r (2)

Block RAM Capacity

(bits)

1 0 1 14 16384 16384

2 0 2 13 8192 16384

4 0 4 12 4096 16384

8 1 9 11 2048 18432

16 2 18 10 1024 18432

32 4 36 9 512 18432

CLK

WE

DI

ADDR

DO

EN

DISABLED READ

XXXX 1111 2222 XXXX

aa bb cc dd

0000 MEM(aa) 1111 2222 MEM(dd)

WRITEMEM(cc)=2222

DS099-2_14_030403

CLK

WE

DI

ADDR

DO

EN

DISABLED READ

XXXX 1111 2222 XXXX

aa bb cc dd

WRITEMEM(cc)=2222

DS099-2_15_030403

CLK

WE

DI

ADDR

DO

EN

DISABLED READ

XXXX 1111 2222 XXXX

aa bb cc dd

WRITEMEM(cc)=2222

DS099-2_16_030403

DS099-2_17_091302

A[170]

B[170]

P[350]MULT18X18

A[170]

B[170]

CLK

CE

RST

P[350]MULT18X18S

DS099-2_07_040103

PSINCDECPSEN

PSCLK

CLKIN

CLKFB

RSTSTATUS [70]

LOCKED8

CLKFX180

CLKFX

CLK0

PSDONE

ClockDistribution

StatusLogic

DFSDLL

PhaseShifter

Del

ay T

aps

Out

put S

tage

Inpu

t Sta

ge

DCM

DS099-2_08_041103

CLKINDelay

n

CLKFB

RST

CLK0

CLK90

CLK180

CLK270

CLK2X

CLK2X180

CLKDV

Out

put S

ectio

n

Control

Delayn-1

PhaseDetection

LOCKED

Delay2

Delay1

Mode Support

Low Frequency

High Frequency

Yes Yes

Yes No

Yes Yes

Yes No

Yes Yes

NONE 1X 2X

LOW HIGH

TRUE FALSE

15 2 25 3 35 4 45 5 55 60 65 70 75 8 9 10 11 12 13 14 15 and 16

TRUE FALSE

DS099-2_09_071003

CLK2X180

CLK0

ClockNet Delay

BUFGMUX

BUFG

FPGA

CLKIN

DCM

CLKFB

CLK2X180

CLK0

ClockNet Delay

IBUFG

FPGA

CLKIN

DCM

CLKFB

OBUFG

CLK2X

IBUFG

FPGA

CLKIN

DCM

CLKFB

OBUFG

CLK0CLK90

CLK180CLK270CLKDV

CLK2X180

CLK2X

ClockNet Delay

BUFGMUX

BUFG

FPGA

CLKIN

DCM

CLKFB

CLK0CLK90

CLK180CLK270CLKDV

CLK2X180

Phase

0o 90o 180o 270o 0o 90o 180o 270o 0o

DS099-2_10_031303

CLK2X

CLK2X180

CLKIN

CLKDV(1)

CLK0

CLK90

CLK180

CLK270

CLK0

CLK90

CLK180

CLK270

t

NONE FIXED VARIABLE

DS099-2_11_031303

CLKIN

CLKFB

TCLKINP

256

TCLKINP

256

0

ndash255 +255

CLKIN

TCLKINN

256

CLKIN

CLKFB

2 Reserved -

3 Reserved -

4 Reserved -

5 Reserved -

6 Reserved -

7 Reserved -

4

8

4

88

Horizontal Spine

Top

Spi

neB

otto

m S

pine

4

DCM DCM

Array Dependent

bull

DS099-2_18_070203

4 BUFGMUX

GCLK2GCLK3

GCLK0GCLK1

4 BUFGMUX

6 6 6 6 6

DS099-2_19_040103

(a) Long Line

8

DS099-2_20_040103

(b) Hex Line

CLB

2

CLB CLB

DS099-2_21_040103

CLBCLB CLB

DS099-2_22_040103

(d) Direct Lines

(c) Double Line

Device File Sizes

XC3S200 1047616 XCF01S XCF08P

XC3S400 1699136 XCF02S XCF08P

XC3S1000 3223488 XCF04S XCF08P

XC3S1500 5214784 XCF08P XCF08P

XC3S2000 7673024 XCF08P XCF08P

XC3S4000 11316864 XCF16P XCF16P

XC3S5000 13271936 XCF16P XCF16P

11491)

DOUTDIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Master

PROG_B

DIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Slave

PROG_B

DS099_23_041103

D0

CLK

CE

OERESET

CF

PlatformFlash PROM

XCF0xSor

XCFxxP

VCCINT

12V

VCCAUX

VCCO Bank 4

25V

47KΩAll

25V

VCCAUX VCCINT

VCCO Bank 412V

33V

VCC VCCJ

VCCO

25V

M0M1M2

GNDGNDGND

PROG_B

INIT_B

DONE

Spartan-3Slave

INIT_B

D[07]

CCLK

RDWR_B

BUSY

CS_B

PROG_B

DONE

CS_B

Spartan-3Slave

INIT_B

GND

D[07]

CCLK

RDWR_B

BUSY

CS_B

D[07]

CCLK

RDWR_B

BUSY

PROG_B

DONE

CS_B

DS099_24_041103

25V

M1M2M0

25V

M1M2M0

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

47KΩ 47KΩ

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

25V

GND

Spartan-3Master

D[07]

CCLK

PROG_B

DONE

INIT_B

DATA[07]

CCLK

RDWR_B

CS_B

CF

CE

OERESET

Platform Flash PROM

DS099_25_041103

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

GND

33V

VCC VCCJ

VCCO

25V

XCFxxP

25V

All47KΩ

Sample mode pins

No

Yes

NoCRCcorrect

YesNoReconfigure

Start-Upsequence

User mode

INIT_ B = High

PROG_B = Low

DS099_26_041103

Samplemode pins

Clearconfiguration

memory

No

Yes

No

Yes

Power-On

CRCcorrect

Shutdownsequence

Reconfigure

Start-Upsequence

User mode

INIT_B = High

PROG_B = Low

No

DS099_27_041103

Start-Up Clock

Default Cycles

Sync-to-DONE

0 1 2 3 4 5 6 7

0 1

DONE High

2 3 4 5 6 7

Phase

Start-Up Clock

Phase

DONE

GTS

GSR

GWE

DS099_028_040803

DONE

GTS

GSR

GWE

Revision History

IOBs
- IOB Overview
- ESD Protection
- - CLB Overview
    - Main Logic Paths
        
        
        
        Port Aspect Ratios
        
        
        
        
        
        
        
        
        DLL Frequency Modes
        
        
        
        
        
        
        DFS Frequency Modes
        
        
        
        Phase Shifter (PS)
        
        
        
        
        
        
        
        Interconnect
        
        Configuration
        
        
        
        Configuration Modes
        
        Slave Serial Mode
        
        Master Serial Mode
        
        Slave Parallel Mode
        
        
        
        
        Readback
        
        Revision History

Page 8: R Spartan-3 1.2V FPGA Family: Functional Description€¦ · IFF2 Q SR Fixed Delay LVCMOS, LVTTL, PCI Single-ended Standards using V REF Differential Standards REV D CE CK Q SR REV

DS099-2_04_091602

VCCO

VRN

VRP

RREF (1)

DS099-2_03_060102

Bank 0 Bank 1

Bank 5 Bank 4

Ban

k 7

Ban

k 6

Ban

k 2

Ban

k 3

DS099-2_05_040703

or Shift Register)

CIN

SLICEX0Y1

SLICEX0Y0

SwitchMatrix

COUT

CLB

COUT

SHIFTOUTSHIFTIN

CIN

SLICEX1Y1

SLICEX1Y0

DeviceTotal Number

of RAM Blocks

Total Addressable

Locations (bits)

Number of

Columns

XC3S50 4 73728 1

XC3S200 12 221184 2

XC3S400 16 294912 2

XC3S1000 24 442368 2

XC3S1500 32 589824 2

XC3S2000 40 737280 2

XC3S4000 96 1769472 4

XC3S5000 104 1916928 4

DS099-2_12_030703

Spartan-3Dual Port

Block RAM

Read

Write

Read

Write

Read

Por

t A

Por

t B

21

4

DS099-2_13_091302

WEAENA

SSRACLKA

DIPA[30]

DOPA[pA 10]

DOA[wA 10]

RAM16_wA_wB

DOPB[pB 10]

DOB[wB 10]

WEBENB

SSRBCLKB

DIPB[30]

WEEN

SSRCLK

ADDR[r 10]DI[w 10]

DIP[p 10]

DOP[p 10]

DO[w 10]

RAM16_Sw

Signal Description

Port A Signal Name

Data Output Bus

Signal Description

Port A Signal Name

n = 2r (2)

Block RAM Capacity

(bits)

1 0 1 14 16384 16384

2 0 2 13 8192 16384

4 0 4 12 4096 16384

8 1 9 11 2048 18432

16 2 18 10 1024 18432

32 4 36 9 512 18432

CLK

WE

DI

ADDR

DO

EN

DISABLED READ

XXXX 1111 2222 XXXX

aa bb cc dd

0000 MEM(aa) 1111 2222 MEM(dd)

WRITEMEM(cc)=2222

DS099-2_14_030403

CLK

WE

DI

ADDR

DO

EN

DISABLED READ

XXXX 1111 2222 XXXX

aa bb cc dd

WRITEMEM(cc)=2222

DS099-2_15_030403

CLK

WE

DI

ADDR

DO

EN

DISABLED READ

XXXX 1111 2222 XXXX

aa bb cc dd

WRITEMEM(cc)=2222

DS099-2_16_030403

DS099-2_17_091302

A[170]

B[170]

P[350]MULT18X18

A[170]

B[170]

CLK

CE

RST

P[350]MULT18X18S

DS099-2_07_040103

PSINCDECPSEN

PSCLK

CLKIN

CLKFB

RSTSTATUS [70]

LOCKED8

CLKFX180

CLKFX

CLK0

PSDONE

ClockDistribution

StatusLogic

DFSDLL

PhaseShifter

Del

ay T

aps

Out

put S

tage

Inpu

t Sta

ge

DCM

DS099-2_08_041103

CLKINDelay

n

CLKFB

RST

CLK0

CLK90

CLK180

CLK270

CLK2X

CLK2X180

CLKDV

Out

put S

ectio

n

Control

Delayn-1

PhaseDetection

LOCKED

Delay2

Delay1

Mode Support

Low Frequency

High Frequency

Yes Yes

Yes No

Yes Yes

Yes No

Yes Yes

NONE 1X 2X

LOW HIGH

TRUE FALSE

15 2 25 3 35 4 45 5 55 60 65 70 75 8 9 10 11 12 13 14 15 and 16

TRUE FALSE

DS099-2_09_071003

CLK2X180

CLK0

ClockNet Delay

BUFGMUX

BUFG

FPGA

CLKIN

DCM

CLKFB

CLK2X180

CLK0

ClockNet Delay

IBUFG

FPGA

CLKIN

DCM

CLKFB

OBUFG

CLK2X

IBUFG

FPGA

CLKIN

DCM

CLKFB

OBUFG

CLK0CLK90

CLK180CLK270CLKDV

CLK2X180

CLK2X

ClockNet Delay

BUFGMUX

BUFG

FPGA

CLKIN

DCM

CLKFB

CLK0CLK90

CLK180CLK270CLKDV

CLK2X180

Phase

0o 90o 180o 270o 0o 90o 180o 270o 0o

DS099-2_10_031303

CLK2X

CLK2X180

CLKIN

CLKDV(1)

CLK0

CLK90

CLK180

CLK270

CLK0

CLK90

CLK180

CLK270

t

NONE FIXED VARIABLE

DS099-2_11_031303

CLKIN

CLKFB

TCLKINP

256

TCLKINP

256

0

ndash255 +255

CLKIN

TCLKINN

256

CLKIN

CLKFB

2 Reserved -

3 Reserved -

4 Reserved -

5 Reserved -

6 Reserved -

7 Reserved -

4

8

4

88

Horizontal Spine

Top

Spi

neB

otto

m S

pine

4

DCM DCM

Array Dependent

bull

DS099-2_18_070203

4 BUFGMUX

GCLK2GCLK3

GCLK0GCLK1

4 BUFGMUX

6 6 6 6 6

DS099-2_19_040103

(a) Long Line

8

DS099-2_20_040103

(b) Hex Line

CLB

2

CLB CLB

DS099-2_21_040103

CLBCLB CLB

DS099-2_22_040103

(d) Direct Lines

(c) Double Line

Device File Sizes

XC3S200 1047616 XCF01S XCF08P

XC3S400 1699136 XCF02S XCF08P

XC3S1000 3223488 XCF04S XCF08P

XC3S1500 5214784 XCF08P XCF08P

XC3S2000 7673024 XCF08P XCF08P

XC3S4000 11316864 XCF16P XCF16P

XC3S5000 13271936 XCF16P XCF16P

11491)

DOUTDIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Master

PROG_B

DIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Slave

PROG_B

DS099_23_041103

D0

CLK

CE

OERESET

CF

PlatformFlash PROM

XCF0xSor

XCFxxP

VCCINT

12V

VCCAUX

VCCO Bank 4

25V

47KΩAll

25V

VCCAUX VCCINT

VCCO Bank 412V

33V

VCC VCCJ

VCCO

25V

M0M1M2

GNDGNDGND

PROG_B

INIT_B

DONE

Spartan-3Slave

INIT_B

D[07]

CCLK

RDWR_B

BUSY

CS_B

PROG_B

DONE

CS_B

Spartan-3Slave

INIT_B

GND

D[07]

CCLK

RDWR_B

BUSY

CS_B

D[07]

CCLK

RDWR_B

BUSY

PROG_B

DONE

CS_B

DS099_24_041103

25V

M1M2M0

25V

M1M2M0

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

47KΩ 47KΩ

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

25V

GND

Spartan-3Master

D[07]

CCLK

PROG_B

DONE

INIT_B

DATA[07]

CCLK

RDWR_B

CS_B

CF

CE

OERESET

Platform Flash PROM

DS099_25_041103

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

GND

33V

VCC VCCJ

VCCO

25V

XCFxxP

25V

All47KΩ

Sample mode pins

No

Yes

NoCRCcorrect

YesNoReconfigure

Start-Upsequence

User mode

INIT_ B = High

PROG_B = Low

DS099_26_041103

Samplemode pins

Clearconfiguration

memory

No

Yes

No

Yes

Power-On

CRCcorrect

Shutdownsequence

Reconfigure

Start-Upsequence

User mode

INIT_B = High

PROG_B = Low

No

DS099_27_041103

Start-Up Clock

Default Cycles

Sync-to-DONE

0 1 2 3 4 5 6 7

0 1

DONE High

2 3 4 5 6 7

Phase

Start-Up Clock

Phase

DONE

GTS

GSR

GWE

DS099_028_040803

DONE

GTS

GSR

GWE

Revision History

IOBs
- IOB Overview
- ESD Protection
- - CLB Overview
    - Main Logic Paths
        
        
        
        Port Aspect Ratios
        
        
        
        
        
        
        
        
        DLL Frequency Modes
        
        
        
        
        
        
        DFS Frequency Modes
        
        
        
        Phase Shifter (PS)
        
        
        
        
        
        
        
        Interconnect
        
        Configuration
        
        
        
        Configuration Modes
        
        Slave Serial Mode
        
        Master Serial Mode
        
        Slave Parallel Mode
        
        
        
        
        Readback
        
        Revision History

Page 9: R Spartan-3 1.2V FPGA Family: Functional Description€¦ · IFF2 Q SR Fixed Delay LVCMOS, LVTTL, PCI Single-ended Standards using V REF Differential Standards REV D CE CK Q SR REV

DS099-2_05_040703

or Shift Register)

CIN

SLICEX0Y1

SLICEX0Y0

SwitchMatrix

COUT

CLB

COUT

SHIFTOUTSHIFTIN

CIN

SLICEX1Y1

SLICEX1Y0

DeviceTotal Number

of RAM Blocks

Total Addressable

Locations (bits)

Number of

Columns

XC3S50 4 73728 1

XC3S200 12 221184 2

XC3S400 16 294912 2

XC3S1000 24 442368 2

XC3S1500 32 589824 2

XC3S2000 40 737280 2

XC3S4000 96 1769472 4

XC3S5000 104 1916928 4

DS099-2_12_030703

Spartan-3Dual Port

Block RAM

Read

Write

Read

Write

Read

Por

t A

Por

t B

21

4

DS099-2_13_091302

WEAENA

SSRACLKA

DIPA[30]

DOPA[pA 10]

DOA[wA 10]

RAM16_wA_wB

DOPB[pB 10]

DOB[wB 10]

WEBENB

SSRBCLKB

DIPB[30]

WEEN

SSRCLK

ADDR[r 10]DI[w 10]

DIP[p 10]

DOP[p 10]

DO[w 10]

RAM16_Sw

Signal Description

Port A Signal Name

Data Output Bus

Signal Description

Port A Signal Name

n = 2r (2)

Block RAM Capacity

(bits)

1 0 1 14 16384 16384

2 0 2 13 8192 16384

4 0 4 12 4096 16384

8 1 9 11 2048 18432

16 2 18 10 1024 18432

32 4 36 9 512 18432

CLK

WE

DI

ADDR

DO

EN

DISABLED READ

XXXX 1111 2222 XXXX

aa bb cc dd

0000 MEM(aa) 1111 2222 MEM(dd)

WRITEMEM(cc)=2222

DS099-2_14_030403

CLK

WE

DI

ADDR

DO

EN

DISABLED READ

XXXX 1111 2222 XXXX

aa bb cc dd

WRITEMEM(cc)=2222

DS099-2_15_030403

CLK

WE

DI

ADDR

DO

EN

DISABLED READ

XXXX 1111 2222 XXXX

aa bb cc dd

WRITEMEM(cc)=2222

DS099-2_16_030403

DS099-2_17_091302

A[170]

B[170]

P[350]MULT18X18

A[170]

B[170]

CLK

CE

RST

P[350]MULT18X18S

DS099-2_07_040103

PSINCDECPSEN

PSCLK

CLKIN

CLKFB

RSTSTATUS [70]

LOCKED8

CLKFX180

CLKFX

CLK0

PSDONE

ClockDistribution

StatusLogic

DFSDLL

PhaseShifter

Del

ay T

aps

Out

put S

tage

Inpu

t Sta

ge

DCM

DS099-2_08_041103

CLKINDelay

n

CLKFB

RST

CLK0

CLK90

CLK180

CLK270

CLK2X

CLK2X180

CLKDV

Out

put S

ectio

n

Control

Delayn-1

PhaseDetection

LOCKED

Delay2

Delay1

Mode Support

Low Frequency

High Frequency

Yes Yes

Yes No

Yes Yes

Yes No

Yes Yes

NONE 1X 2X

LOW HIGH

TRUE FALSE

15 2 25 3 35 4 45 5 55 60 65 70 75 8 9 10 11 12 13 14 15 and 16

TRUE FALSE

DS099-2_09_071003

CLK2X180

CLK0

ClockNet Delay

BUFGMUX

BUFG

FPGA

CLKIN

DCM

CLKFB

CLK2X180

CLK0

ClockNet Delay

IBUFG

FPGA

CLKIN

DCM

CLKFB

OBUFG

CLK2X

IBUFG

FPGA

CLKIN

DCM

CLKFB

OBUFG

CLK0CLK90

CLK180CLK270CLKDV

CLK2X180

CLK2X

ClockNet Delay

BUFGMUX

BUFG

FPGA

CLKIN

DCM

CLKFB

CLK0CLK90

CLK180CLK270CLKDV

CLK2X180

Phase

0o 90o 180o 270o 0o 90o 180o 270o 0o

DS099-2_10_031303

CLK2X

CLK2X180

CLKIN

CLKDV(1)

CLK0

CLK90

CLK180

CLK270

CLK0

CLK90

CLK180

CLK270

t

NONE FIXED VARIABLE

DS099-2_11_031303

CLKIN

CLKFB

TCLKINP

256

TCLKINP

256

0

ndash255 +255

CLKIN

TCLKINN

256

CLKIN

CLKFB

2 Reserved -

3 Reserved -

4 Reserved -

5 Reserved -

6 Reserved -

7 Reserved -

4

8

4

88

Horizontal Spine

Top

Spi

neB

otto

m S

pine

4

DCM DCM

Array Dependent

bull

DS099-2_18_070203

4 BUFGMUX

GCLK2GCLK3

GCLK0GCLK1

4 BUFGMUX

6 6 6 6 6

DS099-2_19_040103

(a) Long Line

8

DS099-2_20_040103

(b) Hex Line

CLB

2

CLB CLB

DS099-2_21_040103

CLBCLB CLB

DS099-2_22_040103

(d) Direct Lines

(c) Double Line

Device File Sizes

XC3S200 1047616 XCF01S XCF08P

XC3S400 1699136 XCF02S XCF08P

XC3S1000 3223488 XCF04S XCF08P

XC3S1500 5214784 XCF08P XCF08P

XC3S2000 7673024 XCF08P XCF08P

XC3S4000 11316864 XCF16P XCF16P

XC3S5000 13271936 XCF16P XCF16P

11491)

DOUTDIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Master

PROG_B

DIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Slave

PROG_B

DS099_23_041103

D0

CLK

CE

OERESET

CF

PlatformFlash PROM

XCF0xSor

XCFxxP

VCCINT

12V

VCCAUX

VCCO Bank 4

25V

47KΩAll

25V

VCCAUX VCCINT

VCCO Bank 412V

33V

VCC VCCJ

VCCO

25V

M0M1M2

GNDGNDGND

PROG_B

INIT_B

DONE

Spartan-3Slave

INIT_B

D[07]

CCLK

RDWR_B

BUSY

CS_B

PROG_B

DONE

CS_B

Spartan-3Slave

INIT_B

GND

D[07]

CCLK

RDWR_B

BUSY

CS_B

D[07]

CCLK

RDWR_B

BUSY

PROG_B

DONE

CS_B

DS099_24_041103

25V

M1M2M0

25V

M1M2M0

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

47KΩ 47KΩ

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

25V

GND

Spartan-3Master

D[07]

CCLK

PROG_B

DONE

INIT_B

DATA[07]

CCLK

RDWR_B

CS_B

CF

CE

OERESET

Platform Flash PROM

DS099_25_041103

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

GND

33V

VCC VCCJ

VCCO

25V

XCFxxP

25V

All47KΩ

Sample mode pins

No

Yes

NoCRCcorrect

YesNoReconfigure

Start-Upsequence

User mode

INIT_ B = High

PROG_B = Low

DS099_26_041103

Samplemode pins

Clearconfiguration

memory

No

Yes

No

Yes

Power-On

CRCcorrect

Shutdownsequence

Reconfigure

Start-Upsequence

User mode

INIT_B = High

PROG_B = Low

No

DS099_27_041103

Start-Up Clock

Default Cycles

Sync-to-DONE

0 1 2 3 4 5 6 7

0 1

DONE High

2 3 4 5 6 7

Phase

Start-Up Clock

Phase

DONE

GTS

GSR

GWE

DS099_028_040803

DONE

GTS

GSR

GWE

Revision History

IOBs
- IOB Overview
- ESD Protection
- - CLB Overview
    - Main Logic Paths
        
        
        
        Port Aspect Ratios
        
        
        
        
        
        
        
        
        DLL Frequency Modes
        
        
        
        
        
        
        DFS Frequency Modes
        
        
        
        Phase Shifter (PS)
        
        
        
        
        
        
        
        Interconnect
        
        Configuration
        
        
        
        Configuration Modes
        
        Slave Serial Mode
        
        Master Serial Mode
        
        Slave Parallel Mode
        
        
        
        
        Readback
        
        Revision History

Page 10: R Spartan-3 1.2V FPGA Family: Functional Description€¦ · IFF2 Q SR Fixed Delay LVCMOS, LVTTL, PCI Single-ended Standards using V REF Differential Standards REV D CE CK Q SR REV

DS099-2_05_040703

or Shift Register)

CIN

SLICEX0Y1

SLICEX0Y0

SwitchMatrix

COUT

CLB

COUT

SHIFTOUTSHIFTIN

CIN

SLICEX1Y1

SLICEX1Y0

DeviceTotal Number

of RAM Blocks

Total Addressable

Locations (bits)

Number of

Columns

XC3S50 4 73728 1

XC3S200 12 221184 2

XC3S400 16 294912 2

XC3S1000 24 442368 2

XC3S1500 32 589824 2

XC3S2000 40 737280 2

XC3S4000 96 1769472 4

XC3S5000 104 1916928 4

DS099-2_12_030703

Spartan-3Dual Port

Block RAM

Read

Write

Read

Write

Read

Por

t A

Por

t B

21

4

DS099-2_13_091302

WEAENA

SSRACLKA

DIPA[30]

DOPA[pA 10]

DOA[wA 10]

RAM16_wA_wB

DOPB[pB 10]

DOB[wB 10]

WEBENB

SSRBCLKB

DIPB[30]

WEEN

SSRCLK

ADDR[r 10]DI[w 10]

DIP[p 10]

DOP[p 10]

DO[w 10]

RAM16_Sw

Signal Description

Port A Signal Name

Data Output Bus

Signal Description

Port A Signal Name

n = 2r (2)

Block RAM Capacity

(bits)

1 0 1 14 16384 16384

2 0 2 13 8192 16384

4 0 4 12 4096 16384

8 1 9 11 2048 18432

16 2 18 10 1024 18432

32 4 36 9 512 18432

CLK

WE

DI

ADDR

DO

EN

DISABLED READ

XXXX 1111 2222 XXXX

aa bb cc dd

0000 MEM(aa) 1111 2222 MEM(dd)

WRITEMEM(cc)=2222

DS099-2_14_030403

CLK

WE

DI

ADDR

DO

EN

DISABLED READ

XXXX 1111 2222 XXXX

aa bb cc dd

WRITEMEM(cc)=2222

DS099-2_15_030403

CLK

WE

DI

ADDR

DO

EN

DISABLED READ

XXXX 1111 2222 XXXX

aa bb cc dd

WRITEMEM(cc)=2222

DS099-2_16_030403

DS099-2_17_091302

A[170]

B[170]

P[350]MULT18X18

A[170]

B[170]

CLK

CE

RST

P[350]MULT18X18S

DS099-2_07_040103

PSINCDECPSEN

PSCLK

CLKIN

CLKFB

RSTSTATUS [70]

LOCKED8

CLKFX180

CLKFX

CLK0

PSDONE

ClockDistribution

StatusLogic

DFSDLL

PhaseShifter

Del

ay T

aps

Out

put S

tage

Inpu

t Sta

ge

DCM

DS099-2_08_041103

CLKINDelay

n

CLKFB

RST

CLK0

CLK90

CLK180

CLK270

CLK2X

CLK2X180

CLKDV

Out

put S

ectio

n

Control

Delayn-1

PhaseDetection

LOCKED

Delay2

Delay1

Mode Support

Low Frequency

High Frequency

Yes Yes

Yes No

Yes Yes

Yes No

Yes Yes

NONE 1X 2X

LOW HIGH

TRUE FALSE

15 2 25 3 35 4 45 5 55 60 65 70 75 8 9 10 11 12 13 14 15 and 16

TRUE FALSE

DS099-2_09_071003

CLK2X180

CLK0

ClockNet Delay

BUFGMUX

BUFG

FPGA

CLKIN

DCM

CLKFB

CLK2X180

CLK0

ClockNet Delay

IBUFG

FPGA

CLKIN

DCM

CLKFB

OBUFG

CLK2X

IBUFG

FPGA

CLKIN

DCM

CLKFB

OBUFG

CLK0CLK90

CLK180CLK270CLKDV

CLK2X180

CLK2X

ClockNet Delay

BUFGMUX

BUFG

FPGA

CLKIN

DCM

CLKFB

CLK0CLK90

CLK180CLK270CLKDV

CLK2X180

Phase

0o 90o 180o 270o 0o 90o 180o 270o 0o

DS099-2_10_031303

CLK2X

CLK2X180

CLKIN

CLKDV(1)

CLK0

CLK90

CLK180

CLK270

CLK0

CLK90

CLK180

CLK270

t

NONE FIXED VARIABLE

DS099-2_11_031303

CLKIN

CLKFB

TCLKINP

256

TCLKINP

256

0

ndash255 +255

CLKIN

TCLKINN

256

CLKIN

CLKFB

2 Reserved -

3 Reserved -

4 Reserved -

5 Reserved -

6 Reserved -

7 Reserved -

4

8

4

88

Horizontal Spine

Top

Spi

neB

otto

m S

pine

4

DCM DCM

Array Dependent

bull

DS099-2_18_070203

4 BUFGMUX

GCLK2GCLK3

GCLK0GCLK1

4 BUFGMUX

6 6 6 6 6

DS099-2_19_040103

(a) Long Line

8

DS099-2_20_040103

(b) Hex Line

CLB

2

CLB CLB

DS099-2_21_040103

CLBCLB CLB

DS099-2_22_040103

(d) Direct Lines

(c) Double Line

Device File Sizes

XC3S200 1047616 XCF01S XCF08P

XC3S400 1699136 XCF02S XCF08P

XC3S1000 3223488 XCF04S XCF08P

XC3S1500 5214784 XCF08P XCF08P

XC3S2000 7673024 XCF08P XCF08P

XC3S4000 11316864 XCF16P XCF16P

XC3S5000 13271936 XCF16P XCF16P

11491)

DOUTDIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Master

PROG_B

DIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Slave

PROG_B

DS099_23_041103

D0

CLK

CE

OERESET

CF

PlatformFlash PROM

XCF0xSor

XCFxxP

VCCINT

12V

VCCAUX

VCCO Bank 4

25V

47KΩAll

25V

VCCAUX VCCINT

VCCO Bank 412V

33V

VCC VCCJ

VCCO

25V

M0M1M2

GNDGNDGND

PROG_B

INIT_B

DONE

Spartan-3Slave

INIT_B

D[07]

CCLK

RDWR_B

BUSY

CS_B

PROG_B

DONE

CS_B

Spartan-3Slave

INIT_B

GND

D[07]

CCLK

RDWR_B

BUSY

CS_B

D[07]

CCLK

RDWR_B

BUSY

PROG_B

DONE

CS_B

DS099_24_041103

25V

M1M2M0

25V

M1M2M0

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

47KΩ 47KΩ

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

25V

GND

Spartan-3Master

D[07]

CCLK

PROG_B

DONE

INIT_B

DATA[07]

CCLK

RDWR_B

CS_B

CF

CE

OERESET

Platform Flash PROM

DS099_25_041103

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

GND

33V

VCC VCCJ

VCCO

25V

XCFxxP

25V

All47KΩ

Sample mode pins

No

Yes

NoCRCcorrect

YesNoReconfigure

Start-Upsequence

User mode

INIT_ B = High

PROG_B = Low

DS099_26_041103

Samplemode pins

Clearconfiguration

memory

No

Yes

No

Yes

Power-On

CRCcorrect

Shutdownsequence

Reconfigure

Start-Upsequence

User mode

INIT_B = High

PROG_B = Low

No

DS099_27_041103

Start-Up Clock

Default Cycles

Sync-to-DONE

0 1 2 3 4 5 6 7

0 1

DONE High

2 3 4 5 6 7

Phase

Start-Up Clock

Phase

DONE

GTS

GSR

GWE

DS099_028_040803

DONE

GTS

GSR

GWE

Revision History

IOBs
- IOB Overview
- ESD Protection
- - CLB Overview
    - Main Logic Paths
        
        
        
        Port Aspect Ratios
        
        
        
        
        
        
        
        
        DLL Frequency Modes
        
        
        
        
        
        
        DFS Frequency Modes
        
        
        
        Phase Shifter (PS)
        
        
        
        
        
        
        
        Interconnect
        
        Configuration
        
        
        
        Configuration Modes
        
        Slave Serial Mode
        
        Master Serial Mode
        
        Slave Parallel Mode
        
        
        
        
        Readback
        
        Revision History

Page 11: R Spartan-3 1.2V FPGA Family: Functional Description€¦ · IFF2 Q SR Fixed Delay LVCMOS, LVTTL, PCI Single-ended Standards using V REF Differential Standards REV D CE CK Q SR REV

DeviceTotal Number

of RAM Blocks

Total Addressable

Locations (bits)

Number of

Columns

XC3S50 4 73728 1

XC3S200 12 221184 2

XC3S400 16 294912 2

XC3S1000 24 442368 2

XC3S1500 32 589824 2

XC3S2000 40 737280 2

XC3S4000 96 1769472 4

XC3S5000 104 1916928 4

DS099-2_12_030703

Spartan-3Dual Port

Block RAM

Read

Write

Read

Write

Read

Por

t A

Por

t B

21

4

DS099-2_13_091302

WEAENA

SSRACLKA

DIPA[30]

DOPA[pA 10]

DOA[wA 10]

RAM16_wA_wB

DOPB[pB 10]

DOB[wB 10]

WEBENB

SSRBCLKB

DIPB[30]

WEEN

SSRCLK

ADDR[r 10]DI[w 10]

DIP[p 10]

DOP[p 10]

DO[w 10]

RAM16_Sw

Signal Description

Port A Signal Name

Data Output Bus

Signal Description

Port A Signal Name

n = 2r (2)

Block RAM Capacity

(bits)

1 0 1 14 16384 16384

2 0 2 13 8192 16384

4 0 4 12 4096 16384

8 1 9 11 2048 18432

16 2 18 10 1024 18432

32 4 36 9 512 18432

CLK

WE

DI

ADDR

DO

EN

DISABLED READ

XXXX 1111 2222 XXXX

aa bb cc dd

0000 MEM(aa) 1111 2222 MEM(dd)

WRITEMEM(cc)=2222

DS099-2_14_030403

CLK

WE

DI

ADDR

DO

EN

DISABLED READ

XXXX 1111 2222 XXXX

aa bb cc dd

WRITEMEM(cc)=2222

DS099-2_15_030403

CLK

WE

DI

ADDR

DO

EN

DISABLED READ

XXXX 1111 2222 XXXX

aa bb cc dd

WRITEMEM(cc)=2222

DS099-2_16_030403

DS099-2_17_091302

A[170]

B[170]

P[350]MULT18X18

A[170]

B[170]

CLK

CE

RST

P[350]MULT18X18S

DS099-2_07_040103

PSINCDECPSEN

PSCLK

CLKIN

CLKFB

RSTSTATUS [70]

LOCKED8

CLKFX180

CLKFX

CLK0

PSDONE

ClockDistribution

StatusLogic

DFSDLL

PhaseShifter

Del

ay T

aps

Out

put S

tage

Inpu

t Sta

ge

DCM

DS099-2_08_041103

CLKINDelay

n

CLKFB

RST

CLK0

CLK90

CLK180

CLK270

CLK2X

CLK2X180

CLKDV

Out

put S

ectio

n

Control

Delayn-1

PhaseDetection

LOCKED

Delay2

Delay1

Mode Support

Low Frequency

High Frequency

Yes Yes

Yes No

Yes Yes

Yes No

Yes Yes

NONE 1X 2X

LOW HIGH

TRUE FALSE

15 2 25 3 35 4 45 5 55 60 65 70 75 8 9 10 11 12 13 14 15 and 16

TRUE FALSE

DS099-2_09_071003

CLK2X180

CLK0

ClockNet Delay

BUFGMUX

BUFG

FPGA

CLKIN

DCM

CLKFB

CLK2X180

CLK0

ClockNet Delay

IBUFG

FPGA

CLKIN

DCM

CLKFB

OBUFG

CLK2X

IBUFG

FPGA

CLKIN

DCM

CLKFB

OBUFG

CLK0CLK90

CLK180CLK270CLKDV

CLK2X180

CLK2X

ClockNet Delay

BUFGMUX

BUFG

FPGA

CLKIN

DCM

CLKFB

CLK0CLK90

CLK180CLK270CLKDV

CLK2X180

Phase

0o 90o 180o 270o 0o 90o 180o 270o 0o

DS099-2_10_031303

CLK2X

CLK2X180

CLKIN

CLKDV(1)

CLK0

CLK90

CLK180

CLK270

CLK0

CLK90

CLK180

CLK270

t

NONE FIXED VARIABLE

DS099-2_11_031303

CLKIN

CLKFB

TCLKINP

256

TCLKINP

256

0

ndash255 +255

CLKIN

TCLKINN

256

CLKIN

CLKFB

2 Reserved -

3 Reserved -

4 Reserved -

5 Reserved -

6 Reserved -

7 Reserved -

4

8

4

88

Horizontal Spine

Top

Spi

neB

otto

m S

pine

4

DCM DCM

Array Dependent

bull

DS099-2_18_070203

4 BUFGMUX

GCLK2GCLK3

GCLK0GCLK1

4 BUFGMUX

6 6 6 6 6

DS099-2_19_040103

(a) Long Line

8

DS099-2_20_040103

(b) Hex Line

CLB

2

CLB CLB

DS099-2_21_040103

CLBCLB CLB

DS099-2_22_040103

(d) Direct Lines

(c) Double Line

Device File Sizes

XC3S200 1047616 XCF01S XCF08P

XC3S400 1699136 XCF02S XCF08P

XC3S1000 3223488 XCF04S XCF08P

XC3S1500 5214784 XCF08P XCF08P

XC3S2000 7673024 XCF08P XCF08P

XC3S4000 11316864 XCF16P XCF16P

XC3S5000 13271936 XCF16P XCF16P

11491)

DOUTDIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Master

PROG_B

DIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Slave

PROG_B

DS099_23_041103

D0

CLK

CE

OERESET

CF

PlatformFlash PROM

XCF0xSor

XCFxxP

VCCINT

12V

VCCAUX

VCCO Bank 4

25V

47KΩAll

25V

VCCAUX VCCINT

VCCO Bank 412V

33V

VCC VCCJ

VCCO

25V

M0M1M2

GNDGNDGND

PROG_B

INIT_B

DONE

Spartan-3Slave

INIT_B

D[07]

CCLK

RDWR_B

BUSY

CS_B

PROG_B

DONE

CS_B

Spartan-3Slave

INIT_B

GND

D[07]

CCLK

RDWR_B

BUSY

CS_B

D[07]

CCLK

RDWR_B

BUSY

PROG_B

DONE

CS_B

DS099_24_041103

25V

M1M2M0

25V

M1M2M0

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

47KΩ 47KΩ

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

25V

GND

Spartan-3Master

D[07]

CCLK

PROG_B

DONE

INIT_B

DATA[07]

CCLK

RDWR_B

CS_B

CF

CE

OERESET

Platform Flash PROM

DS099_25_041103

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

GND

33V

VCC VCCJ

VCCO

25V

XCFxxP

25V

All47KΩ

Sample mode pins

No

Yes

NoCRCcorrect

YesNoReconfigure

Start-Upsequence

User mode

INIT_ B = High

PROG_B = Low

DS099_26_041103

Samplemode pins

Clearconfiguration

memory

No

Yes

No

Yes

Power-On

CRCcorrect

Shutdownsequence

Reconfigure

Start-Upsequence

User mode

INIT_B = High

PROG_B = Low

No

DS099_27_041103

Start-Up Clock

Default Cycles

Sync-to-DONE

0 1 2 3 4 5 6 7

0 1

DONE High

2 3 4 5 6 7

Phase

Start-Up Clock

Phase

DONE

GTS

GSR

GWE

DS099_028_040803

DONE

GTS

GSR

GWE

Revision History

IOBs
- IOB Overview
- ESD Protection
- - CLB Overview
    - Main Logic Paths
        
        
        
        Port Aspect Ratios
        
        
        
        
        
        
        
        
        DLL Frequency Modes
        
        
        
        
        
        
        DFS Frequency Modes
        
        
        
        Phase Shifter (PS)
        
        
        
        
        
        
        
        Interconnect
        
        Configuration
        
        
        
        Configuration Modes
        
        Slave Serial Mode
        
        Master Serial Mode
        
        Slave Parallel Mode
        
        
        
        
        Readback
        
        Revision History

Page 12: R Spartan-3 1.2V FPGA Family: Functional Description€¦ · IFF2 Q SR Fixed Delay LVCMOS, LVTTL, PCI Single-ended Standards using V REF Differential Standards REV D CE CK Q SR REV

DeviceTotal Number

of RAM Blocks

Total Addressable

Locations (bits)

Number of

Columns

XC3S50 4 73728 1

XC3S200 12 221184 2

XC3S400 16 294912 2

XC3S1000 24 442368 2

XC3S1500 32 589824 2

XC3S2000 40 737280 2

XC3S4000 96 1769472 4

XC3S5000 104 1916928 4

DS099-2_12_030703

Spartan-3Dual Port

Block RAM

Read

Write

Read

Write

Read

Por

t A

Por

t B

21

4

DS099-2_13_091302

WEAENA

SSRACLKA

DIPA[30]

DOPA[pA 10]

DOA[wA 10]

RAM16_wA_wB

DOPB[pB 10]

DOB[wB 10]

WEBENB

SSRBCLKB

DIPB[30]

WEEN

SSRCLK

ADDR[r 10]DI[w 10]

DIP[p 10]

DOP[p 10]

DO[w 10]

RAM16_Sw

Signal Description

Port A Signal Name

Data Output Bus

Signal Description

Port A Signal Name

n = 2r (2)

Block RAM Capacity

(bits)

1 0 1 14 16384 16384

2 0 2 13 8192 16384

4 0 4 12 4096 16384

8 1 9 11 2048 18432

16 2 18 10 1024 18432

32 4 36 9 512 18432

CLK

WE

DI

ADDR

DO

EN

DISABLED READ

XXXX 1111 2222 XXXX

aa bb cc dd

0000 MEM(aa) 1111 2222 MEM(dd)

WRITEMEM(cc)=2222

DS099-2_14_030403

CLK

WE

DI

ADDR

DO

EN

DISABLED READ

XXXX 1111 2222 XXXX

aa bb cc dd

WRITEMEM(cc)=2222

DS099-2_15_030403

CLK

WE

DI

ADDR

DO

EN

DISABLED READ

XXXX 1111 2222 XXXX

aa bb cc dd

WRITEMEM(cc)=2222

DS099-2_16_030403

DS099-2_17_091302

A[170]

B[170]

P[350]MULT18X18

A[170]

B[170]

CLK

CE

RST

P[350]MULT18X18S

DS099-2_07_040103

PSINCDECPSEN

PSCLK

CLKIN

CLKFB

RSTSTATUS [70]

LOCKED8

CLKFX180

CLKFX

CLK0

PSDONE

ClockDistribution

StatusLogic

DFSDLL

PhaseShifter

Del

ay T

aps

Out

put S

tage

Inpu

t Sta

ge

DCM

DS099-2_08_041103

CLKINDelay

n

CLKFB

RST

CLK0

CLK90

CLK180

CLK270

CLK2X

CLK2X180

CLKDV

Out

put S

ectio

n

Control

Delayn-1

PhaseDetection

LOCKED

Delay2

Delay1

Mode Support

Low Frequency

High Frequency

Yes Yes

Yes No

Yes Yes

Yes No

Yes Yes

NONE 1X 2X

LOW HIGH

TRUE FALSE

15 2 25 3 35 4 45 5 55 60 65 70 75 8 9 10 11 12 13 14 15 and 16

TRUE FALSE

DS099-2_09_071003

CLK2X180

CLK0

ClockNet Delay

BUFGMUX

BUFG

FPGA

CLKIN

DCM

CLKFB

CLK2X180

CLK0

ClockNet Delay

IBUFG

FPGA

CLKIN

DCM

CLKFB

OBUFG

CLK2X

IBUFG

FPGA

CLKIN

DCM

CLKFB

OBUFG

CLK0CLK90

CLK180CLK270CLKDV

CLK2X180

CLK2X

ClockNet Delay

BUFGMUX

BUFG

FPGA

CLKIN

DCM

CLKFB

CLK0CLK90

CLK180CLK270CLKDV

CLK2X180

Phase

0o 90o 180o 270o 0o 90o 180o 270o 0o

DS099-2_10_031303

CLK2X

CLK2X180

CLKIN

CLKDV(1)

CLK0

CLK90

CLK180

CLK270

CLK0

CLK90

CLK180

CLK270

t

NONE FIXED VARIABLE

DS099-2_11_031303

CLKIN

CLKFB

TCLKINP

256

TCLKINP

256

0

ndash255 +255

CLKIN

TCLKINN

256

CLKIN

CLKFB

2 Reserved -

3 Reserved -

4 Reserved -

5 Reserved -

6 Reserved -

7 Reserved -

4

8

4

88

Horizontal Spine

Top

Spi

neB

otto

m S

pine

4

DCM DCM

Array Dependent

bull

DS099-2_18_070203

4 BUFGMUX

GCLK2GCLK3

GCLK0GCLK1

4 BUFGMUX

6 6 6 6 6

DS099-2_19_040103

(a) Long Line

8

DS099-2_20_040103

(b) Hex Line

CLB

2

CLB CLB

DS099-2_21_040103

CLBCLB CLB

DS099-2_22_040103

(d) Direct Lines

(c) Double Line

Device File Sizes

XC3S200 1047616 XCF01S XCF08P

XC3S400 1699136 XCF02S XCF08P

XC3S1000 3223488 XCF04S XCF08P

XC3S1500 5214784 XCF08P XCF08P

XC3S2000 7673024 XCF08P XCF08P

XC3S4000 11316864 XCF16P XCF16P

XC3S5000 13271936 XCF16P XCF16P

11491)

DOUTDIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Master

PROG_B

DIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Slave

PROG_B

DS099_23_041103

D0

CLK

CE

OERESET

CF

PlatformFlash PROM

XCF0xSor

XCFxxP

VCCINT

12V

VCCAUX

VCCO Bank 4

25V

47KΩAll

25V

VCCAUX VCCINT

VCCO Bank 412V

33V

VCC VCCJ

VCCO

25V

M0M1M2

GNDGNDGND

PROG_B

INIT_B

DONE

Spartan-3Slave

INIT_B

D[07]

CCLK

RDWR_B

BUSY

CS_B

PROG_B

DONE

CS_B

Spartan-3Slave

INIT_B

GND

D[07]

CCLK

RDWR_B

BUSY

CS_B

D[07]

CCLK

RDWR_B

BUSY

PROG_B

DONE

CS_B

DS099_24_041103

25V

M1M2M0

25V

M1M2M0

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

47KΩ 47KΩ

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

25V

GND

Spartan-3Master

D[07]

CCLK

PROG_B

DONE

INIT_B

DATA[07]

CCLK

RDWR_B

CS_B

CF

CE

OERESET

Platform Flash PROM

DS099_25_041103

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

GND

33V

VCC VCCJ

VCCO

25V

XCFxxP

25V

All47KΩ

Sample mode pins

No

Yes

NoCRCcorrect

YesNoReconfigure

Start-Upsequence

User mode

INIT_ B = High

PROG_B = Low

DS099_26_041103

Samplemode pins

Clearconfiguration

memory

No

Yes

No

Yes

Power-On

CRCcorrect

Shutdownsequence

Reconfigure

Start-Upsequence

User mode

INIT_B = High

PROG_B = Low

No

DS099_27_041103

Start-Up Clock

Default Cycles

Sync-to-DONE

0 1 2 3 4 5 6 7

0 1

DONE High

2 3 4 5 6 7

Phase

Start-Up Clock

Phase

DONE

GTS

GSR

GWE

DS099_028_040803

DONE

GTS

GSR

GWE

Revision History

IOBs
- IOB Overview
- ESD Protection
- - CLB Overview
    - Main Logic Paths
        
        
        
        Port Aspect Ratios
        
        
        
        
        
        
        
        
        DLL Frequency Modes
        
        
        
        
        
        
        DFS Frequency Modes
        
        
        
        Phase Shifter (PS)
        
        
        
        
        
        
        
        Interconnect
        
        Configuration
        
        
        
        Configuration Modes
        
        Slave Serial Mode
        
        Master Serial Mode
        
        Slave Parallel Mode
        
        
        
        
        Readback
        
        Revision History

Page 13: R Spartan-3 1.2V FPGA Family: Functional Description€¦ · IFF2 Q SR Fixed Delay LVCMOS, LVTTL, PCI Single-ended Standards using V REF Differential Standards REV D CE CK Q SR REV

DeviceTotal Number

of RAM Blocks

Total Addressable

Locations (bits)

Number of

Columns

XC3S50 4 73728 1

XC3S200 12 221184 2

XC3S400 16 294912 2

XC3S1000 24 442368 2

XC3S1500 32 589824 2

XC3S2000 40 737280 2

XC3S4000 96 1769472 4

XC3S5000 104 1916928 4

DS099-2_12_030703

Spartan-3Dual Port

Block RAM

Read

Write

Read

Write

Read

Por

t A

Por

t B

21

4

DS099-2_13_091302

WEAENA

SSRACLKA

DIPA[30]

DOPA[pA 10]

DOA[wA 10]

RAM16_wA_wB

DOPB[pB 10]

DOB[wB 10]

WEBENB

SSRBCLKB

DIPB[30]

WEEN

SSRCLK

ADDR[r 10]DI[w 10]

DIP[p 10]

DOP[p 10]

DO[w 10]

RAM16_Sw

Signal Description

Port A Signal Name

Data Output Bus

Signal Description

Port A Signal Name

n = 2r (2)

Block RAM Capacity

(bits)

1 0 1 14 16384 16384

2 0 2 13 8192 16384

4 0 4 12 4096 16384

8 1 9 11 2048 18432

16 2 18 10 1024 18432

32 4 36 9 512 18432

CLK

WE

DI

ADDR

DO

EN

DISABLED READ

XXXX 1111 2222 XXXX

aa bb cc dd

0000 MEM(aa) 1111 2222 MEM(dd)

WRITEMEM(cc)=2222

DS099-2_14_030403

CLK

WE

DI

ADDR

DO

EN

DISABLED READ

XXXX 1111 2222 XXXX

aa bb cc dd

WRITEMEM(cc)=2222

DS099-2_15_030403

CLK

WE

DI

ADDR

DO

EN

DISABLED READ

XXXX 1111 2222 XXXX

aa bb cc dd

WRITEMEM(cc)=2222

DS099-2_16_030403

DS099-2_17_091302

A[170]

B[170]

P[350]MULT18X18

A[170]

B[170]

CLK

CE

RST

P[350]MULT18X18S

DS099-2_07_040103

PSINCDECPSEN

PSCLK

CLKIN

CLKFB

RSTSTATUS [70]

LOCKED8

CLKFX180

CLKFX

CLK0

PSDONE

ClockDistribution

StatusLogic

DFSDLL

PhaseShifter

Del

ay T

aps

Out

put S

tage

Inpu

t Sta

ge

DCM

DS099-2_08_041103

CLKINDelay

n

CLKFB

RST

CLK0

CLK90

CLK180

CLK270

CLK2X

CLK2X180

CLKDV

Out

put S

ectio

n

Control

Delayn-1

PhaseDetection

LOCKED

Delay2

Delay1

Mode Support

Low Frequency

High Frequency

Yes Yes

Yes No

Yes Yes

Yes No

Yes Yes

NONE 1X 2X

LOW HIGH

TRUE FALSE

15 2 25 3 35 4 45 5 55 60 65 70 75 8 9 10 11 12 13 14 15 and 16

TRUE FALSE

DS099-2_09_071003

CLK2X180

CLK0

ClockNet Delay

BUFGMUX

BUFG

FPGA

CLKIN

DCM

CLKFB

CLK2X180

CLK0

ClockNet Delay

IBUFG

FPGA

CLKIN

DCM

CLKFB

OBUFG

CLK2X

IBUFG

FPGA

CLKIN

DCM

CLKFB

OBUFG

CLK0CLK90

CLK180CLK270CLKDV

CLK2X180

CLK2X

ClockNet Delay

BUFGMUX

BUFG

FPGA

CLKIN

DCM

CLKFB

CLK0CLK90

CLK180CLK270CLKDV

CLK2X180

Phase

0o 90o 180o 270o 0o 90o 180o 270o 0o

DS099-2_10_031303

CLK2X

CLK2X180

CLKIN

CLKDV(1)

CLK0

CLK90

CLK180

CLK270

CLK0

CLK90

CLK180

CLK270

t

NONE FIXED VARIABLE

DS099-2_11_031303

CLKIN

CLKFB

TCLKINP

256

TCLKINP

256

0

ndash255 +255

CLKIN

TCLKINN

256

CLKIN

CLKFB

2 Reserved -

3 Reserved -

4 Reserved -

5 Reserved -

6 Reserved -

7 Reserved -

4

8

4

88

Horizontal Spine

Top

Spi

neB

otto

m S

pine

4

DCM DCM

Array Dependent

bull

DS099-2_18_070203

4 BUFGMUX

GCLK2GCLK3

GCLK0GCLK1

4 BUFGMUX

6 6 6 6 6

DS099-2_19_040103

(a) Long Line

8

DS099-2_20_040103

(b) Hex Line

CLB

2

CLB CLB

DS099-2_21_040103

CLBCLB CLB

DS099-2_22_040103

(d) Direct Lines

(c) Double Line

Device File Sizes

XC3S200 1047616 XCF01S XCF08P

XC3S400 1699136 XCF02S XCF08P

XC3S1000 3223488 XCF04S XCF08P

XC3S1500 5214784 XCF08P XCF08P

XC3S2000 7673024 XCF08P XCF08P

XC3S4000 11316864 XCF16P XCF16P

XC3S5000 13271936 XCF16P XCF16P

11491)

DOUTDIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Master

PROG_B

DIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Slave

PROG_B

DS099_23_041103

D0

CLK

CE

OERESET

CF

PlatformFlash PROM

XCF0xSor

XCFxxP

VCCINT

12V

VCCAUX

VCCO Bank 4

25V

47KΩAll

25V

VCCAUX VCCINT

VCCO Bank 412V

33V

VCC VCCJ

VCCO

25V

M0M1M2

GNDGNDGND

PROG_B

INIT_B

DONE

Spartan-3Slave

INIT_B

D[07]

CCLK

RDWR_B

BUSY

CS_B

PROG_B

DONE

CS_B

Spartan-3Slave

INIT_B

GND

D[07]

CCLK

RDWR_B

BUSY

CS_B

D[07]

CCLK

RDWR_B

BUSY

PROG_B

DONE

CS_B

DS099_24_041103

25V

M1M2M0

25V

M1M2M0

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

47KΩ 47KΩ

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

25V

GND

Spartan-3Master

D[07]

CCLK

PROG_B

DONE

INIT_B

DATA[07]

CCLK

RDWR_B

CS_B

CF

CE

OERESET

Platform Flash PROM

DS099_25_041103

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

GND

33V

VCC VCCJ

VCCO

25V

XCFxxP

25V

All47KΩ

Sample mode pins

No

Yes

NoCRCcorrect

YesNoReconfigure

Start-Upsequence

User mode

INIT_ B = High

PROG_B = Low

DS099_26_041103

Samplemode pins

Clearconfiguration

memory

No

Yes

No

Yes

Power-On

CRCcorrect

Shutdownsequence

Reconfigure

Start-Upsequence

User mode

INIT_B = High

PROG_B = Low

No

DS099_27_041103

Start-Up Clock

Default Cycles

Sync-to-DONE

0 1 2 3 4 5 6 7

0 1

DONE High

2 3 4 5 6 7

Phase

Start-Up Clock

Phase

DONE

GTS

GSR

GWE

DS099_028_040803

DONE

GTS

GSR

GWE

Revision History

IOBs
- IOB Overview
- ESD Protection
- - CLB Overview
    - Main Logic Paths
        
        
        
        Port Aspect Ratios
        
        
        
        
        
        
        
        
        DLL Frequency Modes
        
        
        
        
        
        
        DFS Frequency Modes
        
        
        
        Phase Shifter (PS)
        
        
        
        
        
        
        
        Interconnect
        
        Configuration
        
        
        
        Configuration Modes
        
        Slave Serial Mode
        
        Master Serial Mode
        
        Slave Parallel Mode
        
        
        
        
        Readback
        
        Revision History

Page 14: R Spartan-3 1.2V FPGA Family: Functional Description€¦ · IFF2 Q SR Fixed Delay LVCMOS, LVTTL, PCI Single-ended Standards using V REF Differential Standards REV D CE CK Q SR REV

DS099-2_13_091302

WEAENA

SSRACLKA

DIPA[30]

DOPA[pA 10]

DOA[wA 10]

RAM16_wA_wB

DOPB[pB 10]

DOB[wB 10]

WEBENB

SSRBCLKB

DIPB[30]

WEEN

SSRCLK

ADDR[r 10]DI[w 10]

DIP[p 10]

DOP[p 10]

DO[w 10]

RAM16_Sw

Signal Description

Port A Signal Name

Data Output Bus

Signal Description

Port A Signal Name

n = 2r (2)

Block RAM Capacity

(bits)

1 0 1 14 16384 16384

2 0 2 13 8192 16384

4 0 4 12 4096 16384

8 1 9 11 2048 18432

16 2 18 10 1024 18432

32 4 36 9 512 18432

CLK

WE

DI

ADDR

DO

EN

DISABLED READ

XXXX 1111 2222 XXXX

aa bb cc dd

0000 MEM(aa) 1111 2222 MEM(dd)

WRITEMEM(cc)=2222

DS099-2_14_030403

CLK

WE

DI

ADDR

DO

EN

DISABLED READ

XXXX 1111 2222 XXXX

aa bb cc dd

WRITEMEM(cc)=2222

DS099-2_15_030403

CLK

WE

DI

ADDR

DO

EN

DISABLED READ

XXXX 1111 2222 XXXX

aa bb cc dd

WRITEMEM(cc)=2222

DS099-2_16_030403

DS099-2_17_091302

A[170]

B[170]

P[350]MULT18X18

A[170]

B[170]

CLK

CE

RST

P[350]MULT18X18S

DS099-2_07_040103

PSINCDECPSEN

PSCLK

CLKIN

CLKFB

RSTSTATUS [70]

LOCKED8

CLKFX180

CLKFX

CLK0

PSDONE

ClockDistribution

StatusLogic

DFSDLL

PhaseShifter

Del

ay T

aps

Out

put S

tage

Inpu

t Sta

ge

DCM

DS099-2_08_041103

CLKINDelay

n

CLKFB

RST

CLK0

CLK90

CLK180

CLK270

CLK2X

CLK2X180

CLKDV

Out

put S

ectio

n

Control

Delayn-1

PhaseDetection

LOCKED

Delay2

Delay1

Mode Support

Low Frequency

High Frequency

Yes Yes

Yes No

Yes Yes

Yes No

Yes Yes

NONE 1X 2X

LOW HIGH

TRUE FALSE

15 2 25 3 35 4 45 5 55 60 65 70 75 8 9 10 11 12 13 14 15 and 16

TRUE FALSE

DS099-2_09_071003

CLK2X180

CLK0

ClockNet Delay

BUFGMUX

BUFG

FPGA

CLKIN

DCM

CLKFB

CLK2X180

CLK0

ClockNet Delay

IBUFG

FPGA

CLKIN

DCM

CLKFB

OBUFG

CLK2X

IBUFG

FPGA

CLKIN

DCM

CLKFB

OBUFG

CLK0CLK90

CLK180CLK270CLKDV

CLK2X180

CLK2X

ClockNet Delay

BUFGMUX

BUFG

FPGA

CLKIN

DCM

CLKFB

CLK0CLK90

CLK180CLK270CLKDV

CLK2X180

Phase

0o 90o 180o 270o 0o 90o 180o 270o 0o

DS099-2_10_031303

CLK2X

CLK2X180

CLKIN

CLKDV(1)

CLK0

CLK90

CLK180

CLK270

CLK0

CLK90

CLK180

CLK270

t

NONE FIXED VARIABLE

DS099-2_11_031303

CLKIN

CLKFB

TCLKINP

256

TCLKINP

256

0

ndash255 +255

CLKIN

TCLKINN

256

CLKIN

CLKFB

2 Reserved -

3 Reserved -

4 Reserved -

5 Reserved -

6 Reserved -

7 Reserved -

4

8

4

88

Horizontal Spine

Top

Spi

neB

otto

m S

pine

4

DCM DCM

Array Dependent

bull

DS099-2_18_070203

4 BUFGMUX

GCLK2GCLK3

GCLK0GCLK1

4 BUFGMUX

6 6 6 6 6

DS099-2_19_040103

(a) Long Line

8

DS099-2_20_040103

(b) Hex Line

CLB

2

CLB CLB

DS099-2_21_040103

CLBCLB CLB

DS099-2_22_040103

(d) Direct Lines

(c) Double Line

Device File Sizes

XC3S200 1047616 XCF01S XCF08P

XC3S400 1699136 XCF02S XCF08P

XC3S1000 3223488 XCF04S XCF08P

XC3S1500 5214784 XCF08P XCF08P

XC3S2000 7673024 XCF08P XCF08P

XC3S4000 11316864 XCF16P XCF16P

XC3S5000 13271936 XCF16P XCF16P

11491)

DOUTDIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Master

PROG_B

DIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Slave

PROG_B

DS099_23_041103

D0

CLK

CE

OERESET

CF

PlatformFlash PROM

XCF0xSor

XCFxxP

VCCINT

12V

VCCAUX

VCCO Bank 4

25V

47KΩAll

25V

VCCAUX VCCINT

VCCO Bank 412V

33V

VCC VCCJ

VCCO

25V

M0M1M2

GNDGNDGND

PROG_B

INIT_B

DONE

Spartan-3Slave

INIT_B

D[07]

CCLK

RDWR_B

BUSY

CS_B

PROG_B

DONE

CS_B

Spartan-3Slave

INIT_B

GND

D[07]

CCLK

RDWR_B

BUSY

CS_B

D[07]

CCLK

RDWR_B

BUSY

PROG_B

DONE

CS_B

DS099_24_041103

25V

M1M2M0

25V

M1M2M0

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

47KΩ 47KΩ

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

25V

GND

Spartan-3Master

D[07]

CCLK

PROG_B

DONE

INIT_B

DATA[07]

CCLK

RDWR_B

CS_B

CF

CE

OERESET

Platform Flash PROM

DS099_25_041103

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

GND

33V

VCC VCCJ

VCCO

25V

XCFxxP

25V

All47KΩ

Sample mode pins

No

Yes

NoCRCcorrect

YesNoReconfigure

Start-Upsequence

User mode

INIT_ B = High

PROG_B = Low

DS099_26_041103

Samplemode pins

Clearconfiguration

memory

No

Yes

No

Yes

Power-On

CRCcorrect

Shutdownsequence

Reconfigure

Start-Upsequence

User mode

INIT_B = High

PROG_B = Low

No

DS099_27_041103

Start-Up Clock

Default Cycles

Sync-to-DONE

0 1 2 3 4 5 6 7

0 1

DONE High

2 3 4 5 6 7

Phase

Start-Up Clock

Phase

DONE

GTS

GSR

GWE

DS099_028_040803

DONE

GTS

GSR

GWE

Revision History

IOBs
- IOB Overview
- ESD Protection
- - CLB Overview
    - Main Logic Paths
        
        
        
        Port Aspect Ratios
        
        
        
        
        
        
        
        
        DLL Frequency Modes
        
        
        
        
        
        
        DFS Frequency Modes
        
        
        
        Phase Shifter (PS)
        
        
        
        
        
        
        
        Interconnect
        
        Configuration
        
        
        
        Configuration Modes
        
        Slave Serial Mode
        
        Master Serial Mode
        
        Slave Parallel Mode
        
        
        
        
        Readback
        
        Revision History

Page 15: R Spartan-3 1.2V FPGA Family: Functional Description€¦ · IFF2 Q SR Fixed Delay LVCMOS, LVTTL, PCI Single-ended Standards using V REF Differential Standards REV D CE CK Q SR REV

Data Output Bus

Signal Description

Port A Signal Name

n = 2r (2)

Block RAM Capacity

(bits)

1 0 1 14 16384 16384

2 0 2 13 8192 16384

4 0 4 12 4096 16384

8 1 9 11 2048 18432

16 2 18 10 1024 18432

32 4 36 9 512 18432

CLK

WE

DI

ADDR

DO

EN

DISABLED READ

XXXX 1111 2222 XXXX

aa bb cc dd

0000 MEM(aa) 1111 2222 MEM(dd)

WRITEMEM(cc)=2222

DS099-2_14_030403

CLK

WE

DI

ADDR

DO

EN

DISABLED READ

XXXX 1111 2222 XXXX

aa bb cc dd

WRITEMEM(cc)=2222

DS099-2_15_030403

CLK

WE

DI

ADDR

DO

EN

DISABLED READ

XXXX 1111 2222 XXXX

aa bb cc dd

WRITEMEM(cc)=2222

DS099-2_16_030403

DS099-2_17_091302

A[170]

B[170]

P[350]MULT18X18

A[170]

B[170]

CLK

CE

RST

P[350]MULT18X18S

DS099-2_07_040103

PSINCDECPSEN

PSCLK

CLKIN

CLKFB

RSTSTATUS [70]

LOCKED8

CLKFX180

CLKFX

CLK0

PSDONE

ClockDistribution

StatusLogic

DFSDLL

PhaseShifter

Del

ay T

aps

Out

put S

tage

Inpu

t Sta

ge

DCM

DS099-2_08_041103

CLKINDelay

n

CLKFB

RST

CLK0

CLK90

CLK180

CLK270

CLK2X

CLK2X180

CLKDV

Out

put S

ectio

n

Control

Delayn-1

PhaseDetection

LOCKED

Delay2

Delay1

Mode Support

Low Frequency

High Frequency

Yes Yes

Yes No

Yes Yes

Yes No

Yes Yes

NONE 1X 2X

LOW HIGH

TRUE FALSE

15 2 25 3 35 4 45 5 55 60 65 70 75 8 9 10 11 12 13 14 15 and 16

TRUE FALSE

DS099-2_09_071003

CLK2X180

CLK0

ClockNet Delay

BUFGMUX

BUFG

FPGA

CLKIN

DCM

CLKFB

CLK2X180

CLK0

ClockNet Delay

IBUFG

FPGA

CLKIN

DCM

CLKFB

OBUFG

CLK2X

IBUFG

FPGA

CLKIN

DCM

CLKFB

OBUFG

CLK0CLK90

CLK180CLK270CLKDV

CLK2X180

CLK2X

ClockNet Delay

BUFGMUX

BUFG

FPGA

CLKIN

DCM

CLKFB

CLK0CLK90

CLK180CLK270CLKDV

CLK2X180

Phase

0o 90o 180o 270o 0o 90o 180o 270o 0o

DS099-2_10_031303

CLK2X

CLK2X180

CLKIN

CLKDV(1)

CLK0

CLK90

CLK180

CLK270

CLK0

CLK90

CLK180

CLK270

t

NONE FIXED VARIABLE

DS099-2_11_031303

CLKIN

CLKFB

TCLKINP

256

TCLKINP

256

0

ndash255 +255

CLKIN

TCLKINN

256

CLKIN

CLKFB

2 Reserved -

3 Reserved -

4 Reserved -

5 Reserved -

6 Reserved -

7 Reserved -

4

8

4

88

Horizontal Spine

Top

Spi

neB

otto

m S

pine

4

DCM DCM

Array Dependent

bull

DS099-2_18_070203

4 BUFGMUX

GCLK2GCLK3

GCLK0GCLK1

4 BUFGMUX

6 6 6 6 6

DS099-2_19_040103

(a) Long Line

8

DS099-2_20_040103

(b) Hex Line

CLB

2

CLB CLB

DS099-2_21_040103

CLBCLB CLB

DS099-2_22_040103

(d) Direct Lines

(c) Double Line

Device File Sizes

XC3S200 1047616 XCF01S XCF08P

XC3S400 1699136 XCF02S XCF08P

XC3S1000 3223488 XCF04S XCF08P

XC3S1500 5214784 XCF08P XCF08P

XC3S2000 7673024 XCF08P XCF08P

XC3S4000 11316864 XCF16P XCF16P

XC3S5000 13271936 XCF16P XCF16P

11491)

DOUTDIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Master

PROG_B

DIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Slave

PROG_B

DS099_23_041103

D0

CLK

CE

OERESET

CF

PlatformFlash PROM

XCF0xSor

XCFxxP

VCCINT

12V

VCCAUX

VCCO Bank 4

25V

47KΩAll

25V

VCCAUX VCCINT

VCCO Bank 412V

33V

VCC VCCJ

VCCO

25V

M0M1M2

GNDGNDGND

PROG_B

INIT_B

DONE

Spartan-3Slave

INIT_B

D[07]

CCLK

RDWR_B

BUSY

CS_B

PROG_B

DONE

CS_B

Spartan-3Slave

INIT_B

GND

D[07]

CCLK

RDWR_B

BUSY

CS_B

D[07]

CCLK

RDWR_B

BUSY

PROG_B

DONE

CS_B

DS099_24_041103

25V

M1M2M0

25V

M1M2M0

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

47KΩ 47KΩ

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

25V

GND

Spartan-3Master

D[07]

CCLK

PROG_B

DONE

INIT_B

DATA[07]

CCLK

RDWR_B

CS_B

CF

CE

OERESET

Platform Flash PROM

DS099_25_041103

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

GND

33V

VCC VCCJ

VCCO

25V

XCFxxP

25V

All47KΩ

Sample mode pins

No

Yes

NoCRCcorrect

YesNoReconfigure

Start-Upsequence

User mode

INIT_ B = High

PROG_B = Low

DS099_26_041103

Samplemode pins

Clearconfiguration

memory

No

Yes

No

Yes

Power-On

CRCcorrect

Shutdownsequence

Reconfigure

Start-Upsequence

User mode

INIT_B = High

PROG_B = Low

No

DS099_27_041103

Start-Up Clock

Default Cycles

Sync-to-DONE

0 1 2 3 4 5 6 7

0 1

DONE High

2 3 4 5 6 7

Phase

Start-Up Clock

Phase

DONE

GTS

GSR

GWE

DS099_028_040803

DONE

GTS

GSR

GWE

Revision History

IOBs
- IOB Overview
- ESD Protection
- - CLB Overview
    - Main Logic Paths
        
        
        
        Port Aspect Ratios
        
        
        
        
        
        
        
        
        DLL Frequency Modes
        
        
        
        
        
        
        DFS Frequency Modes
        
        
        
        Phase Shifter (PS)
        
        
        
        
        
        
        
        Interconnect
        
        Configuration
        
        
        
        Configuration Modes
        
        Slave Serial Mode
        
        Master Serial Mode
        
        Slave Parallel Mode
        
        
        
        
        Readback
        
        Revision History

Page 16: R Spartan-3 1.2V FPGA Family: Functional Description€¦ · IFF2 Q SR Fixed Delay LVCMOS, LVTTL, PCI Single-ended Standards using V REF Differential Standards REV D CE CK Q SR REV

n = 2r (2)

Block RAM Capacity

(bits)

1 0 1 14 16384 16384

2 0 2 13 8192 16384

4 0 4 12 4096 16384

8 1 9 11 2048 18432

16 2 18 10 1024 18432

32 4 36 9 512 18432

CLK

WE

DI

ADDR

DO

EN

DISABLED READ

XXXX 1111 2222 XXXX

aa bb cc dd

0000 MEM(aa) 1111 2222 MEM(dd)

WRITEMEM(cc)=2222

DS099-2_14_030403

CLK

WE

DI

ADDR

DO

EN

DISABLED READ

XXXX 1111 2222 XXXX

aa bb cc dd

WRITEMEM(cc)=2222

DS099-2_15_030403

CLK

WE

DI

ADDR

DO

EN

DISABLED READ

XXXX 1111 2222 XXXX

aa bb cc dd

WRITEMEM(cc)=2222

DS099-2_16_030403

DS099-2_17_091302

A[170]

B[170]

P[350]MULT18X18

A[170]

B[170]

CLK

CE

RST

P[350]MULT18X18S

DS099-2_07_040103

PSINCDECPSEN

PSCLK

CLKIN

CLKFB

RSTSTATUS [70]

LOCKED8

CLKFX180

CLKFX

CLK0

PSDONE

ClockDistribution

StatusLogic

DFSDLL

PhaseShifter

Del

ay T

aps

Out

put S

tage

Inpu

t Sta

ge

DCM

DS099-2_08_041103

CLKINDelay

n

CLKFB

RST

CLK0

CLK90

CLK180

CLK270

CLK2X

CLK2X180

CLKDV

Out

put S

ectio

n

Control

Delayn-1

PhaseDetection

LOCKED

Delay2

Delay1

Mode Support

Low Frequency

High Frequency

Yes Yes

Yes No

Yes Yes

Yes No

Yes Yes

NONE 1X 2X

LOW HIGH

TRUE FALSE

15 2 25 3 35 4 45 5 55 60 65 70 75 8 9 10 11 12 13 14 15 and 16

TRUE FALSE

DS099-2_09_071003

CLK2X180

CLK0

ClockNet Delay

BUFGMUX

BUFG

FPGA

CLKIN

DCM

CLKFB

CLK2X180

CLK0

ClockNet Delay

IBUFG

FPGA

CLKIN

DCM

CLKFB

OBUFG

CLK2X

IBUFG

FPGA

CLKIN

DCM

CLKFB

OBUFG

CLK0CLK90

CLK180CLK270CLKDV

CLK2X180

CLK2X

ClockNet Delay

BUFGMUX

BUFG

FPGA

CLKIN

DCM

CLKFB

CLK0CLK90

CLK180CLK270CLKDV

CLK2X180

Phase

0o 90o 180o 270o 0o 90o 180o 270o 0o

DS099-2_10_031303

CLK2X

CLK2X180

CLKIN

CLKDV(1)

CLK0

CLK90

CLK180

CLK270

CLK0

CLK90

CLK180

CLK270

t

NONE FIXED VARIABLE

DS099-2_11_031303

CLKIN

CLKFB

TCLKINP

256

TCLKINP

256

0

ndash255 +255

CLKIN

TCLKINN

256

CLKIN

CLKFB

2 Reserved -

3 Reserved -

4 Reserved -

5 Reserved -

6 Reserved -

7 Reserved -

4

8

4

88

Horizontal Spine

Top

Spi

neB

otto

m S

pine

4

DCM DCM

Array Dependent

bull

DS099-2_18_070203

4 BUFGMUX

GCLK2GCLK3

GCLK0GCLK1

4 BUFGMUX

6 6 6 6 6

DS099-2_19_040103

(a) Long Line

8

DS099-2_20_040103

(b) Hex Line

CLB

2

CLB CLB

DS099-2_21_040103

CLBCLB CLB

DS099-2_22_040103

(d) Direct Lines

(c) Double Line

Device File Sizes

XC3S200 1047616 XCF01S XCF08P

XC3S400 1699136 XCF02S XCF08P

XC3S1000 3223488 XCF04S XCF08P

XC3S1500 5214784 XCF08P XCF08P

XC3S2000 7673024 XCF08P XCF08P

XC3S4000 11316864 XCF16P XCF16P

XC3S5000 13271936 XCF16P XCF16P

11491)

DOUTDIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Master

PROG_B

DIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Slave

PROG_B

DS099_23_041103

D0

CLK

CE

OERESET

CF

PlatformFlash PROM

XCF0xSor

XCFxxP

VCCINT

12V

VCCAUX

VCCO Bank 4

25V

47KΩAll

25V

VCCAUX VCCINT

VCCO Bank 412V

33V

VCC VCCJ

VCCO

25V

M0M1M2

GNDGNDGND

PROG_B

INIT_B

DONE

Spartan-3Slave

INIT_B

D[07]

CCLK

RDWR_B

BUSY

CS_B

PROG_B

DONE

CS_B

Spartan-3Slave

INIT_B

GND

D[07]

CCLK

RDWR_B

BUSY

CS_B

D[07]

CCLK

RDWR_B

BUSY

PROG_B

DONE

CS_B

DS099_24_041103

25V

M1M2M0

25V

M1M2M0

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

47KΩ 47KΩ

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

25V

GND

Spartan-3Master

D[07]

CCLK

PROG_B

DONE

INIT_B

DATA[07]

CCLK

RDWR_B

CS_B

CF

CE

OERESET

Platform Flash PROM

DS099_25_041103

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

GND

33V

VCC VCCJ

VCCO

25V

XCFxxP

25V

All47KΩ

Sample mode pins

No

Yes

NoCRCcorrect

YesNoReconfigure

Start-Upsequence

User mode

INIT_ B = High

PROG_B = Low

DS099_26_041103

Samplemode pins

Clearconfiguration

memory

No

Yes

No

Yes

Power-On

CRCcorrect

Shutdownsequence

Reconfigure

Start-Upsequence

User mode

INIT_B = High

PROG_B = Low

No

DS099_27_041103

Start-Up Clock

Default Cycles

Sync-to-DONE

0 1 2 3 4 5 6 7

0 1

DONE High

2 3 4 5 6 7

Phase

Start-Up Clock

Phase

DONE

GTS

GSR

GWE

DS099_028_040803

DONE

GTS

GSR

GWE

Revision History

IOBs
- IOB Overview
- ESD Protection
- - CLB Overview
    - Main Logic Paths
        
        
        
        Port Aspect Ratios
        
        
        
        
        
        
        
        
        DLL Frequency Modes
        
        
        
        
        
        
        DFS Frequency Modes
        
        
        
        Phase Shifter (PS)
        
        
        
        
        
        
        
        Interconnect
        
        Configuration
        
        
        
        Configuration Modes
        
        Slave Serial Mode
        
        Master Serial Mode
        
        Slave Parallel Mode
        
        
        
        
        Readback
        
        Revision History

Page 17: R Spartan-3 1.2V FPGA Family: Functional Description€¦ · IFF2 Q SR Fixed Delay LVCMOS, LVTTL, PCI Single-ended Standards using V REF Differential Standards REV D CE CK Q SR REV

CLK

WE

DI

ADDR

DO

EN

DISABLED READ

XXXX 1111 2222 XXXX

aa bb cc dd

0000 MEM(aa) 1111 2222 MEM(dd)

WRITEMEM(cc)=2222

DS099-2_14_030403

CLK

WE

DI

ADDR

DO

EN

DISABLED READ

XXXX 1111 2222 XXXX

aa bb cc dd

WRITEMEM(cc)=2222

DS099-2_15_030403

CLK

WE

DI

ADDR

DO

EN

DISABLED READ

XXXX 1111 2222 XXXX

aa bb cc dd

WRITEMEM(cc)=2222

DS099-2_16_030403

DS099-2_17_091302

A[170]

B[170]

P[350]MULT18X18

A[170]

B[170]

CLK

CE

RST

P[350]MULT18X18S

DS099-2_07_040103

PSINCDECPSEN

PSCLK

CLKIN

CLKFB

RSTSTATUS [70]

LOCKED8

CLKFX180

CLKFX

CLK0

PSDONE

ClockDistribution

StatusLogic

DFSDLL

PhaseShifter

Del

ay T

aps

Out

put S

tage

Inpu

t Sta

ge

DCM

DS099-2_08_041103

CLKINDelay

n

CLKFB

RST

CLK0

CLK90

CLK180

CLK270

CLK2X

CLK2X180

CLKDV

Out

put S

ectio

n

Control

Delayn-1

PhaseDetection

LOCKED

Delay2

Delay1

Mode Support

Low Frequency

High Frequency

Yes Yes

Yes No

Yes Yes

Yes No

Yes Yes

NONE 1X 2X

LOW HIGH

TRUE FALSE

15 2 25 3 35 4 45 5 55 60 65 70 75 8 9 10 11 12 13 14 15 and 16

TRUE FALSE

DS099-2_09_071003

CLK2X180

CLK0

ClockNet Delay

BUFGMUX

BUFG

FPGA

CLKIN

DCM

CLKFB

CLK2X180

CLK0

ClockNet Delay

IBUFG

FPGA

CLKIN

DCM

CLKFB

OBUFG

CLK2X

IBUFG

FPGA

CLKIN

DCM

CLKFB

OBUFG

CLK0CLK90

CLK180CLK270CLKDV

CLK2X180

CLK2X

ClockNet Delay

BUFGMUX

BUFG

FPGA

CLKIN

DCM

CLKFB

CLK0CLK90

CLK180CLK270CLKDV

CLK2X180

Phase

0o 90o 180o 270o 0o 90o 180o 270o 0o

DS099-2_10_031303

CLK2X

CLK2X180

CLKIN

CLKDV(1)

CLK0

CLK90

CLK180

CLK270

CLK0

CLK90

CLK180

CLK270

t

NONE FIXED VARIABLE

DS099-2_11_031303

CLKIN

CLKFB

TCLKINP

256

TCLKINP

256

0

ndash255 +255

CLKIN

TCLKINN

256

CLKIN

CLKFB

2 Reserved -

3 Reserved -

4 Reserved -

5 Reserved -

6 Reserved -

7 Reserved -

4

8

4

88

Horizontal Spine

Top

Spi

neB

otto

m S

pine

4

DCM DCM

Array Dependent

bull

DS099-2_18_070203

4 BUFGMUX

GCLK2GCLK3

GCLK0GCLK1

4 BUFGMUX

6 6 6 6 6

DS099-2_19_040103

(a) Long Line

8

DS099-2_20_040103

(b) Hex Line

CLB

2

CLB CLB

DS099-2_21_040103

CLBCLB CLB

DS099-2_22_040103

(d) Direct Lines

(c) Double Line

Device File Sizes

XC3S200 1047616 XCF01S XCF08P

XC3S400 1699136 XCF02S XCF08P

XC3S1000 3223488 XCF04S XCF08P

XC3S1500 5214784 XCF08P XCF08P

XC3S2000 7673024 XCF08P XCF08P

XC3S4000 11316864 XCF16P XCF16P

XC3S5000 13271936 XCF16P XCF16P

11491)

DOUTDIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Master

PROG_B

DIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Slave

PROG_B

DS099_23_041103

D0

CLK

CE

OERESET

CF

PlatformFlash PROM

XCF0xSor

XCFxxP

VCCINT

12V

VCCAUX

VCCO Bank 4

25V

47KΩAll

25V

VCCAUX VCCINT

VCCO Bank 412V

33V

VCC VCCJ

VCCO

25V

M0M1M2

GNDGNDGND

PROG_B

INIT_B

DONE

Spartan-3Slave

INIT_B

D[07]

CCLK

RDWR_B

BUSY

CS_B

PROG_B

DONE

CS_B

Spartan-3Slave

INIT_B

GND

D[07]

CCLK

RDWR_B

BUSY

CS_B

D[07]

CCLK

RDWR_B

BUSY

PROG_B

DONE

CS_B

DS099_24_041103

25V

M1M2M0

25V

M1M2M0

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

47KΩ 47KΩ

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

25V

GND

Spartan-3Master

D[07]

CCLK

PROG_B

DONE

INIT_B

DATA[07]

CCLK

RDWR_B

CS_B

CF

CE

OERESET

Platform Flash PROM

DS099_25_041103

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

GND

33V

VCC VCCJ

VCCO

25V

XCFxxP

25V

All47KΩ

Sample mode pins

No

Yes

NoCRCcorrect

YesNoReconfigure

Start-Upsequence

User mode

INIT_ B = High

PROG_B = Low

DS099_26_041103

Samplemode pins

Clearconfiguration

memory

No

Yes

No

Yes

Power-On

CRCcorrect

Shutdownsequence

Reconfigure

Start-Upsequence

User mode

INIT_B = High

PROG_B = Low

No

DS099_27_041103

Start-Up Clock

Default Cycles

Sync-to-DONE

0 1 2 3 4 5 6 7

0 1

DONE High

2 3 4 5 6 7

Phase

Start-Up Clock

Phase

DONE

GTS

GSR

GWE

DS099_028_040803

DONE

GTS

GSR

GWE

Revision History

IOBs
- IOB Overview
- ESD Protection
- - CLB Overview
    - Main Logic Paths
        
        
        
        Port Aspect Ratios
        
        
        
        
        
        
        
        
        DLL Frequency Modes
        
        
        
        
        
        
        DFS Frequency Modes
        
        
        
        Phase Shifter (PS)
        
        
        
        
        
        
        
        Interconnect
        
        Configuration
        
        
        
        Configuration Modes
        
        Slave Serial Mode
        
        Master Serial Mode
        
        Slave Parallel Mode
        
        
        
        
        Readback
        
        Revision History

Page 18: R Spartan-3 1.2V FPGA Family: Functional Description€¦ · IFF2 Q SR Fixed Delay LVCMOS, LVTTL, PCI Single-ended Standards using V REF Differential Standards REV D CE CK Q SR REV

CLK

WE

DI

ADDR

DO

EN

DISABLED READ

XXXX 1111 2222 XXXX

aa bb cc dd

WRITEMEM(cc)=2222

DS099-2_16_030403

DS099-2_17_091302

A[170]

B[170]

P[350]MULT18X18

A[170]

B[170]

CLK

CE

RST

P[350]MULT18X18S

DS099-2_07_040103

PSINCDECPSEN

PSCLK

CLKIN

CLKFB

RSTSTATUS [70]

LOCKED8

CLKFX180

CLKFX

CLK0

PSDONE

ClockDistribution

StatusLogic

DFSDLL

PhaseShifter

Del

ay T

aps

Out

put S

tage

Inpu

t Sta

ge

DCM

DS099-2_08_041103

CLKINDelay

n

CLKFB

RST

CLK0

CLK90

CLK180

CLK270

CLK2X

CLK2X180

CLKDV

Out

put S

ectio

n

Control

Delayn-1

PhaseDetection

LOCKED

Delay2

Delay1

Mode Support

Low Frequency

High Frequency

Yes Yes

Yes No

Yes Yes

Yes No

Yes Yes

NONE 1X 2X

LOW HIGH

TRUE FALSE

15 2 25 3 35 4 45 5 55 60 65 70 75 8 9 10 11 12 13 14 15 and 16

TRUE FALSE

DS099-2_09_071003

CLK2X180

CLK0

ClockNet Delay

BUFGMUX

BUFG

FPGA

CLKIN

DCM

CLKFB

CLK2X180

CLK0

ClockNet Delay

IBUFG

FPGA

CLKIN

DCM

CLKFB

OBUFG

CLK2X

IBUFG

FPGA

CLKIN

DCM

CLKFB

OBUFG

CLK0CLK90

CLK180CLK270CLKDV

CLK2X180

CLK2X

ClockNet Delay

BUFGMUX

BUFG

FPGA

CLKIN

DCM

CLKFB

CLK0CLK90

CLK180CLK270CLKDV

CLK2X180

Phase

0o 90o 180o 270o 0o 90o 180o 270o 0o

DS099-2_10_031303

CLK2X

CLK2X180

CLKIN

CLKDV(1)

CLK0

CLK90

CLK180

CLK270

CLK0

CLK90

CLK180

CLK270

t

NONE FIXED VARIABLE

DS099-2_11_031303

CLKIN

CLKFB

TCLKINP

256

TCLKINP

256

0

ndash255 +255

CLKIN

TCLKINN

256

CLKIN

CLKFB

2 Reserved -

3 Reserved -

4 Reserved -

5 Reserved -

6 Reserved -

7 Reserved -

4

8

4

88

Horizontal Spine

Top

Spi

neB

otto

m S

pine

4

DCM DCM

Array Dependent

bull

DS099-2_18_070203

4 BUFGMUX

GCLK2GCLK3

GCLK0GCLK1

4 BUFGMUX

6 6 6 6 6

DS099-2_19_040103

(a) Long Line

8

DS099-2_20_040103

(b) Hex Line

CLB

2

CLB CLB

DS099-2_21_040103

CLBCLB CLB

DS099-2_22_040103

(d) Direct Lines

(c) Double Line

Device File Sizes

XC3S200 1047616 XCF01S XCF08P

XC3S400 1699136 XCF02S XCF08P

XC3S1000 3223488 XCF04S XCF08P

XC3S1500 5214784 XCF08P XCF08P

XC3S2000 7673024 XCF08P XCF08P

XC3S4000 11316864 XCF16P XCF16P

XC3S5000 13271936 XCF16P XCF16P

11491)

DOUTDIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Master

PROG_B

DIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Slave

PROG_B

DS099_23_041103

D0

CLK

CE

OERESET

CF

PlatformFlash PROM

XCF0xSor

XCFxxP

VCCINT

12V

VCCAUX

VCCO Bank 4

25V

47KΩAll

25V

VCCAUX VCCINT

VCCO Bank 412V

33V

VCC VCCJ

VCCO

25V

M0M1M2

GNDGNDGND

PROG_B

INIT_B

DONE

Spartan-3Slave

INIT_B

D[07]

CCLK

RDWR_B

BUSY

CS_B

PROG_B

DONE

CS_B

Spartan-3Slave

INIT_B

GND

D[07]

CCLK

RDWR_B

BUSY

CS_B

D[07]

CCLK

RDWR_B

BUSY

PROG_B

DONE

CS_B

DS099_24_041103

25V

M1M2M0

25V

M1M2M0

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

47KΩ 47KΩ

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

25V

GND

Spartan-3Master

D[07]

CCLK

PROG_B

DONE

INIT_B

DATA[07]

CCLK

RDWR_B

CS_B

CF

CE

OERESET

Platform Flash PROM

DS099_25_041103

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

GND

33V

VCC VCCJ

VCCO

25V

XCFxxP

25V

All47KΩ

Sample mode pins

No

Yes

NoCRCcorrect

YesNoReconfigure

Start-Upsequence

User mode

INIT_ B = High

PROG_B = Low

DS099_26_041103

Samplemode pins

Clearconfiguration

memory

No

Yes

No

Yes

Power-On

CRCcorrect

Shutdownsequence

Reconfigure

Start-Upsequence

User mode

INIT_B = High

PROG_B = Low

No

DS099_27_041103

Start-Up Clock

Default Cycles

Sync-to-DONE

0 1 2 3 4 5 6 7

0 1

DONE High

2 3 4 5 6 7

Phase

Start-Up Clock

Phase

DONE

GTS

GSR

GWE

DS099_028_040803

DONE

GTS

GSR

GWE

Revision History

IOBs
- IOB Overview
- ESD Protection
- - CLB Overview
    - Main Logic Paths
        
        
        
        Port Aspect Ratios
        
        
        
        
        
        
        
        
        DLL Frequency Modes
        
        
        
        
        
        
        DFS Frequency Modes
        
        
        
        Phase Shifter (PS)
        
        
        
        
        
        
        
        Interconnect
        
        Configuration
        
        
        
        Configuration Modes
        
        Slave Serial Mode
        
        Master Serial Mode
        
        Slave Parallel Mode
        
        
        
        
        Readback
        
        Revision History

Page 19: R Spartan-3 1.2V FPGA Family: Functional Description€¦ · IFF2 Q SR Fixed Delay LVCMOS, LVTTL, PCI Single-ended Standards using V REF Differential Standards REV D CE CK Q SR REV

DS099-2_07_040103

PSINCDECPSEN

PSCLK

CLKIN

CLKFB

RSTSTATUS [70]

LOCKED8

CLKFX180

CLKFX

CLK0

PSDONE

ClockDistribution

StatusLogic

DFSDLL

PhaseShifter

Del

ay T

aps

Out

put S

tage

Inpu

t Sta

ge

DCM

DS099-2_08_041103

CLKINDelay

n

CLKFB

RST

CLK0

CLK90

CLK180

CLK270

CLK2X

CLK2X180

CLKDV

Out

put S

ectio

n

Control

Delayn-1

PhaseDetection

LOCKED

Delay2

Delay1

Mode Support

Low Frequency

High Frequency

Yes Yes

Yes No

Yes Yes

Yes No

Yes Yes

NONE 1X 2X

LOW HIGH

TRUE FALSE

15 2 25 3 35 4 45 5 55 60 65 70 75 8 9 10 11 12 13 14 15 and 16

TRUE FALSE

DS099-2_09_071003

CLK2X180

CLK0

ClockNet Delay

BUFGMUX

BUFG

FPGA

CLKIN

DCM

CLKFB

CLK2X180

CLK0

ClockNet Delay

IBUFG

FPGA

CLKIN

DCM

CLKFB

OBUFG

CLK2X

IBUFG

FPGA

CLKIN

DCM

CLKFB

OBUFG

CLK0CLK90

CLK180CLK270CLKDV

CLK2X180

CLK2X

ClockNet Delay

BUFGMUX

BUFG

FPGA

CLKIN

DCM

CLKFB

CLK0CLK90

CLK180CLK270CLKDV

CLK2X180

Phase

0o 90o 180o 270o 0o 90o 180o 270o 0o

DS099-2_10_031303

CLK2X

CLK2X180

CLKIN

CLKDV(1)

CLK0

CLK90

CLK180

CLK270

CLK0

CLK90

CLK180

CLK270

t

NONE FIXED VARIABLE

DS099-2_11_031303

CLKIN

CLKFB

TCLKINP

256

TCLKINP

256

0

ndash255 +255

CLKIN

TCLKINN

256

CLKIN

CLKFB

2 Reserved -

3 Reserved -

4 Reserved -

5 Reserved -

6 Reserved -

7 Reserved -

4

8

4

88

Horizontal Spine

Top

Spi

neB

otto

m S

pine

4

DCM DCM

Array Dependent

bull

DS099-2_18_070203

4 BUFGMUX

GCLK2GCLK3

GCLK0GCLK1

4 BUFGMUX

6 6 6 6 6

DS099-2_19_040103

(a) Long Line

8

DS099-2_20_040103

(b) Hex Line

CLB

2

CLB CLB

DS099-2_21_040103

CLBCLB CLB

DS099-2_22_040103

(d) Direct Lines

(c) Double Line

Device File Sizes

XC3S200 1047616 XCF01S XCF08P

XC3S400 1699136 XCF02S XCF08P

XC3S1000 3223488 XCF04S XCF08P

XC3S1500 5214784 XCF08P XCF08P

XC3S2000 7673024 XCF08P XCF08P

XC3S4000 11316864 XCF16P XCF16P

XC3S5000 13271936 XCF16P XCF16P

11491)

DOUTDIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Master

PROG_B

DIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Slave

PROG_B

DS099_23_041103

D0

CLK

CE

OERESET

CF

PlatformFlash PROM

XCF0xSor

XCFxxP

VCCINT

12V

VCCAUX

VCCO Bank 4

25V

47KΩAll

25V

VCCAUX VCCINT

VCCO Bank 412V

33V

VCC VCCJ

VCCO

25V

M0M1M2

GNDGNDGND

PROG_B

INIT_B

DONE

Spartan-3Slave

INIT_B

D[07]

CCLK

RDWR_B

BUSY

CS_B

PROG_B

DONE

CS_B

Spartan-3Slave

INIT_B

GND

D[07]

CCLK

RDWR_B

BUSY

CS_B

D[07]

CCLK

RDWR_B

BUSY

PROG_B

DONE

CS_B

DS099_24_041103

25V

M1M2M0

25V

M1M2M0

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

47KΩ 47KΩ

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

25V

GND

Spartan-3Master

D[07]

CCLK

PROG_B

DONE

INIT_B

DATA[07]

CCLK

RDWR_B

CS_B

CF

CE

OERESET

Platform Flash PROM

DS099_25_041103

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

GND

33V

VCC VCCJ

VCCO

25V

XCFxxP

25V

All47KΩ

Sample mode pins

No

Yes

NoCRCcorrect

YesNoReconfigure

Start-Upsequence

User mode

INIT_ B = High

PROG_B = Low

DS099_26_041103

Samplemode pins

Clearconfiguration

memory

No

Yes

No

Yes

Power-On

CRCcorrect

Shutdownsequence

Reconfigure

Start-Upsequence

User mode

INIT_B = High

PROG_B = Low

No

DS099_27_041103

Start-Up Clock

Default Cycles

Sync-to-DONE

0 1 2 3 4 5 6 7

0 1

DONE High

2 3 4 5 6 7

Phase

Start-Up Clock

Phase

DONE

GTS

GSR

GWE

DS099_028_040803

DONE

GTS

GSR

GWE

Revision History

IOBs
- IOB Overview
- ESD Protection
- - CLB Overview
    - Main Logic Paths
        
        
        
        Port Aspect Ratios
        
        
        
        
        
        
        
        
        DLL Frequency Modes
        
        
        
        
        
        
        DFS Frequency Modes
        
        
        
        Phase Shifter (PS)
        
        
        
        
        
        
        
        Interconnect
        
        Configuration
        
        
        
        Configuration Modes
        
        Slave Serial Mode
        
        Master Serial Mode
        
        Slave Parallel Mode
        
        
        
        
        Readback
        
        Revision History

Page 20: R Spartan-3 1.2V FPGA Family: Functional Description€¦ · IFF2 Q SR Fixed Delay LVCMOS, LVTTL, PCI Single-ended Standards using V REF Differential Standards REV D CE CK Q SR REV

DS099-2_07_040103

PSINCDECPSEN

PSCLK

CLKIN

CLKFB

RSTSTATUS [70]

LOCKED8

CLKFX180

CLKFX

CLK0

PSDONE

ClockDistribution

StatusLogic

DFSDLL

PhaseShifter

Del

ay T

aps

Out

put S

tage

Inpu

t Sta

ge

DCM

DS099-2_08_041103

CLKINDelay

n

CLKFB

RST

CLK0

CLK90

CLK180

CLK270

CLK2X

CLK2X180

CLKDV

Out

put S

ectio

n

Control

Delayn-1

PhaseDetection

LOCKED

Delay2

Delay1

Mode Support

Low Frequency

High Frequency

Yes Yes

Yes No

Yes Yes

Yes No

Yes Yes

NONE 1X 2X

LOW HIGH

TRUE FALSE

15 2 25 3 35 4 45 5 55 60 65 70 75 8 9 10 11 12 13 14 15 and 16

TRUE FALSE

DS099-2_09_071003

CLK2X180

CLK0

ClockNet Delay

BUFGMUX

BUFG

FPGA

CLKIN

DCM

CLKFB

CLK2X180

CLK0

ClockNet Delay

IBUFG

FPGA

CLKIN

DCM

CLKFB

OBUFG

CLK2X

IBUFG

FPGA

CLKIN

DCM

CLKFB

OBUFG

CLK0CLK90

CLK180CLK270CLKDV

CLK2X180

CLK2X

ClockNet Delay

BUFGMUX

BUFG

FPGA

CLKIN

DCM

CLKFB

CLK0CLK90

CLK180CLK270CLKDV

CLK2X180

Phase

0o 90o 180o 270o 0o 90o 180o 270o 0o

DS099-2_10_031303

CLK2X

CLK2X180

CLKIN

CLKDV(1)

CLK0

CLK90

CLK180

CLK270

CLK0

CLK90

CLK180

CLK270

t

NONE FIXED VARIABLE

DS099-2_11_031303

CLKIN

CLKFB

TCLKINP

256

TCLKINP

256

0

ndash255 +255

CLKIN

TCLKINN

256

CLKIN

CLKFB

2 Reserved -

3 Reserved -

4 Reserved -

5 Reserved -

6 Reserved -

7 Reserved -

4

8

4

88

Horizontal Spine

Top

Spi

neB

otto

m S

pine

4

DCM DCM

Array Dependent

bull

DS099-2_18_070203

4 BUFGMUX

GCLK2GCLK3

GCLK0GCLK1

4 BUFGMUX

6 6 6 6 6

DS099-2_19_040103

(a) Long Line

8

DS099-2_20_040103

(b) Hex Line

CLB

2

CLB CLB

DS099-2_21_040103

CLBCLB CLB

DS099-2_22_040103

(d) Direct Lines

(c) Double Line

Device File Sizes

XC3S200 1047616 XCF01S XCF08P

XC3S400 1699136 XCF02S XCF08P

XC3S1000 3223488 XCF04S XCF08P

XC3S1500 5214784 XCF08P XCF08P

XC3S2000 7673024 XCF08P XCF08P

XC3S4000 11316864 XCF16P XCF16P

XC3S5000 13271936 XCF16P XCF16P

11491)

DOUTDIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Master

PROG_B

DIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Slave

PROG_B

DS099_23_041103

D0

CLK

CE

OERESET

CF

PlatformFlash PROM

XCF0xSor

XCFxxP

VCCINT

12V

VCCAUX

VCCO Bank 4

25V

47KΩAll

25V

VCCAUX VCCINT

VCCO Bank 412V

33V

VCC VCCJ

VCCO

25V

M0M1M2

GNDGNDGND

PROG_B

INIT_B

DONE

Spartan-3Slave

INIT_B

D[07]

CCLK

RDWR_B

BUSY

CS_B

PROG_B

DONE

CS_B

Spartan-3Slave

INIT_B

GND

D[07]

CCLK

RDWR_B

BUSY

CS_B

D[07]

CCLK

RDWR_B

BUSY

PROG_B

DONE

CS_B

DS099_24_041103

25V

M1M2M0

25V

M1M2M0

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

47KΩ 47KΩ

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

25V

GND

Spartan-3Master

D[07]

CCLK

PROG_B

DONE

INIT_B

DATA[07]

CCLK

RDWR_B

CS_B

CF

CE

OERESET

Platform Flash PROM

DS099_25_041103

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

GND

33V

VCC VCCJ

VCCO

25V

XCFxxP

25V

All47KΩ

Sample mode pins

No

Yes

NoCRCcorrect

YesNoReconfigure

Start-Upsequence

User mode

INIT_ B = High

PROG_B = Low

DS099_26_041103

Samplemode pins

Clearconfiguration

memory

No

Yes

No

Yes

Power-On

CRCcorrect

Shutdownsequence

Reconfigure

Start-Upsequence

User mode

INIT_B = High

PROG_B = Low

No

DS099_27_041103

Start-Up Clock

Default Cycles

Sync-to-DONE

0 1 2 3 4 5 6 7

0 1

DONE High

2 3 4 5 6 7

Phase

Start-Up Clock

Phase

DONE

GTS

GSR

GWE

DS099_028_040803

DONE

GTS

GSR

GWE

Revision History

IOBs
- IOB Overview
- ESD Protection
- - CLB Overview
    - Main Logic Paths
        
        
        
        Port Aspect Ratios
        
        
        
        
        
        
        
        
        DLL Frequency Modes
        
        
        
        
        
        
        DFS Frequency Modes
        
        
        
        Phase Shifter (PS)
        
        
        
        
        
        
        
        Interconnect
        
        Configuration
        
        
        
        Configuration Modes
        
        Slave Serial Mode
        
        Master Serial Mode
        
        Slave Parallel Mode
        
        
        
        
        Readback
        
        Revision History

Page 21: R Spartan-3 1.2V FPGA Family: Functional Description€¦ · IFF2 Q SR Fixed Delay LVCMOS, LVTTL, PCI Single-ended Standards using V REF Differential Standards REV D CE CK Q SR REV

Mode Support

Low Frequency

High Frequency

Yes Yes

Yes No

Yes Yes

Yes No

Yes Yes

NONE 1X 2X

LOW HIGH

TRUE FALSE

15 2 25 3 35 4 45 5 55 60 65 70 75 8 9 10 11 12 13 14 15 and 16

TRUE FALSE

DS099-2_09_071003

CLK2X180

CLK0

ClockNet Delay

BUFGMUX

BUFG

FPGA

CLKIN

DCM

CLKFB

CLK2X180

CLK0

ClockNet Delay

IBUFG

FPGA

CLKIN

DCM

CLKFB

OBUFG

CLK2X

IBUFG

FPGA

CLKIN

DCM

CLKFB

OBUFG

CLK0CLK90

CLK180CLK270CLKDV

CLK2X180

CLK2X

ClockNet Delay

BUFGMUX

BUFG

FPGA

CLKIN

DCM

CLKFB

CLK0CLK90

CLK180CLK270CLKDV

CLK2X180

Phase

0o 90o 180o 270o 0o 90o 180o 270o 0o

DS099-2_10_031303

CLK2X

CLK2X180

CLKIN

CLKDV(1)

CLK0

CLK90

CLK180

CLK270

CLK0

CLK90

CLK180

CLK270

t

NONE FIXED VARIABLE

DS099-2_11_031303

CLKIN

CLKFB

TCLKINP

256

TCLKINP

256

0

ndash255 +255

CLKIN

TCLKINN

256

CLKIN

CLKFB

2 Reserved -

3 Reserved -

4 Reserved -

5 Reserved -

6 Reserved -

7 Reserved -

4

8

4

88

Horizontal Spine

Top

Spi

neB

otto

m S

pine

4

DCM DCM

Array Dependent

bull

DS099-2_18_070203

4 BUFGMUX

GCLK2GCLK3

GCLK0GCLK1

4 BUFGMUX

6 6 6 6 6

DS099-2_19_040103

(a) Long Line

8

DS099-2_20_040103

(b) Hex Line

CLB

2

CLB CLB

DS099-2_21_040103

CLBCLB CLB

DS099-2_22_040103

(d) Direct Lines

(c) Double Line

Device File Sizes

XC3S200 1047616 XCF01S XCF08P

XC3S400 1699136 XCF02S XCF08P

XC3S1000 3223488 XCF04S XCF08P

XC3S1500 5214784 XCF08P XCF08P

XC3S2000 7673024 XCF08P XCF08P

XC3S4000 11316864 XCF16P XCF16P

XC3S5000 13271936 XCF16P XCF16P

11491)

DOUTDIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Master

PROG_B

DIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Slave

PROG_B

DS099_23_041103

D0

CLK

CE

OERESET

CF

PlatformFlash PROM

XCF0xSor

XCFxxP

VCCINT

12V

VCCAUX

VCCO Bank 4

25V

47KΩAll

25V

VCCAUX VCCINT

VCCO Bank 412V

33V

VCC VCCJ

VCCO

25V

M0M1M2

GNDGNDGND

PROG_B

INIT_B

DONE

Spartan-3Slave

INIT_B

D[07]

CCLK

RDWR_B

BUSY

CS_B

PROG_B

DONE

CS_B

Spartan-3Slave

INIT_B

GND

D[07]

CCLK

RDWR_B

BUSY

CS_B

D[07]

CCLK

RDWR_B

BUSY

PROG_B

DONE

CS_B

DS099_24_041103

25V

M1M2M0

25V

M1M2M0

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

47KΩ 47KΩ

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

25V

GND

Spartan-3Master

D[07]

CCLK

PROG_B

DONE

INIT_B

DATA[07]

CCLK

RDWR_B

CS_B

CF

CE

OERESET

Platform Flash PROM

DS099_25_041103

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

GND

33V

VCC VCCJ

VCCO

25V

XCFxxP

25V

All47KΩ

Sample mode pins

No

Yes

NoCRCcorrect

YesNoReconfigure

Start-Upsequence

User mode

INIT_ B = High

PROG_B = Low

DS099_26_041103

Samplemode pins

Clearconfiguration

memory

No

Yes

No

Yes

Power-On

CRCcorrect

Shutdownsequence

Reconfigure

Start-Upsequence

User mode

INIT_B = High

PROG_B = Low

No

DS099_27_041103

Start-Up Clock

Default Cycles

Sync-to-DONE

0 1 2 3 4 5 6 7

0 1

DONE High

2 3 4 5 6 7

Phase

Start-Up Clock

Phase

DONE

GTS

GSR

GWE

DS099_028_040803

DONE

GTS

GSR

GWE

Revision History

IOBs
- IOB Overview
- ESD Protection
- - CLB Overview
    - Main Logic Paths
        
        
        
        Port Aspect Ratios
        
        
        
        
        
        
        
        
        DLL Frequency Modes
        
        
        
        
        
        
        DFS Frequency Modes
        
        
        
        Phase Shifter (PS)
        
        
        
        
        
        
        
        Interconnect
        
        Configuration
        
        
        
        Configuration Modes
        
        Slave Serial Mode
        
        Master Serial Mode
        
        Slave Parallel Mode
        
        
        
        
        Readback
        
        Revision History

Page 22: R Spartan-3 1.2V FPGA Family: Functional Description€¦ · IFF2 Q SR Fixed Delay LVCMOS, LVTTL, PCI Single-ended Standards using V REF Differential Standards REV D CE CK Q SR REV

NONE 1X 2X

LOW HIGH

TRUE FALSE

15 2 25 3 35 4 45 5 55 60 65 70 75 8 9 10 11 12 13 14 15 and 16

TRUE FALSE

DS099-2_09_071003

CLK2X180

CLK0

ClockNet Delay

BUFGMUX

BUFG

FPGA

CLKIN

DCM

CLKFB

CLK2X180

CLK0

ClockNet Delay

IBUFG

FPGA

CLKIN

DCM

CLKFB

OBUFG

CLK2X

IBUFG

FPGA

CLKIN

DCM

CLKFB

OBUFG

CLK0CLK90

CLK180CLK270CLKDV

CLK2X180

CLK2X

ClockNet Delay

BUFGMUX

BUFG

FPGA

CLKIN

DCM

CLKFB

CLK0CLK90

CLK180CLK270CLKDV

CLK2X180

Phase

0o 90o 180o 270o 0o 90o 180o 270o 0o

DS099-2_10_031303

CLK2X

CLK2X180

CLKIN

CLKDV(1)

CLK0

CLK90

CLK180

CLK270

CLK0

CLK90

CLK180

CLK270

t

NONE FIXED VARIABLE

DS099-2_11_031303

CLKIN

CLKFB

TCLKINP

256

TCLKINP

256

0

ndash255 +255

CLKIN

TCLKINN

256

CLKIN

CLKFB

2 Reserved -

3 Reserved -

4 Reserved -

5 Reserved -

6 Reserved -

7 Reserved -

4

8

4

88

Horizontal Spine

Top

Spi

neB

otto

m S

pine

4

DCM DCM

Array Dependent

bull

DS099-2_18_070203

4 BUFGMUX

GCLK2GCLK3

GCLK0GCLK1

4 BUFGMUX

6 6 6 6 6

DS099-2_19_040103

(a) Long Line

8

DS099-2_20_040103

(b) Hex Line

CLB

2

CLB CLB

DS099-2_21_040103

CLBCLB CLB

DS099-2_22_040103

(d) Direct Lines

(c) Double Line

Device File Sizes

XC3S200 1047616 XCF01S XCF08P

XC3S400 1699136 XCF02S XCF08P

XC3S1000 3223488 XCF04S XCF08P

XC3S1500 5214784 XCF08P XCF08P

XC3S2000 7673024 XCF08P XCF08P

XC3S4000 11316864 XCF16P XCF16P

XC3S5000 13271936 XCF16P XCF16P

11491)

DOUTDIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Master

PROG_B

DIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Slave

PROG_B

DS099_23_041103

D0

CLK

CE

OERESET

CF

PlatformFlash PROM

XCF0xSor

XCFxxP

VCCINT

12V

VCCAUX

VCCO Bank 4

25V

47KΩAll

25V

VCCAUX VCCINT

VCCO Bank 412V

33V

VCC VCCJ

VCCO

25V

M0M1M2

GNDGNDGND

PROG_B

INIT_B

DONE

Spartan-3Slave

INIT_B

D[07]

CCLK

RDWR_B

BUSY

CS_B

PROG_B

DONE

CS_B

Spartan-3Slave

INIT_B

GND

D[07]

CCLK

RDWR_B

BUSY

CS_B

D[07]

CCLK

RDWR_B

BUSY

PROG_B

DONE

CS_B

DS099_24_041103

25V

M1M2M0

25V

M1M2M0

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

47KΩ 47KΩ

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

25V

GND

Spartan-3Master

D[07]

CCLK

PROG_B

DONE

INIT_B

DATA[07]

CCLK

RDWR_B

CS_B

CF

CE

OERESET

Platform Flash PROM

DS099_25_041103

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

GND

33V

VCC VCCJ

VCCO

25V

XCFxxP

25V

All47KΩ

Sample mode pins

No

Yes

NoCRCcorrect

YesNoReconfigure

Start-Upsequence

User mode

INIT_ B = High

PROG_B = Low

DS099_26_041103

Samplemode pins

Clearconfiguration

memory

No

Yes

No

Yes

Power-On

CRCcorrect

Shutdownsequence

Reconfigure

Start-Upsequence

User mode

INIT_B = High

PROG_B = Low

No

DS099_27_041103

Start-Up Clock

Default Cycles

Sync-to-DONE

0 1 2 3 4 5 6 7

0 1

DONE High

2 3 4 5 6 7

Phase

Start-Up Clock

Phase

DONE

GTS

GSR

GWE

DS099_028_040803

DONE

GTS

GSR

GWE

Revision History

IOBs
- IOB Overview
- ESD Protection
- - CLB Overview
    - Main Logic Paths
        
        
        
        Port Aspect Ratios
        
        
        
        
        
        
        
        
        DLL Frequency Modes
        
        
        
        
        
        
        DFS Frequency Modes
        
        
        
        Phase Shifter (PS)
        
        
        
        
        
        
        
        Interconnect
        
        Configuration
        
        
        
        Configuration Modes
        
        Slave Serial Mode
        
        Master Serial Mode
        
        Slave Parallel Mode
        
        
        
        
        Readback
        
        Revision History

Page 23: R Spartan-3 1.2V FPGA Family: Functional Description€¦ · IFF2 Q SR Fixed Delay LVCMOS, LVTTL, PCI Single-ended Standards using V REF Differential Standards REV D CE CK Q SR REV

DS099-2_09_071003

CLK2X180

CLK0

ClockNet Delay

BUFGMUX

BUFG

FPGA

CLKIN

DCM

CLKFB

CLK2X180

CLK0

ClockNet Delay

IBUFG

FPGA

CLKIN

DCM

CLKFB

OBUFG

CLK2X

IBUFG

FPGA

CLKIN

DCM

CLKFB

OBUFG

CLK0CLK90

CLK180CLK270CLKDV

CLK2X180

CLK2X

ClockNet Delay

BUFGMUX

BUFG

FPGA

CLKIN

DCM

CLKFB

CLK0CLK90

CLK180CLK270CLKDV

CLK2X180

Phase

0o 90o 180o 270o 0o 90o 180o 270o 0o

DS099-2_10_031303

CLK2X

CLK2X180

CLKIN

CLKDV(1)

CLK0

CLK90

CLK180

CLK270

CLK0

CLK90

CLK180

CLK270

t

NONE FIXED VARIABLE

DS099-2_11_031303

CLKIN

CLKFB

TCLKINP

256

TCLKINP

256

0

ndash255 +255

CLKIN

TCLKINN

256

CLKIN

CLKFB

2 Reserved -

3 Reserved -

4 Reserved -

5 Reserved -

6 Reserved -

7 Reserved -

4

8

4

88

Horizontal Spine

Top

Spi

neB

otto

m S

pine

4

DCM DCM

Array Dependent

bull

DS099-2_18_070203

4 BUFGMUX

GCLK2GCLK3

GCLK0GCLK1

4 BUFGMUX

6 6 6 6 6

DS099-2_19_040103

(a) Long Line

8

DS099-2_20_040103

(b) Hex Line

CLB

2

CLB CLB

DS099-2_21_040103

CLBCLB CLB

DS099-2_22_040103

(d) Direct Lines

(c) Double Line

Device File Sizes

XC3S200 1047616 XCF01S XCF08P

XC3S400 1699136 XCF02S XCF08P

XC3S1000 3223488 XCF04S XCF08P

XC3S1500 5214784 XCF08P XCF08P

XC3S2000 7673024 XCF08P XCF08P

XC3S4000 11316864 XCF16P XCF16P

XC3S5000 13271936 XCF16P XCF16P

11491)

DOUTDIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Master

PROG_B

DIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Slave

PROG_B

DS099_23_041103

D0

CLK

CE

OERESET

CF

PlatformFlash PROM

XCF0xSor

XCFxxP

VCCINT

12V

VCCAUX

VCCO Bank 4

25V

47KΩAll

25V

VCCAUX VCCINT

VCCO Bank 412V

33V

VCC VCCJ

VCCO

25V

M0M1M2

GNDGNDGND

PROG_B

INIT_B

DONE

Spartan-3Slave

INIT_B

D[07]

CCLK

RDWR_B

BUSY

CS_B

PROG_B

DONE

CS_B

Spartan-3Slave

INIT_B

GND

D[07]

CCLK

RDWR_B

BUSY

CS_B

D[07]

CCLK

RDWR_B

BUSY

PROG_B

DONE

CS_B

DS099_24_041103

25V

M1M2M0

25V

M1M2M0

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

47KΩ 47KΩ

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

25V

GND

Spartan-3Master

D[07]

CCLK

PROG_B

DONE

INIT_B

DATA[07]

CCLK

RDWR_B

CS_B

CF

CE

OERESET

Platform Flash PROM

DS099_25_041103

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

GND

33V

VCC VCCJ

VCCO

25V

XCFxxP

25V

All47KΩ

Sample mode pins

No

Yes

NoCRCcorrect

YesNoReconfigure

Start-Upsequence

User mode

INIT_ B = High

PROG_B = Low

DS099_26_041103

Samplemode pins

Clearconfiguration

memory

No

Yes

No

Yes

Power-On

CRCcorrect

Shutdownsequence

Reconfigure

Start-Upsequence

User mode

INIT_B = High

PROG_B = Low

No

DS099_27_041103

Start-Up Clock

Default Cycles

Sync-to-DONE

0 1 2 3 4 5 6 7

0 1

DONE High

2 3 4 5 6 7

Phase

Start-Up Clock

Phase

DONE

GTS

GSR

GWE

DS099_028_040803

DONE

GTS

GSR

GWE

Revision History

IOBs
- IOB Overview
- ESD Protection
- - CLB Overview
    - Main Logic Paths
        
        
        
        Port Aspect Ratios
        
        
        
        
        
        
        
        
        DLL Frequency Modes
        
        
        
        
        
        
        DFS Frequency Modes
        
        
        
        Phase Shifter (PS)
        
        
        
        
        
        
        
        Interconnect
        
        Configuration
        
        
        
        Configuration Modes
        
        Slave Serial Mode
        
        Master Serial Mode
        
        Slave Parallel Mode
        
        
        
        
        Readback
        
        Revision History

Page 24: R Spartan-3 1.2V FPGA Family: Functional Description€¦ · IFF2 Q SR Fixed Delay LVCMOS, LVTTL, PCI Single-ended Standards using V REF Differential Standards REV D CE CK Q SR REV

Phase

0o 90o 180o 270o 0o 90o 180o 270o 0o

DS099-2_10_031303

CLK2X

CLK2X180

CLKIN

CLKDV(1)

CLK0

CLK90

CLK180

CLK270

CLK0

CLK90

CLK180

CLK270

t

NONE FIXED VARIABLE

DS099-2_11_031303

CLKIN

CLKFB

TCLKINP

256

TCLKINP

256

0

ndash255 +255

CLKIN

TCLKINN

256

CLKIN

CLKFB

2 Reserved -

3 Reserved -

4 Reserved -

5 Reserved -

6 Reserved -

7 Reserved -

4

8

4

88

Horizontal Spine

Top

Spi

neB

otto

m S

pine

4

DCM DCM

Array Dependent

bull

DS099-2_18_070203

4 BUFGMUX

GCLK2GCLK3

GCLK0GCLK1

4 BUFGMUX

6 6 6 6 6

DS099-2_19_040103

(a) Long Line

8

DS099-2_20_040103

(b) Hex Line

CLB

2

CLB CLB

DS099-2_21_040103

CLBCLB CLB

DS099-2_22_040103

(d) Direct Lines

(c) Double Line

Device File Sizes

XC3S200 1047616 XCF01S XCF08P

XC3S400 1699136 XCF02S XCF08P

XC3S1000 3223488 XCF04S XCF08P

XC3S1500 5214784 XCF08P XCF08P

XC3S2000 7673024 XCF08P XCF08P

XC3S4000 11316864 XCF16P XCF16P

XC3S5000 13271936 XCF16P XCF16P

11491)

DOUTDIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Master

PROG_B

DIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Slave

PROG_B

DS099_23_041103

D0

CLK

CE

OERESET

CF

PlatformFlash PROM

XCF0xSor

XCFxxP

VCCINT

12V

VCCAUX

VCCO Bank 4

25V

47KΩAll

25V

VCCAUX VCCINT

VCCO Bank 412V

33V

VCC VCCJ

VCCO

25V

M0M1M2

GNDGNDGND

PROG_B

INIT_B

DONE

Spartan-3Slave

INIT_B

D[07]

CCLK

RDWR_B

BUSY

CS_B

PROG_B

DONE

CS_B

Spartan-3Slave

INIT_B

GND

D[07]

CCLK

RDWR_B

BUSY

CS_B

D[07]

CCLK

RDWR_B

BUSY

PROG_B

DONE

CS_B

DS099_24_041103

25V

M1M2M0

25V

M1M2M0

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

47KΩ 47KΩ

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

25V

GND

Spartan-3Master

D[07]

CCLK

PROG_B

DONE

INIT_B

DATA[07]

CCLK

RDWR_B

CS_B

CF

CE

OERESET

Platform Flash PROM

DS099_25_041103

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

GND

33V

VCC VCCJ

VCCO

25V

XCFxxP

25V

All47KΩ

Sample mode pins

No

Yes

NoCRCcorrect

YesNoReconfigure

Start-Upsequence

User mode

INIT_ B = High

PROG_B = Low

DS099_26_041103

Samplemode pins

Clearconfiguration

memory

No

Yes

No

Yes

Power-On

CRCcorrect

Shutdownsequence

Reconfigure

Start-Upsequence

User mode

INIT_B = High

PROG_B = Low

No

DS099_27_041103

Start-Up Clock

Default Cycles

Sync-to-DONE

0 1 2 3 4 5 6 7

0 1

DONE High

2 3 4 5 6 7

Phase

Start-Up Clock

Phase

DONE

GTS

GSR

GWE

DS099_028_040803

DONE

GTS

GSR

GWE

Revision History

IOBs
- IOB Overview
- ESD Protection
- - CLB Overview
    - Main Logic Paths
        
        
        
        Port Aspect Ratios
        
        
        
        
        
        
        
        
        DLL Frequency Modes
        
        
        
        
        
        
        DFS Frequency Modes
        
        
        
        Phase Shifter (PS)
        
        
        
        
        
        
        
        Interconnect
        
        Configuration
        
        
        
        Configuration Modes
        
        Slave Serial Mode
        
        Master Serial Mode
        
        Slave Parallel Mode
        
        
        
        
        Readback
        
        Revision History

Page 25: R Spartan-3 1.2V FPGA Family: Functional Description€¦ · IFF2 Q SR Fixed Delay LVCMOS, LVTTL, PCI Single-ended Standards using V REF Differential Standards REV D CE CK Q SR REV

NONE FIXED VARIABLE

DS099-2_11_031303

CLKIN

CLKFB

TCLKINP

256

TCLKINP

256

0

ndash255 +255

CLKIN

TCLKINN

256

CLKIN

CLKFB

2 Reserved -

3 Reserved -

4 Reserved -

5 Reserved -

6 Reserved -

7 Reserved -

4

8

4

88

Horizontal Spine

Top

Spi

neB

otto

m S

pine

4

DCM DCM

Array Dependent

bull

DS099-2_18_070203

4 BUFGMUX

GCLK2GCLK3

GCLK0GCLK1

4 BUFGMUX

6 6 6 6 6

DS099-2_19_040103

(a) Long Line

8

DS099-2_20_040103

(b) Hex Line

CLB

2

CLB CLB

DS099-2_21_040103

CLBCLB CLB

DS099-2_22_040103

(d) Direct Lines

(c) Double Line

Device File Sizes

XC3S200 1047616 XCF01S XCF08P

XC3S400 1699136 XCF02S XCF08P

XC3S1000 3223488 XCF04S XCF08P

XC3S1500 5214784 XCF08P XCF08P

XC3S2000 7673024 XCF08P XCF08P

XC3S4000 11316864 XCF16P XCF16P

XC3S5000 13271936 XCF16P XCF16P

11491)

DOUTDIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Master

PROG_B

DIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Slave

PROG_B

DS099_23_041103

D0

CLK

CE

OERESET

CF

PlatformFlash PROM

XCF0xSor

XCFxxP

VCCINT

12V

VCCAUX

VCCO Bank 4

25V

47KΩAll

25V

VCCAUX VCCINT

VCCO Bank 412V

33V

VCC VCCJ

VCCO

25V

M0M1M2

GNDGNDGND

PROG_B

INIT_B

DONE

Spartan-3Slave

INIT_B

D[07]

CCLK

RDWR_B

BUSY

CS_B

PROG_B

DONE

CS_B

Spartan-3Slave

INIT_B

GND

D[07]

CCLK

RDWR_B

BUSY

CS_B

D[07]

CCLK

RDWR_B

BUSY

PROG_B

DONE

CS_B

DS099_24_041103

25V

M1M2M0

25V

M1M2M0

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

47KΩ 47KΩ

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

25V

GND

Spartan-3Master

D[07]

CCLK

PROG_B

DONE

INIT_B

DATA[07]

CCLK

RDWR_B

CS_B

CF

CE

OERESET

Platform Flash PROM

DS099_25_041103

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

GND

33V

VCC VCCJ

VCCO

25V

XCFxxP

25V

All47KΩ

Sample mode pins

No

Yes

NoCRCcorrect

YesNoReconfigure

Start-Upsequence

User mode

INIT_ B = High

PROG_B = Low

DS099_26_041103

Samplemode pins

Clearconfiguration

memory

No

Yes

No

Yes

Power-On

CRCcorrect

Shutdownsequence

Reconfigure

Start-Upsequence

User mode

INIT_B = High

PROG_B = Low

No

DS099_27_041103

Start-Up Clock

Default Cycles

Sync-to-DONE

0 1 2 3 4 5 6 7

0 1

DONE High

2 3 4 5 6 7

Phase

Start-Up Clock

Phase

DONE

GTS

GSR

GWE

DS099_028_040803

DONE

GTS

GSR

GWE

Revision History

IOBs
- IOB Overview
- ESD Protection
- - CLB Overview
    - Main Logic Paths
        
        
        
        Port Aspect Ratios
        
        
        
        
        
        
        
        
        DLL Frequency Modes
        
        
        
        
        
        
        DFS Frequency Modes
        
        
        
        Phase Shifter (PS)
        
        
        
        
        
        
        
        Interconnect
        
        Configuration
        
        
        
        Configuration Modes
        
        Slave Serial Mode
        
        Master Serial Mode
        
        Slave Parallel Mode
        
        
        
        
        Readback
        
        Revision History

Page 26: R Spartan-3 1.2V FPGA Family: Functional Description€¦ · IFF2 Q SR Fixed Delay LVCMOS, LVTTL, PCI Single-ended Standards using V REF Differential Standards REV D CE CK Q SR REV

NONE FIXED VARIABLE

DS099-2_11_031303

CLKIN

CLKFB

TCLKINP

256

TCLKINP

256

0

ndash255 +255

CLKIN

TCLKINN

256

CLKIN

CLKFB

2 Reserved -

3 Reserved -

4 Reserved -

5 Reserved -

6 Reserved -

7 Reserved -

4

8

4

88

Horizontal Spine

Top

Spi

neB

otto

m S

pine

4

DCM DCM

Array Dependent

bull

DS099-2_18_070203

4 BUFGMUX

GCLK2GCLK3

GCLK0GCLK1

4 BUFGMUX

6 6 6 6 6

DS099-2_19_040103

(a) Long Line

8

DS099-2_20_040103

(b) Hex Line

CLB

2

CLB CLB

DS099-2_21_040103

CLBCLB CLB

DS099-2_22_040103

(d) Direct Lines

(c) Double Line

Device File Sizes

XC3S200 1047616 XCF01S XCF08P

XC3S400 1699136 XCF02S XCF08P

XC3S1000 3223488 XCF04S XCF08P

XC3S1500 5214784 XCF08P XCF08P

XC3S2000 7673024 XCF08P XCF08P

XC3S4000 11316864 XCF16P XCF16P

XC3S5000 13271936 XCF16P XCF16P

11491)

DOUTDIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Master

PROG_B

DIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Slave

PROG_B

DS099_23_041103

D0

CLK

CE

OERESET

CF

PlatformFlash PROM

XCF0xSor

XCFxxP

VCCINT

12V

VCCAUX

VCCO Bank 4

25V

47KΩAll

25V

VCCAUX VCCINT

VCCO Bank 412V

33V

VCC VCCJ

VCCO

25V

M0M1M2

GNDGNDGND

PROG_B

INIT_B

DONE

Spartan-3Slave

INIT_B

D[07]

CCLK

RDWR_B

BUSY

CS_B

PROG_B

DONE

CS_B

Spartan-3Slave

INIT_B

GND

D[07]

CCLK

RDWR_B

BUSY

CS_B

D[07]

CCLK

RDWR_B

BUSY

PROG_B

DONE

CS_B

DS099_24_041103

25V

M1M2M0

25V

M1M2M0

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

47KΩ 47KΩ

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

25V

GND

Spartan-3Master

D[07]

CCLK

PROG_B

DONE

INIT_B

DATA[07]

CCLK

RDWR_B

CS_B

CF

CE

OERESET

Platform Flash PROM

DS099_25_041103

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

GND

33V

VCC VCCJ

VCCO

25V

XCFxxP

25V

All47KΩ

Sample mode pins

No

Yes

NoCRCcorrect

YesNoReconfigure

Start-Upsequence

User mode

INIT_ B = High

PROG_B = Low

DS099_26_041103

Samplemode pins

Clearconfiguration

memory

No

Yes

No

Yes

Power-On

CRCcorrect

Shutdownsequence

Reconfigure

Start-Upsequence

User mode

INIT_B = High

PROG_B = Low

No

DS099_27_041103

Start-Up Clock

Default Cycles

Sync-to-DONE

0 1 2 3 4 5 6 7

0 1

DONE High

2 3 4 5 6 7

Phase

Start-Up Clock

Phase

DONE

GTS

GSR

GWE

DS099_028_040803

DONE

GTS

GSR

GWE

Revision History

IOBs
- IOB Overview
- ESD Protection
- - CLB Overview
    - Main Logic Paths
        
        
        
        Port Aspect Ratios
        
        
        
        
        
        
        
        
        DLL Frequency Modes
        
        
        
        
        
        
        DFS Frequency Modes
        
        
        
        Phase Shifter (PS)
        
        
        
        
        
        
        
        Interconnect
        
        Configuration
        
        
        
        Configuration Modes
        
        Slave Serial Mode
        
        Master Serial Mode
        
        Slave Parallel Mode
        
        
        
        
        Readback
        
        Revision History

Page 27: R Spartan-3 1.2V FPGA Family: Functional Description€¦ · IFF2 Q SR Fixed Delay LVCMOS, LVTTL, PCI Single-ended Standards using V REF Differential Standards REV D CE CK Q SR REV

DS099-2_11_031303

CLKIN

CLKFB

TCLKINP

256

TCLKINP

256

0

ndash255 +255

CLKIN

TCLKINN

256

CLKIN

CLKFB

2 Reserved -

3 Reserved -

4 Reserved -

5 Reserved -

6 Reserved -

7 Reserved -

4

8

4

88

Horizontal Spine

Top

Spi

neB

otto

m S

pine

4

DCM DCM

Array Dependent

bull

DS099-2_18_070203

4 BUFGMUX

GCLK2GCLK3

GCLK0GCLK1

4 BUFGMUX

6 6 6 6 6

DS099-2_19_040103

(a) Long Line

8

DS099-2_20_040103

(b) Hex Line

CLB

2

CLB CLB

DS099-2_21_040103

CLBCLB CLB

DS099-2_22_040103

(d) Direct Lines

(c) Double Line

Device File Sizes

XC3S200 1047616 XCF01S XCF08P

XC3S400 1699136 XCF02S XCF08P

XC3S1000 3223488 XCF04S XCF08P

XC3S1500 5214784 XCF08P XCF08P

XC3S2000 7673024 XCF08P XCF08P

XC3S4000 11316864 XCF16P XCF16P

XC3S5000 13271936 XCF16P XCF16P

11491)

DOUTDIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Master

PROG_B

DIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Slave

PROG_B

DS099_23_041103

D0

CLK

CE

OERESET

CF

PlatformFlash PROM

XCF0xSor

XCFxxP

VCCINT

12V

VCCAUX

VCCO Bank 4

25V

47KΩAll

25V

VCCAUX VCCINT

VCCO Bank 412V

33V

VCC VCCJ

VCCO

25V

M0M1M2

GNDGNDGND

PROG_B

INIT_B

DONE

Spartan-3Slave

INIT_B

D[07]

CCLK

RDWR_B

BUSY

CS_B

PROG_B

DONE

CS_B

Spartan-3Slave

INIT_B

GND

D[07]

CCLK

RDWR_B

BUSY

CS_B

D[07]

CCLK

RDWR_B

BUSY

PROG_B

DONE

CS_B

DS099_24_041103

25V

M1M2M0

25V

M1M2M0

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

47KΩ 47KΩ

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

25V

GND

Spartan-3Master

D[07]

CCLK

PROG_B

DONE

INIT_B

DATA[07]

CCLK

RDWR_B

CS_B

CF

CE

OERESET

Platform Flash PROM

DS099_25_041103

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

GND

33V

VCC VCCJ

VCCO

25V

XCFxxP

25V

All47KΩ

Sample mode pins

No

Yes

NoCRCcorrect

YesNoReconfigure

Start-Upsequence

User mode

INIT_ B = High

PROG_B = Low

DS099_26_041103

Samplemode pins

Clearconfiguration

memory

No

Yes

No

Yes

Power-On

CRCcorrect

Shutdownsequence

Reconfigure

Start-Upsequence

User mode

INIT_B = High

PROG_B = Low

No

DS099_27_041103

Start-Up Clock

Default Cycles

Sync-to-DONE

0 1 2 3 4 5 6 7

0 1

DONE High

2 3 4 5 6 7

Phase

Start-Up Clock

Phase

DONE

GTS

GSR

GWE

DS099_028_040803

DONE

GTS

GSR

GWE

Revision History

IOBs
- IOB Overview
- ESD Protection
- - CLB Overview
    - Main Logic Paths
        
        
        
        Port Aspect Ratios
        
        
        
        
        
        
        
        
        DLL Frequency Modes
        
        
        
        
        
        
        DFS Frequency Modes
        
        
        
        Phase Shifter (PS)
        
        
        
        
        
        
        
        Interconnect
        
        Configuration
        
        
        
        Configuration Modes
        
        Slave Serial Mode
        
        Master Serial Mode
        
        Slave Parallel Mode
        
        
        
        
        Readback
        
        Revision History

Page 28: R Spartan-3 1.2V FPGA Family: Functional Description€¦ · IFF2 Q SR Fixed Delay LVCMOS, LVTTL, PCI Single-ended Standards using V REF Differential Standards REV D CE CK Q SR REV

2 Reserved -

3 Reserved -

4 Reserved -

5 Reserved -

6 Reserved -

7 Reserved -

4

8

4

88

Horizontal Spine

Top

Spi

neB

otto

m S

pine

4

DCM DCM

Array Dependent

bull

DS099-2_18_070203

4 BUFGMUX

GCLK2GCLK3

GCLK0GCLK1

4 BUFGMUX

6 6 6 6 6

DS099-2_19_040103

(a) Long Line

8

DS099-2_20_040103

(b) Hex Line

CLB

2

CLB CLB

DS099-2_21_040103

CLBCLB CLB

DS099-2_22_040103

(d) Direct Lines

(c) Double Line

Device File Sizes

XC3S200 1047616 XCF01S XCF08P

XC3S400 1699136 XCF02S XCF08P

XC3S1000 3223488 XCF04S XCF08P

XC3S1500 5214784 XCF08P XCF08P

XC3S2000 7673024 XCF08P XCF08P

XC3S4000 11316864 XCF16P XCF16P

XC3S5000 13271936 XCF16P XCF16P

11491)

DOUTDIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Master

PROG_B

DIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Slave

PROG_B

DS099_23_041103

D0

CLK

CE

OERESET

CF

PlatformFlash PROM

XCF0xSor

XCFxxP

VCCINT

12V

VCCAUX

VCCO Bank 4

25V

47KΩAll

25V

VCCAUX VCCINT

VCCO Bank 412V

33V

VCC VCCJ

VCCO

25V

M0M1M2

GNDGNDGND

PROG_B

INIT_B

DONE

Spartan-3Slave

INIT_B

D[07]

CCLK

RDWR_B

BUSY

CS_B

PROG_B

DONE

CS_B

Spartan-3Slave

INIT_B

GND

D[07]

CCLK

RDWR_B

BUSY

CS_B

D[07]

CCLK

RDWR_B

BUSY

PROG_B

DONE

CS_B

DS099_24_041103

25V

M1M2M0

25V

M1M2M0

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

47KΩ 47KΩ

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

25V

GND

Spartan-3Master

D[07]

CCLK

PROG_B

DONE

INIT_B

DATA[07]

CCLK

RDWR_B

CS_B

CF

CE

OERESET

Platform Flash PROM

DS099_25_041103

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

GND

33V

VCC VCCJ

VCCO

25V

XCFxxP

25V

All47KΩ

Sample mode pins

No

Yes

NoCRCcorrect

YesNoReconfigure

Start-Upsequence

User mode

INIT_ B = High

PROG_B = Low

DS099_26_041103

Samplemode pins

Clearconfiguration

memory

No

Yes

No

Yes

Power-On

CRCcorrect

Shutdownsequence

Reconfigure

Start-Upsequence

User mode

INIT_B = High

PROG_B = Low

No

DS099_27_041103

Start-Up Clock

Default Cycles

Sync-to-DONE

0 1 2 3 4 5 6 7

0 1

DONE High

2 3 4 5 6 7

Phase

Start-Up Clock

Phase

DONE

GTS

GSR

GWE

DS099_028_040803

DONE

GTS

GSR

GWE

Revision History

IOBs
- IOB Overview
- ESD Protection
- - CLB Overview
    - Main Logic Paths
        
        
        
        Port Aspect Ratios
        
        
        
        
        
        
        
        
        DLL Frequency Modes
        
        
        
        
        
        
        DFS Frequency Modes
        
        
        
        Phase Shifter (PS)
        
        
        
        
        
        
        
        Interconnect
        
        Configuration
        
        
        
        Configuration Modes
        
        Slave Serial Mode
        
        Master Serial Mode
        
        Slave Parallel Mode
        
        
        
        
        Readback
        
        Revision History

Page 29: R Spartan-3 1.2V FPGA Family: Functional Description€¦ · IFF2 Q SR Fixed Delay LVCMOS, LVTTL, PCI Single-ended Standards using V REF Differential Standards REV D CE CK Q SR REV

2 Reserved -

3 Reserved -

4 Reserved -

5 Reserved -

6 Reserved -

7 Reserved -

4

8

4

88

Horizontal Spine

Top

Spi

neB

otto

m S

pine

4

DCM DCM

Array Dependent

bull

DS099-2_18_070203

4 BUFGMUX

GCLK2GCLK3

GCLK0GCLK1

4 BUFGMUX

6 6 6 6 6

DS099-2_19_040103

(a) Long Line

8

DS099-2_20_040103

(b) Hex Line

CLB

2

CLB CLB

DS099-2_21_040103

CLBCLB CLB

DS099-2_22_040103

(d) Direct Lines

(c) Double Line

Device File Sizes

XC3S200 1047616 XCF01S XCF08P

XC3S400 1699136 XCF02S XCF08P

XC3S1000 3223488 XCF04S XCF08P

XC3S1500 5214784 XCF08P XCF08P

XC3S2000 7673024 XCF08P XCF08P

XC3S4000 11316864 XCF16P XCF16P

XC3S5000 13271936 XCF16P XCF16P

11491)

DOUTDIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Master

PROG_B

DIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Slave

PROG_B

DS099_23_041103

D0

CLK

CE

OERESET

CF

PlatformFlash PROM

XCF0xSor

XCFxxP

VCCINT

12V

VCCAUX

VCCO Bank 4

25V

47KΩAll

25V

VCCAUX VCCINT

VCCO Bank 412V

33V

VCC VCCJ

VCCO

25V

M0M1M2

GNDGNDGND

PROG_B

INIT_B

DONE

Spartan-3Slave

INIT_B

D[07]

CCLK

RDWR_B

BUSY

CS_B

PROG_B

DONE

CS_B

Spartan-3Slave

INIT_B

GND

D[07]

CCLK

RDWR_B

BUSY

CS_B

D[07]

CCLK

RDWR_B

BUSY

PROG_B

DONE

CS_B

DS099_24_041103

25V

M1M2M0

25V

M1M2M0

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

47KΩ 47KΩ

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

25V

GND

Spartan-3Master

D[07]

CCLK

PROG_B

DONE

INIT_B

DATA[07]

CCLK

RDWR_B

CS_B

CF

CE

OERESET

Platform Flash PROM

DS099_25_041103

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

GND

33V

VCC VCCJ

VCCO

25V

XCFxxP

25V

All47KΩ

Sample mode pins

No

Yes

NoCRCcorrect

YesNoReconfigure

Start-Upsequence

User mode

INIT_ B = High

PROG_B = Low

DS099_26_041103

Samplemode pins

Clearconfiguration

memory

No

Yes

No

Yes

Power-On

CRCcorrect

Shutdownsequence

Reconfigure

Start-Upsequence

User mode

INIT_B = High

PROG_B = Low

No

DS099_27_041103

Start-Up Clock

Default Cycles

Sync-to-DONE

0 1 2 3 4 5 6 7

0 1

DONE High

2 3 4 5 6 7

Phase

Start-Up Clock

Phase

DONE

GTS

GSR

GWE

DS099_028_040803

DONE

GTS

GSR

GWE

Revision History

IOBs
- IOB Overview
- ESD Protection
- - CLB Overview
    - Main Logic Paths
        
        
        
        Port Aspect Ratios
        
        
        
        
        
        
        
        
        DLL Frequency Modes
        
        
        
        
        
        
        DFS Frequency Modes
        
        
        
        Phase Shifter (PS)
        
        
        
        
        
        
        
        Interconnect
        
        Configuration
        
        
        
        Configuration Modes
        
        Slave Serial Mode
        
        Master Serial Mode
        
        Slave Parallel Mode
        
        
        
        
        Readback
        
        Revision History

Page 30: R Spartan-3 1.2V FPGA Family: Functional Description€¦ · IFF2 Q SR Fixed Delay LVCMOS, LVTTL, PCI Single-ended Standards using V REF Differential Standards REV D CE CK Q SR REV

4

8

4

88

Horizontal Spine

Top

Spi

neB

otto

m S

pine

4

DCM DCM

Array Dependent

bull

DS099-2_18_070203

4 BUFGMUX

GCLK2GCLK3

GCLK0GCLK1

4 BUFGMUX

6 6 6 6 6

DS099-2_19_040103

(a) Long Line

8

DS099-2_20_040103

(b) Hex Line

CLB

2

CLB CLB

DS099-2_21_040103

CLBCLB CLB

DS099-2_22_040103

(d) Direct Lines

(c) Double Line

Device File Sizes

XC3S200 1047616 XCF01S XCF08P

XC3S400 1699136 XCF02S XCF08P

XC3S1000 3223488 XCF04S XCF08P

XC3S1500 5214784 XCF08P XCF08P

XC3S2000 7673024 XCF08P XCF08P

XC3S4000 11316864 XCF16P XCF16P

XC3S5000 13271936 XCF16P XCF16P

11491)

DOUTDIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Master

PROG_B

DIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Slave

PROG_B

DS099_23_041103

D0

CLK

CE

OERESET

CF

PlatformFlash PROM

XCF0xSor

XCFxxP

VCCINT

12V

VCCAUX

VCCO Bank 4

25V

47KΩAll

25V

VCCAUX VCCINT

VCCO Bank 412V

33V

VCC VCCJ

VCCO

25V

M0M1M2

GNDGNDGND

PROG_B

INIT_B

DONE

Spartan-3Slave

INIT_B

D[07]

CCLK

RDWR_B

BUSY

CS_B

PROG_B

DONE

CS_B

Spartan-3Slave

INIT_B

GND

D[07]

CCLK

RDWR_B

BUSY

CS_B

D[07]

CCLK

RDWR_B

BUSY

PROG_B

DONE

CS_B

DS099_24_041103

25V

M1M2M0

25V

M1M2M0

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

47KΩ 47KΩ

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

25V

GND

Spartan-3Master

D[07]

CCLK

PROG_B

DONE

INIT_B

DATA[07]

CCLK

RDWR_B

CS_B

CF

CE

OERESET

Platform Flash PROM

DS099_25_041103

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

GND

33V

VCC VCCJ

VCCO

25V

XCFxxP

25V

All47KΩ

Sample mode pins

No

Yes

NoCRCcorrect

YesNoReconfigure

Start-Upsequence

User mode

INIT_ B = High

PROG_B = Low

DS099_26_041103

Samplemode pins

Clearconfiguration

memory

No

Yes

No

Yes

Power-On

CRCcorrect

Shutdownsequence

Reconfigure

Start-Upsequence

User mode

INIT_B = High

PROG_B = Low

No

DS099_27_041103

Start-Up Clock

Default Cycles

Sync-to-DONE

0 1 2 3 4 5 6 7

0 1

DONE High

2 3 4 5 6 7

Phase

Start-Up Clock

Phase

DONE

GTS

GSR

GWE

DS099_028_040803

DONE

GTS

GSR

GWE

Revision History

IOBs
- IOB Overview
- ESD Protection
- - CLB Overview
    - Main Logic Paths
        
        
        
        Port Aspect Ratios
        
        
        
        
        
        
        
        
        DLL Frequency Modes
        
        
        
        
        
        
        DFS Frequency Modes
        
        
        
        Phase Shifter (PS)
        
        
        
        
        
        
        
        Interconnect
        
        Configuration
        
        
        
        Configuration Modes
        
        Slave Serial Mode
        
        Master Serial Mode
        
        Slave Parallel Mode
        
        
        
        
        Readback
        
        Revision History

Page 31: R Spartan-3 1.2V FPGA Family: Functional Description€¦ · IFF2 Q SR Fixed Delay LVCMOS, LVTTL, PCI Single-ended Standards using V REF Differential Standards REV D CE CK Q SR REV

6 6 6 6 6

DS099-2_19_040103

(a) Long Line

8

DS099-2_20_040103

(b) Hex Line

CLB

2

CLB CLB

DS099-2_21_040103

CLBCLB CLB

DS099-2_22_040103

(d) Direct Lines

(c) Double Line

Device File Sizes

XC3S200 1047616 XCF01S XCF08P

XC3S400 1699136 XCF02S XCF08P

XC3S1000 3223488 XCF04S XCF08P

XC3S1500 5214784 XCF08P XCF08P

XC3S2000 7673024 XCF08P XCF08P

XC3S4000 11316864 XCF16P XCF16P

XC3S5000 13271936 XCF16P XCF16P

11491)

DOUTDIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Master

PROG_B

DIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Slave

PROG_B

DS099_23_041103

D0

CLK

CE

OERESET

CF

PlatformFlash PROM

XCF0xSor

XCFxxP

VCCINT

12V

VCCAUX

VCCO Bank 4

25V

47KΩAll

25V

VCCAUX VCCINT

VCCO Bank 412V

33V

VCC VCCJ

VCCO

25V

M0M1M2

GNDGNDGND

PROG_B

INIT_B

DONE

Spartan-3Slave

INIT_B

D[07]

CCLK

RDWR_B

BUSY

CS_B

PROG_B

DONE

CS_B

Spartan-3Slave

INIT_B

GND

D[07]

CCLK

RDWR_B

BUSY

CS_B

D[07]

CCLK

RDWR_B

BUSY

PROG_B

DONE

CS_B

DS099_24_041103

25V

M1M2M0

25V

M1M2M0

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

47KΩ 47KΩ

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

25V

GND

Spartan-3Master

D[07]

CCLK

PROG_B

DONE

INIT_B

DATA[07]

CCLK

RDWR_B

CS_B

CF

CE

OERESET

Platform Flash PROM

DS099_25_041103

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

GND

33V

VCC VCCJ

VCCO

25V

XCFxxP

25V

All47KΩ

Sample mode pins

No

Yes

NoCRCcorrect

YesNoReconfigure

Start-Upsequence

User mode

INIT_ B = High

PROG_B = Low

DS099_26_041103

Samplemode pins

Clearconfiguration

memory

No

Yes

No

Yes

Power-On

CRCcorrect

Shutdownsequence

Reconfigure

Start-Upsequence

User mode

INIT_B = High

PROG_B = Low

No

DS099_27_041103

Start-Up Clock

Default Cycles

Sync-to-DONE

0 1 2 3 4 5 6 7

0 1

DONE High

2 3 4 5 6 7

Phase

Start-Up Clock

Phase

DONE

GTS

GSR

GWE

DS099_028_040803

DONE

GTS

GSR

GWE

Revision History

IOBs
- IOB Overview
- ESD Protection
- - CLB Overview
    - Main Logic Paths
        
        
        
        Port Aspect Ratios
        
        
        
        
        
        
        
        
        DLL Frequency Modes
        
        
        
        
        
        
        DFS Frequency Modes
        
        
        
        Phase Shifter (PS)
        
        
        
        
        
        
        
        Interconnect
        
        Configuration
        
        
        
        Configuration Modes
        
        Slave Serial Mode
        
        Master Serial Mode
        
        Slave Parallel Mode
        
        
        
        
        Readback
        
        Revision History

Page 32: R Spartan-3 1.2V FPGA Family: Functional Description€¦ · IFF2 Q SR Fixed Delay LVCMOS, LVTTL, PCI Single-ended Standards using V REF Differential Standards REV D CE CK Q SR REV

Device File Sizes

XC3S200 1047616 XCF01S XCF08P

XC3S400 1699136 XCF02S XCF08P

XC3S1000 3223488 XCF04S XCF08P

XC3S1500 5214784 XCF08P XCF08P

XC3S2000 7673024 XCF08P XCF08P

XC3S4000 11316864 XCF16P XCF16P

XC3S5000 13271936 XCF16P XCF16P

11491)

DOUTDIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Master

PROG_B

DIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Slave

PROG_B

DS099_23_041103

D0

CLK

CE

OERESET

CF

PlatformFlash PROM

XCF0xSor

XCFxxP

VCCINT

12V

VCCAUX

VCCO Bank 4

25V

47KΩAll

25V

VCCAUX VCCINT

VCCO Bank 412V

33V

VCC VCCJ

VCCO

25V

M0M1M2

GNDGNDGND

PROG_B

INIT_B

DONE

Spartan-3Slave

INIT_B

D[07]

CCLK

RDWR_B

BUSY

CS_B

PROG_B

DONE

CS_B

Spartan-3Slave

INIT_B

GND

D[07]

CCLK

RDWR_B

BUSY

CS_B

D[07]

CCLK

RDWR_B

BUSY

PROG_B

DONE

CS_B

DS099_24_041103

25V

M1M2M0

25V

M1M2M0

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

47KΩ 47KΩ

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

25V

GND

Spartan-3Master

D[07]

CCLK

PROG_B

DONE

INIT_B

DATA[07]

CCLK

RDWR_B

CS_B

CF

CE

OERESET

Platform Flash PROM

DS099_25_041103

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

GND

33V

VCC VCCJ

VCCO

25V

XCFxxP

25V

All47KΩ

Sample mode pins

No

Yes

NoCRCcorrect

YesNoReconfigure

Start-Upsequence

User mode

INIT_ B = High

PROG_B = Low

DS099_26_041103

Samplemode pins

Clearconfiguration

memory

No

Yes

No

Yes

Power-On

CRCcorrect

Shutdownsequence

Reconfigure

Start-Upsequence

User mode

INIT_B = High

PROG_B = Low

No

DS099_27_041103

Start-Up Clock

Default Cycles

Sync-to-DONE

0 1 2 3 4 5 6 7

0 1

DONE High

2 3 4 5 6 7

Phase

Start-Up Clock

Phase

DONE

GTS

GSR

GWE

DS099_028_040803

DONE

GTS

GSR

GWE

Revision History

IOBs
- IOB Overview
- ESD Protection
- - CLB Overview
    - Main Logic Paths
        
        
        
        Port Aspect Ratios
        
        
        
        
        
        
        
        
        DLL Frequency Modes
        
        
        
        
        
        
        DFS Frequency Modes
        
        
        
        Phase Shifter (PS)
        
        
        
        
        
        
        
        Interconnect
        
        Configuration
        
        
        
        Configuration Modes
        
        Slave Serial Mode
        
        Master Serial Mode
        
        Slave Parallel Mode
        
        
        
        
        Readback
        
        Revision History

Page 33: R Spartan-3 1.2V FPGA Family: Functional Description€¦ · IFF2 Q SR Fixed Delay LVCMOS, LVTTL, PCI Single-ended Standards using V REF Differential Standards REV D CE CK Q SR REV

11491)

DOUTDIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Master

PROG_B

DIN

CCLK

DONE

INIT_B

Spartan-3FPGA

Slave

PROG_B

DS099_23_041103

D0

CLK

CE

OERESET

CF

PlatformFlash PROM

XCF0xSor

XCFxxP

VCCINT

12V

VCCAUX

VCCO Bank 4

25V

47KΩAll

25V

VCCAUX VCCINT

VCCO Bank 412V

33V

VCC VCCJ

VCCO

25V

M0M1M2

GNDGNDGND

PROG_B

INIT_B

DONE

Spartan-3Slave

INIT_B

D[07]

CCLK

RDWR_B

BUSY

CS_B

PROG_B

DONE

CS_B

Spartan-3Slave

INIT_B

GND

D[07]

CCLK

RDWR_B

BUSY

CS_B

D[07]

CCLK

RDWR_B

BUSY

PROG_B

DONE

CS_B

DS099_24_041103

25V

M1M2M0

25V

M1M2M0

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

47KΩ 47KΩ

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

25V

GND

Spartan-3Master

D[07]

CCLK

PROG_B

DONE

INIT_B

DATA[07]

CCLK

RDWR_B

CS_B

CF

CE

OERESET

Platform Flash PROM

DS099_25_041103

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

GND

33V

VCC VCCJ

VCCO

25V

XCFxxP

25V

All47KΩ

Sample mode pins

No

Yes

NoCRCcorrect

YesNoReconfigure

Start-Upsequence

User mode

INIT_ B = High

PROG_B = Low

DS099_26_041103

Samplemode pins

Clearconfiguration

memory

No

Yes

No

Yes

Power-On

CRCcorrect

Shutdownsequence

Reconfigure

Start-Upsequence

User mode

INIT_B = High

PROG_B = Low

No

DS099_27_041103

Start-Up Clock

Default Cycles

Sync-to-DONE

0 1 2 3 4 5 6 7

0 1

DONE High

2 3 4 5 6 7

Phase

Start-Up Clock

Phase

DONE

GTS

GSR

GWE

DS099_028_040803

DONE

GTS

GSR

GWE

Revision History

IOBs
- IOB Overview
- ESD Protection
- - CLB Overview
    - Main Logic Paths
        
        
        
        Port Aspect Ratios
        
        
        
        
        
        
        
        
        DLL Frequency Modes
        
        
        
        
        
        
        DFS Frequency Modes
        
        
        
        Phase Shifter (PS)
        
        
        
        
        
        
        
        Interconnect
        
        Configuration
        
        
        
        Configuration Modes
        
        Slave Serial Mode
        
        Master Serial Mode
        
        Slave Parallel Mode
        
        
        
        
        Readback
        
        Revision History

Page 34: R Spartan-3 1.2V FPGA Family: Functional Description€¦ · IFF2 Q SR Fixed Delay LVCMOS, LVTTL, PCI Single-ended Standards using V REF Differential Standards REV D CE CK Q SR REV

PROG_B

INIT_B

DONE

Spartan-3Slave

INIT_B

D[07]

CCLK

RDWR_B

BUSY

CS_B

PROG_B

DONE

CS_B

Spartan-3Slave

INIT_B

GND

D[07]

CCLK

RDWR_B

BUSY

CS_B

D[07]

CCLK

RDWR_B

BUSY

PROG_B

DONE

CS_B

DS099_24_041103

25V

M1M2M0

25V

M1M2M0

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

47KΩ 47KΩ

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

25V

GND

Spartan-3Master

D[07]

CCLK

PROG_B

DONE

INIT_B

DATA[07]

CCLK

RDWR_B

CS_B

CF

CE

OERESET

Platform Flash PROM

DS099_25_041103

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

GND

33V

VCC VCCJ

VCCO

25V

XCFxxP

25V

All47KΩ

Sample mode pins

No

Yes

NoCRCcorrect

YesNoReconfigure

Start-Upsequence

User mode

INIT_ B = High

PROG_B = Low

DS099_26_041103

Samplemode pins

Clearconfiguration

memory

No

Yes

No

Yes

Power-On

CRCcorrect

Shutdownsequence

Reconfigure

Start-Upsequence

User mode

INIT_B = High

PROG_B = Low

No

DS099_27_041103

Start-Up Clock

Default Cycles

Sync-to-DONE

0 1 2 3 4 5 6 7

0 1

DONE High

2 3 4 5 6 7

Phase

Start-Up Clock

Phase

DONE

GTS

GSR

GWE

DS099_028_040803

DONE

GTS

GSR

GWE

Revision History

IOBs
- IOB Overview
- ESD Protection
- - CLB Overview
    - Main Logic Paths
        
        
        
        Port Aspect Ratios
        
        
        
        
        
        
        
        
        DLL Frequency Modes
        
        
        
        
        
        
        DFS Frequency Modes
        
        
        
        Phase Shifter (PS)
        
        
        
        
        
        
        
        Interconnect
        
        Configuration
        
        
        
        Configuration Modes
        
        Slave Serial Mode
        
        Master Serial Mode
        
        Slave Parallel Mode
        
        
        
        
        Readback
        
        Revision History

Page 35: R Spartan-3 1.2V FPGA Family: Functional Description€¦ · IFF2 Q SR Fixed Delay LVCMOS, LVTTL, PCI Single-ended Standards using V REF Differential Standards REV D CE CK Q SR REV

PROG_B

INIT_B

DONE

Spartan-3Slave

INIT_B

D[07]

CCLK

RDWR_B

BUSY

CS_B

PROG_B

DONE

CS_B

Spartan-3Slave

INIT_B

GND

D[07]

CCLK

RDWR_B

BUSY

CS_B

D[07]

CCLK

RDWR_B

BUSY

PROG_B

DONE

CS_B

DS099_24_041103

25V

M1M2M0

25V

M1M2M0

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

47KΩ 47KΩ

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

25V

GND

Spartan-3Master

D[07]

CCLK

PROG_B

DONE

INIT_B

DATA[07]

CCLK

RDWR_B

CS_B

CF

CE

OERESET

Platform Flash PROM

DS099_25_041103

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

GND

33V

VCC VCCJ

VCCO

25V

XCFxxP

25V

All47KΩ

Sample mode pins

No

Yes

NoCRCcorrect

YesNoReconfigure

Start-Upsequence

User mode

INIT_ B = High

PROG_B = Low

DS099_26_041103

Samplemode pins

Clearconfiguration

memory

No

Yes

No

Yes

Power-On

CRCcorrect

Shutdownsequence

Reconfigure

Start-Upsequence

User mode

INIT_B = High

PROG_B = Low

No

DS099_27_041103

Start-Up Clock

Default Cycles

Sync-to-DONE

0 1 2 3 4 5 6 7

0 1

DONE High

2 3 4 5 6 7

Phase

Start-Up Clock

Phase

DONE

GTS

GSR

GWE

DS099_028_040803

DONE

GTS

GSR

GWE

Revision History

IOBs
- IOB Overview
- ESD Protection
- - CLB Overview
    - Main Logic Paths
        
        
        
        Port Aspect Ratios
        
        
        
        
        
        
        
        
        DLL Frequency Modes
        
        
        
        
        
        
        DFS Frequency Modes
        
        
        
        Phase Shifter (PS)
        
        
        
        
        
        
        
        Interconnect
        
        Configuration
        
        
        
        Configuration Modes
        
        Slave Serial Mode
        
        Master Serial Mode
        
        Slave Parallel Mode
        
        
        
        
        Readback
        
        Revision History

Page 36: R Spartan-3 1.2V FPGA Family: Functional Description€¦ · IFF2 Q SR Fixed Delay LVCMOS, LVTTL, PCI Single-ended Standards using V REF Differential Standards REV D CE CK Q SR REV

Spartan-3Master

D[07]

CCLK

PROG_B

DONE

INIT_B

DATA[07]

CCLK

RDWR_B

CS_B

CF

CE

OERESET

Platform Flash PROM

DS099_25_041103

25V

VCCAUX

VCCO Banks 4 amp 5

VCCINT

12V

GND

33V

VCC VCCJ

VCCO

25V

XCFxxP

25V

All47KΩ

Sample mode pins

No

Yes

NoCRCcorrect

YesNoReconfigure

Start-Upsequence

User mode

INIT_ B = High

PROG_B = Low

DS099_26_041103

Samplemode pins

Clearconfiguration

memory

No

Yes

No

Yes

Power-On

CRCcorrect

Shutdownsequence

Reconfigure

Start-Upsequence

User mode

INIT_B = High

PROG_B = Low

No

DS099_27_041103

Start-Up Clock

Default Cycles

Sync-to-DONE

0 1 2 3 4 5 6 7

0 1

DONE High

2 3 4 5 6 7

Phase

Start-Up Clock

Phase

DONE

GTS

GSR

GWE

DS099_028_040803

DONE

GTS

GSR

GWE

Revision History

IOBs
- IOB Overview
- ESD Protection
- - CLB Overview
    - Main Logic Paths
        
        
        
        Port Aspect Ratios
        
        
        
        
        
        
        
        
        DLL Frequency Modes
        
        
        
        
        
        
        DFS Frequency Modes
        
        
        
        Phase Shifter (PS)
        
        
        
        
        
        
        
        Interconnect
        
        Configuration
        
        
        
        Configuration Modes
        
        Slave Serial Mode
        
        Master Serial Mode
        
        Slave Parallel Mode
        
        
        
        
        Readback
        
        Revision History

Page 37: R Spartan-3 1.2V FPGA Family: Functional Description€¦ · IFF2 Q SR Fixed Delay LVCMOS, LVTTL, PCI Single-ended Standards using V REF Differential Standards REV D CE CK Q SR REV

Sample mode pins

No

Yes

NoCRCcorrect

YesNoReconfigure

Start-Upsequence

User mode

INIT_ B = High

PROG_B = Low

DS099_26_041103

Samplemode pins

Clearconfiguration

memory

No

Yes

No

Yes

Power-On

CRCcorrect

Shutdownsequence

Reconfigure

Start-Upsequence

User mode

INIT_B = High

PROG_B = Low

No

DS099_27_041103

Start-Up Clock

Default Cycles

Sync-to-DONE

0 1 2 3 4 5 6 7

0 1

DONE High

2 3 4 5 6 7

Phase

Start-Up Clock

Phase

DONE

GTS

GSR

GWE

DS099_028_040803

DONE

GTS

GSR

GWE

Revision History

IOBs
- IOB Overview
- ESD Protection
- - CLB Overview
    - Main Logic Paths
        
        
        
        Port Aspect Ratios
        
        
        
        
        
        
        
        
        DLL Frequency Modes
        
        
        
        
        
        
        DFS Frequency Modes
        
        
        
        Phase Shifter (PS)
        
        
        
        
        
        
        
        Interconnect
        
        Configuration
        
        
        
        Configuration Modes
        
        Slave Serial Mode
        
        Master Serial Mode
        
        Slave Parallel Mode
        
        
        
        
        Readback
        
        Revision History

Page 38: R Spartan-3 1.2V FPGA Family: Functional Description€¦ · IFF2 Q SR Fixed Delay LVCMOS, LVTTL, PCI Single-ended Standards using V REF Differential Standards REV D CE CK Q SR REV

Samplemode pins

Clearconfiguration

memory

No

Yes

No

Yes

Power-On

CRCcorrect

Shutdownsequence

Reconfigure

Start-Upsequence

User mode

INIT_B = High

PROG_B = Low

No

DS099_27_041103

Start-Up Clock

Default Cycles

Sync-to-DONE

0 1 2 3 4 5 6 7

0 1

DONE High

2 3 4 5 6 7

Phase

Start-Up Clock

Phase

DONE

GTS

GSR

GWE

DS099_028_040803

DONE

GTS

GSR

GWE

Revision History

IOBs
- IOB Overview
- ESD Protection
- - CLB Overview
    - Main Logic Paths
        
        
        
        Port Aspect Ratios
        
        
        
        
        
        
        
        
        DLL Frequency Modes
        
        
        
        
        
        
        DFS Frequency Modes
        
        
        
        Phase Shifter (PS)
        
        
        
        
        
        
        
        Interconnect
        
        Configuration
        
        
        
        Configuration Modes
        
        Slave Serial Mode
        
        Master Serial Mode
        
        Slave Parallel Mode
        
        
        
        
        Readback
        
        Revision History

Page 39: R Spartan-3 1.2V FPGA Family: Functional Description€¦ · IFF2 Q SR Fixed Delay LVCMOS, LVTTL, PCI Single-ended Standards using V REF Differential Standards REV D CE CK Q SR REV

Start-Up Clock

Default Cycles

Sync-to-DONE

0 1 2 3 4 5 6 7

0 1

DONE High

2 3 4 5 6 7

Phase

Start-Up Clock

Phase

DONE

GTS

GSR

GWE

DS099_028_040803

DONE

GTS

GSR

GWE

Revision History

IOBs
- IOB Overview
- ESD Protection
- - CLB Overview
    - Main Logic Paths
        
        
        
        Port Aspect Ratios
        
        
        
        
        
        
        
        
        DLL Frequency Modes
        
        
        
        
        
        
        DFS Frequency Modes
        
        
        
        Phase Shifter (PS)
        
        
        
        
        
        
        
        Interconnect
        
        Configuration
        
        
        
        Configuration Modes
        
        Slave Serial Mode
        
        Master Serial Mode
        
        Slave Parallel Mode
        
        
        
        
        Readback
        
        Revision History

Page 40: R Spartan-3 1.2V FPGA Family: Functional Description€¦ · IFF2 Q SR Fixed Delay LVCMOS, LVTTL, PCI Single-ended Standards using V REF Differential Standards REV D CE CK Q SR REV

Revision History

IOBs
- IOB Overview
- ESD Protection
- - CLB Overview
    - Main Logic Paths
        
        
        
        Port Aspect Ratios
        
        
        
        
        
        
        
        
        DLL Frequency Modes
        
        
        
        
        
        
        DFS Frequency Modes
        
        
        
        Phase Shifter (PS)
        
        
        
        
        
        
        
        Interconnect
        
        Configuration
        
        
        
        Configuration Modes
        
        Slave Serial Mode
        
        Master Serial Mode
        
        Slave Parallel Mode
        
        
        
        
        Readback
        
        Revision History

Date post:	02-Aug-2020
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