IEEE TRANSACTIONS ON COMPUTERS, JULY 1970

Reviews of Papers in the Computer Field

D. L. EPLEY, Paper Reviews Editor

D. W. FIFE, A. I. RUBIN, R. A. SHORT, H. S. STONEAssistant Paper Reviews Editors

Please address your comments and suggestions to the Paper Reviews Editor: Donald L. Epley,Department of Electrical Engineering, University of Iowa, Iowa City, Iowa 52240.

A. SWITCHING AND AUTOMATA THEORY

R70-17 Asynchronous Sequential Circuits with Feedback-S. Singh(IEEE Trans. Computers, vol. C-18, pp. 440-450, May 1969).

In the design of synchronous sequential machines, various canonicalrealizations which make use of feedback shift registers have been devel-oped [1], [2]. This paper attempts to extend some of these results to realizeasynchronous machines in a similar manner.

In an earlier paper by Brzozowski and Singh [3], in which canonicalfeedback-free realizations of definite machines' were considered, theasynchronous unit delay (AUD) was introduced. The AUD is an n-inputn-output asynchronous sequential circuit in which the present value of theoutput n-tuple is equal to the value of the input n-tuple before the last inputchange.

Extending the results of the earlier paper [3] it is shown that any fun-damental mode asynchronous sequential machine M can be realized bya circuit of feedback index m with one (n + m) x (n + m) AUD element andm inertial delays2 where n is the number of binary inputs and mn is thesmallest integer not less than log2 S& where & is the maximum number ofstable states in any column of M. Realizations with the same feedbackindex have been obtained elsewhere [4], [5] and the relative virtues ofthese different realizations are debatable.

It is also shown that any fundamental mode asynchronous sequentialmachine M can be realized by an asynchronous circuit of feedback index 1with 1 inertial delay and a chain of k(n + 1) x (n + 1) AUD elements. Ineffect the chain of AUD elements operates as a synchronous shift register.The inertial delay elements are needed in order to prevent the circuit frommalfunctioning due to races and hazards.

The paper is generally well written and has several examples whichmake it easy to read. As with the related material on synchronous realiza-tions, the results seem to be primarily of theoretical rather than practicalsignificance at this time.

It should be noted that the realization of the AUD from basic gate ele-ments itself requires the presence of feedback. Hence the realizations con-sidered in this paper could really best be compared with minimum feedbackrealizations of synchronous machines using memory elements more com-plex than delay elements, such as SR flip-flops, a problem which, inciden-tally, has not been solved.

A. D. FRIEDMANBell Telephone Labs.Murray Hill, N. J.

1 A definite machine is a sequential machine in which the output is dependent only onthe last k values of the input for some finite value of k.

2 An inertial delay of magnitude D acts like a pure delay to pulses of width >D butdoes not respond to pulses of width < D.

REFERENCES

[1] J. A. Brzozowski, "An essay on feedback," Dept. of Elec. Engrg., University of Ottawa,Ontario, Canada, Tech. Rept. 65-2, March 1965.

[2] A. D. Friedman, "Feedback in synchronous sequential circuits," IEEE Trans. Elec-tronic Computers, vol. EC-1 5, pp. 354-367, June 1966.

[3] J. A. Brzozowski and S. Singh, "Definite asynchronous sequential circuits," IEFETrans. Computers, vol. C-17, pp. 18-26, January 1968.

[4] E. B. Eichelberger, "Sequential circuit synthesis using hazards and delays," Dept. ofElec. Engrg., Princeton University, Princeton, N. J., Digital System Tech. Rept. 19,June 1962.

[5] A. D. Friedman, "Feedback in asynchronous sequential circuits," IEEE Trans. Elec-tronic Computers, vol. EC-15, pp. 740-749, October 1966.

R70-18 Real-Time Computation by n-Dimensional Iterative Arrays ofFinite-State Machines-S. N. Cole (IEEE Trans. Computers, vol. C-18,pp. 349-365, April 1969).

The paper begins with a good formal introduction to iterative arrays,discussing briefly their relation to other automata, particularly the"tessellation structures" of Moore [1] and von Neumann [2]. Attention isthen restricted to iterative arrays viewed as real-time tape acceptors. Theauthor proves a speedup theorem, which shows how to speed up an arrayby a constant factor k. The speedup is done by using a length k encodingof the input tapes, and realizing blocks of the array as finite-state machinesin a new array which operates k times as fast. The complexity classes ofarrays defined by the author ignore the complexity of the modules ofwhich the array is composed. Thus, the speeded-up array is a member ofthe same class of arrays as the array whose behavior it imitates. The authorthen proves that the pattern of interconnection ("stencil") of any arraymay be reduced to allow direct communication only between nearestneighbors without reducing the real-time computing power of the array.This again involves increasing the complexity of the finite-state machinesin the array.

Arrays to accept two languages (YY and palindromes) are presented,and it is shown that the context-free languages neither contain nor arecontained in the set of languages accepted by real-time iterative arrays.The languages accepted are shown to be closed under union, intersection,and complementation, but not under reflection or concatenation. Theauthor constructs a language XA which he shows is not accepted by anyn-dimensional (real-time) iterative array, and which he elsewhere [3 ] showsis accepted by an (n + 1) dimensional iterative array. Thus, a hierarchy oflanguages is established, based on the dimension of the iterative arrayswhich-accept them.

While the speedup theorem the author obtains is of some interest, thisresult shares with many others of this type a certain lack of practical ap-plicability. It can only be obtained by lumping together all finite-stateautomata without regard to their relative complexities. The stencil reduc-tion result depends on this same lumping of automata. In this respect, theauthor's approach can be seen to be radically different from those of

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IEEE TRANSACTIONS ON COMPUTERS, JULY 1970

von Neumann [2], Codd [4], and others who attempt to achieve variouscomputational goals using minimal (for example, fewest states) primitivemodules. Input and output are all done from a single machine, which,while no theoretical limitation because of the lumping of finite-state ma-chines, is a further dissimilarity between the author's arrays and practicalparallel-processing computing schemes.

Together, the results on the hierarchy (based on dimension) and thepower of arrays with a simple stencil (only nearest neighbors) constitutea principle that having an extra dimension available is more powerful thanmerely having a broader reach in fewer dimensions. It might be interestingto see how this principle would be affected by placing various restrictionson the classes of finite-state machines in the array.

ERIK D. GOODMANLogic of Computers GroupUniversity of MichiganAnn Arbor, Mich.

REFERENCES[1] E. F. Moore, "Machines models of self-reproduction," Proc. Symp. in Applied Math.,

vol. 14, pp. 17-33, December 1962.[2] von Neumann, Theory of Self-Reproducing Automata, A. W. Burks, Ed. Urbana,

Ill.: University of Illinois Press, 1966.[3] S. N. Cole, "Real-time computation by iterative arrays of finite-state machines,"

Ph.D. dissertation, Dept. of Applied Mathematics, Harvard University, Cambridge,Mass., August 1964.

[4] E. F. Codd, Cellular Automata. New York: Academic Press, 1968.

R70-19 Frequency of Decomposability Among Machines with a LargeNumber of States-David E. Muller and Gianfranco R. Putzolu (J. Com-puter and System Sciences, vol. 2, pp. 219-227, 1969).

An arbitrary sequential machine M may or may not be able to be de-composed into a series-parallel interconnection of two or more smallermachines. It seems natural to ask the following.

1) What algebraic properties if possessed by M are sufficient to guar-antee that M admits a series-parallel decomposition?

2) What algebraic properties if possessed by M are sufficient to guar-antee that M does not admit a series-parallel decomposition?

3) What is the probability of a randomly chosen machine admitting a

series-parallel decomposition?

Muller and Putzolu consider these questions in their paper.Putzolu earlier considered these questions assuming state behavior

decompositions in which state splitting was not allowed. Under these con-

ditions he found that for a randomly chosen machineM with n states and plabeled inputs, the probability of nontrivially decomposing M approaches1 if (ln n)/p> and approaches 0 if (ln nlp) < 1 as n-c oo and p-+ o .

In the paper under review, the authors attack the more general decom-position case where state splitting is allowed. It seems reasonable that byallowing state splitting the probability of randomly chosen machineshaving nontrivial series-parallel decompositions should increase, and thisis proved by the authors. They show that with state splitting the probabilityof nontrivially decomposing a randomly chosen machine approaches 1 if(n/ln p)> 1 and approaches 0 if (n/ln p)< I as n-oo and p-+ oo.

The authors first develop sufficient conditions which guarantee that a

series-parallel decomposition exists, and then they develop sufficient con-ditions which guarantee the opposite. Their conditions are just slightlymore than sufficient, and they suggest it may be possible to relax themsomewhat. In particular, they feel that it may be possible to relax the suffi-cient conditions which guarantee that a decomposition does not exist.

In several places in the paper the authors state that "ifpn 12e&-no asn-- oo, then. . ". It seems that they intended to say that "if pn1/2e-"nas n-+oo and p-.+oo, then... ". In several other limit expressions in thepaper the authors again omit specifying that in addition to n-* ac, p alsomust approach infinity.

In summary, the paper is a rather elegant mathematical exercise andthe results add greater significance to the work of Hartmanis and Stearns,Zeiger, and Krohn and Rhodes.

MONROE NEWBORNDept. of Elec. Engrg.Columbia UniversityNew York, N. Y. 10027

R70-20 Sequential Boolean Equations-Shimon Even and Albert R.Meyer (IEEE Trans. Computers, vol. C-18, pp. 230-240, March 1969).

H. Wang ("Circuit synthesis by solving sequential Boolean equations,"Zeit. fir Math. Logik und Grundlagen der Math., vol. 5 pp. 291-322, 1959)pointed out that sequential Boolean equations, obtained by adding a se-quential operator to take care of the time element to the ordinary Booleanoperations, provided a convenient language for expressing conditions tobe satisfied by circuits or automata. Among other things he described algo-rithms for deciding whether an equation has a solution, and for decidingwhether it has a solution with finite delay. The present paper presentsalgorithms which are thought to be more efficient.

The basic equation considered is

E: F(X, Y, dY) =0.

Here X=X(t)=(xl(t), *, xm(t)), Y= Y(t)=(yj(t), y*,yj(t)) where thexi(t), yj(t) are Boolean-valued variables, dY(t)= Y(t+ 1), and F is aBoolean expression. It is said to have a solution if for every finite sequenceX(1),.* , X(L) of values of X there exists a sequence of values for Y,Y(1), , Y(L+ 1) such that E holds for all t= 1, 2, *.. , L. Similarly it issaid to have a solution with delay d if the knowledge of X(1), -* , X(d) issufficient to determine a value for Y(l). Thereafter, for all t, knowledge ofY(t), X(t), X(t +1), , X(t + d) is sufficient to determine a value forY(t + 1) so that the determined part of the sequence for Y is a part of asolution for the given sequence of X. The authors observe that the form Eincludes the apparently more general form G(X, Y, dX, dY) = 0 consideredby Wang, and of course finite sets of such equations; also, as Wang ob-served, equations involving d2 Y, d3 Y, etc.

The first result is that the problem of deciding whether E has a solutionis equivalent to the problem of deciding whether a finite labeled graph Gis solvable, i.e., whether for every tape on the alphabet E of labels thereexists a path on G whose sequence of label is the given tape. This is clearlyequivalent to the problem of deciding whether a nondeterministic autom-aton accepts all tapes, which is easily solvable. For solvability with delayd the treatment is similar but more complicated. Bounds are obtained forthe minimal possible delay which throw doubt on some of Wang's resultsfor this case. The paper contains a useful Appendix on the solution of or-dinary Boolean equations.

J. C. SHEPHERDSONUniversity of BristolBristol, England

R70-21 Time and Tape Complexity of Pushdown Automaton Languages-A. V. Aho, J. E. Hopcroft, and J. D. Ullman (Information and Control,vol. 13, pp. 186-206, 1968).

This paper is concerned with the recognition of words which are con-tained in languages defined by pushdown store machines. Such languagesexhibit many of the syntactic properties of algorithmic programming lan-guages. Thus the recognition problem for languages generated by push-down store machines is related to compilation of programming languages.A pushdown automaton (PDA) consists of a finite state control which

can scan an input tape and can read from and write onto a pushdown store.If the finite state control can scan the input tape in only one direction, it

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