R8C/13 Group Datasheetdocs-europe.electrocomponents.com/webdocs/0862/0900766b8086252… · Rev.1.20...

R8C/13 GroupSINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Rev.1.20 Jan 27, 2006 page 1 of 27REJ03B0069-0120

REJ03B0069-0120Rev.1.20

Jan 27, 2006

1. OverviewThis MCU is built using the high-performance silicon gate CMOS process using a R8C/Tiny Series CPU

core and is packaged in a 32-pin plastic molded LQFP. This MCU operates using sophisticated instructions

featuring a high level of instruction efficiency. With 1M bytes of address space, it is capable of executing

instructions at high speed.

The data flash ROM (2 KB X 2 blocks) is embedded.

1.1 Applications

Electric household appliance, office equipment, housing equipment (sensor, security), general industrial

equipment, audio, etc.


R8C/13 Group 1. Overview

Table 1.1 Performance outline

1.2 Performance OverviewTable 1.1. lists the performance outline of this MCU.

Item PerformanceCPU Number of basic instructions 89 instructions

Minimum instruction execution time 50 ns (f(XIN) = 20 MHZ, VCC = 3.0 to 5.5 V)100 ns (f(XIN) = 10 MHZ, VCC = 2.7 to 5.5 V)

Operating mode Single-chipAddress space 1M bytesMemory capacity See Table 1.2.

Peripheral Port Input/Output: 22 (including LED drive port), Input: 2function LED drive port I/O port: 8

Timer Timer X: 8 bits x 1 channel, Timer Y: 8 bits x 1 channel,Timer Z: 8 bits x 1 channel(Each timer equipped with 8-bit prescaler)Timer C: 16 bits x 1 channel

(Circuits of input capture and output compare)Serial interface •1 channel

Clock synchronous, UART•1 channelUART

A/D converter 10-bit A/D converter: 1 circuit, 12 channelsWatchdog timer 15 bits x 1 (with prescaler)

Reset start function selectableInterrupt Internal: 11 factors, External: 5 factors,

Software: 4 factors, Priority level: 7 levelsClock generation circuit 2 circuits

•Main clock generation circuit (Equipped with a built-infeedback resistor)•On-chip oscillator (high-speed, low-speed)

On high-speed on-chip oscillator the frequency adjust-ment function is usable.

Oscillation stop detection function Main clock oscillation stop detection functionVoltage detection circuit IncludedPower on reset circuit Included

Electrical Supply voltage VCC = 3.0 to 5.5V (f(XIN) = 20MHZ)characteristics VCC = 2.7 to 5.5V (f(XIN) = 10MHZ)

Power consumption Typ.9 mA (VCC = 5.0V, (f(XIN) = 20MHZ)Typ.5 mA (VCC = 3.0V, (f(XIN) = 10MHZ)Typ.35 µA (VCC = 3.0V, Wait mode, Peripheral clock stops)Typ.0.7 µA (VCC = 3.0V, Stop mode)

Flash memory Program/erase supply voltage VCC = 2.7 to 5.5 VProgram/erase endurance 10,000 times (Data flash)

1,000 times (Program ROM)Operating ambient temperature -20 to 85°C

-40 to 85°C (D-version)Package 32-pin plastic mold LQFP



1.3 Block DiagramFigure 1.1 shows this MCU block diagram.

Figure 1.1 Block Diagram

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UART(8 bits 1 channel)

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NOTES:1. ROM size depends on MCU type.2. RAM size depends on MCU type.

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1.4 Product InformationTable 1.2 lists the product information.

Table 1.2 Product Information

RAM capacityROM capacity

Package type RemarksType No.

As of January 2006

Flash memory versionR5F21132FP PLQP0032GB-A8K bytes 512 bytes

PLQP0032GB-A12K bytes 768 bytes

PLQP0032GB-A16K bytes 1K bytes

R5F21133FP

R5F21134FP

R5F21132DFP PLQP0032GB-A8K bytes 512 bytes

PLQP0032GB-A12K bytes 768 bytes

PLQP0032GB-A16K bytes 1K bytes

R5F21133DFP

R5F21134DFP

D version

Program ROM Data flash

2K bytes x 2

2K bytes x 2

2K bytes x 2

2K bytes x 2

2K bytes x 2

2K bytes x 2

Figure 1.2 Type No., Memory Size, and Package

Package type: FP : PLQP0032GB-A

ROM capacity: 2 : 8 KBytes. 3 : 12 KBytes. 4 : 16 KBytes.

Memory type: F: Flash memory version

Type No. R 5 F 21 13 4 D FP

R8C/13 group

R8C/Tiny series

Classification:D: Operating ambient temperature –40 °C to 85 °CNo symbol: Operating ambient temperature –20 °C to 85 °C

Renesas MCU

Renesas semiconductors



Package: PLQP0032GB-A (32P6U-A)

Figure 1.3 Pin Assignments (Top View)

PIN Assignments (top view)

1 2 3 4 5 6 7 8

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NOTES: 1. P47 functions only as an input port. 2. When using On-chip debugger, do not use P00/AN7/TxD11 and P37/TxD10/RxD1 pins. 3. Do not connect IVcc to Vcc.

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1.5 Pin AssignmentsFigure 1.3 shows the pin configuration (top view).



Signal name Pin name I/O typePower supply Vcc, Iinput VssIVcc IVcc O

Analog power AVcc, AVss Isupply input

Reset input___________

RESET ICNVss CNVss IMODE MODE IMain clock input XIN I

Main clock output XOUT O

_____

INT interrupt input_______ _______

INT0 to INT3 IKey input interrupt

_____ _____

KI0 to KI3 IinputTimer X CNTR0 I/O

__________

CNTR0 OTimer Y CNTR1 I/OTimer Z TZOUT OTimer C TCIN I

CMP00 to CMP02, OCMP10 to CMP12

Serial interface CLK0 I/ORxD0, RxD1 ITxD0, TxD10, OTxD11

Reference voltage VREF IinputA/D converter AN0 to AN11 II/O port P00 to P07, I/O

P10 to P17,P30 to P33, P37,P45

Input port P46, P47 I

FunctionApply 2.7 V to 5.5 V to the Vcc pin. Apply 0 V to theVss pin.This pin is to stabilize internal power supply.Connect this pin to Vss via a capacitor (0.1 µF).Do not connect to Vcc.Power supply input pins for A/D converter. Connect theAVcc pin to Vcc. Connect the AVss pin to Vss. Connect acapacitor between pins AVcc and AVss.Input “L” on this pin resets the MCU.Connect this pin to Vss via a resistor.Connect this pin to Vcc via a resistor.These pins are provided for the main clock generat-ing circuit I/O. Connect a ceramic resonator or a crys-tal oscillator between the XIN and XOUT pins. To usean externally derived clock, input it to the XIN pin andleave the XOUT pin open.______

INT interrupt input pins.Key input interrupt pins.

Timer X I/O pinTimer X output pinTimer Y I/O pinTimer Z output pinTimer C input pinThe timer C output pins

Transfer clock I/O pin.Serial data input pins.Serial data output pins.

Reference voltage input pin for A/D converter. Con-nect the VREF pin to Vcc.Analog input pins for A/D converterThese are 8-bit CMOS I/O ports. Each port has an I/Oselect direction register, allowing each pin in that portto be directed for input or output individually.Any port set to input can select whether to use a pull-up resistor or not by program.P10 to P17 also function as LED drive ports.

Port for input-only

1.6 Pin DescriptionTable 1.3 shows the pin description

Table 1.3 Pin description


R8C/13 Group 2. Central Processing Unit (CPU)

2. Central Processing Unit (CPU)Figure 2.1 shows the CPU Register. The CPU contains 13 registers. Of these, R0, R1, R2, R3, A0, A1 and

FB comprise a register bank. Two sets of register banks are provided.

2.1 Data Registers (R0, R1, R2 and R3)

R0 is a 16-bit register for transfer, arithmetic and logic operations. The same applies to R1 to R3. The R0

can be split into high-order bit (R0H) and low-order bit (R0L) to be used separately as 8-bit data registers.

The same applies to R1H and R1L as R0H and R0L. R2 can be combined with R0 to be used as a 32-bit

data register (R2R0). The same applies to R3R1 as R2R0.

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Carry flag

Debug flag

Zero flag

Sign flag

Register bank select flag

Overflow flag

Interrupt enable flag

Stack pointer select flag

Reserved bit

Processor interrupt priority level

The 4-high order bits of INTB are INTBH andthe 16-low bits of INTB are INTBL.

Figure 2.1 CPU Register


R8C/13 Group 2. Central Processing Unit (CPU)

2.2 Address Registers (A0 and A1)A0 is a 16-bit register for address register indirect addressing and address register relative addressing.

They also are used for transfer, arithmetic and logic operations. The same applies to A1 as A0. A0 can be

combined with A0 to be used as a 32-bit address register (A1A0).

2.3 Frame Base Register (FB)

FB is a 16-bit register for FB relative addressing.

2.4 Interrupt Table Register (INTB)

INTB is a 20-bit register indicates the start address of an interrupt vector table.

2.5 Program Counter (PC)

PC, 20 bits wide, indicates the address of an instruction to be executed.

2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)

The stack pointer (SP), USP and ISP, are 16 bits wide each.

The U flag of FLG is used to switch between USP and ISP.

2.7 Static Base Register (SB)SB is a 16-bit register for SB relative addressing.

2.8 Flag Register (FLG)

FLG is a 11-bit register indicating the CPU state.

2.8.1 Carry Flag (C)

The C flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic logic unit.

2.8.2 Debug Flag (D)

The D flag is for debug only. Set to “0”.

2.8.3 Zero Flag (Z)

The Z flag is set to “1” when an arithmetic operation resulted in 0; otherwise, “0”.

2.8.4 Sign Flag (S)

The S flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, “0”.

2.8.5 Register Bank Select Flag (B)

The register bank 0 is selected when the B flag is “0”. The register bank 1 is selected when this flag is

set to “1”.

2.8.6 Overflow Flag (O)

The O flag is set to “1” when the operation resulted in an overflow; otherwise, “0”.

2.8.7 Interrupt Enable Flag (I)

The I flag enables a maskable interrupt.

An interrupt is disabled when the I flag is set to “0”, and are enabled when the I flag is set to “1”. The

I flag is set to “0” when an interrupt request is acknowledged.

2.8.8 Stack Pointer Select Flag (U)

ISP is selected when the U flag is set to “0”, USP is selected when the U flag is set to “1”.

The U flag is set to “0” when a hardware interrupt request is acknowledged or the INT instruction of

software interrupt numbers 0 to 31 is executed.

2.8.9 Processor Interrupt Priority Level (IPL)

IPL, 3 bits wide, assigns processor interrupt priority levels from level 0 to level 7.

If a requested interrupt has greater priority than IPL, the interrupt is enabled.

2.8.10 Reserved Bit

When write to this bit, set to “0”. When read, its content is indeterminate.


R8C/13 Group 3. Memory

3. MemoryFigure 3.1 is a memory map of this MCU. This MCU provides 1-Mbyte address space from addresses

0000016 to FFFFF16.

The internal ROM (program ROM) is allocated lower addresses beginning with address 0FFFF16. For

example, a 16-Kbyte internal ROM is allocated addresses from 0C00016 to 0FFFF16.

The fixed interrupt vector table is allocated addresses 0FFDC16 to 0FFFF16. They store the starting

address of each interrupt routine.

The internal ROM (data flash) is allocated addresses from 0200016 to 02FFF16.

The internal RAM is allocated higher addresses beginning with address 0040016. For example, a 1-Kbyte

internal RAM is allocated addresses 0040016 to 007FF16. The internal RAM is used not only for storing

data, but for calling subroutines and stacks when interrupt request is acknowledged.

Special function registers (SFR) are allocated addresses 0000016 to 002FF16. The peripheral function

control registers are located them. All addresses, which have nothing allocated within the SFR, are re-

served area and cannot be accessed by users.

Figure 3.1 Memory Map

0000016

0YYYY16

0FFFF16

002FF16

0040016

Internal ROM(program ROM)

SFR(See Chapter 4 for details.)

0FFDC16

0FFFF16

Undefined instructionOverflow

BRK instructionAddress match

Single stepWatchdog timer,Oscillation stop detection,Voltage detection

Reset

(Reserved)

Type name

0XXXX16 Internal RAM

FFFFF16

Address 0XXXX16

005FF16

Internal RAMSize

007FF16

512 bytes

1K bytes

006FF16768 bytes

Address 0YYYY16

0E00016

Internal ROMSize

0C00016

8K bytes

16K bytes

0D0001612K bytes

Expansion area

(Reserved)

R5F21134FP, R5F21134DFP

R5F21133FP, R5F21133DFP

R5F21132FP, R5F21132DFP

0200016

02FFF16 Internal ROM

(data flash)(1)

NOTES: 1. The data flash block A (2K bytes) and block B (2K bytes) are shown. 2. Blank spaces are reserved. No access is allowed.


R8C/13 Group 4. Special Function Register (SFR)

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INT0 input filter select register INT0F XXXXX0002

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0

3

B1

6

0

0

3

C1

6

0

0

3

D1

6

0

0

3

E1

6

0

0

3

F1

6

A

d

d

r

e

s

s R

e

g

i

s

t

e

r S

y

m

b

o

l

After reset

A

d

d

r

e

s

s

m

a

t

c

h

i

n

t

e

r

r

u

p

t

r

e

g

i

s

t

e

r

0 R

M

A

D

0 0

01

60

01

6X

01

6

A

d

d

r

e

s

s

m

a

t

c

h

i

n

t

e

r

r

u

p

t

r

e

g

i

s

t

e

r

1 R

M

A

D

1 0

01

60

01

6X

01

6

W

a

t

c

h

d

o

g

t

i

m

e

r

r

e

s

e

t

r

e

g

i

s

t

e

r W

D

T

R X

X1

6

H

i

g

h

-

s

p

e

e

d

o

n

-

c

h

i

p

o

s

c

i

l

l

a

t

o

r

c

o

n

t

r

o

l

r

e

g

i

s

t

e

r

0 H

R

0 0

01

6

H

i

g

h

-

s

p

e

e

d

o

n

-

c

h

i

p

o

s

c

i

l

l

a

t

o

r

c

o

n

t

r

o

l

r

e

g

i

s

t

e

r

1 H

R

1 4

01

6

Voltage detection register 1 VCR1 000010002V

o

l

t

a

g

e

d

e

t

e

c

t

i

o

n

r

e

g

i

s

t

e

r

2 V

C

R

2 0

01

610

0

0

0

0

0

02

V

o

l

t

a

g

e

d

e

t

e

c

t

i

o

n

i

n

t

e

r

r

u

p

t

r

e

g

i

s

t

e

r D

4

I

N

T 0

01

6

X

:

U

n

d

e

f

i

n

e

dN

O

T

E

S

:

1

.

B

l

a

n

k

s

p

a

c

e

s

a

r

e

r

e

s

e

r

v

e

d

.

N

o

a

c

c

e

s

s

i

s

a

l

l

o

w

e

d

.

(1)

(2)

( 2

)

(2)

010000012

(3)

( 4

)

( 3

)

(4)

4. Special Function Register (SFR)SFR(Special Function Register) is the control register of peripheral functions. Tables 4.1 to 4.4 list the SFR

informationTable 4.1 SFR Information(1)(1)



UART0 transmit interrupt control register S0TIC XXXXX0002

UART0 receive interrupt control register S0RIC XXXXX0002UART1 transmit interrupt control register S1TIC XXXXX0002UART1 receive interrupt control register S1RIC XXXXX0002

Key input interrupt control register KUPIC XXXXX0002

A

D

c

o

n

v

e

r

s

i

o

n

i

n

t

e

r

r

u

p

t

c

o

n

t

r

o

l

r

e

g

i

s

t

e

r A

D

I

C X

X

X

X

X

0

0

02

I N

T

1

i

n

t

e

r

r

u

p

t

c

o

n

t

r

o

l

r

e

g

i

s

t

e

r I

N

T

1

I

C X

X

X

X

X

0

0

02

INT2 interrupt control register INT2IC XXXXX0002

INT0 interrupt control register INT0IC XX00X0002

I N

T

3

i

n

t

e

r

r

u

p

t

c

o

n

t

r

o

l

r

e

g

i

s

t

e

r I

N

T

3

I

C X

X

X

X

X

0

0

02

0

0

4

01

6

0

0

4

11

6

0

0

4

21

6

0

0

4

31

6

0

0

4

41

6

0

0

4

51

6

0

0

4

61

6

0

0

4

71

6

0

0

4

81

6

0

0

4

91

6

0

0

4

A1

6

0

0

4

B1

6

0

0

4

C1

6

0

0

4

D1

6

0

0

4

E1

6

0

0

4

F1

6

0

0

5

01

6

0

0

5

11

6

0

0

5

21

6

0

0

5

31

6

0

0

5

41

6

0

0

5

51

6

0

0

5

61

6

0

0

5

71

6

0

0

5

81

6

0

0

5

91

6

0

0

5

A1

6

0

0

5

B1

6

0

0

5

C1

6

0

0

5

D1

6

0

0

5

E1

6

0

0

5

F1

6

0

0

6

01

6

0

0

6

11

6

0

0

6

21

6

0

0

6

31

6

0

0

6

41

6

0

0

6

51

6

0

0

6

61

6

0

0

6

71

6

0

0

6

81

6

0

0

6

91

6

0

0

6

A1

6

0

0

6

B1

6

0

0

6

C1

6

0

0

6

D1

6

0

0

6

E1

6

0

0

6

F1

6

0

0

7

01

6

0

0

7

11

6

0

0

7

21

6

0

0

7

31

6

0

0

7

41

6

0

0

7

51

6

0

0

7

61

6

0

0

7

71

6

0

0

7

81

6

0

0

7

91

6

0

0

7

A1

6

0

0

7

B1

6

0

0

7

C1

6

0

0

7

D1

6

0

0

7

E1

6

0

0

7

F1

6

A

d

d

r

e

s

s R

e

g

i

s

t

e

r Symbol A

f

t

e

r

r

e

s

e

t

Timer X interrupt control register TXIC XXXXX0002Timer Y interrupt control register TYIC XXXXX0002Timer Z interrupt control register TZIC XXXXX0002

Timer C interrupt control register TCIC XXXXX0002

Compare 1 interrupt control register CMP1IC XXXXX0002

Compare 0 interrupt control register CMP0IC XXXXX0002

X

:

U

n

d

e

f

i

n

e

dN

O

T

E

S

:

1

.

B

l

a

n

k

s

p

a

c

e

s

a

r

e

r

e

s

e

r

v

e

d

.

N

o

a

c

c

e

s

s

i

s

a

l

l

o

w

e

d

.

Table 4.2 SFR Information(2)(1)



0

0

8

01

6

0

0

8

11

6

0

0

8

21

6

0

0

8

31

6

0

0

8

41

6

0

0

8

51

6

0

0

8

61

6

0

0

8

71

6

0

0

8

81

6

0

0

8

91

6

0

0

8

A1

6

0

0

8

B1

6

0

0

8

C1

6

0

0

8

D1

6

0

0

8

E1

6

0

0

8

F1

6

0

0

9

01

6

0

0

9

11

6

0

0

9

21

6

0

0

9

31

6

0

0

9

41

6

0

0

9

51

6

0

0

9

61

6

0

0

9

71

6

0

0

9

81

6

0

0

9

91

6

0

0

9

A1

6

0

0

9

B1

6

0

0

9

C1

6

0

0

9

D1

6

0

0

9

E1

6

0

0

9

F1

6

00A016

00A116

00A216

00A316

00A416

00A516

00A616

00A716

00A816

00A916

00AA16

00AB16

00AC16

00AD16

00AE16

00AF16

00B016

00B116

00B216

00B316

00B416

00B516

00B616

00B716

00B816

00B916

00BA16

00BB16

00BC16

00BD16

00BE16

00BF16

T

i

m

e

r

X

r

e

g

i

s

t

e

r T

X F

F1

6

T

i

m

e

r

Y

s

e

c

o

n

d

a

r

y

r

e

g

i

s

t

e

r T

Y

S

C F

F1

6

External input enable register INTEN 0016

P

r

e

s

c

a

l

e

r

Y

r

e

g

i

s

t

e

r P

R

E

Y F

F1

6

UART0 transmit/receive mode register U0MR 0016

U

A

R

T

0

t

r

a

n

s

m

i

t

b

u

f

f

e

r

r

e

g

i

s

t

e

r U

0

T

B X

X1

6X

X1

6

UART0 receive buffer register U0RB XX16XX16

U

A

R

T

1

t

r

a

n

s

m

i

t

/

r

e

c

e

i

v

e

m

o

d

e

r

e

g

i

s

t

e

r U

1

M

R 0

01

6

U

A

R

T

1

t

r

a

n

s

m

i

t

b

u

f

f

e

r

r

e

g

i

s

t

e

r U

1

T

B X

X1

6X

X1

6

U

A

R

T

1

r

e

c

e

i

v

e

b

u

f

f

e

r

r

e

g

i

s

t

e

r

U

1

R

B X

X1

6X

X1

6

U

A

R

T

0

b

i

t

r

a

t

e

r

e

g

i

s

t

e

r U

0

B

R

G X

X1

6

U

A

R

T

0

t

r

a

n

s

m

i

t

/

r

e

c

e

i

v

e

c

o

n

t

r

o

l

r

e

g

i

s

t

e

r

0 U

0

C

0 0

0

0

0

1

0

0

02U

A

R

T

0

t

r

a

n

s

m

i

t

/

r

e

c

e

i

v

e

c

o

n

t

r

o

l

r

e

g

i

s

t

e

r

1 U

0

C

1 0

0

0

0

0

0

1

02

U

A

R

T

1

b

i

t

r

a

t

e

r

e

g

i

s

t

e

r U

1

B

R

G X

X1

6

U

A

R

T

1

t

r

a

n

s

m

i

t

/

r

e

c

e

i

v

e

c

o

n

t

r

o

l

r

e

g

i

s

t

e

r

0 U

1

C

0 0

0

0

0

1

0

0

02U

A

R

T

1

t

r

a

n

s

m

i

t

/

r

e

c

e

i

v

e

c

o

n

t

r

o

l

r

e

g

i

s

t

e

r

1 U

1

C

1 0

0

0

0

0

0

1

02

U

A

R

T

t

r

a

n

s

m

i

t

/

r

e

c

e

i

v

e

c

o

n

t

r

o

l

r

e

g

i

s

t

e

r

2

U

C

O

N 0

01

6

A

d

d

r

e

s

s R

e

g

i

s

t

e

r Symbol A

f

t

e

r

r

e

s

e

t

T

i

m

e

r

Y

,

Z

m

o

d

e

r

e

g

i

s

t

e

r T

Y

Z

M

R 0

01

6

T

i

m

e

r

Y

p

r

i

m

a

r

y

r

e

g

i

s

t

e

r T

Y

P

R F

F1

6T

i

m

e

r

Y

,

Z

w

a

v

e

f

o

r

m

o

u

t

p

u

t

c

o

n

t

r

o

l

r

e

g

i

s

t

e

r P

U

M 0

01

6P

r

e

s

c

a

l

e

r

Z

r

e

g

i

s

t

e

r P

R

E

Z F

F1

6T

i

m

e

r

Z

s

e

c

o

n

d

a

r

y

r

e

g

i

s

t

e

r T

Z

S

C F

F1

6T

i

m

e

r

Z

p

r

i

m

a

r

y

r

e

g

i

s

t

e

r T

Z

P

R F

F1

6

T

i

m

e

r

Y

,

Z

o

u

t

p

u

t

c

o

n

t

r

o

l

r

e

g

i

s

t

e

r T

Y

Z

O

C 0

01

6T

i

m

e

r

X

m

o

d

e

r

e

g

i

s

t

e

r T

X

M

R 0

01

6P

r

e

s

c

a

l

e

r

X

r

e

g

i

s

t

e

r P

R

E

X F

F1

6

C

o

u

n

t

s

o

u

r

c

e

s

e

t

r

e

g

i

s

t

e

r T

C

S

S 0

01

6

T

i

m

e

r

C

r

e

g

i

s

t

e

r T

C 0

01

60

01

6

K

e

y

i

n

p

u

t

e

n

a

b

l

e

r

e

g

i

s

t

e

r K

I

E

N 0

01

6

Timer C control register 0 TCC0 0016T

i

m

e

r

C

c

o

n

t

r

o

l

r

e

g

i

s

t

e

r

1 T

C

C

1 0

01

6Capture, compare 0 register TM0 0016

0016Compare 1 register TM1 FF16

FF16

X

:

U

n

d

e

f

i

n

e

dN

O

T

E

S

:

1

.

B

l

a

n

k

s

p

a

c

e

s

a

r

e

r

e

s

e

r

v

e

d

.

N

o

a

c

c

e

s

s

i

s

a

l

l

o

w

e

d

.

2

.

W

h

e

n

o

u

t

p

u

t

c

o

m

p

a

r

e

m

o

d

e

(

t

h

e

T

C

C

1

3

b

i

t

i

n

t

h

e

T

C

C

1

r

e

g

i

s

t

e

r

=

1

)

i

s

s

e

l

e

c

t

e

d,

t

h

e

v

a

l

u

e

a

f

t

e

r

r

e

s

e

t

i

s

s

e

t

t

o

“

F

F

F

F1

6”.

(2)




0

0

C

01

6

0

0

C

11

6

0

0

C

21

6

0

0

C

31

6

0

0

C

41

6

0

0

C

51

6

0

0

C

61

6

0

0

C

71

6

0

0

C

81

6

0

0

C

91

6

0

0

C

A1

6

0

0

C

B1

6

0

0

C

C1

6

0

0

C

D1

6

0

0

C

E1

6

0

0

C

F1

6

0

0

D

01

6

0

0

D

11

6

0

0

D

21

6

0

0

D

31

6

0

0

D

41

6

0

0

D

51

6

0

0

D

61

6

0

0

D

71

6

0

0

D

81

6

0

0

D

91

6

0

0

D

A1

6

0

0

D

B1

6

0

0

D

C1

6

0

0

D

D1

6

0

0

D

E1

6

0

0

D

F1

6

0

0

E

01

6

0

0

E

11

6

0

0

E

21

6

0

0

E

31

6

0

0

E

41

6

0

0

E

51

6

0

0

E

61

6

0

0

E

71

6

0

0

E

81

6

0

0

E

91

6

0

0

E

A1

6

0

0

E

B1

6

0

0

E

C1

6

0

0

E

D1

6

0

0

E

E1

6

0

0

E

F1

6

0

0

F

01

6

0

0

F

11

6

0

0

F

21

6

0

0

F

31

6

0

0

F

41

6

0

0

F

51

6

0

0

F

61

6

0

0

F

71

6

0

0

F

81

6

0

0

F

91

6

0

3

F

A1

6

0

0

F

B1

6

0

0

F

C1

6

0

0

F

D1

6

0

0

F

E1

6

0

0

F

F1

6

0

1

B

31

6

0

1

B

41

6

0

1

B

51

6

0

1

B

61

6

0

1

B

71

6

A

D

r

e

g

i

s

t

e

r A

D X

X1

6X

X1

6

A

D

c

o

n

t

r

o

l

r

e

g

i

s

t

e

r

0 A

D

C

O

N

0 0

0

0

0

0

X

X

X2

A

D

c

o

n

t

r

o

l

r

e

g

i

s

t

e

r

2 A

D

C

O

N

2 0

01

6

A

D

c

o

n

t

r

o

l

r

e

g

i

s

t

e

r

1

A

D

C

O

N

1 0

01

6

P

o

r

t

P

0

r

e

g

i

s

t

e

r P

0 X

X1

6

P

o

r

t

P

0

d

i

r

e

c

t

i

o

n

r

e

g

i

s

t

e

r P

D

0 0

01

6P

o

r

t

P

1

r

e

g

i

s

t

e

r P

1 X

X1

6

P

o

r

t

P

1

d

i

r

e

c

t

i

o

n

r

e

g

i

s

t

e

r P

D

1 0

01

6

P

o

r

t

P

3

r

e

g

i

s

t

e

r P

3 X

X1

6

P

o

r

t

P

3

d

i

r

e

c

t

i

o

n

r

e

g

i

s

t

e

r P

D

3 0

01

6P

o

r

t

P

4

r

e

g

i

s

t

e

r P

4 X

X1

6

P

o

r

t

P

4

d

i

r

e

c

t

i

o

n

r

e

g

i

s

t

e

r P

D

4 0

01

6

P

u

l

l

-

u

p

c

o

n

t

r

o

l

r

e

g

i

s

t

e

r

0

P

U

R

0 0

0

X

X

0

0

0

02

P

o

r

t

P

1

d

r

i

ve

c

a

p

a

c

i

t

y

c

o

n

t

r

o

l

r

e

g

i

s

t

e

r

D

R

R 0

01

6

R

e

g

i

s

t

e

r S

y

m

b

o

l A

f

t

e

r

r

e

s

e

tA

d

d

r

e

s

s

P

u

l

l

-

u

p

c

o

n

t

r

o

l

r

e

g

i

s

t

e

r

1

P

U

R

1 X

X

X

X

X

X

0

X2

F

l

a

s

h

m

e

m

o

r

y

c

o

n

t

r

o

l

r

e

g

i

s

t

e

r

1

F

M

R

1 1

0

0

0

0

0

0

X2

F

l

a

s

h

m

e

m

o

r

y

c

o

n

t

r

o

l

r

e

g

i

s

t

e

r

0

F

M

R

0 0

0

0

0

0

0

0

12

T

i

m

e

r

C

o

u

t

p

u

t

c

o

n

t

r

o

l

r

e

g

i

s

t

e

r

T

C

O

U

T 0

01

6

F

l

a

s

h

m

e

m

o

r

y

c

o

n

t

r

o

l

r

e

g

i

s

t

e

r

4

F

M

R

4 0

1

0

0

0

0

0

02

0

F

F

F

F1

6 O

p

t

i

o

n

f

u

n

c

t

i

o

n

s

e

l

e

c

t

r

e

g

i

s

t

e

r

O

F

SX

:

U

n

d

e

f

i

n

e

dN

O

T

E

S

:

1

.

B

l

a

n

k

c

o

l

u

m

n

s

,

0

1

0

01

6

t

o

0

1

B

21

6

a

n

d

0

1

B

81

6

t

o

0

2

F

F1

6

a

r

e

a

l

l

r

e

s

e

r

v

e

d

.

N

o

a

c

c

e

s

s

i

s

a

l

l

o

w

e

d

.

2

.

T

h

e

w

a

t

c

h

d

o

g

t

i

m

e

r

c

o

n

t

r

o

l

b

i

t

i

s

a

s

s

i

g

n

e

d

.

R

e

f

e

r

t

o

"

F

i

g

u

r

e

1

1

.

2

O

F

S

,

W

D

C

,

W

D

T

R

a

n

d

W

D

T

S

r

e

g

i

s

t

e

r

s

"

o

f

H

a

r

d

w

a

r

e

M

a

n

u

a

l

f

o

r

d

e

t

a

i

l

s

(2) ( N

o

t

e

2

)


R8C/13 Group 5. Electrical Characteristics


5. Electrical Characteristics

Operating ambient temperature

Parameter UnitSupply voltage

Output voltageVO

Pd Power dissipation

Storage temperature

Rated valueV

V

ConditionVCC

Tstg

Topr

Symbol

mW

VCC=AVCC

VAVCC

V

-0.3 to 6.5

-65 to 150

300

-20 to 85 / -40 to 85 (D version) C

Topr=25 C

Analog supply voltage VCC=AVCC -0.3 to 6.5

VI Input voltage -0.3 to VCC+0.3

-0.3 to VCC+0.3

C

Table 5.1 Absolute Maximum Ratings

Table 5.2 Recommended Operating Conditions

2

.

7 5.5T

y

p

. M

a

x

. U

n

i

tP

a

r

a

m

e

t

e

r

VC

C S

u

p

p

l

y

v

o

l

t

a

g

e

Symbol M

i

n

.S

t

a

n

d

a

r

d

A

n

a

l

o

g

s

u

p

p

l

y

v

o

l

t

a

g

e VC

C(3

)A

V

c

c VV0

0A

n

a

l

o

g

s

u

p

p

l

y

v

o

l

t

a

g

e

S

u

p

p

l

y

v

o

l

t

a

g

e

VI

H

V

s

s

A

V

s

s

0

.

8

VC

C

V

VVC

C

0

.

2

VC

C" L

"

i

n

p

u

t

v

o

l

t

a

g

e

" H

"

i

n

p

u

t

v

o

l

t

a

g

e

V

f (XIN) M

a

i

n

c

l

o

c

k

i

n

p

u

t

o

s

c

i

l

l

a

t

i

o

n

f

r

e

q

u

e

n

c

y

V

VI

L

103.0V ≤ Vcc ≤ 5.5V2.7V ≤ Vcc < 3.0V

MHzMHz

NOTES: 1. VCC = AVCC = 2.7 to 5.5V at Topr = -20 to 85 °C / -40 to 85 °C, unless otherwise specified. 2. The typical values when average output current is 100ms. 3. Hold Vcc=AVcc.

0

IO

H

(

s

u

m

) " H

"

p

e

a

k

a

l

l

o

u

t

p

u

t

c

u

r

r

e

n

t

s

Conditions

S

u

m

o

f

a

l

l

p

i

n

s

'

I

O

H

(

p

e

a

k

)-

6

0

.

0 mA

IOH (peak) "H" peak output current -

1

0

.

0 mAIOH (avg) "

H

"

a

v

e

r

a

g

e

o

u

t

p

u

t

c

u

r

r

e

n

t -

5

.

0 m

A

IO

L

(

s

u

m

) "L" peak all output currents

Sum of all pins' IOL (peak) 60 mA

IOL (peak) "L" peak output current

Except P10 to P17

P10 to P17

10 m

A

Drive ability HIGH

D

r

i

v

e

a

b

i

l

i

t

y

L

O

W

3

0

10

m

A

m

A

IOL (avg)"L" average output current

Except P10 to P17

P10 to P17 D

r

i

v

e

a

b

i

l

i

t

y

H

I

G

H

Drive ability LOW

515

5

mA

m

AmA

00

20



Table 5.3 A/D Conversion CharacteristicsS

t

a

n

d

a

r

dM

i

n

. T

y

p

. M

a

x

.– R

e

s

o

l

u

t

i

o

n B

i

tVref =VCC 1

0

Symbol Parameter Measuring condition Unit

LSB±3

RL

A

D

D

E

R

tC

O

N

V

L a

d

d

e

r

r

e

s

i

s

t

a

n

c

e

Conversion time

R

e

f

e

r

e

n

c

e

v

o

l

t

a

g

e

A

n

a

l

o

g

i

n

p

u

t

v

o

l

t

a

g

e

V

VI

A

VR

E

F

0 Vr

e

f

N

O

T

E

S

:

1

.

VC

C=

A

VC

C=

2

.

7

t

o

5

.

5

V

a

t

T

o

p

r

=

-

2

0

t

o

8

5

°

C

/

-

4

0

t

o

8

5

°

C

,

u

n

l

e

s

s

o

t

h

e

r

w

i

s

e

s

p

e

c

i

f

i

e

d

.

2

.

I

f

fA

D

e

x

c

e

e

d

s

1

0

M

H

z

m

o

r

e

,

d

i

v

i

d

e

t

h

e

fA

D

a

n

d

h

o

l

d

A

/

D

o

p

e

r

a

t

i

n

g

c

l

o

c

k

f

r

e

q

u

e

n

c

y

(

ØA

D

)

1

0

M

H

z

o

r

b

e

l

o

w

.

3

.

I

f

t

h

e

A

V

c

c

i

s

l

e

s

s

t

h

a

n

4

.

2

V

,

d

i

v

i

d

e

t

h

e

fA

D

a

n

d

h

o

l

d

A

/

D

o

p

e

r

a

t

i

n

g

c

l

o

c

k

f

r

e

q

u

e

n

c

y

(

ØA

D

)

fA

D/

2

o

r

b

e

l

o

w

.

4

.

H

o

l

d

V

c

c

=

V

r

e

f

.

ø

A

D

=

1

0

M

H

z

,

V

r

e

f

=

V

c

c

=

5

.

0

V

VR

E

F=

VC

C

–

A

b

s

o

l

u

t

e

a

c

c

u

r

a

c

y– 1

0

b

i

t

m

o

d

e

8

b

i

t

m

o

d

e ø

A

D

=

1

0

M

H

z

,

V

r

e

f

=

V

c

c

=

5

.

0

V ±

2 L

S

B

1 0

b

i

t

m

o

d

e

8

b

i

t

m

o

d

e

ø

A

D

=

1

0

M

H

z

,

V

r

e

f

=

V

c

c

=

3

.

3

V(3

) ± 5 L

S

B

ø

A

D

=

1

0

M

H

z

,

V

r

e

f

=

V

c

c

=

3

.

3

V(

3

) ± 2 L

S

B

10 40 kΩ

10 bit mode

8

b

i

t

m

o

d

e

ø

A

D

=

1

0

M

H

z

,

V

r

e

f

=

V

c

c

=

5

.

0

V

ø

A

D

=

1

0

M

H

z

,

V

r

e

f

=

V

c

c

=

5

.

0

V

3.32.8

µs

µs

V

A

/

D

o

p

e

r

a

t

i

n

gc

l

o

c

k

f

r

e

q

u

e

n

c

y(2

)W

i

t

h

o

u

t

s

a

m

p

l

e

&

h

o

l

d

With sample & hold

0 .

2

5 1

0 M

H

z

1.0 1 0 MHz

VC

C(

4

)

Figure 5.1 Port P0 to P4 measurement circuit

P0

P1

P2

P3

P4

30pF



Table 5.4 Flash Memory (Program ROM) Electrical Characteristics

Byte program time

B

l

o

c

k

e

r

a

s

e

t

i

m

e

P

r

o

g

r

a

m

,

E

r

a

s

e

V

o

l

t

a

g

e

R

e

a

d

V

o

l

t

a

g

e

5

0

0

.

4

µ

s

P

a

r

a

m

e

t

e

rStandard

Min. T

y

p

. M

a

x U

n

i

tMeasuring conditionS

y

m

b

o

l

–

–

–

–

P

r

o

g

r

a

m

,

E

r

a

s

e

T

e

m

p

e

r

a

t

u

r

e

2

.

7

2

.

7

0

5

.

5

5

.

5

60

s

V

V

°

C–

– P

r

o

g

r

a

m

/

E

r

a

s

e

e

n

d

u

r

a

n

c

e(2

) 1000(3) ti

m

e

s

T

i

m

e

d

e

l

a

y

f

r

o

m

S

u

s

p

e

n

d

R

e

q

u

e

s

t

u

n

t

i

l

E

r

a

s

e

S

u

s

p

e

n

d

8 m

std

(

S

R

-

E

S

)

D

a

t

a

h

o

l

d

t

i

m

e(

7

)– Ambient temperature = 55 °C

y

e

a

r20

E

r

a

s

e

S

u

s

p

e

n

d

R

e

q

u

e

s

t

I

n

t

e

r

v

a

l– 10 m

s

N

O

T

E

S

:

1

.

R

e

f

e

r

e

n

c

e

d

t

o

VC

C=

A

V

c

c

=

2

.

7

t

o

5

.

5

V

a

t

T

o

p

r

=

0

°

C

t

o

6

0

°

C

u

n

l

e

s

s

o

t

h

e

r

w

i

s

e

s

p

e

c

i

f

i

e

d

.

2

.

D

e

f

i

n

i

t

i

o

n

o

f

P

r

o

g

r

a

m

/

E

r

a

s

eT

h

e

e

n

d

u

r

a

n

c

e

o

f

P

r

o

g

r

a

m

/

E

r

a

s

e

s

h

o

w

s

a

t

i

m

e

f

o

r

e

a

c

h

b

l

o

c

k

.I

f

t

h

e

p

r

o

g

r

a

m

/

e

r

a

s

e

n

u

m

b

e

r

i

s

“

n

”

(

n

=

1

0

0

0

,

1

0

0

0

0

)

,

“

n

”

t

i

m

e

s

e

r

a

s

e

c

a

n

b

e

p

e

r

f

o

r

m

e

d

f

o

r

e

a

c

h

b

l

o

c

k

.F

o

r

e

x

a

m

p

l

e

,

i

f

p

e

r

f

o

r

m

i

n

g

o

n

e

-

b

y

t

e

w

r

i

t

e

t

o

t

h

e

d

i

s

t

i

n

c

t

a

d

d

r

e

s

s

e

s

o

n

B

l

o

c

k

A

o

f

2

K

-

b

y

t

e

b

l

o

c

k

2

0

4

8

t

i

m

e

s

a

n

d

t

h

e

ne

r

a

s

i

n

g

t

h

a

t

b

l

o

c

k

,

t

h

e

n

u

m

b

e

r

o

f

P

r

o

g

r

a

m

/

E

r

a

s

e

c

y

c

l

e

s

i

s

o

n

e

t

i

m

e

.H

o

w

e

v

e

r

,

p

e

r

f

o

r

m

i

n

g

m

u

l

t

i

p

l

e

w

r

i

t

e

s

t

o

t

h

e

s

a

m

e

a

d

d

r

e

s

s

b

e

f

o

r

e

a

n

e

r

a

s

e

o

p

e

r

a

t

i

o

n

i

s

p

r

o

h

i

b

i

t

e

d

(

o

v

e

r

w

r

i

t

i

n

gp

r

o

h

i

b

i

t

e

d

)

.3

.

N

u

m

b

e

r

s

o

f

P

r

o

g

r

a

m

/

E

r

a

s

e

c

y

c

l

e

s

f

o

r

w

h

i

c

h

a

l

l

e

l

e

c

t

r

i

c

a

l

c

h

a

r

a

c

t

e

r

i

s

t

i

c

s

i

s

g

u

a

r

a

n

t

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r

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p

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p

r

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i

v

e

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.

T

h

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d

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t

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h

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l

d

t

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m

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n

c

l

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p

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l

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f

f

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r

t

h

e

c

l

o

c

k

i

s

n

o

t

s

u

p

p

l

i

e

d

.



Table 5.5 Flash Memory (Data flash Block A, Block B) Electrical Characteristics(4)

B

y

t

e

p

r

o

g

r

a

m

t

i

m

e

(

p

r

o

g

r

a

m

/

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r

a

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e

n

d

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r

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n

c

e≤1

0

0

0

t

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r

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m

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E

r

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e

V

o

l

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g

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R

e

a

d

V

o

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t

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g

e

65

0.3

µs

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r

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i

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y

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n

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e

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e

r

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C=

A

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c

c

=

2

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5

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a

t

T

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r

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2

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5

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5

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.

2

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D

e

f

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m

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E

r

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m

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s

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n

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(

n

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1

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0

,

1

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0

0

0

)

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m

b

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f

P

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a

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p

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) 1

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) t

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y

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a

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9

)

–

A

m

b

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p

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r

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=

5

5

°

C

50

0.2

4

0

0

9

8

2

0

s

µ

s

y

e

a

r

E

r

a

s

e

S

u

s

p

e

n

d

R

e

q

u

e

s

t

I

n

t

e

r

v

a

l– 10 m

s

FMR46

Erase-suspend request(interrupt request)

td(SR-ES)

Figure 5.2 Time delay from Suspend Request until Erase Suspend



Table 5.7 Reset Circuit Electrical Characteristics (When Using Hardware Reset 2(1, 3))

S

y

m

b

o

l StandardT

y

p

. U

n

i

tMeasuring condition

M

i

n

. M

a

x

.P

a

r

a

m

e

t

e

r

V

p

o

r

2 P

o

w

e

r

-

o

n

r

e

s

e

t

v

a

l

i

d

v

o

l

t

a

g

e VV

d

e

t

N

O

T

E

S

:

1

.

T

h

e

v

o

l

t

a

g

e

d

e

t

e

c

t

i

o

n

c

i

r

c

u

i

t

w

h

i

c

h

i

s

e

m

b

e

d

d

e

d

i

n

a

m

i

c

r

o

c

o

m

p

u

t

e

r

i

s

a

f

a

c

t

o

r

t

o

g

e

n

e

r

a

t

e

t

h

e

h

a

r

d

w

a

r

e

r

e

s

e

t

2

.

R

e

f

e

r

t

o

5

.

1

.

2

H

a

r

d

w

a

r

e

R

e

s

e

t

2

o

f

H

a

r

d

w

a

r

e

M

a

n

u

a

l

f

o

r

d

e

t

a

i

l

s

.

2

.

T

h

i

s

c

o

n

d

i

t

i

o

n

i

s

n

o

t

a

p

p

l

i

c

a

b

l

e

w

h

e

n

u

s

i

n

g

VC

C ≥

1

.

0

V

.

3

.

W

h

e

n

t

u

r

n

i

n

g

p

o

w

e

r

o

n

a

f

t

e

r

t

h

e

e

x

t

e

r

n

a

l

p

o

w

e

r

h

a

s

b

e

e

n

h

e

l

d

b

e

l

o

w

t

h

e

v

a

l

i

d

v

o

l

t

a

g

e

(

V

p

o

r

1

)

f

o

r

g

r

e

a

t

e

r

t

h

a

n

1

0

s

e

c

o

n

d

s

,

r

e

f

e

r

t

o

T

a

b

l

e

5

.

8

R

e

s

e

t

C

i

r

c

u

i

t

E

l

e

c

t

r

i

c

a

l

C

h

a

r

a

c

t

e

r

i

s

t

i

c

s

(

W

h

e

n

N

o

t

U

s

i

n

g

H

a

r

d

w

a

r

e

R

e

s

e

t

2

)

.

4

.

t

w

(

p

o

r

2

)

i

s

t

i

m

e

t

o

h

o

l

d

t

h

e

e

x

t

e

r

n

a

l

p

o

w

e

r

b

e

l

o

w

e

f

f

e

c

t

i

v

e

v

o

l

t

a

g

e

(

V

p

o

r

2

)

.

S

u

p

p

l

y

v

o

l

t

a

g

e

r

i

s

i

n

g

t

i

m

e

w

h

e

n

p

o

w

e

r

-

o

n

r

e

s

e

t

i

s

c

a

n

c

e

l

e

d(2

)tW(

V

p

o

r

2

-

V

d

e

t

)m

s1

0

0

–

2

0

°

C

≤

T

o

p

r

<

8

5

°

C

–

2

0

°

C

≤

T

o

p

r

<

8

5

°

C

,

tW(

p

o

r

2

)

≥

0

s(4

)

Figure 5.3 Reset Circuit Electrical Characteristics

Table 5.8 Reset Circuit Electrical Characteristics (When Not Using Hardware Reset 2)

Vpor1

Vcc min

Vdet(3) Vdet(3)

tw(por1) tw(Vpor1–Vdet)

Sampling time(1,2)

Internal reset signal(“L” effective)

fRING-S1 X 32 fRING-S

1 X 32

Vpor2

NOTES: 1. Hold the voltage of the microcomputer operation voltage range (Vccmin or above) within sampling time. 2. A sampling clock is selectable. Refer to “5.4 Voltage Detection Circuit” of Hardware manual for details. 3. Vdet shows the voltage detection level of the voltage detection circuit. Refer to “5.4 Voltage Detection Circuit” of Hardware manual for details.

tw(por2) tw(Vpor2 –Vdet)

Table 5.6 Voltage Detection Circuit Electrical Characteristics

Symbol Standard Typ. Unit Measuring condition

Min. Max. Parameter

Vdet Voltage detection level V3.8 4.3

NOTES: 1. The measuring condition is Vcc=AVcc=2.7V to 5.5V and Topr=-40°C to 85°C. 2. This shows the time until the voltage detection interrupt request is generated since the voltage passes Vdet. 3. This shows the required time until the voltage detection circuit operates when setting to "1" again after setting the VC27 bit in the VCR2 register to “0”.

Voltage detection interrupt request generating time(2) 40

nAVoltage detection circuit self consumption current

Waiting time until voltage detection circuit operation starts(3)td(E-A)

VC27=1, VCC=5.0V

3.3

20

600

µs

µs

Vccmin Microcomputer operation voltage minimum value 2.7 V

Symbol S

t

a

n

d

a

r

dT

y

p

. U

n

i

tM

e

a

s

u

r

i

n

g

c

o

n

d

i

t

i

o

n

Min. M

a

x

.Parameter

0

.

1

N

O

T

E

S

:

1

.

W

h

e

n

n

o

t

u

s

i

n

g

h

a

r

d

w

a

r

e

r

e

s

e

t

2

,

u

s

e

w

i

t

h

V

c

c

≥

2

.

7

V

.

2

.

t

w

(

p

o

r

1

)

i

s

t

i

m

e

t

o

h

o

l

d

t

h

e

e

x

t

e

r

n

a

l

p

o

w

e

r

b

e

l

o

w

e

f

f

e

c

t

i

v

e

v

o

l

t

a

g

e

(

V

p

o

r

1

)

.

100

1

tW(Vpor1- Vdet)

S

u

p

p

l

y

v

o

l

t

a

g

e

r

i

s

i

n

g

t

i

m

e

w

h

e

n

p

o

w

e

r

-

o

n

r

e

s

e

t

i

s

c

a

n

c

e

l

e

d

0

.

5

tW(Vpor1- Vdet) Supply voltage rising time when power-on reset is canceled

tW(Vpor1- Vdet)

Supply voltage rising time when power-on reset is canceled

VV

p

o

r

1 P

o

w

e

r

-

o

n

r

e

s

e

t

v

a

l

i

d

v

o

l

t

a

g

e

ms

ms

ms

tW(Vpor1- Vdet) Supply voltage rising time when power-on reset is canceled 100 ms

0°C ≤ Topr ≤ 85°C, tW(por1) ≥ 10s(2)

–

2

0

°

C

≤

T

o

p

r

<

0

°

C

,

tW(

p

o

r

1

)

≥

1

0

s(2

)

0°C ≤ Topr ≤ 85°C, tW(por1) ≥ 1s(2)

–

2

0

°

C

≤

T

o

p

r

<

8

5

°

C

–20°C ≤ Topr < 0°C, tW(por1) ≥ 30s(2)



Table 5.11 Electrical Characteristics (1) [Vcc=5V]

S

y

m

b

o

l

VO

H

VO

L

" L

"

o

u

t

p

u

t

v

o

l

t

a

g

e

" H

"

o

u

t

p

u

t

v

o

l

t

a

g

e

S

t

a

n

d

a

r

dTyp. UnitMeasuring condition

V

V

V

Min. Max.VCC-2.0

P

a

r

a

m

e

t

e

r

IO

H=-5m

A

V

H

y

s

t

e

r

e

s

i

s

"H" input currentII

H

" L

"

i

n

p

u

t

c

u

r

r

e

n

tII

L

VR

A

M R

A

M

r

e

t

e

n

t

i

o

n

v

o

l

t

a

g

e

VT

+

-VT

- 0

.

2

V

µA

At stop mode 2

.

0

VI=

5

V

VI=

0

V

Rf

X

I

N F

e

e

d

b

a

c

k

r

e

s

i

s

t

a

n

c

e XI

N MΩRP

U

L

L

U

P P

u

l

l

-

u

p

r

e

s

i

s

t

a

n

c

e 1

6

7 kΩ3

0

12

5

N

O

T

E

S

:

1

.

R

e

f

e

r

e

n

c

e

d

t

o

VC

C

=

A

VC

C

=

4

.

2

t

o

5

.

5

V

a

t

T

o

p

r

=

-

2

0

t

o

8

5

°

C

/

-

4

0

t

o

8

5

°

C

,

f

(

XI

N)

=

2

0

M

H

z

u

n

l

e

s

s

o

t

h

e

r

w

i

s

e

s

p

e

c

i

f

i

e

d

.

VCCExcept XOUT

XOUT

IOH=-200µA

D

r

i

v

e

c

a

p

a

c

i

t

y

H

I

G

H

Drive capacity LOW

VC

C-0

.

3 VC

C V

IOH=-1 mA VC

C-2

.

0

VCC-2.0IOH=-500µAV

V

VCC

VC

C

E

x

c

e

p

t

P

10

t

o

P

17,

XO

U

T

P10 to P17

XO

U

T

Drive capacity HIGH

D

r

i

v

e

c

a

p

a

c

i

t

y

L

O

W

IOL= 5 mA

IOL= 200 µA

IO

L=

1

5

m

A

IOL= 5 mA

2

.

0

0.45 V

2

.

0

2.0 V

Drive capacity HIGH

Drive capacity LOWIOL= 1 mA

IOL=500 µA

2

.

0

2

.

0

V

R

E

S

E

T 0.2

1.

0

2.2

V

5.

0

-5.0 µ

A

VI=0V 50

1.0

fR

I

N

G

-

S L

o

w

-

s

p

e

e

d

o

n

-

c

h

i

p

o

s

c

i

l

l

a

t

o

r

f

r

e

q

u

e

n

c

y 40 2

5

0 k H

z

INT0, INT1, INT2, INT3, KI0, KI1,KI2, KI3, CNTRo, CNTR1, TCIN, RxD0, RxD1, P45

Drive capacity LOW IOL= 200 µA 0.45 V

V

S

y

m

b

o

l S

t

a

n

d

a

r

dT

y

p

. U

n

i

tM

e

a

s

u

r

i

n

g

c

o

n

d

i

t

i

o

n

Min. M

a

x

.P

a

r

a

m

e

t

e

r

H

i

g

h

-

s

p

e

e

d

o

n

-

c

h

i

p

o

s

c

i

l

l

a

t

o

r

f

r

e

q

u

e

n

c

y

1

/

t

d

(

H

R

o

f

f

s

e

t

)

+

t

d

(

H

R

)

w

h

e

n

t

h

e

r

e

s

e

t

i

s

r

e

l

e

a

s

e

d

N

O

T

E

S

:

1

.

T

h

e

m

e

a

s

u

r

i

n

g

c

o

n

d

i

t

i

o

n

i

s

V

c

c

=

A

V

c

c

=

5

.

0

V

a

n

d

T

o

p

r

=

2

5

°

C

.

H

i

g

h

-

s

p

e

e

d

o

n

-

c

h

i

p

o

s

c

i

l

l

a

t

o

r

p

e

r

i

o

d

a

d

j

u

s

t

e

d

u

n

i

t

M

H

z

n

sV

C

C

=

5

.

0

V

,

T

o

p

r

=

2

5

°

CS

e

t

"

0

01

6"

i

n

t

h

e

H

R

1

r

e

g

i

s

t

e

r

8

6

1

Differences when setting "0116" and "0016" in the HR register

S

e

t

t

a

b

l

e

h

i

g

h

-

s

p

e

e

d

o

n

-

c

h

i

p

o

s

c

i

l

l

a

t

o

r

m

i

n

i

m

u

m

p

e

r

i

o

d

High-speed on-chip oscillator frequency temperature dependence(1)

t d

(

H

R

o

f

f

s

e

t

)

td(HR)

V

C

C

=

5

.

0

V

,

T

o

p

r

=

2

5

°

CS

e

t

"

4

01

6"

i

n

t

h

e

H

R

1

r

e

g

i

s

t

e

r

1 n

s

F

r

e

q

u

e

n

c

y

f

l

u

c

t

u

a

t

i

o

n

i

n

t

e

m

p

e

r

a

t

u

r

e

r

a

n

g

e

o

f

-

1

0

°

C

t

o

5

0

°

C ±

5 %

%H

i

g

h

-

s

p

e

e

d

o

n

-

c

h

i

p

o

s

c

i

l

l

a

t

o

r

f

r

e

q

u

e

n

c

y

t

e

m

p

e

r

a

t

u

r

e

d

e

p

e

n

d

e

n

c

e

(

2

) F

r

e

q

u

e

n

c

y

f

l

u

c

t

u

a

t

i

o

n

i

n

t

e

m

p

e

r

a

t

u

r

e

r

a

n

g

e

o

f

-

4

0

°

C

t

o

8

5

°

C ±

1

0

Table 5.9 High-speed On-Chip Oscillator Circuit Electrical Characteristics

Symbol Standard Typ. Unit Measuring condition

Min. Max. Parameter

2000

NOTES: 1. The measuring condition is Vcc=AVcc=2.7 to 5.5 V and Topr=25 °C. 2. This shows the wait time until the internal power supply generating circuit is stabilized during power-on. 3. This shows the time until BCLK starts from the interrupt acknowledgement to cancel stop mode.

150td(R-S) STOP release time(3)

µstd(P-R) Time for internal power supply stabilization during powering-on(2)

µs

1

Table 5.10 Power Circuit Timing Characteristics



S

y

m

b

o

l StandardT

y

p

. U

n

i

tM

e

a

s

u

r

i

n

g

c

o

n

d

i

t

i

o

n

Min. M

a

x

.P

a

r

a

m

e

t

e

r

No division

m

A

I n

s

i

n

g

l

e

-

c

h

i

p

m

o

d

e

,

t

h

e

o

u

t

p

u

t

p

i

n

s

a

r

e

o

p

e

n

a

n

d

o

t

h

e

r

p

i

n

s

a

r

e

VS

S

9 1

5

XIN=20 MHz (square wave)

m

A

High-speed mode

IC

C P

o

w

e

r

s

u

p

p

l

y

c

u

r

r

e

n

t(

VC

C=3

.

3

t

o

5

.

5

V

)

4

7

0

N

O

T

E

S

:

1

.

T

i

m

e

r

Y

i

s

o

p

e

r

a

t

e

d

w

i

t

h

t

i

m

e

r

m

o

d

e

. 2.

R

e

f

e

r

e

n

c

e

d

t

o

VC

C

=

A

VC

C

=

4

.

2

t

o

5

.

5

V

a

t

T

o

p

r

=

-

2

0

t

o

8

5

°

C

/

-

4

0

t

o

8

5

°

C

,

f

(

XI

N)

=

2

0

M

H

z

u

n

l

e

s

s

o

t

h

e

r

w

i

s

e

s

p

e

c

i

f

i

e

d

.

Wait mode

µA

m

AMedium-speed mode

High-speed on-chip oscillator mode

L

o

w

-

s

p

e

e

d

o

n

-

c

h

i

p

o

s

c

i

l

l

a

t

o

r

m

o

d

e

H

i

g

h

-

s

p

e

e

d

o

n

-

c

h

i

p

o

s

c

i

l

l

a

t

o

r

o

f

fL

o

w

-

s

p

e

e

d

o

n

-

c

h

i

p

o

s

c

i

l

l

a

t

o

r

o

n

=

1

2

5

k

H

z

XIN=16 MHz (square wave)H

i

g

h

-

s

p

e

e

d

o

n

-

c

h

i

p

o

s

c

i

l

l

a

t

o

r

o

f

fL

o

w

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4 8 m

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Main clock off

Low-speed on-chip oscillator on=125 kHzDivision by 8

mA1.5

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CHigh-speed on-chip oscillator offLow-speed on-chip oscillator offCM10="1"Peripheral clock off

0.8 3.0

V

C

2

7

=

"

0

"

µ

A

W

a

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t

m

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n

c

l

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k

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fHigh-speed on-chip oscillator offLow-speed on-chip oscillator on=125 kHzWhen a WAIT instruction is executed(1)

38 76

V

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µ

A




Timing requirements [VCC=5V] (Unless otherwise noted: VCC = 5V, VSS = 0V at Topr = 25 °C)

Table 5.13 XIN input

________

Table 5.14 CNTR0 input, CNTR1 input, INT2 input

________

Table 5.15 TCIN input, INT3 input

Symbol

tC(XIN)tWH(XIN)tWL(XIN)

Parameter

XIN input cycle timeXIN input HIGH pulse widthXIN input LOW pulse width

Min.502525

Max.–––

Unit

nsnsns

Standard

Symbol

tC(CNTR0)tWH(CNTR0)tWL(CNTR0)

Parameter

CNTR0 input cycle timeCNTR0 input HIGH pulse widthCNTR0 input LOW pulse width

Min.1004040

Max.–––

Unit

nsnsns

Standard

Symbol

tC(TCIN)tWH(TCIN)tWL(TCIN)

Parameter

TCIN input cycle timeTCIN input HIGH pulse widthTCIN input LOW pulse width

Min.400(1)

200(2)

200(2)

Max.–––

Unit

nsnsns

Standard

NOTES: 1. When using the Timer C input capture mode, adjust the cycle time above ( 1/ Timer C count source

frequency x 3). 2. When using the Timer C input capture mode, adjust the pulse width above ( 1/ Timer C count source

frequency x 1.5).

NOTES:________ ________

1. When selecting the digital filter by the INT0 input filter select bit, use the INT0 input HIGH pulse widthto the greater value,either ( 1/ digital filter clock frequency x 3) or the minimum value of standard.

________ ________

2. When selecting the digital filter by the INT0 input filter select bit, use the INT0 input LOW pusle widthto the greater value,either ( 1/ digital filter clock frequency x 3) or the minimum value of standard.

Table 5.5 Serial Interface

________

Table 5.17 External interrupt INT0 input

Symbol

tC(CK)tW(CKH)tW(CKL)td(C-Q)th(C-Q)tsu(D-C)th(C-D)

Parameter

CLKi input cycle timeCLKi input HIGH pulse widthCLKi input LOW pulse widthTxDi output delay timeTxDi hold timeRxDi input setup timeRxDi input hold time

Min.200100100

–0

3590

Max.–––

–––

Unit

nsnsnsnsnsnsns

Standard

80

Symbol

tW(INH)tW(INL)

Parameter

________

INT0 input HIGH pulse width________

INT0 input LOW pulse width

Min.250(1)

250(2)

Max.––

Unit

nsns

Standard



Figure 5.4 Vcc=5V timing diagram

CLKi

TxDi

RxDi

INTi

tW(CKH)

tc(CK)

tW(CKL)

th(C-Q)

th(C-D)tsu(D-C)td(C-Q)

tW(INL)

tW(INH)

XIN input

tWH(XIN)

tc(XIN)

tWL(XIN)

TCIN input

tWH(TCIN)

tc(TCIN)

tWL(TCIN)

CNTR0 input

tWH(CNTR0)

tc(CNTR0)

tWL(CNTR0)

VCC = 5V



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N=

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3

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fHigh-speed on-chip oscillator on=8 MHzLow-speed on-chip oscillator on=125 kHzNo division

3

.

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A

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m

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m

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s

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5

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N=

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0

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H

z

(

s

q

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a

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1

.

6 m

A

1

2

800

7

4

µ

A

W

a

i

t

m

o

d

e Main clock offHigh-speed on-chip oscillator offLow-speed on-chip oscillator on=125 kHzWhen a WAIT instruction is executed(1)

Peripheral clock off

µA

Stop mode M

a

i

n

c

l

o

c

k

o

f

f

,

T

o

p

r

=

-

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5

°

CHigh-speed on-chip oscillator offL

o

w

-

s

p

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d

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fCM10="1"Peripheral clock off

0.7 3.0

VC27="0"

3

5 7

0

VC27="0"

VC27="0"

µ

A



Timing requirements [VCC=3V] (Unless otherwise noted: VCC = 3V, VSS = 0V at Topr = 25 °C)

Table 5.20 XIN input

________

Table 5.21 CNTR0 input, CNTR1 input, INT2 input

________

Table 5.22 TCIN input, INT3 input

Symbol

tC(XIN)tWH(XIN)tWL(XIN)

Parameter

XIN input cycle timeXIN input HIGH pulse widthXIN input LOW pulse width

Min.1004040

Max.–––

Unit

nsnsns

Standard

Symbol

tC(CNTR0)tWH(CNTR0)tWL(CNTR0)

Parameter

CNTR0 input cycle timeCNTR0 input HIGH pulse widthCNTR0 input LOW pulse width

Min.300120120

Max.–––

Unit

nsnsns

Standard

Symbol

tC(TCIN)tWH(TCIN)tWL(TCIN)

Parameter

TCIN input cycle timeTCIN input HIGH pulse widthTCIN input LOW pulse width

Min.1200(1)

600(2)

600(2)

Max.–––

Unit

nsnsns

Standard

NOTES: 1. When using the Timer C input capture mode, adjust the cycle time above ( 1/ Timer C count source

frequency x 3). 2. When using the Timer C input capture mode, adjust the pulse width above ( 1/ Timer C count source

frequency x 1.5).

NOTES:________ ________

1. When selecting the digital filter by the INT0 input filter select bit, use the INT0 input HIGH pulse widthto the greater value,either ( 1/ digital filter clock frequency x 3) or the minimum value of standard.

________ ________

2 . When selecting the digital filter by the INT0 input filter select bit, use the INT0 input LOW pusle widthto the greater value,either ( 1/ digital filter clock frequency x 3) or the minimum value of standard.

Table 5.23 Serial Interface

________

Table 5.24 External interrupt INT0 input

Symbol

tC(CK)tW(CKH)tW(CKL)td(C-Q)th(C-Q)tsu(D-C)th(C-D)

Parameter

CLKi input cycle timeCLKi input HIGH pulse widthCLKi input LOW pulse widthTxDi output delay timeTxDi hold timeRxDi input setup timeRxDi input hold time

Min.300150150

–05590

Max.–––

–––

Unit

nsnsnsnsnsnsns

Standard

160

Symbol

tW(INH)tW(INL)

Parameter

________

INT0 input HIGH pulse width________

INT0 input LOW pulse width

Min.380(1)

380(2)

Max.––

Unit

nsns

Standard



Figure 5.5 Vcc=3V timing diagram

CLKi

TxDi

RxDi

INTi

tW(CKH)

tc(CK)

tW(CKL)

th(C-Q)

th(C-D)tsu(D-C)td(C-Q)

tW(INL)

tW(INH)

XIN input

tWH(XIN)

tc(XIN)

tWL(XIN)

TCIN input

tWH(TCIN)

tc(TCIN)

tWL(TCIN)

CNTR0 input

tWH(CNTR0)

tc(CNTR0)

tWL(CNTR0)

VCC = 3V

R8C/13 Group Package Dimensions


Package Dimensions

2.

1. DIMENSIONS "*1" AND "*2"DO NOT INCLUDE MOLD FLASH.

NOTE)

DIMENSION "*3" DOES NOTINCLUDE TRIM OFFSET.

y

Index mark

*3

F

32

25

24 17

16

9

81

*1

*2

xbpe

HEE

D

HD

ZD

ZE

Detail F

L1

L

A

cA2

A1

Previous CodeJEITA Package Code RENESAS Code

PLQP0032GB-A 32P6U-A

MASS[Typ.]

0.2gP-LQFP32-7x7-0.80

1.0

0.125

0.35

0.7

0.7

0.20

0.200.1450.09

0.420.370.32

MaxNomMin

Dimension in MillimetersSymbol

Reference

7.17.06.9D

7.17.06.9E

1.4A2

9.29.08.8

9.29.08.8

1.7A

0.20.10

0.70.50.3L

x

8°0°

c

0.8e

0.10y

HD

HE

A1

bp

b1

c1

ZD

ZE

L1

Terminal cross section

b1

c 1

bp

c

REVISION HISTORY R8C/13 Group Datasheet

Rev. Date Description

Page Summary

A-1

0.10 Oct 28, 2003 First edition issued

0.20 Dec05, 2003 5 Figure 1.3 revised

Chapter 4, NOTES revised

Table 5.4 revisedTable 5.5 revised

Table 5.6 revisedFigure 5.3 added

Table 5.8 revisedTable 5.10 revised

Figure 5.3 revised to Figure 5.4

Table 5.17 revised

Figure 5.4 revised to Figure 5.5

10

16

18

21

22

25

17

1.00 Sep 30, 2004 All pages

2

5

6

9

10-13

12

14

15

16

17

18

19

20

22

23

24

Words standardized (on-chip oscillator, serial interface, A/D)

Table 1.1 revised

Figure 1.3, NOTES 3 added

Table 1.3 revised

Figure 3.1, NOTES added

One body sentence in chapter 4 added ; Titles of Table 4.1 to 4.4 added

Table 4.3 revised ; Table 4.4 revised

Table 5.2 revised

Table 5.3 revised

Table 5.4 and Table 5.5 revised

Table 5.6, 5.7 and 5.8 revised ; Figure 5.3 revised

Table 5.9 and 5.11 revised

Table 5.12 revised

Table 5.13 revised

Table 5.18 revised

Table 5.19 revised

Table 5.20 and Table 5.24 revised

1.10 Apr.27.2005 4 Table 1.2, Figure 1.2 package name revised

5 Figure 1.3 package name revised

10 Table 4.1 revised

12 Table 4.3 revised

15 Table 5.3 partly revised

16 Table 5.4, Table 5.5 partly added



Page Summary

A-2

1.10 Apr.27.2005 17 Table 5.7, 5.8 revised

18 Table 5.10, Table 5.11 partly revised

22 Table 5.18 partly revised

26 Package Dimensions revised

1.20 Jan.27.2006 2 Table 1.1 Performance outline revised3 Figure 1.1 Block diagram partly revised4 1.4 Product Information, title of Table 1.2

“Product List” → “Product Informaton” revisedROM capacity; “Program area” → “Program ROM”,

“Data area” → “Data flash” revisedFigure 1.2 Type No., Memory Size, and Package partly revised

6 Table 1.3 Pin description revised7-8 2 Central Processing Unit (CPU) revised

Figure 2.1 CPU register revised9 3 Memory, Figure 3.1 Memory Map;

“Program area” → “Program ROM”, “Data area” → “Data flash” revised10 Table 4.1 SFR Information(1) NOTES:1 revised11 Table 4.2 SFR Information(2) NOTES:1 revised12 Table 4.3 SFR Information(3);

008116: “Prescaler Y” → “Prescaler Y Register”008216: “Timer Y Secondary” → “Timer Y Secondary Register”008316: “Timer Y Primary” → “Timer Y Primary Register”008516: “Prescaler Z” → “Prescaler Z Register”008616: “Timer Z Secondary” → “Timer Z Secondary Register”008716: “Timer Z Primary” → “Timer Z Primary Register”008C16: “Prescaler X” → “Prescaler X Register” revisedNOTES:1, 2 revised

13 Table 4.4 SFR Information(4) NOTES:1 revised14 Table 5.2 Recommended Operating Conditions; NOTES: 1, 2, 3 revised15 Table 5.3 A/D Conversion Characteristics;

“A/D operation clock frequency” → “A/D operating clock frequency” revisedNOTES: 1, 2, 3, 4 revised

16 Table 5.4 Flash Memory (Program ROM) Electrical Characteristics;“Data retention duration” → “Data hold time” revised“Topr” → “Ambient temperature”NOTES: 1 to 7 addedMeasuring condition of byte program time and block erase time deleted

17 Table 5.5 Flash Memory (Data flash Block A, Block B) Electrical characteristics“Data retention duration” → “Data hold time” revised“Topr” → “Ambient temperature”NOTES: 1, 3 revised, NOTES: 9 addedMeasuring condition of byte program time and block erase time deleted

18 Table 5.7 Reset Circuit Electrical Characteristics (When Using Hardware Reset 2)NOTES: 3 revised

19 Table 5.9 High-speed On-Chip Oscillator Circuit Electrical Characteristics;“High-speed on-chip oscillator temperature dependence” →“High-speed on-chip oscillator frequency temperature dependence” revisedTable 5.11 Electrical Characteristics (1) [VCC=5V];“P10 to P17 Except XOUT” → “Except P10 to P17, XOUT” revised



Page Summary

A-3

1.20 Jan.27.2006 20 Table 5.12 Electrical Characteristics (2) [VCC=5V];NOTES: 1, 2 revisedMeasuring condition Stop mode: “Topr=-25 °C” added

23 Table 5.18 Electrical Characteristics (3) [VCC=3V]“P10 to P17 Except XOUT” → “Except P10 to P17, XOUT” revised

24 Table 5.19 Electrical Characteristics (4) [VCC=3V]NOTES: 1, 2 revisedMeasuring condition Stop mode: “Topr=-25 °C” added

Keep safety first in your circuit designs!1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble

may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.

Notes regarding these materials1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's

application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party.2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data,

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evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein.

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