The increasing technology node scaling makes VLSI devices extremely vulnerable to Single Event Effects (SEEs)induced by highly charged particles such as heavy ions, increasing the sensitivity to Single Event Transients(SETs). In this paper, we describe a newmethodology combining an analytical and oriented model for analyzingthe sensitivity of SET nanometric technologies. The paper includes radiation test experiments performed onFlash-based FPGAs using heavy ions radiation beam. Experimental results are detailed and commented demon-strating the effective mitigation capabilities thanks to the adoption of the developed model.
Due to the non-volatile configuration memory, flash-based tech-nology is becoming more interesting in safety critical fields, particu-larly for space and avionic applications. Among the various flash-based devices, Field Programmable Gate Array (FPGA) devicesbased on flash technology are a consolidated device used in spaceapplications. These devices are composed of floating gate basedswitches that can suffer transient effects, also called Single Event Effects(SEEs), if hit by high energetic particles provoking possible criticalconsequences on the implemented circuit. SEEs may become criticalfor a circuit when it induces Single Event Upsets (SEUs). Several studiesinvolve the analysis of SETs on flash-based FPGAs [1]. Several worksinvestigated the nature of these events, analyzing the propagation ofthe transient pulse through the combinational logic data path androuting resources [2]. Previous works reported radiation test experi-ment [3] and electrical fault injection [4] of SET propagation on customcircuits designed specifically to observing SETs; also some results on SETdependency on clock frequency have been presented [5]. Recent exper-iments of accurate SET pulse electrical injection [6] show a strong SETpulse-width modulation when SET pulses traverse logic gates. Besides,it has been observed that the SET pulse width at the input of a storageelement is strictly dependent on the propagation and type of traversedlogic gates [7]. On the other side, a variety of hardening solutions
have been proposed adopting redundancy solution and logic filteringapproaches. The purpose of this work is to provide an effective modelfor the SET phenomena and to analyze the sensitivity of a realistic de-sign implemented using flash-based FPGA technology under radiationbeamwith different fault tolerant design approaches. The presented ex-perimental results show that the usage of traditional fault tolerant strat-egy based on redundancy is not enough tomitigate the SEEs, while SET-model based design flow can be applied with low resource overheadand obtain a reduction of the measured SEE cross-section of morethan the 76% with respect to the original unhardened RISC and around48% versus traditional TMR techniques.
2. The proposed SET nanometer model
The main idea behind the proposed work is based on the accuratemodeling of the SET phenomena generated by radiation particleswithinthe silicon structure of nanometer devices. Themethod consists of threephases: the generation of the SET pulse phenomena which is modeledas transient pulse shape, the localization of all the combinational gateswithin the circuit description and finally the execution of the propaga-tion of the SET pulse starting from each sensitive node of the circuitand traversing the logic gates and routing interconnections untilan input of a storage element (i.e., a Flip-Flop or a Memory Bank) isreached. The model allows the identification of the expected SETwidth and allows estimation of the global sensitivity of the circuit. Tothe best knowledge of the authors, the proposed approach is the first
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Fig. 1. SET pulse shape modeling of the original pulse (i.e., positive transition) generatedfrom the GDS-I model (tn) and after the propagation through a logic gate (tn+ 1).
Fig. 3. RISC5x architecture.
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solution that is able to integrate physical design analysis and Matlabcomputations in order to evaluate the dynamic behavior of a VLSIcircuit.
2.1. SET generation and analytical model
In order to generate the pulse shape, the developed model elabo-rates the physical layout description of each circuit logic gate, describedby standard Graphic Database System for IC layout (GDS-I), whichrepresents a 3D model of the implemented circuit. The model consistsof 3 phases described byMatlab code. The first phase, based on the char-acterization thatwas provided in [4], generates the SETmodel accordingto the definition depicted by the shape tn in Fig. 1.
The second phase executes the propagation on the basis of the Resis-tive and Capacitive load calculated on the GDS-I 3Dmodel of the circuit.The propagation coefficient is used in the model reported in Fig. 2 inorder to generate the expected propagation coefficients for all thelogic paths [6]. Please note that when the coefficient is lower than 0the signal is filtered, and vice versa the original pulse is broadened. InFig. 1, the pulse shape tn + 1 is obtained in case of broadening. Thethird phase includes the execution of the propagation and on the classi-fication of each Flip-Flop sensitivity. Themodel has been used to reducethe sensitivity of the benchmark circuits that we used for the experi-mental evaluation.
2.2. SET characterization
The Single Event Transients (SETs) characterization has beenperformed using the SETA tool, which has been implemented in [11]which is an algorithm that performs the SET propagation analysis of acircuit mapped on a flash-based FPGA. It consists of two phases: theformer locates all circuit combinational gates and identifies theirpropagation nodes until a storage element (a Flip-Flop or a Latch) is
Fig. 2. SET pulse analytical propagation model.
Please cite this article as: L. Sterpone, et al., Radiation-induced singletechnologies, Microelectronics Reliability (2015), http://dx.doi.org/10.101
reached, the latter performs the propagation of a SET pulse startingfrom each sensitive node and traversing all the circuit logic path andstoring the maximal length observed by the SET pulse at the input ofeach storage element. The results are stored in two databases reportingthemaximal SET pulse at the input of each Flip-Flop and the broadeningcoefficient between the couple of gates.
3. Experimental analysis
The experimental analysis we performed in this work consists of aset of radiation test campaigns performed with a heavy ions beam inorder to provoke radiation-induced SET and classify their effects. Theresults are compared with the developed prediction model.
3.1. Tested architectures
RISC5X fromOpenCores is a RISC CPU that is compatiblewith the 12-bit opcode PIC family [8]. It consists of an Instruction Decoder (IDEC), anArithmetic Logic Unit (ALU) which is capable of 8-bit addition, subtrac-tion and logic shift operation, and a register file of 128 bytes used asRAM. The RISC5x has three 8-bit wide ports which can be used asinput and output ports connecting to different peripherals. The portsare named PORTA, PORTB and PORTC respectively, as illustrated inFig. 3. To map RISC5x to the FPGA, we added a ROM module holdingthe instructions by means of signal array in VHDL, which was inferredas logic gates instead of Flip-Flops or latches by the Synplify tool inLibero IDE from Microsemi.
The original RISC5x from OpenCores has no fault tolerant strategyapplied. In order to reduce data corruptions in RAM caused by SEUs
Fig. 4. ECC scheme adopted in order to protect RISC register file, implemented using Flash-based FPGA embedded RAMmodules versus SEU accumulation.
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and to focus on the analysis of SETs induced by the radiation particles,we replaced the original RAM module with another version protectedby a Hamming Code which is enabled to correct two bit errors whenthey reside separately in the higher and lower half of the 8-bit register.The scheme of the Error Correction Code (ECC) applied to the registerfile RAM resources is depicted in Fig. 4.
We developed a hardened implementation of the RISCmicroproces-sor described above, applying TMR at different logic levels in order todrastically mitigate SEUs. We used two different methods. The firstmethod consists in applying the Synplify tool oriented to radiation hard-ened FPGA designs [9]; it applies the triplication of all the Flip-Flopsinserting amajority voter on their outputs. The second has been appliedat the entity level, in which the components in RISC5x, such as IDEC andALU are directly triplicated as represented in Fig. 5, except for the regis-ter file module (REGS) which has been already protected by ECC imple-mentation as mentioned above.
3.2. Fault tolerant strategies
Furthermore, we designed a RISC using a SET-aware Place and Routealgorithmapplied on the netlist generated by Synplify therefore appliedonly with TMR Flip-Flop. The SEE-aware place and route algorithm,
Fig. 6. Radiation expe
Please cite this article as: L. Sterpone, et al., Radiation-induced singletechnologies, Microelectronics Reliability (2015), http://dx.doi.org/10.101
which is based on a greedy approach that is able to reduce the SETbroadening effects [10], has the principal characteristics of performinga placement of the circuit logic resources by regulating the timingand capacitive load allowing modification of the original logic gateplacement positions into the regular array of the flash-based FPGAs inorder to achieve an optimal condition for the SETs mitigation. The PRalgorithm is part of a SEE-aware design flow by which an estimationof SET broadening effect of the design is made firstly, followed byguard gates insertions on user Flip-Flops where electrical filtering isnecessary. Finally, the PR algorithm implements the target circuit in-creasing the combinational logic filtering capabilities of each data pathby reducing and nullifying the broadening phenomena. Adopting thisdesign flow, SETs can be effectively mitigated with low resourcesoverhead.
3.3. Radiation test setup
The same test program implemented to capture the SEEs and prop-agate to the outputs to be captured has been used on the differentRISC5x implementations. The developed test program, generates asequence of data output with fixed time gap between each output.During execution of the test program, SEEs can cause errors in differentcomponents in FPGA, which can lead to corrupted data outputs andwrong time gaps between outputs. At this step, still there are errorsthat will be silenced by the fault tolerant strategies we applied or theinitialization stage in the test program.
The flash-based FPGA we used for the radiation test is A3P250 ofthe ProASIC3 family from Microsemi in 130-nm technology node.Another FPGA board from Altera was used as monitor board to con-trol theMicrosemi board, capture the data outputs and communicatewith the host PC outside the radiation beam chamber, as illustratedin the scheme reported in Fig. 6. As the three ports in RISC5x weresynchronized with clock source in the Microsemi board which was
rimental setup.
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Fig. 7. SEE cross-section comparison between different RISC5x implementation.
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not shared with the Altera board, another port (PORTB) was used toindicate valid data on PORTA so that the asynchronous capturer inthe monitor board can read the correct data from PORTA and storethem in SRAM. The monitor board also controls the reset signal ofthe Microsemi board, and to avoid reset signal hazard, we triplicatedthe reset signal and used a voter in the design to ensure that the testprogram will be executed and stopped, as we wanted.
Experimental analysis has been performed on the RISC processor byheavy-ions radiation beam. The RISC has been implemented on aMicrosemi A3P250 flash-based FPGA and running a testing applicationconsisting in an iterative counter. A radiation campaign has been per-formed in September 2013 at the Cyclotron of the Université Catholiquede Louvain (UCL) on four different versions of the RISC processor:unhardened, TMR Synplify, TMR + GG and our method. The details ofthe resource usage are reported in Table 1. The RISC working frequencyhas been settled to 20MHzwhile the experiments have beenperformedusing a Kripton ion with a fluence of 3.04E8 [particles] and an averageflux of 1E4 [particles/sec]. A suitable monitor board has been developedin order to continuously monitor the RISC output and comparing themwith the expected data.
3.4. Results and discussion
The experimental results have been collected comparing the cross-section [errors/particles] for each of the implemented RISC version.The results obtained during the radiation test campaign demonstratedthat the RISC5x implementedwith SEE-aware placement tool has a sen-sitivity of about two orders of magnitude with respect to the RISC hard-ened with full TMR and guard-gate filtering 1 ns. Error bars werecomputed on the basis of the Monte Carlo process, which is calculatedas 1/√N where N corresponds to the number of errors counted. In the
Fig. 8. Error events
Please cite this article as: L. Sterpone, et al., Radiation-induced singletechnologies, Microelectronics Reliability (2015), http://dx.doi.org/10.101
worst case, the statistical error is 10%; the obtained results are reportedin Fig. 7.
The plain version of the RISC only protected with the ECC mecha-nism applied to the register file memory, reports a cross-section of1.52E−6 cm2. The TMR implementations, either using Guard-Gates(Full TMR + GG) and adopting TMR on sequential element (TMR–FF)have a reduction of cross-section of about 55% versus the plain version,while a negligible difference between the two TMR solutions is ob-served. On the other hand, the RISC5x implemented and mappedusing the SEE aware placement provides a reduction of more than 78%with respect to the plain version and about 48% less SEE sensibilitycompared to the TMR RISC5x implementations. Please note that perfor-mances are not degraded among the execution of three different RISC5xversions. In order to characterize the collected data, we analyzed thedata outputs provided by the RISC5x from the PORTA which can be di-vided into sequences containing 8 data output records each. The timedifference between two adjacent data records in a sequence wasmeasured by the monitor board and reports a fixed number ofclock cycles when no error is presented in the design. According tothe data outputs collected by the monitor board, the errors causedby SEEs can be functionally classified into 4 types: time gap, corre-sponding to the time difference between two data output outsidethe margin of the corrected ones; wrong data, corrupted data reportedon the PORTA output; wrong records, an erroneous number of recordsin a data sequence; and wrong sequence, an erroneous number ofdata sequences. The classification, reported in Fig. 8, gives insight onthe improvements performed by the SEE aware placement design ofthe RISC5x. In particular, the SEE-aware RISC5x reports a drastic reduc-tion of the wrong data effect (i.e., more than 60% versus the plainRISC5x) and an evident reduction of about 25% and 30% versus theTMR implementations, related to the time gap and missing sequenceeffects.
4. Conclusions and future works
In this paper we have analyzed the sensitiveness of a RISC micro-processor against SEEs induced by radiation particles, with differentfault tolerant strategies on flash-based FPGA. The experimental resultsdemonstrate the effectiveness of the proposed approach and providea reduction of the SET-sensitivity of more than 76% versus a not-mitigated version, while 48% versus traditional TMR methods.
In the future, we intend to extend the studies on the effectiveness ofASIC cell libraries based on a 15 nm technology.
Acknowledgments
The radiation test experiments performed at the Cyclotron of theUniversité Catholique de Louvain (UCL) have been supported by theEuropean Space Agency (ESA) (4000105142).
classification.
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