Radio Engineering (From Software To Cognitive Radio) || Transmitter/Receiver Analog Front End

Chapter 7

Transmitter/Receiver Analog Front End

7.1. Introduction

Starting from software-defined radio (SDR) architecture, this chapter deals withthe receiver radio frequency (RF) (or analog) front end. It is therefore assumedthat some analog part is retained in the receiver. Thus, three fundamental partsare studied in this chapter: antennas, power amplifiers, and converters. The SRtechnology actually imposes new constraints on the three steps (bandwidth, linearity,dynamic) and it is therefore necessary to rethink the design. However, this chapterdoes not address mixers, frequency synthesizers, and filters.

7.2. Antennas

7.2.1. Introduction

To analyze the electromagnetic environment and adapt its operation, the cognitiveradio (CR) system is brought to discriminate the radio signals spectrally and spatially.Spatial discrimination is to select a signal according to its direction of arrival. Itrequires a directive antenna of the array type, an antenna capable of steering itsbeam(s) in the desired direction(s). Spectral discrimination requires, in turn, usinga broadband or a multiband antenna. The frequency selection of the signals isperformed using band-pass filters or directly by the antenna if the latter is tunable.Figure 7.1 shows the associated architectures.

Chapter written by Renaud LOISON, Raphaël GILLARD, Yves LOUËT and Gilles TOURNEUR.

162 Radio Engineering

Figure 7.1. Possible architectures for an RF front end forspectral discrimination

The implementation of these antennas is constrained by the context: at the basestation or mobile terminal.

7.2.2. For base stations

7.2.2.1. Constraints on spatial discrimination

Spatial discrimination requires a directional antenna capable of steering the beamin the desired direction. Array antennas [HAN 98], consisting of a combination ofelementary sources whose radiations are combined with an appropriate weight inamplitude and phase, are particularly well suited for the generation of these features.They make it possible to achieve large radiating apertures (necessary for obtaininghigh directivity and therefore a narrow beam) while making it possible to haveelectronic control over the radiation pattern through the commands applied to theelementary sources constituting the array. A multibeam antenna can even go furtherby dealing independently with multiple signals arriving from different directions[MIU 97]. In this case, it combines a single radiating aperture with a beam-formingnetwork responsible for distributing the various signals.

Smart antennas [SAR 03] are able to adjust the radiation pattern according to theenvironment. The typical architecture of the receiver is presented in Figure 7.2.

The receiver consists of an array in which the digitized signals at the output of theN elements, x′i(k), are combined with complex weightsWi to form the overall outputsignal y(k).

The reconfigurability is obtained by recalculating the weights in real time throughan appropriate algorithm and taking into account the received signals. To do this, thealgorithm uses as input the information contained in each of the N individual output

Transmitter/Receiver Analog Front End 163

signals and the overall output signal (which may eventually be completed by theknown data, for example, the position of fixed jammers). It then modifies the weightsto maximize the signal-to-noise ratio (SNR), cancels out the contributions comingfrom certain parasitic directions or other appropriate processing [RAZ 99]. Followingthe same principle, several distinct output signals can be generated simultaneously byusing several different sets of weights. This results in an intelligent multibeam antennathat is able to manage communication with different receivers. The application ofintelligent base stations is discussed in [PER 01].

Figure 7.2. Architecture of a smart antenna at the receiver


7.2.2.2. Constraints on the spectral discrimination

Spectral discrimination requires the use of a wideband (or multiband) antennaassociated with a duplexer separating the signals at different frequencies. In practice,the direct design of the broadband antenna arrays faces two antagonistic constraints:

– the size L of a broadband source is constrained by the low frequencies:

L ∝ λmax

where λmax = c/fmin is the wavelength at the minimum frequency fmin in free space.It may be quite large when the minimum frequency is low;

– on the contrary, spacing between the sources of an array (interelement spacingd) is limited by the higher frequencies:

d <λmin

1 + |sin θ|where λmin represents the wavelength in free space at the maximum frequency fmax

and θ represents the scan angle of the beam relative to broadside. As the maximumfrequency increases, the allowed spacing decreases. In addition, it further reduces thegrazing beam (|θ| closer to π/2) and thus is generally fixed at λmin/2. This conditionaims to avoid the appearance of lobes, sources of decrease in gain, and potentialinterference when the beam scans.

In the end, the following two conditions simultaneously can be impossible becauseit needs to accommodate elementary sources potentially bulky in a limited space.Even when a compromise on the size can be found, the excessive proximity of theelementary sources may result in a significant coupling altering the ideal operationof the array. This problem is particularly critical when the beam is scanned as thecoupling varies with the steering direction, which makes its correction even moredifficult.

Moreover, the realization of a fixed tilt on wideband is in itself a complexoperation. The simplest solution, which consists of applying a progressive phaseshifting along the array elementary sources, leads to a modification in the beamdirection with a frequency according to the law:

sin [θ(f)] =f0f

sin [θ(f0)]

where f0 is an arbitrary reference frequency. Only the introduction of a true timedelay between the two successive sources can overcome this defect at the cost ofgreater complexity of control circuitry [WIL 00]. Note also that the directivity of anantenna is directly proportional to the electric length (or area) of the radiating aperture.Consequently, the gain of a wideband array generally varies with frequency.


To avoid these problems, juxtaposition or rather interleaving of severalindependent narrowband arrays may be preferred to make a true wideband array. Itcan also make the autonomous spatial and spectral discrimination easier. However, theproblem of congestion remains the same as in this case it is about the accommodationof several arrays in the same space.

7.2.2.3. Sample topologies and concepts

The design of the dual-band or tri-band arrays has resulted in many publications,especially in the context of GSM900, DCS1800, and UMTS standards. These aregenerally linear arrays (the beam formation takes place in one plane only) withfixed radiation (the tilt is fixed and mechanically adjustable), thereby relaxingthe tight design constraints. Generally, the wideband or multiband antenna arrayshave been studied extensively, particularly for airborne applications in which asingle antenna could perform several functions (radar, communication) [OUA 07].Simultaneous coverage of several bands can be achieved by using an elementarywideband source [PIV 03, YAO 07]. In this context, frequency-independent antennassuch as the spiral [MUL 07], log-periodic [HAL 08], or Vivaldi antenna are naturallygood candidates for wideband arrays. However, they generally have large dimensions,at least in two directions in space. Fractal antennas such as the Sierpinski antenna[ANG 01, LIM 05] make it possible, through their property of self-similarity, to covermultiple frequency bands with optimal space occupation as high-frequency elementscan be directly integrated within the low-frequency components. However, for allthese solutions, the electrical length of the radiating aperture varies with frequency,resulting in gain variations in the band.

The use of interleaved independent arrays has been proposed for the phased arrayrequired for radars [CHU 96]. It consists of nesting two or more arrays, operating atdifferent frequencies and having independent control. The size of each array can bechosen independently according to the gain constraints at different frequencies. Thegeometries of the primary sources must be sufficiently complementary to allow us theinterleaving of all arrays while limiting the couplings. One possible application forbase station antennas is given in [KIT 01] and [STA 09].

In [BRE 92], the principle of the original array architecture is proposed, whichis independent of the frequency: on the basis of a multilayer structure, it allows usto keep the electric dimensions of the antenna constant with frequency (interelementspacing and distance from the ground plane). However, its practical implementationis not as straightforward, for example, as the excitement of array sources.

Antenna reconfigurability requires implementation of the active or controllablecircuitry. In [SIA 04], the spatial discrimination is achieved using a multibeamantenna that generates up to 29 beams with a Buttler matrix and a set of switches.Use of new technologies such as micro-electro-mechanical systems (MEMS) or


electromagnetic band gap (EBG) material offers very promising prospects in thisrespect. In [WU 08], frequency discrimination is proposed by switching betweenmultiple sources radiating at different frequencies, using MEMS micro-switches.

Figure 7.3. Fractal antenna of the Sierpinski Bow-tie type for multibandapplication [LIM 05]

In [RAT 06], the beam scan in the horizontal plane is achieved using a cylindricalEBG structure that covers a frequency band including GSM, DCS, and UMTSstandards.

These few examples illustrate the problems encountered and suggest somesolutions. Nevertheless, the spatial and spectral discrimination are usually treatedindependently of each other and the practical realization of a true antenna that isefficient in both frequency and space remains a major challenge for the antennadesigners.


Figure 7.4. Quad-band antenna with MEMS switching [WU 08]

Figure 7.5. Adaptive base station with reconfigurable EBG [RAT 06]

7.2.3. For mobile terminals

7.2.3.1. Constraints

At the terminal end, compactness is a major constraint in the design of an antennacapable of both spectral and spatial discriminations.


In fact, at the scale of a terminal and for the usual operating frequencies, it isimpossible to implement a large antenna array of several wavelengths and thereforewe need to consider beam-forming techniques. Therefore, the spatial discriminationaspect is not addressed in this section.

On the other hand, the fundamental laws of electromagnetism show that radiationefficiency and bandwidth of an antenna decrease with its electric dimensions(expressed in fractions of the wavelength) [HAN 81]. Specifically, it is possible todesign a small-sized antenna of large bandwidth but at the cost of low radiationefficiency that results in substantial losses. The notion of smallness for an antennais relative to its minimum operational frequency. Below λmax/6 (where λmax is thewavelength at the minimum frequency), an antenna is considered small. To establishan order of magnitude, the largest dimension an efficient wideband antenna operatingbeyond 1 GHz may have is less than 5 cm.

The implementation of an efficient wideband antenna will therefore be possibleonly when a sufficient space is allocated for the radiating device. This prohibits theintegration of the antenna within the terminal and requires the use of an externalantenna [FAR 07, KEL 08]. Then, if possible, the antenna is associated with a filteringfunction to select the desired frequency bands. The filtering of bands is usually doneby using several selectable filters through a switching system.

However, a wideband antenna is needed only if a wide-frequency band must becovered at a given time. This characteristic is required in only ultra-wideband (UWB)systems operating with wideband signals. A more conventional and more favorableview point from the antenna perspective is that in a CR system the antenna operatesin narrow-band mode with the frequency reconfiguration capability over a wideband.In this case, the required instantaneous bandwidth is reduced and it is possible toimplement smaller and more efficient antennas. This operation can be envisaged withthree antenna architectures:

– the first architecture is to couple a fixed, non-reconfigurable multiband antennawith a filtering function. There have been numerous publications on the developmentof multiband antennas recently [CIA 04, GUO 05, LIM 05, LUX 06, SIM 08].Efforts focused on the design and integration of antennas suitable for major mobilephone standards and wireless local area networks (LANs) have been made. Veryschematically, these antennas are composed of several nested resonators to minimizespace congestion. These solutions exist in today’s mobile devices and are thus proven.However, this solution limits the operation of the terminal over the bands or standardsfor which it was designed. This limits the frequency reconfigurability in a CR context;

– the second architecture is to combine the functions of radiation and filteringthem in one component using a multiband reconfigurable antenna [HAL 08, LOI 09,PAN 08]. These antennas incorporate switchable active elements such as PIN diodesor MEMS switches. Activation of these components makes it possible to change the


resonant mode of the antenna. This allows us to modify the band of operation andadjust the antenna according to a given number of predefined standards. Thus, theseantennas can operate on limited and fixed bands. This ability to select the operatingband makes it possible to liberate the filtering step and to simplify and compact the RFstage. In contrast, as for the previous architecture, operation on predefined standardsor bands limits the use of this solution in the CR context. Finally, the design of theantenna switchable over several bands is not a simple problem, although promisingsolutions have been proposed and demonstrated in the literature;

– the last architecture proposes use of a wideband tunable antenna [ABE 05,MAN 09]. These antennas allow us to have an almost continuous adjustment ofthe band over a wide-frequency band. In theory, both the bandwidth and the centerfrequency can be easily adjusted over the whole operating band of the antenna. Thismode of operation is ideal for a CR system; it offers the flexibility necessary forthe frequency agility of the system. Naturally, this concept is the least mature, notmuch demonstrated, and the agility capabilities are still limited. All the topologiesproposed in the literature are based on the use of impedance or a reconfigurableimpedance transformer. When connected to a simple antenna, these devices can eitherchange the antenna resonant frequency (load impedance) or dynamically adjust theirinput impedance (impedance transformer). These circuits are made using variablecomponents such as varactor diode or switchable grids of capacitance and inductance.The implementation and use of these devices may create new problems such as loss,consumption, size, switching speed, and also parasitic radiations. These problemsincrease with device agility. Indeed, increased flexibility requires increased degreesof freedom and therefore larger and more complex circuits. The viability of theseconcepts will depend on their technological feasibility. For example, the use ofMEMS-based switches will improve performance in terms of losses and consumption.

Four possible architectures with their positive and negative characteristics aresummarized in Table 7.1.

Architecture Benefits LimitationsWB + filters Ultra-wideband functionality Antennas are difficult to

possible integrateMB + filters Integrated antennas Useful bands are fixedReconfigurable MB Integrated antennas, filtering Useful bands are fixed

by antennasTunable WB Integrated antennas, filtering Complexity, size, and

by antennas, flexible in consumption of switchingfrequency reconfiguration circuits

Table 7.1. Possible antenna architectures within the terminal(MB = multiband, WB = wideband)


Figure 7.6. Wideband antenna placed on printed circuit board [FAR 07]

7.2.3.2. Sample topologies and concepts

All the four examples discussed in this section are from the literature and areintended to illustrate the four antenna architectures given below:

Wideband antenna: Figure 7.6 depicts an external wideband antenna given in[FAR 07]. With this topology, it is possible to design an antenna matched over severaloctaves from approximately 1 GHz. Starting bandwidth from a lower frequency ispossible at the cost of larger dimensions.

Multiband fixed antenna: Figure 7.7 shows a prototype of a multiband antennaproposed in [LUX 06]. As in the previous section, the antenna is presented in thepresence of a ground plane modeling the printed circuit board. The antenna is smalland can be easily integrated inside the terminal. This antenna covers five standards:GSM, DCS, PCS, UMTS, and WLAN. It consists of several nested resonators for thesake of compactness.

Switchable multiband antenna: a switchable multiband antenna configurationis shown in Figure 7.8. This switchable (planar inverted F antenna PIFA) antenna,consisting of a metal plate suspended above a ground plane is proposed in [LOI 09].The patch is fed by a coaxial probe and is connected to the ground plane by twometallic pins. This connection is achieved by two active switches. Thus, groundingof the antenna is adjustable through the independent activation of the two metallicpins to the ground. Based on the state of the two switches, the antenna can operate infour different modes. The optimization of the shape of the antenna and the position ofthe metallic pins can adjust four independent bands of operation.

Broadband tunable antenna: the concept of tunable antenna is proposed in[ABE 05]. This principle is based on using a reconfigurable matching circuit


(Figure 7.9) responsible for dynamically tuning a PIFA antenna on targetedfrequencies. In [ABE 05], the optimized circuit has six switches and thus can adjust64 different impedances. This allows us a dynamic reconfiguration of the antenna tobe used in the range of 900 MHz to 1.9 GHz. Enlargement of the useful band towarda broadband operation would require more degrees of freedom and therefore a morecomplex, cumbersome, and consuming circuit.

Figure 7.7. Multiband antenna (GSM/DCS/PCS/UMTS/WLAN) [LUX 06]

Figure 7.8. Switchable multiband antenna [LOI 09]

Figure 7.9. Reconfigurable impedance transformer (6 bits)for dynamic matching of antenna [ABE 05]


7.3. Nonlinear amplification

7.3.1. Introduction

The SR concept implies the processing of a multiplex of standards resulting fromreconfigurable terminals. The signals to be processed are of much higher bandwidthand this has fundamental implications on the equipment and, in particular, onthe power amplifier. Chapter 9 of this book addresses the question of nonlinearityprocessing related to power amplification. The power amplification of signals in thecontext of the SR was discussed in the European project TRUST [TRU 00], which hasresulted in a survey of the constraints to be taken into account for designing an SRterminal.

7.3.2. Characteristics of a power amplifier

To ensure correct information transmission, the transmitters need to amplify thesignals to provide power to the signals (RF signals) and prevent them from weakeningduring their propagation in free space. The amplifier actually draws the necessarypower useful to the signal in a continuous current source then injected into it.Generally, two types of power amplifiers are used in communication systems:

– the traveling wave tube amplifier (TWTA): this is mostly used in satellitetransmission requiring high power;

– solid-state power amplifier (SSPA): this is used in radio terrestrial transmissionsfor low power levels.

The TWTA amplifiers are microwave tubes in which electron beam andelectromagnetic field interact. Because of the interaction between the signal and theflow of electrons, the signal captures the kinetic energy of the electrons, which resultsin increased signal strength. The nominal characteristics of the TWTA amplifiers are:

– saturation power: 20–200 W;

– efficiency at saturation: 50–70%;

– gain of about 55 dB;

– weight: 1.5–2.2 kg.

The SSPAs consist of several amplification stages based on transistors. The laststage contains several transistors working in parallel.

These types of amplifiers have nonlinear gain characteristics. This point isdiscussed in the next section.


7.3.2.1. AM/AM and AM/PM characteristics

These characteristics are also known as transfer characteristics and translate theinput/output relation around the fundamental frequency in a comprehensive way.

AM/AM (amplitude/amplitude) characteristics reflect the variation in theamplitude (or power) of the output voltage according to the input amplitude (voltage).The AM/PM (for amplitude/phase) transfer curve reflects the variation in phase of theoutput voltage depending on the input amplitude. The two characteristics of an SSPAamplifier are shown in Figure 7.10.

Figure 7.10. (a) Amplitude and (b) phase characteristics of an SSPA

Let us focus on the AM/AM characteristics. This curve is linear at first, then forlarger input amplitudes the output is no longer proportional to the input voltage andthen tends to a saturation value. This curve may be divided into three zones:

Linear zone: the amplifier has a behavior similar to that of a linear system.The output power is proportional to the input power and the ratio is called gain ofthe amplifier. The input powers are low (according to the technology). Distortionsproduced in this area are almost non-existent.

Gain compression zone: in this zone, the output is no longer proportional tothe input power. The curve begins to turn and distortions at the output signal appear.The amplifier gain decreases at large input powers. We talk of the zone of gaincompression.

Saturation zone: in this zone, the output power is almost constant regardless ofthe input power. This is called saturation power.

The AM/PM curve is a bit different; the linearity is manifested by a constant phase.In the TWTA amplifier, the phase is constant and then increases until a saturationvalue. In the SSPA amplifier, the phase varies but relatively little and it requires highvoltages to change it significantly.


7.3.2.2. The efficiency

Figure 7.11 shows a simplified balance sheet of the different power levels duringthe amplification of a signal. However, it is impossible to have a complete energytransfer to the signal and thus the need of defining the term efficiency.

Pdc

Battery

Output power

Pin

Pdiss

PoutAmplifier

Input power

Dissipated power

Figure 7.11. Simplified power balance of an amplifier

Let Pin be the input power and Pout be the corresponding output power. Pdc andPdiss are the battery power and dissipated power, respectively. The power equation isthen given by:

Pin + Pdc = Pout + Pdiss [7.1]

There are two types of efficiency:

– power efficiency Rp: this expresses the ratio between the output power and thepower supplied by the battery. This parameter is extremely important as it reflects theamplifier consumption. It is given by the following relationship:

Rp =Pout

Pdc[7.2]

– power-added efficiency Rpa: this takes into account the input power. Just asthe power efficiency, it reflects the consumption of the amplifier. It is given by theequation:

Rpa =Pout − Pin

Pdc[7.3]

7.3.2.3. Input and output back-offs

To avoid, or at least reduce, the adverse effects due to the nonlinearity ofthe amplifiers, it is often necessary to back off from the 1 dB compression pointor from the saturation point to operate in the linear region or close to it. xdB


input compression point corresponds to the input power for which the amplifiercharacteristic differs by xdB from the linear characteristic. We then define inputback-off (IBO) and output back-off (OBO).

Let Pout,1dB be the output power at 1 dB compression point and Pin,1dB thecorresponding input power.

IBO, usually expressed in dBs, is the relationship between input power at 1 dBcompression point and input signal power:

IBO(dB) = Pin,1dB(dB)− Pin(dB) [7.4]

OBO is defined in similar manner but in terms of output power:

OBO(dB) = Pout,1dB(dB)− Pout(dB) [7.5]

From these relationships, we can see that the larger the IBO (or OBO), the lesserthe distortions due to nonlinearities. Also note that in this case, the efficiency drops.

7.3.2.4. Memory effect

In future communication systems, it is clear that the signals will be more andmore wideband. Under these conditions, the power amplifiers will have “memory”,the bandwidth of the amplifier is smaller than that of the signal to be amplified.The memory effect modifies the response of the system based on the input signals.This effect has a significant impact on device performance and it is an importantconsideration in any study on the processing of nonlinearities.

According to duration, the memory effect can be classified into two categories:

– the effects of high-frequency memory: these are due to phenomena whose timeconstants are short, i.e. the same order of magnitude as the period of the excitationsignal. These constants are mainly generated by reactive elements of matching circuitsand the physical characteristics of semiconductors;

– the effects of low-frequency memory: these result from phenomena whosetime constants are long, i.e. the same order of magnitude as those present in themodulating signal. They are mainly related to electrical phenomena (trapping effectsin transistors, impedances, etc.) and electro-thermal phenomena (temperatures).

7.3.3. Merit criteria of a power amplifier

The merit criteria are used to describe an amplifier under some parameters. Theseparameters will characterize the severity of the nonlinearities.


7.3.3.1. Intermodulation

One effect of the nonlinearity of the power amplifier is the appearance of newfrequencies in the signal band and the neighboring bands. This phenomenon is calledintermodulation. The output frequencies are linear combinations of input frequenciesfi. These are of type:

fs =N∑i=1

mifi [7.6]

The frequency fs is called intermodulation product of order∑N

i=1 |mi|, wheremi

are integers.

The intermodulation products of even order are not in the band of the amplifiershaving a far greater center frequency. However, the intermodulation products of theodd order are particularly troublesome because they are very close to the fundamentalcomponent of the input signal, and therefore difficult to remove even with a filter ofhigh order.

To illustrate the effects of nonlinearity, two types of signals are considered: signalsconsisting of pure frequencies (1-tone and 2-tone signal) and modulated signal.

Concerning the pure frequencies, let e(t) be the input signal of the form:

e(t) = A cos(2πf0t+Φ) [7.7]

The passage of this signal from a nonlinear power amplifier will generatenew frequencies (or harmonics). Assuming that the output s(t) of the amplifieris expressed as a function of the input e(t) according to a polynomial model:(s(t) = G1e(t) + G2e

2(t) + G3e3(t) + ....), Figure 7.12 illustrates the generation

and superposition of harmonics.

When the input signal consists of two pure frequencies (f0, f1) of identicalamplitude a, the phenomenon is identical to the previous phenomenon but is morecomplex in terms of computation. The weights for a few frequencies are illustrated inFigure 7.13.

Now considering the case of modulated carriers, the cases encountered in practiceconsider the so-called broadband signals (having a bandwidthB).

Figure 7.14 illustrates the contributions of the third and fifth order on the widebandsignal. Intermodulation levels decrease with the order but spread over wider bands.


f0

f0

a

G1a

2f0

½*G2a2 ½*G2a2

0

3f0f0

3/4*G3a3 1/4*G3a3

2f0

1/2*G4a4

0

3/8*G4a4

4f0

1/8*G4a4

…

Figure 7.12. Illustration of harmonics created during thenonlinear amplification of a single frequency signal

Frequencies Weight of G1a Weight of G2a2 Weight of G3a3 Weight of G4a4

0 1 9/4

f0

2f0

2f1

1 9/4

f1 1 9/4

½ 2

½ 2

f0±f1

2f0±f1

f0±2f1

1 3

¾

¾

Figure 7.13. Illustration of intermodulations created during thenonlinear amplification of bifrequency signal


Figure 7.14. Illustration of the intermodulation created during the nonlinearamplification of wideband signal

7.3.3.2. The C/I ratio

It is a quantity that indicates the level of the intermodulation product bynonlinearity of the power amplifier. The C/I ratio (carrier to intermodulation),also called IM (intermodulation), corresponds to the power difference between thefundamental and intermodulation components. We can define the C/I ratio of order3,5,7, ...if the line in question is of order 3,5,7, ... they are noted by C

I3 , CI5 , C

I7 , ... .

7.3.3.3. Interception point

The interception point (IP) is also another useful criterion of merit for translatingIM. It is defined as being the point where the output power at the fundamentalfrequency is equal to that of IM frequency. In the same way as C/I can have IP3,IP5, IP7, ... Figure 7.15 describes IP3.

Considering the effects due to nonlinearities, it is clear that these two criteria ofmerit do not characterize certain phenomena such as the noise generated inside thesignal band. These phenomena are not confined to a single IM product but ratherresult due to sum of IM product amplitudes.

7.3.3.4. Noise power ratio (NPR)

The NPR is a quantity used to measure the noise generated inside the signal banddue to nonlinearity of the amplifier. This parameter quantifies the degree of self-interference. Its measurement is illustrated in Figure 7.16.


1 dB

Input power

Output power

Input power at 1 dB compression point

Evolution of fundamentalcomponent

Evolution of intermodulationcomponent of third order

Third-order interception point

Pin,1 dB

Figure 7.15. Illustration of third-order interception point (IP3)

Figure 7.16. Illustration of calculating the NPR

It is given by the equation:

NPR =

∫carrier

P (f)df∫hole

P (f)df.BWhole

BWcarrier[7.8]

BWhole represents the spectrum hole in the center of the signal spectrum tosimulate the measurement. Thus, the IM noise can evaluate the noise power inthe hole.


7.3.3.5. Adjacent channel power ratio (ACPR)

Now to characterize the IM noise generated in adjacent channels, another criterionof merit is defined. The ACPR is the ratio of power leaked into an adjacent channel tothe power in the useful band. For power spectral density P (f), the ACPR is given bythe equation:

ACPR =2∫ f2f1P (f)df∫ f4

f3P (f)df +

∫ f6f5P (f)df

[7.9]

Figure 7.17 illustrates the calculation of the ACPR.

Figure 7.17. Illustration of the calculation of the ACPR

7.3.3.6. Error vector magnitude (EVM)

The EVM is a merit criterion used to measure the errors that appear between theoriginal constellation and the measured constellation (after degradation). The EVM isthe absolute value of error vector

−−→RM in the (I , Q) plane, as shown in Figure 7.18,

where R and M are the coordinate points (IR, QR) and (IM , QM ), respectively.

The EVM is mathematically averaged over N measurements and given by:

EVM =

√√√√∑N−1n=0 (IM (n)− IR(n))2 + (QM (n)−QR(n))2∑N−1

n=0 (IR(n))2 + (QR(n))2

[7.10]

The EVM states that there is a memory effect related to the filtering stages beforethe power amplification.


Figure 7.18. Illustration of the EVM’s calculation

7.3.4. Modeling of a memoryless power amplifier

An amplifier is memoryless if its output at a time t0 depends uniquely at its inputat t0. In terms of frequency, this reflects the fact that the bandwidth of the amplifieris much greater than that of the signal to be amplified. We will examine more closelythe input–output relations in this case.

7.3.4.1. Input–output relationship of an amplifier

Let x(t) and y(t) be the input and output of a memoryless amplifier, respectively.The signal x(t) is:

x(t) = |x(t)|cos(ωct+ ψ(t)) [7.11]

After amplification without memory, the output is written as:

y(t) = A(|x(t))|cos(ωct+ ψ(t) + Ψ(|x(t)|) [7.12]

where A(.) and Ψ(.) are AM/AM and AM/PM characteristics of the amplifier,respectively. Different characteristics are possible for the functions A(.) and Ψ(.).This point is discussed in the next section.


7.3.4.2. The polynomial model

The polynomial model is perhaps the most basic model to study the nonlinearbehavior of the power amplifier. For the relations of amplitude and phase:

A(|x(t)|) =n∑

k=1

ak|x(t)|k [7.13]

and:

Ψ(|x(t)|) =n∑

k=1

bk|x(t)|k [7.14]

The index n can be made as large as desired for the required accuracy. Thecoefficients ak and bk are generally obtained by regression calculations.

7.3.4.3. The Saleh model

The most common model of TWTA amplifiers is the Saleh model according towhich:

A(|x(t)| = ν|x(t)|1 + α|x(t)|2 [7.15]

and:

Ψ(|x(t)|) = β|x(t)|21 + γ|x(t)|2 [7.16]

where ν is the gain of the amplifier. Coefficients α, β, γ are the characteristics of eachamplifier.

7.3.4.4. The Rapp model

The most common model of SSPA amplifier is the Rapp model, given by:

A(|x(t)| = ν|x(t)|[1 + [ ν|x(t)|A0

]2p]12p

[7.17]

and:

Ψ(|x(t)| ≈ 0 [7.18]

whereA0 = νAS is the output saturation amplitude. p is an integer that is adjusted sothat the theoretical values approach the experimental values. When p becomes large,the AM/AM curve approaches the ideal transformation, as shown in Figure 7.19.


y(t)

νAS

S(t)

AS

Figure 7.19. Representation of the ideal limiter

7.3.5. Modeling of a power amplifier with memory

In practice, the amplifiers have different AM/AM and AM/PM characteristicsdepending on the frequency, which must be taken into account in widebandapplications. The models that incorporate this aspect are the models with memory.Models have been proposed to take into account this frequency dependence, includingSaleh’s model, the Wiener–Hammerstein model, the Volterra, and the polynomialmodels with memory.

7.3.5.1. The Saleh model

It is possible to adapt the memoryless Saleh model to a model with memory byincluding a frequency dependence in the coefficients of equations [7.15] and [7.16].The Saleh model with memory is therefore given by [KEN 00]:

A(|x(t)|, f) = ν(f)|x(t)|1 + α(f)|x(t)|2 [7.19]

Ψ(|x(t)|, f) = β(f)|x(t)|3[1 + γ(f)|x(t)|2]2 [7.20]

Relations ν(f), α(f), β(f), and γ(f) characterize the frequency dependence ofthe model. They are usually obtained using simulation by comparing input and outputof the amplifier fed by a variable frequency.


7.3.5.2. The Volterra model

The relationship between the complex envelopes of input x(n) and output y(n) ofa nonlinear amplifier with memory can be described using a Volterra series, given by[KEN 00]:

y(n) =

N∑i=0

h1(i)x(n−i)+N∑i=0

N∑j=0

N∑k=0

h3(i, j, k)z(n−i)z(n−j)z∗(n−k)...+ε(n)

[7.21]

The notations used are as follows:

– h1 and h3 are the Volterra kernels (linear and cubic, respectively);

– n is the time index;

– N is the depth of the memory;

– ε is the modeling error.

IfK is the order of nonlinearity, the Volterra model requires (N+1)K coefficientsfor hi kernels. As it can quickly become prohibitive in terms of complexity, othermodels have been proposed.

7.3.5.3. The Wiener–Hammerstein model

The Wiener–Hammerstein model is one of the models that concatenate a dynamiclinear system (filters h in Figures 7.20 and 7.21) with a static nonlinear system (filtersb and c in Figures 7.20 and 7.21, respectively) [CRA 02]. We often associate it withthe Hammerstein–Wiener model. They are shown in Figure 7.20.

h1(n) b h2(n)

z(n) u(n) w(n)za (n)

b h(n) c

z(n) u(n) w(n) za (n)

Figure 7.20. The Wiener–Hammerstein model (above) and theHammerstein–Wiener model (below)

The simplified versions of these models are known as the Wiener model and theHammerstein model and are given in Figure 7.21.


z(n)

z(n) u(n)

u(n)

za (n)

za (n)

b h(n)

h(n) c

Figure 7.21. Wiener (above) and Hammerstein (below) models

On the basis of such a simplified model of Hammerstein, the overall response isgiven by:

za(n) =

Q∑q=0

h(q)K∑

k=1

bkz(n− q)|z(n− q)|k−1 [7.22]

where bk and h(q) are the coefficients of the linear and nonlinear stages, respectively.

7.3.5.4. The polynomial model with memory

Inspired by the Volterra and Wiener–Hammerstein models, the polynomial modelwith memory is given by:

za(n) =

K∑k=1

L∑l=0

fklz(n− ln0)|z(n− ln0)|k−1 [7.23]

where K and L are the degrees of nonlinearity and memory depth of the amplifier,respectively, and n0 a variable that models the delay introduced by the memory effect.The Hammerstein model presented above is a special case of polynomial model withfkl = ckh(l).

7.4. Converters

7.4.1. Introduction

The analog-to-digital conversion (ADC) and digital-to-analog conversion (DAC)are key elements in the SR. We will present the constraints and the compromisesabout the conversion. We will initially analyze the different phenomena thatlimit performance and highlight the relationships between them. The objectiveis to understand the complex relationships between accuracy, speed, cost, andconsumption, which depend on noise, linearity, and technology.


7.4.1.1. Requirements for the software radio

The SDR would like to have a very wideband analog front end (AFE) todigitally process the signals contained in this band, but what about the constraintsrelated to ADC? This approach often raises delicate problems such as thermalnoise, intermodulation, phase noise of the clock, and consumption [LOU 02, PIT 07,PLA 05]. Note that consumption constraints are not the same in the case of anembedded system (battery powered) and a base station that has all the energy required.Some keywords in the context of SDR deserve explanation:

– direct sampling of RF, or ideal software radio (SR) (see section 6.4.1), requiresthe extreme performance of ADC, which is about to be achieved soon, but at the costof high consumption, often unrealistic for a battery-powered system. In this context,SDR will probably be a better choice. Otherwise, a careful study should focus on thelinearity of the circuits in the presence of interference signals of high amplitude andthe SNR when the bandwidth is increased;

– a first goal might be to achieve a multistandard converter, such a convertercompatible with GSM/DECT/GPS. The difficulty is to meet very diversifiedconstraints with the same architecture: in fact, the constraints (for example jammers1)are very different from one standard to another, and so is the sensitivity or frequencyof the signals;

– a second goal would be to convert the entire frequency band in the digital domainto extract each channel digitally (in the case of GSM, for example): the extension ofthe bandwidth therefore requires a converter of high resolution that will necessarily beof high consumption;

– a third objective would be to digitize a wideband including different standards:in addition to the constraints of SNR, linearity, and consumption, there is the difficultyof assessing the extreme conditions of conversion, i.e. to characterize blockers2 andjammers. The question that arises is the following: would it not be better to useseveral specific converters according to the standards than a single converter todigitize the entire band? In the analog domain, given the large number of constraints,performance is easier to adapt to a restricted domain.

The well-defined objectives can lead to different architectures:

– choice of a zero intermediate frequency (ZIF) or low (NZIF): this is acompromise taking into account the sampling phase noise, the ability to compensateor eliminate the direct current (DC) component generated by auto-coupling of thelocal oscillator (possibility to cut the low-frequencies, IP2 linearity of the mixer, the

1 Large amplitude signals present in the spectrum in the receiver can interfere with the weaksignals under the effect of nonlinearities (intermodulation).2 Large amplitude signals that could lead to the saturation of the analog circuits.


dynamics of the converter, etc.), such an architecture, also called direct conversion, isshown in Figure 6.6;

– use of a low IF: this solution does not generate a DC component at the cost ofhigher sampling frequency at the ADC stage and therefore increased consumption (atleast double). This second architecture is depicted in Figure 6.9;

– under- or oversampling: the undersampling of a signal at IF or RF may be usedto achieve frequency transposition (the role of the mixer), but anti-aliasing filtering isa problem that can become difficult (necessarily analog filtering). This third approachis described in section 6.4.2.3. In contrast, oversampling is widely used to increasethe resolution of the converter; the interest is different.

7.4.2. Characteristics of the converters

To better understand the constraints related to conversion, the crux of the SDR, letus define the main errors generated by the converters. We can consider that the noiseis the set of phenomena that degrade the SNR. The noise may interfere with the signalor its harmonics or even with quantization noise and result in a particular spectralshape. Let us describe the main features of these phenomena.

7.4.2.1. Quantization noise

We can easily show that an N-bit conversion of the signal generates a quantizationnoise that is assumed to be white and uniformly distributed throughout the band; theSNR is then given by equation [7.24] [JES 01]:

SNR = 6.02N + 1.76 dB [7.24]

Note that this expression is given for a full-scale input signal (voltage full scale).For a lower level, the SNR is proportional to the amplitude of the signal (seeFigure 7.22). The signal-to-noise-and-distortion ratio (SiNAD) is more realistic thanthe SNR. It takes into account the total harmonic distortion (THD) that may occurwhen the signal has high-frequency and high amplitude. It is the same phenomenonresponsible for the generation of intermodulations. Intermodulation products areincluded in this measure. It can be seen in Figure 7.22 that SiNAD is less than theSNR expressed previously.

The inversion of relation [7.24] gives the effective number of bits (ENOB) versusthe SiNAD:

ENOB =SiNAD − 1.76 dB

6.02[7.25]

We note that the power of quantization noise does not depend on the bandwidth ofthe converter (this is not true for its power density). Let us take, for example, the case


of a sinusoidal signal of 1 V peak and a 14-bit conversion. The quantization noisehas a power of 10 dBm − 86 dB = 76 dBm, whatever the bandwidth may be. This isillustrated in Figure 7.23.

Figure 7.22. Example of the evolution of the SiNAD, SNR, and THD, expressed in dB, as a function of the signal amplitude (horizontal axis, the level is given in dBFS, i.e. a signal level in decibels relative to the full-scale amplitude): at low amplitude, it is mainly the quantization noise that degrades the signal, the SiNAD is equal to the SNR, then at high amplitude and high frequency, the harmonic distortion that degrades the signal, the SiNAD decreases when the amplitude approaches the full scale

Figure 7.23. Spectrum of a sinusoidal signal and quantization noise: bothfigures show the spreading of quantization noise when the bandwidth increases

(by a factor of 4): although the quantization noise power (the shaded area)remains constant

It is noteworthy that oversampling spreads the quantization noise; with thecondition of eliminating the noise outside the useful band by digital filtering, the SNRis improved by 3 dB (0.5 bit) on doubling the sampling frequency (which can beassumed by doubling the consumption). Note that oversampling can also simplify theanti-aliasing filtering.


7.4.2.2. Thermal noise

Any receiver chain generates a thermal noise of power proportional to thebandwidth B. Noise KTB (with K , the Boltzmann constant and T , the absolutetemperature) is affected by the noise figure of the analog front end (Figure 7.24),before being converted. The noise power is proportional to the bandwidthB V 2

n = KTB, which in dBm is: V 2n = −174 dBm + 10 log(B). The noise thus

has a minimum value, proportional to the bandwidth. The signal, in turn, is limited toa value that depends on the technology used (less than 1 V peak in CMOS 90 nm); theSNR is thus reduced on increasing the bandwidth.

One can reasonably assume that the converter also generates a noise proportional tothe bandwidth by including thermal noise and shot noise of the transistors. However,the SNR is degraded mainly by the first stages of the receiver chain, the low noiseamplifier and the mixer. Figure 7.24 illustrates the evolution of signal and noise alongthe receiver chain.

Figure 7.24. The evolution of the signal and the noise power from the input to the output in a receiver chain; noise power is proportional to the bandwidth B and is given by (vn)2 = –174dBm + 10log(B). KTB noise is then amplified and affected by the noise figure of the chain, before being digitized by the ADC. The signal is then amplified by the channel, but it has large crests (PAPR) and must be less than the full scale of the converter


For the bandwidth, thermal noise has a different behavior than quantization noise;thermal noise has a constant power density when we vary the bandB of the converter.

The issue of thermal noise arises differently depending on whether we work on anarrowband channel or we digitize a large number of channels:

– in narrowband case, it is possible to digitally filter noise outside the band inorder to limit its effects. Then the quantization noise and phase noise of the clockdominate. Note that if the sampling frequency is small compared to the bandwidth ofthe converter, thermal noise may fold into the Nyquist band and degrade the SNR;

– if we try to digitize a large number of channels, the problem is different. Byincreasing the bandwidth by a factor γ, the noise power is also multiplied by γ, whilethe input signal power is limited and remains constant. The power of each channelis then reduced, leading to a loss of SNR in each subband by 10log(γ2), whichcorresponds to a loss of 2 bit (−12 dB) whenever we multiply the number of channelsby 4, as shown in Figure 7.25.

Figure 7.25. Spectral shape of thermal noise as a function of the bandwidth and when the signal energy is spread over different channels: when more bands are converted, the power density of the signal is reduced while the noise remains constant. To maintain the same signal-to-noise ratio in each channel, we must increase the number of bits of the converter and its bandwidth at the same time

Thus, for GSM, while the conversion of a channel can be done with 9 bits over abandwidth of 200 kHz, the conversion of 128 channels requires a 14-bit converter witha bandwidth of 25 MHz. We should be aware of the consequences in terms of powerconsumption: this converter will consume about 16, 000 times more power than thatfor a single channel, a solution hardly applicable to mobiles.

7.4.2.3. Sampling phase noise

The generation of the clock signal remains a significant problem today, especiallywhen we try to achieve rapid and accurate converters [BER 06]. To convert a sinewave of frequency fin, the phase noise τj of the sampling clock (also called jitter)is translated into noise (see Figure 7.26): it limits ENOB of the converter followingrelation [7.26]. In this equation, τj corresponds to the quadratic sum of various jitter


sources: generation jitter, distribution, and internal jitter of the ADC:

2ENOB ≤ 1

2π.τj .fin[7.26]

This noise is common to all architectures of the converters. The complexrelationship between the phase noise of the oscillator and the induced noise dependson the slope of the signal (see Figure 7.27): the noise generated is increased for a fastsignal, so it is proportional to the bandwidth. This induced noise is correlated to theinput signal and is therefore capable of generating spurious components in the signalspectrum.

Figure 7.26. Sampling noise generated by the jitterof the sampling clock

A clock phase noise of τj = 0.2 ps does not allow us to exceeding the 13-bitprecision when a signal at fin = 100 MHz is converted (see Figure 7.27). Caremust therefore be taken regarding the clock driver circuitry, the groundings andelectromagnetic compatibility issues (EMC). Clock noise is often reduced using aphase locked loop external to the converter that reduces the frequency dispersion ofthe carrier [PIT 07]. This problem of clock phase noise becomes a major constraintwhen we reach the sampling frequency of 100 MHz with resolutions of 12− 14 bits.The evolution of technology suggests very slow progress in resolving this problem[WAL 99].

Finally, note that the conversion at undersampling is very sensitive to phase noisesince SNR degradation due to phase noise is given by equation [7.27] [WAL 99].

D = 20 log2Fsignal

Fclock[7.27]


Figure 7.27. Sampling phase noise becomes the predominant limitation in fastand precise converters. We see in this graph the maximum number of effective

bits depending on the frequency of the input signal for different values ofclock jitter

7.4.2.4. Measuring spectral purity: the spurious free dynamic range (SFDR)

The energy representation of the SNR is not always significant: there are indeed,in the spectrum of the converted signal, many peaks (spurious) that are replicas ofthe input signal, subharmonics of the clock signal, or intermodulation of all theseparasites. The SNR can then be reduced: to express the spectral purity of signal, weprefer to refer to the SFDR rather than the SNR (Figure 7.28) [BER 06].

These spurious peaks appear as the effect of nonlinearity and also by parasiticcouplings. To minimize parasitic couplings, special care must be taken decouple tothe power supplies. In the receiver chain, the nonlinearities are also generated bythe converters themselves, especially when the speed (dv/dt) of the input signalexceeds the slew rate of the internal amplifiers of the converters. The slew ratecorresponds to the maximum speed dv/dt, which the amplifiers may reach: this is afundamental limitation and explains the drop in SiNAD when the signal amplitudeapproaches the full scale (Figure 7.22). As the slew rate is proportional to theamplifiers’ consumption, improvement in the converter’s spectral purity goes throughits increased consumption [PIT 07]. The SFDR, however, depends on the conversionconditions, sampling frequency, input signal, etc. The converters are often optimizedfor very specific conditions.


Figure 7.28. Frequency spurious appear as a result of intermodulationbetween the signals, their harmonics, the clock signal, etc. Spectral purity is

better defined by the SFDR than SNR

Figure 7.29. SFDR is the ratio between the signal and the highest parasiticpeak: these peaks are created by intermodulation with the input signal.

(a) The dither is about adding noise either in the band of unused frequencies;(b) or over the entire band; (c) it results in an improved SFDR

7.4.2.5. SFDR improvement by adding noise: the dither

To improve the SFDR, some converters use the dither. The dither3 is about addingnoise to the signal we want to convert to improve spectral purity. This additional noisecan decorrelate the quantization noise of the signal, which improves the SFDR. Thenoise signal that is introduced can be of several kinds: either white (spread on theoverall bandwidth) or shifted outside the useful signal band, as shown in Figure 7.29.The SNR is then degraded, either locally or uniformly, but the SFDR is greatly

3 It is a technique of adding noise to eliminate some of the intermodulation with the input signaland thus improve the SFDR.


enhanced. Note that the dither is increasingly used in ADCs of type pipeline andsigma-delta (see section 7.4.4) and also in the DACs (see section 7.4.3).

7.4.2.6. Switched capacitor converters: the KT/C noise

Many switched capacitor converters (CMOS or BiCMOS) operate up to clockfrequencies of the order of 100 MHz. However, the thermal noise power generatedby a switched capacitor is equal to KT/C, where K is the Boltzmann constant, T theabsolute temperature, and C the capacitance value. To achieve the desired accuracy,a converter must use a minimum value of capacitance, which has the effect ofeither reducing the sampling frequency or increasing power consumption. Improvingthe SNR consequently increases the surface area of the circuit and hence its cost.Meanwhile, the increased capacity reduces the slew rate of the internal amplifiers ofthe converters. This leads to a degradation of the harmonic distortion and the SFDR:consequently, improvement of the SNR is thus dependent on the SFDR.

7.4.2.7. Signal dynamics

In radio, the received signals may vary over a large dynamic [HEN 01] (of the orderof 100 dB for GSM and UMTS): demanding such a dynamic from the converter wouldbe at the cost of complexity and excessive power consumption. To limit the scope,an automatic gain control (AGC) is usually necessary. It is located just before theconverter (see Figure 7.24). It reduces the converter’s dynamic range by dividing thesensitivity range of the receiver by the number of AGC segments. A fair compromisebetween the number segments and the dynamics of the converter must be found(linearity constraint of the AGC, performance of the converter, etc.).

Figure 7.30. The automatic gain control device is an amplifier whosegain can vary in steps: the dynamics of the input signal can be much greater

than those of the ADC

7.4.2.8. Blockers

The dynamics of the converter must also take into account the dynamic variationsin the amplitude of the signal (the peak-to-average power ratio (PAPR), preciselydescribed in Chapter 9). We should also consider blockers: in the received signalspectrum there is the useful signal that can be of very low power, but there are alsoadjacent channels that may have large power. These large signals can lead the ADC to


saturation (the standards are not always realistic about this) [HEN 01]. The saturationof the converter can provide the maximum instantaneous values of the signal andits probability can be estimated [ROU 09]. For some converter architectures suchas sigma-delta or pipeline converters, the saturation can lead to a divergence of theconverter.

7.4.2.9. Linearity constraints

Linearity errors are very important to study in a RF receiver chain because theycreate intermodulation between signals. These intermodulations can be calculatedtaking into account the IP3, IP2, and IP5 interception points according to the situation.The constraints of linearity of the analog chain are crucial and often difficult tomaintain: it is sometimes necessary to accept a higher error rate to relax the constraintsof linearity.

7.4.2.10. Jammers

The jammers are defined as high-amplitude signals that can degrade the SNRby intermodulation (mainly IP3). The addition of analog filtering frees the linearityconstraints by reducing the amplitude of the jammers (this technique is sometimesdeveloped even within the converter [LEG 05]). However, it is difficult to envisagethis approach in software radio (SR) as frequencies and filter responses are differentaccording to each communication standard. The situation is even more difficult if thereceiver has to cover several standards in the same band: the extreme conditions arenot necessarily expressed as a standard over another.

7.4.2.11. Bandwidth and slew rate

The slew rate of the first amplifier of the converter is critical to the linearity of theconversion: for a sinusoidal signal, its value is given by:

dvindt

≥ 2πfinvpeak [7.28]

It determines the minimum consumption of the amplifier. The search of high slewrate has the consequence that some converters have a bandwidth that is much greaterthan the sampling frequency: this benefit allows eventual undersampling of the signal.

7.4.2.12. Consumption constraints: the figure of merit (FOM)

Whether it is DAC or ADC, we define the FOM by:

FOM =P

2.B.2ENOB[7.29]

where B is the bandwidth of the converter, P the power consumption, and ENOB theeffective number of bits [LOU 02].


This factor expresses the energy consumed by one conversion (pJ/conversion).The objective is to minimize this factor. The evolution of technology and certainarchitectures makes it possible to play with this factor, but it remains difficult topredetermine accurately (the FOM is between 0.1 and 10 pJ/conversion). We shouldbe careful while analyzing this factor, because to be fully meaningful it is necessarythat the number of effective bits takes into account all the distortions and the phasenoise of the clock, described above. This formula leads us to believe that, as we havealready seen, trying to convert a large number of channels (γ) for digital processing,consumption is multiplied by γ2 (given the increase in the band and the number ofbits). Note that the consumption of the converter is two times lower in the case of aZIF architecture than that for a NZIF. However, this advantage of the ZIF architectureis balanced by the generation of a DC component created by the parasitic couplingsbetween the LNA and the local oscillator as it is presented in Figures 6.7 and 6.8, evenif this DC component can be compensated.

7.4.2.13. Constraints on digital ports

One last important point concerns the digital links between the converters and thefield programmable gate array (FPGA) circuits for which we try to limit the numberof high-rate interconnections. This issue affects both analog-to-digital and digital-to-analog converters and has a direct impact is on the cost of the equipment. Seeing theperformances achieved, today the digital information rate reaches the extreme valuesthat must conform to the JESD204A12 specifications4. Links up to 500 Mbps inLVDS can rise up to 3 Gbps in CML logic. For example, a 12-bit converter witha sampling frequency of 1 GHz requires a connection to 12 Gbps posing seriousproblems: it is typically performed by a partial serialization of data such as four-portat 3 Gbps. It should be added that the serialization of data is usually made with an 8-bit/10-bit encoding: addition of the equivalent 2-bit pseudorandom keeps the averagevalue of the signal, and has the consequence of breaking the periodicity of digitalsignals which degrade the SFDR (spurious appearance generated by the digital link).

7.4.3. Digital to analog conversion architectures

The DAC in SR is used either for the transmission in up-conversion of the mixer orinternally in some analog-to-digital converters (successive approximations or sigma-delta (SD) for example).

7.4.3.1. Current source of DAC architectures

We can distinguish two types of converter architectures: converters that work onswitching current or on the electric charge redistribution [JES 01]. Because of thereduction in battery voltage in recent technologies, voltage switching is less used.

4 Standard of serial link converters.


The fastest converters that work on current source switching are composed of twostructures: one is simple and fast, and the other more accurate but slower [JES 01].The switching of the weighted sources (1, 2, 4, 8, etc.) directly controlled by thebits is simple to implement, in principle, but suffers from very poor quality interms of linearity: the monotonicity is not guaranteed and the overall linearity ispoor. Structures of unit sources provide much better linearity, but the complexity ofaddressing the sources and routing of interconnections is structurally complex andslower. Therefore, a current source of DAC often uses the two systems (subrangingtechnique): unitary for the more significant bits and weighted for the less significantbits, as shown in Figure 7.31.

Figure 7.31. The fastest converters operate by adding current sources to theoutput load. In this example, the sources are weighted for the LSB (weights of1, 2, 4) and unit (weight 8) for the MSB. The thermometric decoder connects

the unit sources, one after the other

A technique increasingly used is the pseudorandom mixing of current sources,which is called shuffling or dynamic element matching (DEM). In this structureconnection with the unit current sources is made by using a pseudorandom generator:the integral linearity error is replaced by white noise (improving SFDR by reducingintermodulation, versus SNR degradation). This technique is increasingly used withinthe sigma-delta converters because of oversampling and due to this the noise can berejected out of the bandwidth.

7.4.3.2. Switched capacitor DAC architecture

Switched capacitor converters are more accurate but slower; sampling noiseKT/C requires the use of relatively high capacitance values, which increases the


charging time. The amplifiers must present a high slew rate at the cost of largerparasitic capacitances and increased consumption.

Switched capacitor structures can also compensate the offset of the amplifiers bysampling it (see Figure 7.32). This approach also compensates for the low-frequencynoise 1/f (flicker noise), which consistently increases when reducing the size of theMOS transistors.

Figure 7.32. Schematic diagram of a switched capacitor DAC: a structurewhich requires the use of high capacitances if we want to reduce the thermal

noise generated by the switches (the noise power is equal to KT/C)

7.4.3.3. Evolution of the DAC

Reducing the size of the transistors increases the matching errors and the low-frequency noise but reduces the parasitic capacitances in return. Therefore, theevolution of MOS technologies can increase the conversion rate but not the precisionand the linearity; techniques such as mixing of sources (as mentioned earlier) are oneresponse to these problems. Generally, the DAC is much faster than ADC and mayeventually work at the RF.

7.4.4. Analog to digital conversion architecture

A certain number of architectures are implemented for ADC; they share the speedand accuracy space (see Figure 7.33). There is no real boundary between them andthese territories are ever changing. The description of these architectures is largelycovered by the literature [LOU 02, PLA 05]. We will limit ourselves here to discusingthe main features and deliver a few remarks concerning the SR.

Figure 7.33 illustrates the performance of several converters in a number ofbits/bandwidth5 planes.

5 These results are from recent publications (2007–2009), and also references from theindustrial domain (Texas Instruments, Analog Devices, National Semiconductors).


Figure 7.33. The number of effective bits as the function of bandwidth is shown.Power consumption is represented by the size of the balls: we clearly see the increase in consumption when the effective number of bits and bandwidth increase. The dotted lines represent constant power consumption, for a given figure of merit (FOM = 0.5 pJ/conversion)

7.4.4.1. Flash structure

Flash structure is found only in the fastest converters; the sampling frequencyreaches 10 GHz (on silicon) but with a resolution limited by architecture complexity(limited to 8 or 6 bits due to the 2N comparators and by the very precise referenceneeded. This is illustrated in Figure 7.34).

It should be noted that the flash architecture is also found inside the multibit sigma-delta or pipeline converters that we will see later.

7.4.4.2. Folding ADC

This technique seems to be coming back slowly in fashion for 8-bit converterstypically. It uses two small flash structures (see Figure 7.35). A reduction of 1 bitallows halving of the size of the converter, but it requires an analog folding block thatremains difficult to implement (in speed and linearity).


Figure 7.34. Architecture of a Flash ADC, the input voltage VE is comparedto 2N elementary reference voltages, using 2N comparators. The structure,

very fast being parallel, is limited to 6- even 8-bits maximum

Figure 7.35. Architecture of a folding ADC: the conversion is done using twosmall Flash ADCs in parallel. LSB converts the signal from the folding block

that operates in a purely analog manner

7.4.4.3. Pipeline structure

It is a repetitive structure (Figure 7.36) of 1 bit or 1.5 bits (with few linearityproblems) or multibit, for example consisting of four stages of 3 bits (linearity of theelementary DACs must be of the order of the overall DAC). This architecture showsinteresting performances for 10- to 16-bit converters. We will also see interleavedpipeline structures that can increase the conversion frequency.

One difficulty with this type of structure is the exigency required in the amplifierand the input sampler. The bandwidth of the amplifier must be three times higher than


the product of the number of bits and the sampling rate [MAT 06], requiring significantconsumption.

Figure 7.36. Architecture of pipeline ADC: it is the repetition of stages thatbehaves in the same manner and operates in parallel. The ADC assesses the k

MSB bits, the DAC, and the subtraction creates the residue that is thenamplified (by 2k) before being processed by the next stage

Many pipeline converters have a bandwidth much higher than the samplingfrequency (e.g. five times). This may allow to operate undersampling therebyreducing consumption (we must of course pay attention to the spectrum aliasing).

7.4.4.4. Successive approximation architecture

This architecture (Figure 7.37) remains competitive in terms of consumption(low figure of merit). The linearity of the converter is directly linked to that of theDAC. There is usually a very large bandwidth, which makes it possible to achievethe undersampling using the sample and holding at input. However, it is a type ofconverter rather opens with precision (16–18 bits) at the cost of speed.

7.4.4.5. Sigma-delta architecture

The converter is composed of two parts: a sigma-delta modulator (which containsan analog filter, an ADC, and a DAC) and a digital filter, as illustrated in Figure 7.38.

Its operation is based on two phenomena: the oversampling that spreads thequantization noise and noise shaping induced by analog filtering. Quantization noiseis rejected outside the bandwidth of the signal and is then eliminated by the digitalfilter [JES 01]. The latter also realizes the decimation to return to the Nyquistsampling conditions.


Figure 7.37. Architecture of a successive approximation ADC: the conversionis done in N cycles where the N bits are evaluated, from the MSB to the LSB,

as in a weighing. The logic block manages the sequence of weights bycontrolling the DAC until it reaches the input voltage value

Figure 7.38. Architecture of a sigma-delta ADC (block diagram): the looped system works on oversampling (at the frequency K fn) and it can reject the quantization noiseoutside the signal bandwidth. The digital filter removes this noise and at the same time achieves the decimation to produce the digital output at the sampling frequency fn

The SNR can be approximated by:

SNR =3

2

(2L+ 1

π2L

)22Nm2L+1 [7.30]

where m is the oversampling ratio (OSR6), L the order of the loop filter, and N thenumber of quantizer bits [MAT 06]. We can find a better resolution by:

– increasing the number of quantizer bits (problems of precision and linearity);

– increasing the filter order, which poses stability problems (the cascadingstructures simplify the stability but raise problems of matching filters);

– increasing the OSR, which reduces the bandwidth.

6 The OSR is the ratio between the sampling frequency and twice the bandwidth.


These compromises open this architecture to many possible solutions. Note thatthe idea of conversion at oversampling is in contradiction with the conversion atundersampling (unless we add a sample and hold a block at the converter input).

There are two types of realizations:

– the discrete time delta-sigma, usually with switched capacitors (Figure 7.39),which is the preferred structure for the most accurate converters (16–24 bits);

– the continuous time delta-sigma (see Figure 7.38) for which there is no samplerat the input. This is somehow achieved by the comparator. This structure favors speedover accuracy. The analog filter of the modulator, suffers from weaknesses in terms oflinearity, precision, and stability (e.g. temperature). These structures are developingwith the demand for converters that are applicable to telecommunications(12–14 bits).

Figure 7.39. Example of a discrete time switched capacitors sigma-delta ADCarchitecture. This is a precise structure with the sampler at the input.

Charging time of the capacitors limits converter speed

Figure 7.40. Architecture of a continuous time sigma-delta ADC. Sampling issomehow performed by the comparator. The analog filters are fast but limit the

linearity and temperature stability, and thus the accuracy


In the category of continuous-time DS, we find structures with different types offiltering:

– Bandpass DS [BEN 09]: the loop filter is a bandpass filter (LC or Gm-C) thatallows us a conversion around an IF: Quantization noise is first rejected outside thefilter bandwidth and then removed by digital filtering. Its consumption is probablytwice that of a low-pass converter. In return, the converter partially provides the roleof filtering the IF.

– Low-pass DS: it uses complex analog filters such as notches to reduce theinfluence of the jammers. The complexity of the converter increases with the benefitof a relaxation in the linearity constraints of analog circuits that precede (LNA, mixer,AGC) [LEG 05]. But this approach is difficult to adapt to different standards when weplace ourselves in the context of SR.

7.4.4.6. Evolution of the ADC analog-to-digital converters

The evolution in the performance of the converters is largely related to technologydevelopments. But the evolution of digital structures is not similar to that for theanalog; in the analog, there are many constraints and it is difficult to predict on whichcharacteristics the evolution will abut.

Generally, new CMOS technology appears every two to three years with theminimum dimensions divided by 1.4. It follows not only the parasitic capacitancesand consumption reduced by the same factor, but also a reduction in supply voltagesand the amplitude of the signals: the amplitude of the signals being reduced, thermalnoise must be reduced at the same time, which prevents reduction in the consumptionof the converter. A significant increase in the leakage currents (below thresholdcurrent and gate current), the matching component errors, and ficker noise can beseen as negative effects.

New technologies can therefore gain in speed over accuracy of analog converters:the evolution of the converters is often made by adding digital processing to correctthese defects.

Another problem associated with technological evolution is cost. At the sametime, reducing the supply voltage requires increased capacitors (KT/C noise), i.e.the occupied surface area while the cost of finer technology dramatically grows. Thissupplementary constraint often leads to the cyclic jumps between performance andlower costs [BRA 08].

7.4.5. Summarizing the converters

The ADC and DAC are complex devices and are optimized according to severaldimensions as the power consumption, the SNR, the SFDR, the bandwidth, or


the cost. We have seen that increasing the bandwidth requires the converters to befaster and more accurate at the same time. The figure of merit reminds us thatincreased consumption of the converters can be critical (especially in battery-poweredapplications) and it must be verified that multistandard or reconfigurable solutionsare possible within the considered context. Another factor is the phase noise of thesampling clock, which is a real limit to the fast and precise conversion of the signals;the SNR and ENOB are more pertinent measures than the converter’s number of bits.

All these issues are different if the goal is to design an adaptable system to manystandards (multistandard equipment) or design a system open to future standards (idealSDR). The definition of objectives is crucial because it will have a significant impacton the consumption and the cost of the equipment. We have discussed the difficultyin implementing high-speed digital links that are used with high resolution and fastconverters, naturally implemented in SR.

7.5. Conclusion

The new constraints imposed by the design of a multistandard terminal have strongrepercussions on the AFE of the transmitter and the receiver. Taking the exampleof the antennas, the converters, or the power amplifiers, this chapter has shownthat the technological obstacles are far from being overcome. Indeed, SDR requiresbandwidths, dynamics or linearities much larger than what current technology permits.Restricted versions of SR (SDR) are to be considered. They will develop medium-term multistandard equipment. Nevertheless, converging progress of technology andsignal processing strongly suggests that current constraints will be overcome. Forexample, the latest generation of power amplifiers have quasi-linear characteristics.

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