Radio-Frequency Effects inIntegrated Circuits

Yun Bai

Directed by Professor Neil Goldsman

Abstract

• Tendency of IC evolvement: faster speed and higher chip density.

• Inductance of on-chip interconnects draws more attention in terms of signal transmission and circuit design.

• Skin effects and semiconductor substrate losses are considered.

• Electromagnetic coupling happens between on-chip components and affects circuit performance.

Thesis Outline

I. Introduction to Inductance

II. Characterization of On-Chip Interconnects

III. Characterization of On-Chip Inductors

IV. High-Speed On-Chip Digital Signal Transmission

V. Electromagnetic Coupling Effects

Transmission Line Theory

L R

C G

Distributed Circuit Model

Semiconductor Substrate

Inter

conn

ect

Insulator

Metal Plate

Metal – SiO2 – Si – Ground Plane

freq > 1GHzChip density > tens of millions of transistors

RLC delay due to interconnects become significant

On-Chip Inductors

Insulator

Insulator

Semiconductor Substrate

Port 1

Port 2

Metal

Via

Metal Ground Plane

Analog RF Circuits:• Low Noise Amplifiers• Mixers• Voltage-Controlled Oscillators

Experimental

EM Simulator

Numerical Modeling

Empirical Equations

Electromagnetic Coupling

Substrate

Insulator

Meta

l

Meta

l

qp

Metal Plate

• Bus Lines• Interconnects

EM Simulator

Numerical Modeling

Empirical Equations

What is Inductance?

• Energy Definition: Magnetic Energy Storage

• Flux Definition: Magnetic Flux Leakage

• Circuit Definition: Induced Voltage by AC Current

*

4

1

4

1Re LIIdvBHW

V

m

IL

dt

dILV

Inductance Classification

Inductance

Self Mutual

Internal External

Internal Self-Inductance

t

BE

EJ

t

DJH

Skin Effect:

iR iL

iii LjRZ

I

EmZ z

i0/

t

EE

tE 2

Maxwell’s Equation:

Internal Impedance:

2

External Self-Inductance

JH

t

BE

I

a

daa

1

ILe

Average Flux:

Loop Inductance

Mutual Inductance

jij JH

t

BE ij

ij

jI

iI

j

i

i

i j

j

j

a

jj

a

c

b a

c

b jiij

jij

iijm

daJ

dadaR

ldldJ

aL

1

4,

AB

Magnetic Vector Potential:

ijR

ild

jld

i

j

What is L for an Interconnect

Semiconductor Substrate

Inter

conn

ect

Insulator

Metal Plate

Internal + External

Interconnect Internal Impedance

-2 -1.5 -1 -0.5 0 0.5 1 1.5 2

0.2

0.4

0.6

0.8

1

1.2

x, m

|Jz/J

z0|

f=1GHzf=5GHzf=10GHz

2tan2

kWk

Zi

1D approximation:

Current Distribution:

x

y

z

0

2

W

2

W

xx EjE 22

Complex Image Theory

I

I

PerfectGround Plane

22

811321ln

4 h

w

w

hLeff

subox

hjjhD

1tanh12

jR

LLeff

D

Insulatoroxh

Metal Plate

subh Substrate

Signal Current

Image Current

Interconnect External Impedance

1 2 3 4 5 6 7 8 9 1010

10.5

11

11.5

12

12.5

13

Frequency, GHz

Ext

erna

l Sel

f-In

duct

ance

, nH

/cm

Na=1015

cm-3

Na=1016cm-3

Na=1017cm-3

I

I

I

I

1 2 3 4 5 6 7 8 9 100

10

20

30

40

50

60

70

80

90

100

Frequency, GHz

Ext

erna

l Sel

f-R

esis

tanc

e,

/cm

Na=1015cm-3

Na=1016cm-3

Na=1017cm-3

Quasi-TEM

Slow Mode

Coupled Interconnects

Substrate

Insulator

Meta

l

Meta

l

qp

Metal Plate

xpx qx

2pW

2pW

2qW

2qW

qxJ

qxJ

'qqh

yz

Virtual Ground Plane

qp

'q (image)

1py

2py

1qy

2qy

pqh

2

2

2

2

2

2222

,

1

1

2

1

1

1

2

11

4 q

q

pp

pp

p

p

qq

qq

q

q

W

W qqq

Wx

Wx

y

y

Wx

Wx

y

y qqpp

pqqpqp

qq

ppqm

dxxJ

dydxdydxhyyxx

xJ

WL

2

2

2

2

2

2222

,

1

1

2

1

1

1

2

1

1

4 q

q

pp

pp

p

p

qq

qq

q

q

W

W qqq

Wx

Wx

y

y

Wx

Wx

y

y qqpp

pqqpqp

qq

ppqm

dxxJ

dydxdydxhyyxx

xJ

WL

Mutual Impedance

1 2 3 4 5 6 7 8 9 104

4.5

5

5.5

6

6.5

7

7.5

8

8.5

9

9.5

Frequency, GHz

Mut

ual I

nduc

tanc

e, n

H/c

m

Na=1019cm-3

Na=1018

cm-3

Na=1017cm-3

Na=1016cm-3

1 2 3 4 5 6 7 8 9 100

10

20

30

40

50

60

70

80

90

100

Frequency, GHz

Mut

ual I

nduc

tanc

e, n

H/c

m

Na=1019cm-3

Na=1018cm-3

Na=1017cm-3

Na=1016cm-3

xpx qx

2pW

2pW

2qW

2qW

qxJ

qxJ

'qqh

yz

Virtual Ground Plane

qp

'q (image)

1py

2py

1qy

2qy

pqh

On-Chip Inductors

Insulator

Insulator

Semiconductor Substrate

Port 1

Port 2

Metal

Via

Metal Ground Plane

NNNmNm

Nmm

Nmm

LLL

LLL

LLL

L

4424,14,

42,2221,

41,12,11

Seg

men

t 1

Segment 2

Segment 4N

Seg

men

t (4N

-1)

Segm

ent i

Inductor Inductance

1 2 3 4 5 6 7 8 9 101

2

3

4

5

6

7

8

Frequency, GHz

Indu

ctan

ce, n

H

Total Length = 3000mTotal Length = 2000mTotal Length = 1000m

1 2 3 4 5 6 7 8 9 10

5.8

6

6.2

6.4

6.6

6.8

Frequency, GHz

Indu

ctan

ce, n

H

N=3N=4N=5

1 2 3 4 5 6 7 8 9 105.7

5.8

5.9

6

6.1

6.2

6.3

6.4

6.5

Frequency, GHz

Indu

ctan

ce, n

H

S=2mS=4mS=6m

1 2 3 4 5 6 7 8 9 104.6

4.8

5

5.2

5.4

5.6

5.8

6

6.2

6.4

6.6

Frequency, GHz

Indu

ctan

ce, n

H

Na=1016

cm-3

Na=1017

cm-3

Na=1018

cm-3

Na=1019

cm-3

NL

S Na

Inductor Resistance

1 2 3 4 5 6 7 8 9 100

5

10

15

20

25

Frequency, GHz

Res

ista

nce,

Total Length = 3000mTotal Length = 2000mTotal Length = 1000m

1 2 3 4 5 6 7 8 9 100

5

10

15

20

25

Frequency, GHz

Res

ista

nce,

nH

N=3N=4N=5

1 2 3 4 5 6 7 8 9 100

5

10

15

20

25

Frequency, GHz

Res

ista

nce,

S=2mS=4mS=6m

1 2 3 4 5 6 7 8 9 10-10

0

10

20

30

40

50

60

70

80

Frequency, GHz

Res

ista

nce,

Na=1016

cm-3

Na=1017

cm-3

Na=1018

cm-3

Na=1019

cm-3

L

S

N

Na

Multi-Layer Spiral

Port 1

Port 2

• Higher Inductance

• Less Chip Area

• Higher Q Factor

On-Chip Digital Transmission

V10 VoVs V0 V1 V2 V3 V4 V5 V6 V7 V8 V9

MOSFET_PMOSMOSFET3

Width=30 umLength=0.24 umModel=PMOS

V_DCSRC3Vdc=2.5 V

MOSFET_NMOSMOSFET4

Width=10 umLength=0.24 umModel=NMOS

VtPulseSRC4

Period=100 psecWidth=50 psecFall=10 psecRise=10 psecEdge=linearDelay=1 psecVhigh=0 VVlow=2.5 V

t

I_ProbeI_dd

V_DCSRC1Vdc=2.5 V

BSIM3_ModelPMOS

BSIM3_ModelNMOS

TranTran1

MaxTimeStep=1 psecStopTime=1000.0 psec

TRANSIENT

S2PSNP10File="tl_4u_x_1mm.s2p"

21

Ref

S2PSNP9File="tl_4u_x_1mm.s2p"

21

Ref

S2PSNP8File="tl_4u_x_1mm.s2p"

21

Ref

S2PSNP7File="tl_4u_x_1mm.s2p"

21

Ref

S2PSNP6File="tl_4u_x_1mm.s2p"

21

Ref

S2PSNP5File="tl_4u_x_1mm.s2p"

21

Ref

S2PSNP4File="tl_4u_x_1mm.s2p"

21

Ref

S2PSNP3File="tl_4u_x_1mm.s2p"

21

Ref

S2PSNP2File="tl_4u_x_1mm.s2p"

21

Ref

S2PSNP1File="tl_4u_x_1mm.s2p"

21

Ref

MOSFET_PMOSMOSFET2

Width=150 umLength=0.24 umModel=PMOS

MOSFET_NMOSMOSFET1

Width=50 umLength=0.24 umModel=NMOS

Semiconductor Substrate

Inter

conn

ect

Insulator

Metal Plate

Each Box: 1 mm

Intrinsic Interver Delay

0.00.51.0

1.52.0

2.5

-0.5

3.0

Vs,

V

20 40 60 80 100 120 140 160 1800 200

0

2

-2

4

time, psec

Vo,

V

rising/falling < 10 ps

0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.250.00 2.50

0.25

0.50

0.75

1.00

1.25

1.50

1.75

2.00

2.25

0.00

2.50

Vin

Vout

Inverter Transfer Characteristics

Vs = 1.26 V

Signal Attenuation, Delay, Dispersion

1

2

0

3

Vs,

V

012

-1

3

V0,

V

012

-1

3

V1,

V

0.00.51.01.5

-0.5

2.0

V2,

V

0.00.51.0

-0.5

1.5

V3,

V

0.00.51.0

-0.5

1.5

V4,

V

0.00.51.0

-0.5

1.5

V5,

V

0.00.51.0

-0.5

1.5

V6,

V

0.00.51.0

-0.5

1.5

V7,

V

0.00.51.0

-0.5

1.5

V8,

V

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.90.0 1.0

1.82.02.22.42.6

1.6

2.8

time, nsec

Vo,

V

0.5

0.0

1.0

Vs1, V

-0.5

0.0

0.5

-1.0

1.0

Vs3, V

-0.5

0.0

0.5

-1.0

1.0

Vs5, V

-0.5

0.0

0.5

-1.0

1.0

Vs7, V

100 200 300 4000 500

-0.5

0.0

0.5

-1.0

1.0

time, psec

Vs9, V

200

400

600

0

800

Vo1, m

V

-200

0

200

400

-400

600

Vo3, m

V

-200

0

200

-400

400

Vo5, m

V

-200

0

200

-400

400

Vo7, m

V

100 200 300 4000 500

-200

0

200

-400

400

time, psec

Vo9, m

V

Critical Length: 8 mm

1 GHz : 220 ps9 GHz : 150 ps

CLv

1

Electromagnetic Coupling

SMA SMA

Device1

Device2

Bond Padwith ESD

Bond Padwith ESD

P+ Guard Ring

Die: P-Type Substrate

Inte

rcon

nect

Inte

rcon

nect

Pin(Leadless)

Pin(Leadless)

Bond Wire Bond Wire

LCC-28 IC Package

Trace Trace

Print Circuit Board

Instruments

Cable Cable

Scattering Parameters

1V

1V

2V

3V

NV

2V

3V

NV

NNNNN

N

N

N V

V

V

SSS

SSS

SSS

V

V

V

2

1

21

22221

11211

2

1

S11: Insertion Loss at Port 1 when Port 2 is matched

S21: Forward Gain from Port 1 to Port 2 when Port 2 is matched

N-Wells

P-Type Silicon Substrate

N Well N Well

Oxide

Metal Contact

Port 1 Port 2

m8.28 m8.28m45.102

2 3 4 5 6 7 8 9 10-30

-28

-26

-24

-22

-20

-18

-16

Frequency, GHz

|S21

|, dB

Measured DataFitted Curve

Transformer

Port 1

Port 2

Metal 3

Metal 2

2 3 4 5 6 7 8 9 10-35

-30

-25

-20

-15

-10

Frequency, GHz

|S21

|, dB

Measured DataFitted Curve

subC subCsubR subR

oxC oxC

2L 2R

2sC

Port 1

12,oxC0L 0R

1sC

Port 1

12,mL12,oxC

Spiral and Transistor

Port 1

Port 2

n+ n+

P-Type Silicon Substrate

2 3 4 5 6 7 8 9 10-55

-50

-45

-40

-35

-30

-25

-20

-15

Frequency, GHz

|S21

|, dB

Measured Data (N=1)Measured Data (N=5)Fitted Curve (N=1)Fitted Curve (N=5)

mW 300

D SG

mW 60

G

D

S

Digital Switching NoisePort 1 Port 2

n+ n+

P-Type Silicon Substrate

n+ n+ p+ p+n

GNDVDD

Acknowledgement

• Professor Neil Goldsman

• Our Group: Zeynep, Xi, Akin, Bo, …

• Committee: Professor Peckerar and Orloff