10 Gb/s Bang-Bang Clock and Data Recovery (CDR) for opticaltransmission systems
N. Dodel1 and H. Klar 2
1MergeOptics GmbH, Am Borsigturm 17, 13507 Berlin, Germany2Technical University of Berlin, Institut fur Technische Informatik und Mikroelektronik, Einsteinufer 17, 10587 Berlin,Germany
Abstract. A Bang-Bang Clock-Data Recovery (CDR) for10 Gb/s optical transmission systems is presented. A directmodulated architecture is used for the design. Its loop char-acteristics can be derived using an analogy to61 theory.The circuit was produced and measured in a commercial0.25µm BiCMOS technology with a transition frequencyfT =70 GHz.
1 Introduction
Linear charge pump-PLLs with the so-called “Hogge” phasedetector (Hogge, 1985) played a long time a favorite role inrealizing Clock-Data-Recovery circuits for optical transmis-sion systems. Its loop characteristic is well known (Gardner,1980) and the low complexity of the phase detector allowsefficient implementation. However, with the migration tohigher data rates the influence of second order effects in thephase detector grows rapidly. Transition mismatches in thedata paths can result in a constant phase error, which is wors-ening the bit-error-rate(BER) of the system. The trend tohigher integration density, system-on-chip and smaller pack-ages made the search for other solutions inevitable.
2 Bang-Bang PLLs
The output characteristic of a Bang-Bang phase detector doesnot contain any information about the absolute value of thephase error|φe|, but only about its sign, as it can be seenat Fig.1. Thus a linearized analysis of the loop behavior asdone in (Gardner, 1980) is not possible.
The first systematical analysis of the bang-bang PLL(Walker, 2003) describes its loop behavior using61 con-version theory in the phase domain.
To understand the system behavior of the Bang-Bang-PLLwe will priorly examine a simplified model of a 1st-orderBang-Bang PLL (see Fig. 2).
It consists of a D-flip-flop and a voltage-controlled-oscillator (VCO), that can be switched between two discretefrequencies, which have a distance offbb to its center fre-quencyf0. The flip-flop has the function of a Bang-Bangphase-detector for a clock signal, instead of a NRZ-data sig-nal as input signal. The applied clock signal with the fre-quencyfin is sampled by the flip-flop at the rising edge ofthe VCO signal.
The VCO is controlled by the outputQ of the flip-flop.For its output frequencyfout holds:
fout (Kin) =
{f0 + fbb if Kin = 0f0 − fbb if Kin = 1
(1)
2.2 Control mechanism of PLL for frequency deviationδf
We assume that the input signal has a clock frequencyfin
which has a frequency deviation ofδf to the VCOs centerfrequencyf0. Furthermore should be|δf |<fbb. Under theseconditions a square wave is generated at the control nodeKin
of the VCO. The duty cycleC of this square wave is depen-dent to the frequency deviationδf of the input signal. Theduty cycleC is given by (Walker, 2003)
C =
(1
2+
δf
2fbb
). (2)
2.3 Control mechanism of PLL to sinusoidal input jitter
To examine the control mechanism of the circuit to sinusoidalinput jitter, we presume that the clock frequency of the inputfin is equal to the center frequency of the VCO (δf =0). Thusthe signal at the control node of the VCO has a duty cycleC=0.5.
294 N. Dodel and H. Klar: 10 Gb/s Bang-Bang Clock and Data Recovery (CDR)
10Gb/s Bang-Bang Clock and Data Recovery(CDR) for opticaltransmission systems
Norman Dodel1 and Prof. Dr. Heinrich Klar 2
1Mergeoptics GmbH2Institut fur Mikroelektronik, Technische Universitat Berlin
Abstract. A Bang-Bang Clock-Data Recovery(CDR) for10Gb/s optical transmission systems is presented. A directmodulated architecture is used for the design. Its loop char-acteristics can be derived using an analogy toΣ∆ theory.The circuit was produced and measured in a commercial0.25µm BiCMOS technology with a transition frequencyfT = 70 GHz.
1 Introduction
Linear charge pump-PLLs with the so-called ”Hogge” phasedetector (Hogge, 1985) played a long time a favorite role inrealizing Clock-Data-Recovery circuits for optical transmis-sion systems. Its loop characteristic is well known (Gardner,1980) and the low complexity of the phase detector allowsefficient implementation. However, with the migration tohigher data rates the influence of second order effects in thephase detector grows rapidly. Transition mismatches in thedata paths can result in a constant phase error, which is wors-ening the bit-error-rate(BER) of the system. The trend tohigher integration density, system-on-chip and smaller pack-ages made the search for other solutions inevitable.
2 Bang-Bang PLLs
The output characteristic of a Bang-Bang phase detector doesnot contain any information about the absolute value of thephase error|φe|, but only about its sign, as it can be seenat Fig. 1. Thus a linearized analysis of the loop behavior asdone in (Gardner, 1980) is not possible.The first systematical analysis of the bang-bang PLL(Walker, 2003) describes its loop behavior usingΣ∆ con-version theory in the phase domain.
Fig. 1. Output characteristic of a Bang-Bang phase-detector
2.1 System analysis of 1st-order Bang-Bang PLL
To understand the system behavior of the Bang-Bang-PLLwe will priorly examine a simplified model of a 1st-orderBang-Bang PLL (seeFig. 2).It consists of a D-flip-flop and a voltage-controlled-oscillator(VCO), that can be switched between two discrete frequen-cies, which have a distance offbb to its center frequencyf0.The flip-flop has the function of a Bang-Bang phase-detectorfor a clock signal, instead of a NRZ-data signal as input sig-nal. The applied clock signal with the frequencyfin is sam-pled by the flip-flop at the rising edge of the VCO signal.The VCO is controlled by the outputQ of the flip-flop. Forits output frequencyfout holds:
fout(Kin) ={f0 + fbb if Kin = 0f0 − fbb if Kin = 1 (1)
Fig. 1. Output characteristic of a Bang-Bang phase-detector
2
2.2 Control mechanism of PLL for frequency deviationδf
We assume that the input signal has a clock frequencyfinwhich has a frequency deviation ofδf to the VCOs centerfrequencyf0. Furthermore should be|δf | < fbb. Underthese conditions a square wave is generated at the controlnodeKin of the VCO. The duty cycleC of this square waveis dependent to the frequency deviationδf of the input sig-nal. The duty cycleC is given by (Walker, 2003)
C =(
12
+δf
2fbb
)(2)
2.3 Control mechanism of PLL to sinusoidal input jitter
To examine the control mechanism of the circuit to sinusoidalinput jitter, we presume that the clock frequency of the inputfin is equal to the center frequency of the VCO (δf = 0).Thus the signal at the control node of the VCO has a dutycycleC = 0.5.The input signal should now exhibit a sinusoidal jitterφD(t).This jitter has a amplitudeJUI (UI meansUnit Interval thatis equivalent to a bit lengthTB) and a frequencyfjitter andis defined by
φD(t) = 2π · JUI · sin (2πfjittert) (3)
moreover the following assumption should be made:
fin =1TB
>> fjitter (4)
As priorly presumed the data rate1/TB (the clock frequencyfin respectively) is now equal to the center frequencyf0, butthe VCO frequency changes from(f0−fbb) to (f0 +fbb) andvice-versa. Thus during every sample periodTB the VCOphase experiences a phase deviationφbb to the phase of theideal input signal without jitter.Which is
φbb = 2π · fbb · TB = 2π · fbbf0
(5)
Now we can define a slew-rateSRbb of the PLL. It can becalculated to
SRbb =φbbTB
= 2π · fbb (6)
This slew rate determines the maximum input jitter deviationthat could be transferred to the output. It follows for a giveninput jitterφD that
δφDδt≤ SRTbb (7)
With the sinusoidal input jitter ofEq. 3andEq. 6followsthat
A Bang-Bang PLL is a so-called slew rate limited system.
D Q
VCOInput Clock Signal
Kin
fout= f0+fbb for Kin= 0
f0-fbb for Kin= 1fout=Input ClockFrequency =(fout+δf)
fout
Fig. 2. 1st-order Bang-Bang PLL
UP
DOWN
Data
Clock
D Q D Q
D Q D QA
T
B
Latch
recovered Data
Fig. 3. Bang-Bang phase detector
3 Bang-Bang phase detector
Until now we assumed that the PLL input signal is a clocksignal, in this case a D-flip-flop is sufficient as phase detec-tor. To implement the phase detector function for a NRZ-data stream as PLL-input signal we will use the so calledAlexander-PD (Alexander, 1975).The block diagram of this phase detector is shown onFig. 3.The circuit samples two consequent data bitsA andB aswell as the transitionT between the two bits. In two XOR-gates the VCO-control signalsUP and DOWN are created(seeFig. 4).
A T B
0
0
0
0 1
1 0
1 1
1 0 0
1 10
1 1
1 1 1
0
0 0 0
DOWN
DOWN
UP
UP
Fig. 4. Timing diagram of the Bang-Bang phase detector
Fig. 2. 1st-order Bang-Bang PLL.
The input signal should now exhibit a sinusoidal jitterφD(t). This jitter has a amplitudeJUI (UI meansUnitInterval that is equivalent to a bit lengthTB ) and a frequencyfjitter and is defined by
φD(t) = 2π · JUI · sin(2πfjitter t
)(3)
moreover the following assumption should be made:
fin =1
TB
>> fjitter . (4)
As priorly presumed the data rate 1/TB (the clock frequencyfin respectively) is now equal to the center frequencyf0, butthe VCO frequency changes from(f0−fbb) to (f0+fbb) andvice-versa. Thus during every sample periodTB the VCOphase experiences a phase deviationφbb to the phase of theideal input signal without jitter.Which is
φbb = 2π · fbb · TB = 2π ·fbb
f0. (5)
Now we can define a slew-rateSRbb of the PLL. It can becalculated to
SRbb =φbb
TB
= 2π · fbb . (6)
This slew rate determines the maximum input jitter deviationthat could be transferred to the output. It follows for a giveninput jitterφD that
δφD
δt≤ SRTbb . (7)
2
2.2 Control mechanism of PLL for frequency deviationδf
We assume that the input signal has a clock frequencyfinwhich has a frequency deviation ofδf to the VCOs centerfrequencyf0. Furthermore should be|δf | < fbb. Underthese conditions a square wave is generated at the controlnodeKin of the VCO. The duty cycleC of this square waveis dependent to the frequency deviationδf of the input sig-nal. The duty cycleC is given by (Walker, 2003)
C =(
12
+δf
2fbb
)(2)
2.3 Control mechanism of PLL to sinusoidal input jitter
To examine the control mechanism of the circuit to sinusoidalinput jitter, we presume that the clock frequency of the inputfin is equal to the center frequency of the VCO (δf = 0).Thus the signal at the control node of the VCO has a dutycycleC = 0.5.The input signal should now exhibit a sinusoidal jitterφD(t).This jitter has a amplitudeJUI (UI meansUnit Interval thatis equivalent to a bit lengthTB) and a frequencyfjitter andis defined by
φD(t) = 2π · JUI · sin (2πfjittert) (3)
moreover the following assumption should be made:
fin =1TB
>> fjitter (4)
As priorly presumed the data rate1/TB (the clock frequencyfin respectively) is now equal to the center frequencyf0, butthe VCO frequency changes from(f0−fbb) to (f0 +fbb) andvice-versa. Thus during every sample periodTB the VCOphase experiences a phase deviationφbb to the phase of theideal input signal without jitter.Which is
φbb = 2π · fbb · TB = 2π · fbbf0
(5)
Now we can define a slew-rateSRbb of the PLL. It can becalculated to
SRbb =φbbTB
= 2π · fbb (6)
This slew rate determines the maximum input jitter deviationthat could be transferred to the output. It follows for a giveninput jitterφD that
δφDδt≤ SRTbb (7)
With the sinusoidal input jitter ofEq. 3andEq. 6followsthat
A Bang-Bang PLL is a so-called slew rate limited system.
D Q
VCOInput Clock Signal
Kin
fout= f0+fbb for Kin= 0
f0-fbb for Kin= 1fout=Input ClockFrequency =(fout+δf)
fout
Fig. 2. 1st-order Bang-Bang PLL
UP
DOWN
Data
Clock
D Q D Q
D Q D QA
T
B
Latch
recovered Data
Fig. 3. Bang-Bang phase detector
3 Bang-Bang phase detector
Until now we assumed that the PLL input signal is a clocksignal, in this case a D-flip-flop is sufficient as phase detec-tor. To implement the phase detector function for a NRZ-data stream as PLL-input signal we will use the so calledAlexander-PD (Alexander, 1975).The block diagram of this phase detector is shown onFig. 3.The circuit samples two consequent data bitsA andB aswell as the transitionT between the two bits. In two XOR-gates the VCO-control signalsUP and DOWN are created(seeFig. 4).
A T B
0
0
0
0 1
1 0
1 1
1 0 0
1 10
1 1
1 1 1
0
0 0 0
DOWN
DOWN
UP
UP
Fig. 4. Timing diagram of the Bang-Bang phase detector
Fig. 3. Bang-Bang phase detector.
2
2.2 Control mechanism of PLL for frequency deviationδf
We assume that the input signal has a clock frequencyfinwhich has a frequency deviation ofδf to the VCOs centerfrequencyf0. Furthermore should be|δf | < fbb. Underthese conditions a square wave is generated at the controlnodeKin of the VCO. The duty cycleC of this square waveis dependent to the frequency deviationδf of the input sig-nal. The duty cycleC is given by (Walker, 2003)
C =(
12
+δf
2fbb
)(2)
2.3 Control mechanism of PLL to sinusoidal input jitter
To examine the control mechanism of the circuit to sinusoidalinput jitter, we presume that the clock frequency of the inputfin is equal to the center frequency of the VCO (δf = 0).Thus the signal at the control node of the VCO has a dutycycleC = 0.5.The input signal should now exhibit a sinusoidal jitterφD(t).This jitter has a amplitudeJUI (UI meansUnit Interval thatis equivalent to a bit lengthTB) and a frequencyfjitter andis defined by
φD(t) = 2π · JUI · sin (2πfjittert) (3)
moreover the following assumption should be made:
fin =1TB
>> fjitter (4)
As priorly presumed the data rate1/TB (the clock frequencyfin respectively) is now equal to the center frequencyf0, butthe VCO frequency changes from(f0−fbb) to (f0 +fbb) andvice-versa. Thus during every sample periodTB the VCOphase experiences a phase deviationφbb to the phase of theideal input signal without jitter.Which is
φbb = 2π · fbb · TB = 2π · fbbf0
(5)
Now we can define a slew-rateSRbb of the PLL. It can becalculated to
SRbb =φbbTB
= 2π · fbb (6)
This slew rate determines the maximum input jitter deviationthat could be transferred to the output. It follows for a giveninput jitterφD that
δφDδt≤ SRTbb (7)
With the sinusoidal input jitter ofEq. 3andEq. 6followsthat
A Bang-Bang PLL is a so-called slew rate limited system.
D Q
VCOInput Clock Signal
Kin
fout= f0+fbb for Kin= 0
f0-fbb for Kin= 1fout=Input ClockFrequency =(fout+δf)
fout
Fig. 2. 1st-order Bang-Bang PLL
UP
DOWN
Data
Clock
D Q D Q
D Q D QA
T
B
Latch
recovered Data
Fig. 3. Bang-Bang phase detector
3 Bang-Bang phase detector
Until now we assumed that the PLL input signal is a clocksignal, in this case a D-flip-flop is sufficient as phase detec-tor. To implement the phase detector function for a NRZ-data stream as PLL-input signal we will use the so calledAlexander-PD (Alexander, 1975).The block diagram of this phase detector is shown onFig. 3.The circuit samples two consequent data bitsA andB aswell as the transitionT between the two bits. In two XOR-gates the VCO-control signalsUP and DOWN are created(seeFig. 4).
A T B
0
0
0
0 1
1 0
1 1
1 0 0
1 10
1 1
1 1 1
0
0 0 0
DOWN
DOWN
UP
UP
Fig. 4. Timing diagram of the Bang-Bang phase detectorFig. 4. Timing diagram of the Bang-Bang phase detector.
With the sinusoidal input jitter of Eq.3 and Eq.6 followsthat
JUI · 4π2fjitter · cos(2πfjitter t
)≤ 2π · fbb . (8)
Thus the loop condition is
2πJUI · fjitter ≤ fbb . (9)
A Bang-Bang PLL is a so-called slew rate limited system.
3 Bang-Bang phase detector
Until now we assumed that the PLL input signal is a clocksignal, in this case a D-flip-flop is sufficient as phase detec-tor. To implement the phase detector function for a NRZ-data stream as PLL-input signal we will use the so calledAlexander-PD (Alexander, 1975).
The block diagram of this phase detector is shown onFig. 3.
The circuit samples two consequent data bitsA andB aswell as the transitionT between the two bits. In two XOR-gates the VCO-control signalsUP and DOWN are created(see Fig.4).
N. Dodel and H. Klar: 10 Gb/s Bang-Bang Clock and Data Recovery (CDR) 2953
VCOData
Charge pump
Bang- Bang Phase-Detector
Clf
direct modulation path∆fBB
integration pathsign(φe)
sign(φe) dt
Fig. 5. 2nd-order Bang-Bang PLL with Integrator for frequencycontrol
f0 t
fout
f0
fout
t
f0
fout
t
f0-fbb
f0 +fbb
f0-fbb
f0+fbb
f0 +fbb
f0-fbb
sign(φe)dt
t
t
t
1/Tb = f0
1/Tb < f0
1/Tb > f0
sign(φe)dt
sign(φe)dt
Fig. 6. Frequency control with a integrator in a 2nd-order Bang-Bang PLL
3.1 2nd-order Bang-Bang PLL
In the analysis in 2.3 we assumed that the data rate1/TB(theclock signalfin in the simplified model respectively) of thesystem is equal to the center frequency of the VCOf0. Fur-thermore we have seen in 2.2 that the 1st-order Bang-BangPLL has a very limited frequency range of2 · fbb around thecenter frequencyf0.In a real circuit the center frequency of the VCO has to beguided towards the data rate1/TB . This is achieved by themeans of a integrator consisting of a charge pump and a ca-pacitorClf , as depicted inFig. 5. The output of this integra-tor is connected to a separate control node of the VCO.The mechanism of this frequency control is shown in detailonFig. 6. Assuming a data rate1/TB equal to the center fre-quency of the VCO, we get fromEq. 2a duty cycleC of 0.5.Thus a triangle signal with constant average can be seen atthe output of the integrator. The system is in equilibrium. Ifthe data rate1/TB is lower than the center frequencyf0 ofthe VCO the duty cycleC of the phase detector output willbe smaller than 0.5. Thus the average of the triangle signalwill decrease, which again regulates the VCO frequency ver-sus a lower frequency. An analogous behavior can be seenfor data rates1/TB higher than the center frequencyf0.
4 Dimensioning for SONET-Specifications
The most important specifications of a CDR circuit are its
1. Jitter transfer
t
1/fJitter21/fJitter1
JUI1
JUI2
ω
0 dB
Jitter Transfer
fcutoff2 fcutoff1 = 2 * fcutoff2
Jitter AmplitudeδJ/δt= max.
Fig. 7. Jitter transfer characteristics for two different jitter ampli-tudes
2. Jitter tolerance
3. Jitter generation
The following section explains the way how PLL-parametershave influence on these specifications.
4.1 Jitter transfer
The jitter transfer gives the quantity of jitter that is passedfrom the CDR-input to its output.
In 2.3 we showed that the control behavior of the Bang-Bang-CDR is limited by its slew rate. FromEq. 9 followsthat the jitter transfer is dependent on the jitter amplitude.The jitter transfer for two different jitter amplitudesJUI1 andJUI2 is shown onFig. 7.For jitter frequencies< fcutoff the control conditionEq. 9 isfulfilled. Thus for jitter transfer can be written
JoutJin≈ 1 (10)
When control conditionEq. 9is not fulfilled the slewing be-gins. As it can be seen onFig. 8 the output phaseΦout isnow triangle-shaped for a sinusoidal input phaseΦin. Thejitter transfer function can now be approximated.(Lee et al.,2004)
∣∣∣∣ΦoutΦin
∣∣∣∣ ≈ΦoutΦin
=fbb ·∆T
Φin=
fbb
4 · fjitter · Φin(11)
This function has a slope of−20dB/Decade.
4.2 Jitter tolerance
The jitter tolerance determines the peak-to-peak valueJP−Pof the input jitter for a jitter frequencyfjitter, that can beapplied to the CDR input without worsening the bit-error-rate (BER) of10−12. In the SONET specifications a jittertolerance mask is given that must be respected by the jittertolerance characteristic of the Bang-Bang CDR.(seeFig. 9).The jitter tolerance characteristic of a Bang-Bang CDR canbe divided in three different regions. The slew-rate-limitingleads to a slope of−20dB/Decade in the middle region of thecharacteristic(seeEq. 11). In the low frequency regions theincreasing influence of the integrator path of the frequency
Fig. 5. 2nd-order Bang-Bang PLL with Integrator for frequencycontrol.
3
VCOData
Charge pump
Bang- Bang Phase-Detector
Clf
direct modulation path∆fBB
integration pathsign(φe)
sign(φe) dt
Fig. 5. 2nd-order Bang-Bang PLL with Integrator for frequencycontrol
f0 t
fout
f0
fout
t
f0
fout
t
f0-fbb
f0 +fbb
f0-fbb
f0+fbb
f0 +fbb
f0-fbb
sign(φe)dt
t
t
t
1/Tb = f0
1/Tb < f0
1/Tb > f0
sign(φe)dt
sign(φe)dt
Fig. 6. Frequency control with a integrator in a 2nd-order Bang-Bang PLL
3.1 2nd-order Bang-Bang PLL
In the analysis in 2.3 we assumed that the data rate1/TB(theclock signalfin in the simplified model respectively) of thesystem is equal to the center frequency of the VCOf0. Fur-thermore we have seen in 2.2 that the 1st-order Bang-BangPLL has a very limited frequency range of2 · fbb around thecenter frequencyf0.In a real circuit the center frequency of the VCO has to beguided towards the data rate1/TB . This is achieved by themeans of a integrator consisting of a charge pump and a ca-pacitorClf , as depicted inFig. 5. The output of this integra-tor is connected to a separate control node of the VCO.The mechanism of this frequency control is shown in detailonFig. 6. Assuming a data rate1/TB equal to the center fre-quency of the VCO, we get fromEq. 2a duty cycleC of 0.5.Thus a triangle signal with constant average can be seen atthe output of the integrator. The system is in equilibrium. Ifthe data rate1/TB is lower than the center frequencyf0 ofthe VCO the duty cycleC of the phase detector output willbe smaller than 0.5. Thus the average of the triangle signalwill decrease, which again regulates the VCO frequency ver-sus a lower frequency. An analogous behavior can be seenfor data rates1/TB higher than the center frequencyf0.
4 Dimensioning for SONET-Specifications
The most important specifications of a CDR circuit are its
1. Jitter transfer
t
1/fJitter21/fJitter1
JUI1
JUI2
ω
0 dB
Jitter Transfer
fcutoff2 fcutoff1 = 2 * fcutoff2
Jitter AmplitudeδJ/δt= max.
Fig. 7. Jitter transfer characteristics for two different jitter ampli-tudes
2. Jitter tolerance
3. Jitter generation
The following section explains the way how PLL-parametershave influence on these specifications.
4.1 Jitter transfer
The jitter transfer gives the quantity of jitter that is passedfrom the CDR-input to its output.
In 2.3 we showed that the control behavior of the Bang-Bang-CDR is limited by its slew rate. FromEq. 9 followsthat the jitter transfer is dependent on the jitter amplitude.The jitter transfer for two different jitter amplitudesJUI1 andJUI2 is shown onFig. 7.For jitter frequencies< fcutoff the control conditionEq. 9 isfulfilled. Thus for jitter transfer can be written
JoutJin≈ 1 (10)
When control conditionEq. 9is not fulfilled the slewing be-gins. As it can be seen onFig. 8 the output phaseΦout isnow triangle-shaped for a sinusoidal input phaseΦin. Thejitter transfer function can now be approximated.(Lee et al.,2004)
∣∣∣∣ΦoutΦin
∣∣∣∣ ≈ΦoutΦin
=fbb ·∆T
Φin=
fbb
4 · fjitter · Φin(11)
This function has a slope of−20dB/Decade.
4.2 Jitter tolerance
The jitter tolerance determines the peak-to-peak valueJP−Pof the input jitter for a jitter frequencyfjitter, that can beapplied to the CDR input without worsening the bit-error-rate (BER) of10−12. In the SONET specifications a jittertolerance mask is given that must be respected by the jittertolerance characteristic of the Bang-Bang CDR.(seeFig. 9).The jitter tolerance characteristic of a Bang-Bang CDR canbe divided in three different regions. The slew-rate-limitingleads to a slope of−20dB/Decade in the middle region of thecharacteristic(seeEq. 11). In the low frequency regions theincreasing influence of the integrator path of the frequency
Fig. 6. Frequency control with a integrator in a 2nd-order Bang-Bang PLL.
3.1 2nd-order Bang-Bang PLL
In the analysis in2.3we assumed that the data rate 1/TB (theclock signalfin in the simplified model respectively) of thesystem is equal to the center frequency of the VCOf0. Fur-thermore we have seen in2.2 that the 1st-order Bang-BangPLL has a very limited frequency range of 2· fbb around thecenter frequencyf0.
In a real circuit the center frequency of the VCO has tobe guided towards the data rate 1/TB . This is achieved bythe means of a integrator consisting of a charge pump anda capacitorClf , as depicted in Fig.5. The output of thisintegrator is connected to a separate control node of theVCO.
The mechanism of this frequency control is shown in detailon Fig. 6. Assuming a data rate 1/TB equal to the centerfrequency of the VCO, we get from Eq.2 a duty cycleC of0.5. Thus a triangle signal with constant average can be seenat the output of the integrator. The system is in equilibrium.If the data rate 1/TB is lower than the center frequencyf0 ofthe VCO the duty cycleC of the phase detector output will besmaller than 0.5. Thus the average of the triangle signal willdecrease, which again regulates the VCO frequency versus alower frequency. An analogous behavior can be seen for datarates 1/TB higher than the center frequencyf0.
3
VCOData
Charge pump
Bang- Bang Phase-Detector
Clf
direct modulation path∆fBB
integration pathsign(φe)
sign(φe) dt
Fig. 5. 2nd-order Bang-Bang PLL with Integrator for frequencycontrol
f0 t
fout
f0
fout
t
f0
fout
t
f0-fbb
f0 +fbb
f0-fbb
f0+fbb
f0 +fbb
f0-fbb
sign(φe)dt
t
t
t
1/Tb = f0
1/Tb < f0
1/Tb > f0
sign(φe)dt
sign(φe)dt
Fig. 6. Frequency control with a integrator in a 2nd-order Bang-Bang PLL
3.1 2nd-order Bang-Bang PLL
In the analysis in 2.3 we assumed that the data rate1/TB(theclock signalfin in the simplified model respectively) of thesystem is equal to the center frequency of the VCOf0. Fur-thermore we have seen in 2.2 that the 1st-order Bang-BangPLL has a very limited frequency range of2 · fbb around thecenter frequencyf0.In a real circuit the center frequency of the VCO has to beguided towards the data rate1/TB . This is achieved by themeans of a integrator consisting of a charge pump and a ca-pacitorClf , as depicted inFig. 5. The output of this integra-tor is connected to a separate control node of the VCO.The mechanism of this frequency control is shown in detailonFig. 6. Assuming a data rate1/TB equal to the center fre-quency of the VCO, we get fromEq. 2a duty cycleC of 0.5.Thus a triangle signal with constant average can be seen atthe output of the integrator. The system is in equilibrium. Ifthe data rate1/TB is lower than the center frequencyf0 ofthe VCO the duty cycleC of the phase detector output willbe smaller than 0.5. Thus the average of the triangle signalwill decrease, which again regulates the VCO frequency ver-sus a lower frequency. An analogous behavior can be seenfor data rates1/TB higher than the center frequencyf0.
4 Dimensioning for SONET-Specifications
The most important specifications of a CDR circuit are its
1. Jitter transfer
t
1/fJitter21/fJitter1
JUI1
JUI2
ω
0 dB
Jitter Transfer
fcutoff2 fcutoff1 = 2 * fcutoff2
Jitter AmplitudeδJ/δt= max.
Fig. 7. Jitter transfer characteristics for two different jitter ampli-tudes
2. Jitter tolerance
3. Jitter generation
The following section explains the way how PLL-parametershave influence on these specifications.
4.1 Jitter transfer
The jitter transfer gives the quantity of jitter that is passedfrom the CDR-input to its output.
In 2.3 we showed that the control behavior of the Bang-Bang-CDR is limited by its slew rate. FromEq. 9 followsthat the jitter transfer is dependent on the jitter amplitude.The jitter transfer for two different jitter amplitudesJUI1 andJUI2 is shown onFig. 7.For jitter frequencies< fcutoff the control conditionEq. 9 isfulfilled. Thus for jitter transfer can be written
JoutJin≈ 1 (10)
When control conditionEq. 9is not fulfilled the slewing be-gins. As it can be seen onFig. 8 the output phaseΦout isnow triangle-shaped for a sinusoidal input phaseΦin. Thejitter transfer function can now be approximated.(Lee et al.,2004)
∣∣∣∣ΦoutΦin
∣∣∣∣ ≈ΦoutΦin
=fbb ·∆T
Φin=
fbb
4 · fjitter · Φin(11)
This function has a slope of−20dB/Decade.
4.2 Jitter tolerance
The jitter tolerance determines the peak-to-peak valueJP−Pof the input jitter for a jitter frequencyfjitter, that can beapplied to the CDR input without worsening the bit-error-rate (BER) of10−12. In the SONET specifications a jittertolerance mask is given that must be respected by the jittertolerance characteristic of the Bang-Bang CDR.(seeFig. 9).The jitter tolerance characteristic of a Bang-Bang CDR canbe divided in three different regions. The slew-rate-limitingleads to a slope of−20dB/Decade in the middle region of thecharacteristic(seeEq. 11). In the low frequency regions theincreasing influence of the integrator path of the frequency
Fig. 7. Jitter transfer characteristics for two different jitter ampli-tudes.
4
t
t
Φin
fbb
fout
Φout
VCO-Frequency
Input and Output Phase of CDRslope = fbb
∆T=1/(4fjitter)
Φout
Fig. 8. Effect of slewing on the jitter transfer
control results in a slope of−40dB/Decade. For jitter am-plitudes lower than0.15UI the jitter has no influence on theBER, thus the jitter tolerance characteristic is flat in this re-gion.
4.3 Jitter generation
The jitter generation numbers the amount of jitter that ex-hibits the recovered clock of the CDR with a ideal input sig-nal without jitter.The SONET-Specification allows a jitter generation of
JP−P ≤ 0.1UI for 50kHz≤ fjitter ≤ 80MHz (12)
For a Bit-Error-Rate of10−12 we get a rms-value of the jitter
JRMS =JP−P
2 · √2erfc−1(2 · BER)
≈ JP−P14
= 0.7ps
(13)
The two dominant sources for jitter in a Bang-Bang-CDR arethe phase noiseL of the VCO and the so-called ’hunting’-jitter JrmsBB that is generated by the VCO switching.The phase noiseL is high-pass filtered in the PLL with atransfer function
GHP (s) =s
1 + s/ω−3dBPLL
(14)
The resulting jitterJrmsvco (in UI) can be calculated with
Jrmsvco =1
2π
√2 ·
∫ f2
f1
|GHP (j2πf)|L(f)df (15)
With a NRZ-coded PRBS data streamVData
VD(t− nTB) ∈ [0; 1] mit n = 1, 2, 3, 4...undTB = bit length
(16)
as input signal results a VCO output signal
VV CO(t) = V · sin [(ω0 + ωbb · Xmod(t)) · t] (17)
0.15UI
1.5UI
4MHz400kHz20kHz 80MHz
JPP
fJ
20dB/dec 40dB/dec
SONET Jittertolerance Mask
Influence of Integral Path
Only influenced by Proportional Path
Jitter Amplitude < 0.15UIno influence on BER
for greater fbb
Fig. 9. Jitter tolerance
with
Xmod(t) ={
0 if VD(t− nTB) = VD(t− (n− 1)TB)
±1 if VD(t− nTB) 6= VD(t− (n− 1)TB)(18)
The rms-value of the jitter can be calculated integrating thespectrum ofEq. 17over the frequency range
JrmsBB =1
2π
√2 ·
∫ f2
f1
FT [VV CO(t)](f)df (in UI)
(19)As both jitter sources are uncorrelated, the overall jitter
can be calculated with
J2rmsges = J2
rmsV CO + J2rmsBB (20)
5 Measurement results
A CDR-prototype was produced in a commercial0.25µmBiCMOS technology.Fig. 12shows the CDR block diagramandFig. 11 the die photography of the prototype. The powerconsumption of the IC is750mW. OnFig. 10 is shown thejitter histogram of the recovered clock from a231−1 PRBS-input signal. The measured rms-value of the jitter is1.15ps.
6 Conclusions
The use of linear charge pump PLLs with ’Hogge’-phase de-tector for clock-data-recovery in optical 10Gb/s systems islimited by the increasing influence of parasitic effects on theloop performance. Bang-Bang-CDRs present a promising al-ternative to linear CDRs. A direct modulated Bang-Bang-CDR for 10Gb/s SONET application was presented. Thesystem behavior of the circuit was described be the means ofa non-linear approach (Walker, 2003). These insights wereused to determine the PLL-parameter which have influenceon the most important SONET-specifications.
Fig. 8. Effect of slewing on the jitter transfer
4 Dimensioning for SONET-Specifications
The most important specifications of a CDR circuit are its
1. Jitter transfer
2. Jitter tolerance
3. Jitter generation
The following section explains the way how PLL-parametershave influence on these specifications.
4.1 Jitter transfer
The jitter transfer gives the quantity of jitter that is passedfrom the CDR-input to its output.
In 2.3 we showed that the control behavior of the Bang-Bang-CDR is limited by its slew rate. From Eq.9 followsthat the jitter transfer is dependent on the jitter amplitude.The jitter transfer for two different jitter amplitudesJUI1 andJUI2 is shown on Fig.7.
For jitter frequencies<fcutoff the control condition Eq.9is fulfilled. Thus for jitter transfer can be written
Jout
Jin
≈ 1 . (10)
296 N. Dodel and H. Klar: 10 Gb/s Bang-Bang Clock and Data Recovery (CDR)
4
t
t
Φin
fbb
fout
Φout
VCO-Frequency
Input and Output Phase of CDRslope = fbb
∆T=1/(4fjitter)
Φout
Fig. 8. Effect of slewing on the jitter transfer
control results in a slope of−40dB/Decade. For jitter am-plitudes lower than0.15UI the jitter has no influence on theBER, thus the jitter tolerance characteristic is flat in this re-gion.
4.3 Jitter generation
The jitter generation numbers the amount of jitter that ex-hibits the recovered clock of the CDR with a ideal input sig-nal without jitter.The SONET-Specification allows a jitter generation of
JP−P ≤ 0.1UI for 50kHz≤ fjitter ≤ 80MHz (12)
For a Bit-Error-Rate of10−12 we get a rms-value of the jitter
JRMS =JP−P
2 · √2erfc−1(2 · BER)
≈ JP−P14
= 0.7ps
(13)
The two dominant sources for jitter in a Bang-Bang-CDR arethe phase noiseL of the VCO and the so-called ’hunting’-jitter JrmsBB that is generated by the VCO switching.The phase noiseL is high-pass filtered in the PLL with atransfer function
GHP (s) =s
1 + s/ω−3dBPLL
(14)
The resulting jitterJrmsvco (in UI) can be calculated with
Jrmsvco =1
2π
√2 ·
∫ f2
f1
|GHP (j2πf)|L(f)df (15)
With a NRZ-coded PRBS data streamVData
VD(t− nTB) ∈ [0; 1] mit n = 1, 2, 3, 4...undTB = bit length
(16)
as input signal results a VCO output signal
VV CO(t) = V · sin [(ω0 + ωbb · Xmod(t)) · t] (17)
0.15UI
1.5UI
4MHz400kHz20kHz 80MHz
JPP
fJ
20dB/dec 40dB/dec
SONET Jittertolerance Mask
Influence of Integral Path
Only influenced by Proportional Path
Jitter Amplitude < 0.15UIno influence on BER
for greater fbb
Fig. 9. Jitter tolerance
with
Xmod(t) ={
0 if VD(t− nTB) = VD(t− (n− 1)TB)
±1 if VD(t− nTB) 6= VD(t− (n− 1)TB)(18)
The rms-value of the jitter can be calculated integrating thespectrum ofEq. 17over the frequency range
JrmsBB =1
2π
√2 ·
∫ f2
f1
FT [VV CO(t)](f)df (in UI)
(19)As both jitter sources are uncorrelated, the overall jitter
can be calculated with
J2rmsges = J2
rmsV CO + J2rmsBB (20)
5 Measurement results
A CDR-prototype was produced in a commercial0.25µmBiCMOS technology.Fig. 12shows the CDR block diagramandFig. 11 the die photography of the prototype. The powerconsumption of the IC is750mW. OnFig. 10 is shown thejitter histogram of the recovered clock from a231−1 PRBS-input signal. The measured rms-value of the jitter is1.15ps.
6 Conclusions
The use of linear charge pump PLLs with ’Hogge’-phase de-tector for clock-data-recovery in optical 10Gb/s systems islimited by the increasing influence of parasitic effects on theloop performance. Bang-Bang-CDRs present a promising al-ternative to linear CDRs. A direct modulated Bang-Bang-CDR for 10Gb/s SONET application was presented. Thesystem behavior of the circuit was described be the means ofa non-linear approach (Walker, 2003). These insights wereused to determine the PLL-parameter which have influenceon the most important SONET-specifications.
Fig. 9. Jitter tolerance.5
Fig. 10. Measurement results: clock jitter
VCO
Biasing Network
B a n g -
B a n g P
D
Charge Pump
PFD+Lock Detect
F r e q u e n c y d i v i d e r
Fig. 11. CDR - die photography
VCC
Bang- Bang PD
VCO
Charge pump
VCC
Charge pump PFD
1/16
Proportional Path
Lock Detect
Bias Block
VCC
VEE
VIP VIN
V C
C
CKOP CKON
VCC
DOP DON
CPO
LCK
R E
F P
R
E F
N
Fig. 12. CDR - Block diagram
References
J. D. H. Alexander. Clock recovery from random binary data.Elec-tronics Letters, 11:541–542, 1975.
F. Gardner. Charge-Pump Phase-Lock Loops.Communications,IEEE Transactions on [legacy, pre - 1988], 28(11):1849–1858,1980. TY - JOUR.
Y. Greshishchev and P. Schvan. SiGe clock and data recovery ICwith linear-type PLL for 10-Gb/s SONET application.Solid-State Circuits, IEEE Journal of, 35(9):1353–1359, 2000. TY -JOUR.
J. Hogge, C. A self correcting clock recovery curcuit.LightwaveTechnology, Journal of, 3(6):1312–1314, 1985. TY - JOUR.
J. Lee, K. Kundert, and B. Razavi. Analysis and modeling of bang-bang clock and data recovery circuits.Solid-State Circuits, IEEEJournal of, 39(9):1571–1580, 2004. TY - JOUR.
R. C. Walker. Designing Bang-Bang PLLs for Clock and Data Re-covery in Serial Data Transmission Systems. In B. Razavi, editor,Phase-Locking in High-Performance Systems, IEEE Press, pages34–45. Wiley-Interscience, 2003.Fig. 10. Measurement results: clock jitter.
When control condition Eq.9 is not fulfilled the slewing be-gins. As it can be seen on Fig.8 the output phase8out is nowtriangle-shaped for a sinusoidal input phase8in. The jittertransfer function can now be approximated.(Lee et al., 2004)∣∣∣∣8out
8in
∣∣∣∣ ≈8out
8in
=fbb · 1T
8in
=fbb
4 · fjitter · 8in
. (11)
This function has a slope of−20 dB/Decade.
4.2 Jitter tolerance
The jitter tolerance determines the peak-to-peak valueJP−P
of the input jitter for a jitter frequencyfjitter , that can beapplied to the CDR input without worsening the bit-error-rate (BER) of 10−12.
In the SONET specifications a jitter tolerance mask isgiven that must be respected by the jitter tolerance charac-teristic of the Bang-Bang CDR (see Fig.9).
5
Fig. 10. Measurement results: clock jitter
VCO
Biasing Network
B a n g -
B a n g P
D
Charge Pump
PFD+Lock Detect
F r e q u e n c y d i v i d e r
Fig. 11. CDR - die photography
VCC
Bang- Bang PD
VCO
Charge pump
VCC
Charge pump PFD
1/16
Proportional Path
Lock Detect
Bias Block
VCC
VEE
VIP VIN
V C
C
CKOP CKON
VCC
DOP DON
CPO
LCK
R E
F P
R
E F
N
Fig. 12. CDR - Block diagram
References
J. D. H. Alexander. Clock recovery from random binary data.Elec-tronics Letters, 11:541–542, 1975.
F. Gardner. Charge-Pump Phase-Lock Loops.Communications,IEEE Transactions on [legacy, pre - 1988], 28(11):1849–1858,1980. TY - JOUR.
Y. Greshishchev and P. Schvan. SiGe clock and data recovery ICwith linear-type PLL for 10-Gb/s SONET application.Solid-State Circuits, IEEE Journal of, 35(9):1353–1359, 2000. TY -JOUR.
J. Hogge, C. A self correcting clock recovery curcuit.LightwaveTechnology, Journal of, 3(6):1312–1314, 1985. TY - JOUR.
J. Lee, K. Kundert, and B. Razavi. Analysis and modeling of bang-bang clock and data recovery circuits.Solid-State Circuits, IEEEJournal of, 39(9):1571–1580, 2004. TY - JOUR.
R. C. Walker. Designing Bang-Bang PLLs for Clock and Data Re-covery in Serial Data Transmission Systems. In B. Razavi, editor,Phase-Locking in High-Performance Systems, IEEE Press, pages34–45. Wiley-Interscience, 2003.
Fig. 11. CDR – die photography.
5
Fig. 10. Measurement results: clock jitter
VCO
Biasing Network
B a n g -
B a n g P
D
Charge Pump
PFD+Lock Detect
F r e q u e n c y d i v i d e r
Fig. 11. CDR - die photography
VCC
Bang- Bang PD
VCO
Charge pump
VCC
Charge pump PFD
1/16
Proportional Path
Lock Detect
Bias Block
VCC
VEE
VIP VIN
V C
C
CKOP CKON
VCC
DOP DON
CPO
LCK
R E
F P
R
E F
N
Fig. 12. CDR - Block diagram
References
J. D. H. Alexander. Clock recovery from random binary data.Elec-tronics Letters, 11:541–542, 1975.
F. Gardner. Charge-Pump Phase-Lock Loops.Communications,IEEE Transactions on [legacy, pre - 1988], 28(11):1849–1858,1980. TY - JOUR.
Y. Greshishchev and P. Schvan. SiGe clock and data recovery ICwith linear-type PLL for 10-Gb/s SONET application.Solid-State Circuits, IEEE Journal of, 35(9):1353–1359, 2000. TY -JOUR.
J. Hogge, C. A self correcting clock recovery curcuit.LightwaveTechnology, Journal of, 3(6):1312–1314, 1985. TY - JOUR.
J. Lee, K. Kundert, and B. Razavi. Analysis and modeling of bang-bang clock and data recovery circuits.Solid-State Circuits, IEEEJournal of, 39(9):1571–1580, 2004. TY - JOUR.
R. C. Walker. Designing Bang-Bang PLLs for Clock and Data Re-covery in Serial Data Transmission Systems. In B. Razavi, editor,Phase-Locking in High-Performance Systems, IEEE Press, pages34–45. Wiley-Interscience, 2003.
Fig. 12. CDR – Block diagram.
The jitter tolerance characteristic of a Bang-Bang CDRcan be divided in three different regions. The slew-rate-limiting leads to a slope of−20dB/Decade in the middleregion of the characteristic(see Eq.11). In the low frequencyregions the increasing influence of the integrator path of thefrequency control results in a slope of−40dB/Decade. Forjitter amplitudes lower than 0.15 UI the jitter has no influ-ence on the BER, thus the jitter tolerance characteristic is flatin this region.
4.3 Jitter generation
The jitter generation numbers the amount of jitter that ex-hibits the recovered clock of the CDR with a ideal input sig-nal without jitter.The SONET-Specification allows a jitter generation of
JP−P ≤ 0.1UI for 50 kHz≤ fjitter ≤ 80 MHz (12)
N. Dodel and H. Klar: 10 Gb/s Bang-Bang Clock and Data Recovery (CDR) 297
For a Bit-Error-Rate of 10−12 we get a rms-value of the jitter
JRMS=JP−P
2·√
2erfc−1(2·BER)≈
JP−P
14=0.7 ps. (13)
The two dominant sources for jitter in a Bang-Bang-CDR arethe phase noiseL of the VCO and the so-called “hunting”-jitter JrmsBB
that is generated by the VCO switching.The phase noiseL is high-pass filtered in the PLL with atransfer function
GHP (s) =s
1 + s/ω−3dBPLL
. (14)
The resulting jitterJrmsvco (in UI) can be calculated with
Jrmsvco =1
2π
√2 ·
∫ f 2
f 1|GHP (j2πf )|L(f )df . (15)
With a NRZ-coded PRBS data streamVData
VD(t − nTB) ∈ [0; 1] mit n = 1, 2, 3, 4...
undTB = bit length (16)
as input signal results a VCO output signal
VV CO(t) = V · sin[(ω0 + ωbb · Xmod(t)) · t ] (17)
with
Xmod(t) =
{0 if VD(t − nTB ) = VD(t − (n − 1)TB )
±1 if VD(t − nTB ) 6= VD(t − (n − 1)TB )(18)
The rms-value of the jitter can be calculated integrating thespectrum of Eq.17over the frequency range
JrmsBB=
1
2π
√2·
∫ f2
f1
FT [VV CO(t)](f )df (in UI) . (19)
As both jitter sources are uncorrelated, the overall jittercan be calculated with
J 2rmsges
= J 2rmsV CO
+ J 2rmsBB
. (20)
5 Measurement results
A CDR-prototype was produced in a commercial 0.25µm
BiCMOS technology. Figure 12 shows the CDR block di-agram and Fig.11 the die photography of the prototype.The power consumption of the IC is 750 mW. On Fig.10is shown the jitter histogram of the recovered clock from a231
−1 PRBS-input signal. The measured rms-value of thejitter is 1.15 ps.
6 Conclusions
The use of linear charge pump PLLs with “Hogge”-phase de-tector for clock-data-recovery in optical 10 Gb/s systems islimited by the increasing influence of parasitic effects on theloop performance. Bang-Bang-CDRs present a promising al-ternative to linear CDRs. A direct modulated Bang-Bang-CDR for 10 Gb/s SONET application was presented. Thesystem behavior of the circuit was described be the means ofa non-linear approach (Walker, 2003). These insights wereused to determine the PLL-parameter which have influenceon the most important SONET-specifications.
References
Alexander, J. D. H.: Clock recovery from random binary data. Elec-tronics Letters, 11, 541–542, 1975.
Greshishchev, Y. and Schvan, P.: SiGe clock and data recovery ICwith linear-type PLL for 10-Gb/s SONET application, IEEE J. ofSolid-State Circuits, 35, (9), 1353–1359, 2000.
Hogge, J. C.: A self correcting clock recovery curcuit, J. of Light-wave Technology, 3(6), 1312–1314, 1985.
Lee, J., Kundert, K., and Razavi, B.: Analysis and modeling ofbang-bang clock and data recovery circuits, IEEE J. of Solid-State Circuits, 39(9), 1571–1580, 2004.
Walker, R. C.: Designing Bang-Bang PLLs for Clock and Data Re-covery in Serial Data Transmission Systems, in: Phase-Lockingin High-Performance Systems, edited by: Razavi, B., IEEEPress, Wiley-Interscience, 34–45, 2003.
