RC1000-II Hardware Reference Manual - hu-berlin.defwinkler/psvfpga/celoxica/rc10… · RC1000-II...

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RC1000-II

Hardware Reference Manual

RC1000-II Hardware Reference Manual

ii

Xilinx, XACTstep and M1 are trademarks of Xilinx Corp.Microsoft and MS-DOS are registered trademarks and Windows, Windows 95 and Windows NTare trademarks of Microsoft Corporation.

This manual was written by Charles Sweeney

Embedded Solutions Limited. All rights reservedVersion 1.0

Embedded Solutions Ltd

iii

Table of ContentsConventions.............................................................................................................................. v

1. INTRODUCTION........................................................................................... 1-1

1.1 About This Manual .................................................................................................... 1-2

1.2 References ................................................................................................................ 1-3

2. INSTALLATION ............................................................................................ 2-1

3. OVERVIEW................................................................................................... 3-1

4. ISA INTERFACE........................................................................................... 4-1

4.1 Address Map ............................................................................................................. 4-2

4.2 Configuration Register ............................................................................................. 4-3

4.3 Status Register.......................................................................................................... 4-4

4.4 Control Register........................................................................................................ 4-6

4.5 Reset Register........................................................................................................... 4-8

4.6 Programmable Clock ................................................................................................ 4-9

4.7 Flags Register ......................................................................................................... 4-10

4.8 Data Register........................................................................................................... 4-11

4.9 Address Register .................................................................................................... 4-12

4.10 Interrupts................................................................................................................. 4-13

5. DATA TRANSFERS...................................................................................... 5-1

5.1 Introduction............................................................................................................... 5-2

5.2 Flags.......................................................................................................................... 5-3

5.3 Data Transfers without Polling................................................................................. 5-5

5.4 Host PC to FPGA Data Transfers ............................................................................. 5-7

5.5 FPGA to Host PC Data Transfers ............................................................................. 5-9

5.6 Data Transfers without Clocking of Data ............................................................... 5-11


iv

6. FPGA ............................................................................................................ 6-1

6.1 Introduction............................................................................................................... 6-2

6.2 Configuration ............................................................................................................ 6-36.2.1 Configuration from Host PC ................................................................................ 6-46.2.2 Configuration from XChecker .............................................................................. 6-46.2.3 Configuration from Serial PROM......................................................................... 6-5

6.3 Clocks........................................................................................................................ 6-66.3.1 Primary Global Clock 2 ....................................................................................... 6-66.3.2 Primary Global Clock 4 ....................................................................................... 6-7

7. INDUSTRY PACK INTERFACE ................................................................... 7-1

7.1 Introduction............................................................................................................... 7-2

7.2 Implementation of Industry Pack Specification Features ....................................... 7-3

7.3 Byte Ordering............................................................................................................ 7-4

7.4 Custom FPGA IP Modules ........................................................................................ 7-5

8. RESET .......................................................................................................... 8-1

9. MISCELLANEOUS JUMPERS ..................................................................... 9-1

10. POWER CONSUMPTION......................................................................... 10-1

11. APPENDIX A - FPGA PIN CONNECTIONS............................................. 11-1

Embedded Solutions Ltd

v

Conventions

A number of conventions are used in this document. Theseconventions are detailed below.

Warning Message. These messages warn you thatactions may damage your hardware.

Handy Note. These messages draw your attention tocrucial pieces of information.

Hexadecimal numbers appear in this document. They are prefixedwith ‘0x’ (in common with standard C syntax).

When describing the logic state of signals, the words HIGH andLOW are used for logic levels 1 and 0 respectively.

Signals with names prefixed by ‘not’ are active-low.


vi

1. Introduction


1-2

1.1 About This Manual

Welcome to the RC1000-II Hardware Reference Manual. TheRC1000-II is an ISA bus plug-in card for PC’s. It has one FPGA thatcan be programmed as a co-processor for the PC. The FPGA isalso connected to an Industry Pack daughter module to enable I/Owith the outside world.

This manual describes the installation and setup of the board. Italso contains all the information necessary to write host PC andFPGA programs for it. However software host libraries and FPGAmacros are supplied with the board and these should be adequatefor most purposes. See the RC1000-II Software User Guide (ref. 1)and RC1000-II Software Reference Manual (ref. 2) for details of theRC1000-II support software.

The chapters in the manual are as follows.

Chapter 1. Introduction, chapter summary, and references.

Chapter 2. Installation of the board in a PC.

Chapter 3. Brief overview of the board.

Chapter 4. The ISA interface and the board’s registers which areaccessible from the host PC over the ISA bus.

Chapter 5. The methods of data transfer between the host PC andthe FPGA.

Chapter 6. Configuration of the FPGA, and the FPGA clocks.

Chapter 7. Industry Pack interface.

Chapter 8. Ways of resetting the board and the resultant state ofthe registers.

Chapter 9. Power consumption of the board.

Chapter 10. Miscellaneous jumpers.

Appendix A. Signals on all FPGA pins.

Introduction

1-3

1.2 References

The documents from Embedded Solutions Ltd (including this one)are all available for download from the ESL web sitewww.embedded-solutions.ltd.uk.

1. RC1000-II Software User Guide v1.0, Embedded Solutions Ltd.2. RC1000-II Software Reference Manual v1.0, Embedded

Solutions Ltd.3. The Programmable Logic Data Book, Xilinx, PN 0010303,

September 1996.4. ICD2053B Programmable Clock Generator, Cypress

Semiconductor Corporation, October 1995.5. Industry Pack Module Draft Standard, VITA-4-95, SBS

Greenspring Modular I/O, 7th April 1995.6. XC4000 Series Technical Information, Xilinx Application Note,

1st June 1996.7. A Simple Method of Estimating Power in XC4000XL/XE/E

FPGAs, Xilinx Application Brief, 30th June 1997.


1-4

2. Installation


2-2

In order to ensure that the board operates correctly first time,please read these instructions completely before attemptinginstallation. It will also help you to read the whole manual first sothat you know how you want the board to be set up.

Installation should ideally be done in an anti-static area.At the very least you should touch an earth point atregular intervals while handling the board, and onlyhandle the board by its edges.

In the references to jumpers in the following instructions,the letter A refers to pins 1 & 2, B refers to pins 3 & 4, etc.The pins are numbered in a zigzag fashion as shownbelow.

1. Set the base address of the board within I/O space. The boardcovers an address range of 32 bytes and the four possible baseaddresses are shown in Table 1. Find out which addresses areavailable in the host computer, select one of them, and set JP2Aand JP2B accordingly.

JP2B JP2A Base Addressfitted fitted 0x100fitted not fitted 0x180

not fitted fitted 0x200not fitted not fitted 0x300

Table 1. Base Address Settings

For Windows 95 the available I/O addresses can be found bydoing the following.• Select Start -> Settings -> Control Panel -> System -> Device

Manager• Click Computer -> Properties -> View Resources ->

Input/Output (I/O)The hexadecimal I/O addresses that are already used are nowdisplayed.

2. If you are going to use an interrupt to indicate when data isready to be read from the FPGA, select it with JP3 as in table 2.

A 1 2

B 3 4

6C 5

Installation

2-3

The host support libraries supplied by EmbeddedSolutions Ltd with the board do NOT use an interrupt soJP3 MUST NOT be fitted.

JP3A IRQ15JP3B IRQ11JP3C IRQ10JP3D IRQ9

Table 2. Interrupt Selection

3. The 16 bits of data transferred between the host PC and theboard are normally clocked into a registered transceiver. Thetransceiver can also be in a transparent mode that is intendedfor ISA bus monitoring applications. JP1 selects registered(default) mode or transparent mode as in table 3.

JP1A not fitted registeredFPGA to ISA fitted transparentJP1B not fitted registeredISA to FPGA fitted transparent

Table 3. Selection of Registered or Transparent Data Transfers

Table 4 shows that JP6 similarly selects registered (default)mode or transparent mode for ISA address bits 1-3, which canbe used as 3 extra data bits for transfers from the host PC to theboard.

JP6 fitted registeredISA to FPGA not fitted transparent

Table 4. Selection of Registered or Transparent AddressTransfers

4. The FPGA can be configured from the host PC, the on-boardserial PROM, or the XChecker cable. This is selected by JP11and JP13 as in table 5. The mode numbers refer to the FPGAmode pins 0-2. For testing of the board and development of newFPGA programs configuration from the host PC should beselected.


2-4

ConfigurationSource

JP11C,mode 2

JP11B,mode 1

JP11A,mode 0

JP13

Host PC orXChecker

fitted fitted fitted fitted

Serial PROM not fitted not fitted not fitted not fitted

Table 5. Configuration Mode

5. The FPGA has two pins connected to clock sources. Primaryglobal clock 2 (pin 35) is selected by JP9 as in table 6 to beeither the programmable clock (400KHz to 100MHzprogrammed by the host PC) or the ISA bus clock (approx.8MHz, dependent upon the host PC).

JP9A programmableclock

JP9B ISA Bus Clock

Table 6. FPGA PGCK2 Selection

The other FPGA clock pin is the primary global clock 4 (pin 78)selectable JP8 as in table 7 between 8 and 32MHz. This alsoselects the clock for the Industry Pack module.

JP8A 8MHzJP8B 32MHz

Table 7. FPGA PGCK4/Industry Pack Clock Selection

6. Switch off the host PC and disconnect it from the electricitysupply.

7. Remove the case from the host PC.8. Locate a free 16-bit ISA slot and remove the rear panel.9. Push the RC1000-II into the slot.10. Screw down the board’s rear panel with the screw that held

down the previous rear plate. A spare screw is supplied with theboard.

11. Replace the case of the host PC.

Installation

2-5


2-6

3. Overview


3-2

RC1000-II is an ISA PC plug-in card with one FPGA and oneIndustry Pack site. Figure 1 shows the block diagram. The FPGAinterfaces to both the ISA bus and the IP bus.

The programmable clock is programmed by the host PC and has afrequency range of 400KHz to 100MHz. Other possible clocksources are the ISA bus clock (approx. 8MHz dependent on thehost PC) and the IP bus clock, which is jumper selectable to 8MHzor 32 MHz.

The FPGA is a Xilinx 4000E series in 84-pin PLCC package so thelargest device that can be used is the XC4010E. The standardspeed grade fitted is the –4. It is programmable from either the hostPC or the on-board serial PROM.

Industry Pack modules are available from many third partymanufacturers. They provide a comprehensive range of I/Ofunctions including digital and analogue I/O, and serial buses suchas Ethernet and most fieldbuses.

ISA Interface

Xilinx4000series

Industry Pack

Prog Clock

I/O

Figure 1. RC1000-II Block Diagram

Overview

3-3


3-4

4. ISA Interface


4-2

4.1 Address Map

The board is in I/O address space, the base address being selectedby JP2 as in Table 8. JP2A is pins 1 and 2; JP2B is pins 3 and 4.

JP2B JP2A Base Addressfitted fitted 0x100fitted not fitted 0x180

not fitted fitted 0x200not fitted not fitted 0x300

Table 8. Base Address Settings

The board registers cover an address range of 32 bytes at addressoffsets 0x000 to 0x01F.

The data width is 16 bits and byte address bits 1 to 9 are decoded,note that byte address bit 0 is not decoded so all registers are 16bits wide. The registers are defined in Table 9.

Register ByteAddress

Write/Read

Data Bit

Offset 15 3 2 1 0Configuration 0x000 W X X X X Serial DataStatus 0x000 R X 0 DONE notINIT not

PROGRAMControl 0x002 W/R X 0 DONE notINIT not

PROGRAMReset 0x004 W/R X 0 0 Configure ResetProgrammableClock

0x006 W SerialData

X X X X

Flags 0x006 R X 0 0 FPGAData

Ready

not HostData Ready

Data 0x010 –0x01F

W/R Data Bits 15-0 available for application

Address 0x010 –0x01F

W Address bits 3-1 available for application

Table 9. Register Summary

ISA Interface

4-3

4.2 Configuration Register

ByteAddress

Write/Read

Data Bit

Offset 15 3 2 1 00x000 W X X X X Serial Data

When the host PC is configuring the FPGA, the FPGA configurationserial bit stream is written to data bit 0 of this register.

Jumpers JP11 and JP13 must all be fitted as in table 10. The modenumbers refer to the FPGA mode pins 0-2, see ref. 3 forexplanation of the mode pins.

ConfigurationSource

JP11C,mode 2

JP11B,mode 1

JP11A,mode 0

JP13

Host PC orXChecker

fitted fitted fitted fitted

Serial PROM not fitted not fitted not fitted not fitted



4-4

4.3 Status Register

ByteAddress

Write/Read

Data Bit

Offset 15 3 2 1 00x000 R X 0 DONE notINIT not

PROGRAM

The states of the following FPGA pins are read. See the Xilinx DataBook (ref. 3) for full descriptions.

notPROGRAM Control register output to the FPGA, pulsedLOW for 300nS to initiate configuration of theFPGA, normally HIGH.

notINIT This is an open-drain signal which can bedriven LOW by either the Control register orthe FPGA. If neither is driving, it is pulledHIGH by a passive resistor.Before configuration of the FPGA, a LOWoutput from the FPGA indicates that the FPGAis clearing its internal configuration memory. ALOW output from the Control register holdsthe FPGA in an internal wait state.During configuration of the FPGA, a LOWoutput from the FPGA indicates aconfiguration error.After configuration of the FPGA, this is anFPGA input for the flag not Host Data Ready.

DONE This is an open-drain signal which can bedriven LOW by either the Control register orthe FPGA. If neither is driving, it is pulledHIGH by a passive resistor.During configuration of the FPGA, the FPGAdrives it LOW.After configuration of the FPGA, the FPGAreleases it to allow it to go HIGH indicating thecompletion of configuration. The Controlregister can drive it LOW to delay the finalstages of configuration which are global logicinitialization and enabling of outputs.

notPROGRAM, notINIT and DONE in the Status register are thesignals present at the FPGA pins, and the same named signals in

ISA Interface

4-5

the Control register are active low open-drain signals set by thehost PC. When the Control register bits are set low and theconfigure bit in the Reset register is set high, the Control registeroutputs are driven low. Otherwise they are tri-state and the FPGAor serial PROM or XChecker cable can drive these signals with theirequivalent open-drain outputs. Reading the Status register givesthe value of the FPGA pins, NOT the internal bits in the Controlregister.


4-6

4.4 Control Register

ByteAddress

Write/Read

Data Bit

Offset 15 3 2 1 00x002 W/R X 0 DONE notINIT not

PROGRAMDefault stateafter reset

X 0 HIGH HIGH HIGH

The following Control register bits can be written/read. See theXilinx Data Book (ref. 3) for full descriptions of the equivalent FPGApins.

notPROGRAM Output to the FPGA, pulsed LOW for 300nS toinitiate configuration of the FPGA, normallyHIGH.Output to the FPGA is enabled whennotPROGRAM is LOW, otherwise the outputis tri-state to allow control by the serial PROMor the XChecker cable. If nothing is driving, itis pulled HIGH by a passive resistor.

notINIT This is an open-drain signal which can bedriven LOW by either the Control register orthe FPGA. Output to the FPGA is enabledwhen notINIT is LOW and the configure bit inthe Reset register is HIGH. If neither is driving,it is pulled HIGH by a passive resistor.Before configuration of the FPGA, a LOWoutput from the Control register holds theFPGA in an internal wait state.

DONE This is an open-drain signal which can bedriven LOW by either the Control register orthe FPGA. Output to the FPGA is enabledwhen DONE is LOW and the configure bit inthe Reset register is HIGH. If neither is driving,it is pulled HIGH by a passive resistor.The Control register can drive it LOW beforethe end of configuration to delay the finalstages of configuration which are global logicinitialization and enabling of outputs.

ISA Interface

4-7

notPROGRAM, notINIT and DONE in the Status register are thesignals present at the FPGA pins, and the same named signals inthe Control register are active low open-drain signals set by thehost PC. When the Control register bits are set low and theconfigure bit in the Reset register is set high, the Control registeroutputs are driven low. Otherwise they are tri-state and the FPGAor serial PROM or XChecker cable can drive these signals with theirequivalent open-drain outputs. Reading the Control register givesthe value of the internal bits in the Control register, NOT the FPGApins.


4-8

4.5 Reset Register

ByteAddress

Write/Read

Data Bit

Offset 15 3 2 1 00x004 W/R X 0 0 Configure Reset

Default stateafter reset

X 0 0 LOW HIGH

Reset HIGH resets the registers and flags to thestates described in section 8; and drivesFPGA input pin 71, which can be used by theFPGA program in a user-definable way. SetHIGH on power-up and host PC reset so mustbe set LOW before any accesses to this boardcan be made.

Configure Must be set HIGH to enable FPGAconfiguration from the host PC, otherwisemust be set LOW.

ISA Interface

4-9

4.6 Programmable Clock

ByteAddress

Write/Read

Data Bit

Offset 15 3 2 1 00x006 W Serial

DataX X X X

The programmable clock serial bit stream is written in data bit 15 tothis register. The least significant bit is written first.

The serial bit stream is generated by the Cypress BitCalc program.This program and the data sheet of the Cypress ICD2053Bprogrammable clock are available on the Cypress web site atwww.cypress.com. The support software supplied with this boardincludes functions for programming the clock, see ref. 1 and ref. 2.

Also see section 6.3 for more information on all the possible FPGAclock sources.


4-10

4.7 Flags Register

ByteAddress

Write/Read

Data Bit

Offset 15 3 2 1 00x006 R X 0 0 FPGA

DataReady

not HostData Ready

Default stateafter reset

X 0 0 LOW HIGH

Note the opposite polarity of these flags. This is a result of thesharing of not Host Data Ready with the notINIT signal which isactive low, and the sharing of FPGA Data Ready with the ISA businterrupt signal which is active high.

not Host Data Ready LOW indicates the host PC has writtendata to the FPGA and the FPGA has notyet read the data.

FPGA Data Ready HIGH indicates the FPGA has writtendata to the host PC and the host PC hasnot yet read the data.

ISA Interface

4-11

4.8 Data Register

ByteAddress

Write/Read

Data Bit

Offset 15 3 2 1 00x010 –0x01F

W/R Data Bits 15-0 available for application

16-bit wide data interface to the FPGA covering 16 I/O space bytelocations from byte offset 0x010 to 0x01F.

If host PC byte transfer functions are used, then even bytes aretransferred in the lower byte bits 0-7, and odd bytes are transferredin the upper byte bits 8-15.


4-12

4.9 Address Register

ByteAddress

Write/Read

Address Bit

Offset 3 2 1 00x010 –0x01F

W Address Bits 3-1 available forapplication

X

Address bits 1-3 are transferred from the host PC to the FPGA inthe same way as the 16 bits of data. Note that they cannot be readback from the FPGA.

These can be used as 3 extra data bits for writes to the FPGA, soenabling 19-bit writes and 16-bit reads.

ISA Interface

4-13

4.10 Interrupts

There is one interrupt line which can be connected to one of fourISA interrupts selected by JP3 as in table 11. This interrupt line isdriven by the FPGA Data Ready flag which indicates that the FPGAhas data waiting for the host PC to read. If an interrupt is notrequired JP3 should not be inserted.

JP3A IRQ15JP3B IRQ11JP3C IRQ10JP3D IRQ9

Table 11. Interrupt Selection


4-14

5. Data Transfers


5-2

5.1 Introduction

The data path is 16 bits wide. Whenever this board is accessed bythe host PC, it asserts ISA bus signal notIO16 indicating that it is a16-bit device. Odd bytes are therefore placed on the upper 8 databits D8-15.

Since the ISA bus and the FPGA may be clocked by differentclocks, they have to be decoupled from each other to avoidmetastability problems. This is accomplished by clocking the datainto a registered transceiver for transfers in both directions.

The address bits 1-3 are also clocked into a register in host PC toFPGA transfers, but NOT in FPGA to host PC transfers. Since theData register covers 16 byte (8 word) address locations, the valueof address bits 1-3 does not affect the selection of the Data register.Therefore these 3 bits can be used to transfer address informatione.g. for selecting registers within the FPGA. Alternatively they canbe used as 3 extra data bits.

Data Transfers

5-3

5.2 Flags

When the host PC sends data to the FPGA or the FPGA sends datato the host PC, the data is clocked into a registered transceiver. Inthe case of transfers from the host PC to the FPGA address bits 1-3are also clocked into a register. The receiver of the data must thenbe signaled that data is present. After the receiver has read thedata, the transmitter must be signaled that it can send more data.

This communication is achieved with two flags. Note the oppositepolarity of these flags. This is a result of the sharing of not HostData Ready with the notINIT signal which is active low, and thesharing of FPGA Data Ready with the ISA bus interrupt signalwhich is active high. Sections 5.4 and 5.5 describe the transfers inmore detail.

• ‘not Host Data Ready’ signals that data has been written by thehost PC and is ready for reading by the FPGA. Figure 2 showsthe waveforms. The flag is active low and is set LOWautomatically on a write by the host PC. It is connected to pin 41of the FPGA so that the FPGA can monitor its level. When theflag is set LOW, the FPGA can read the data and thisautomatically resets the flag HIGH. The host PC can monitor theflag via the Flags register and write another word of data when itis HIGH.

not Host Write

not Host Data Ready

not FPGA Read

Figure 2. Host PC to FPGA Data Transfers

• ‘FPGA Data Ready’ signals that data has been written by theFPGA and is ready for reading by the host PC. Figure 3 showsthe waveforms. The flag is active high and is set HIGHautomatically on a write by the FPGA. The host PC can monitorthe flag via the Flags register or an interrupt selected by JP3(see section 4.10), and read a word of data when it is HIGH.Reading the data automatically resets the flag LOW, signalingthat the FPGA can write another word of data. It is connected topin 39 of the FPGA so that the FPGA can monitor its level.


5-4

not FPGA Write

FPGA Data Ready

not Host Read

Figure 3. FPGA to Host PC Data Transfers

Data Transfers

5-5

5.3 Data Transfers without Polling

The use of the flags as described in the previous section requiresthe host PC to poll the Flags register and/or use an interrupt. Bothmethods take more time than and so achieve lower bandwidth thanthe method described here.

Both flags drive the ISA bus signal named CHRDY, which is shortfor Channel Ready. If this is asserted low by a board that is beingaccessed, the host PC inserts wait states in the cycle until CHRDYis de-asserted.

So after the host PC has written a word to the FPGA it canimmediately start another write cycle. If the FPGA has not yet readthe data CHRDY will be asserted so holding off the host PC. Assoon as the FPGA has read the data CHRDY is de-asserted andthe host PC write cycle continues so writing in the new word ofdata. Figure 4 shows the waveforms.

not Host Write

CHRDY

not Host Data Ready

not FPGA Read

Figure 4. Host PC to FPGA Data Transfers with CHRDY

Similarly after the host PC has read a word from the FPGA it canimmediately start another read cycle. If the FPGA has not yetwritten the next data CHRDY will be asserted so holding off the hostPC. As soon as the FPGA has written the data CHRDY is de-asserted and the host PC read cycle continues so reading out thenew word of data. Figure 5 shows the waveforms.

not FPGA Write

FPGA Data Ready

CHRDY

not Host Read

Figure 5. FPGA to Host PC Data Transfers with CHRDY


5-6

DEADLOCK WARNING. If the host PC reads and writesare not matched by FPGA writes and reads respectivelythen deadlock will occur. CHRDY will be assertedpermanently, the host PC will hang and it will have to berebooted. It is therefore advisable to do developmentwork with the polling functions supplied with the RC1000-II support software, and only use the non-pollingfunctions once the application has been developed.

Data Transfers

5-7

5.4 Host PC to FPGA Data Transfers

The sequence of operations for transferring data from the host PCto the FPGA is as follows. The waveforms and timings in nS areshown in figure 6.

not Host Write

not Host Data Ready

not FPGA Read

FPGA Data bus

t >= 26.3 + delay from FPGA data pins to register in FPGA + setuptime of data register in FPGA.

Figure 6. Host PC to FPGA Data Transfers

1. OPTIONAL. The host PC polls the flag ‘not Host Data Ready’ inbit 0 of the Flags register until it is HIGH signifying that anyprevious data written by the host PC has been read by theFPGA. This is optional because if this flag is LOW, CHRDY (ISAbus signal Channel Ready) will be pulled LOW when the hostPC attempts a write, thus inserting wait states until the flag is setHIGH by the FPGA completing the read.

2. The host PC writes the new data into the registered transceiverand automatically clocks CHRDY LOW. CHRDY being LOWprevents the host PC making further write accesses to theboard, but it can make read accesses. Address bits 1-3 are alsoclocked into a register.

3. The FPGA monitors the flag not Host Data Ready on its pin 41and, when it is pulled LOW, reads 16 bits of data from theregistered transceiver using its not FPGA Read signal on pin 37.(It can also read address bits 1-3).

4. Data is valid for clocking into the FPGA a maximum of 26.3nSafter not FPGA Read goes LOW (10.0nS for FPGA IOB outputpad in CMOS fast mode plus 8.5nS for delay through CPLD plus7.8nS for transceiver output enable). This assumes the data is

< 26.3 < 24.8

t


5-8

clocked into an IOB flip-flop with the default delay option set forthe data input to the IOB which guarantees zero hold time forthe data. Any delays inside the FPGA must also be allowed fore.g. if the data is clocked into a CLB rather than an IOB.

5. Data is valid after not FPGA Read goes HIGH for a minimum of0.0nS (minimum delays are not specified in the data books) andfor a maximum of 24.8nS (10.0nS for FPGA IOB output pad inCMOS fast mode plus 8.5nS for delay through CPLD plus 6.3nSfor transceiver output disable). During this time the FPGA mustnot start a write cycle to the host because this would cause abus clash between the transceiver and FPGA data buses.

6. The rising edge of signal not FPGA Read sets the flag not HostData Ready HIGH so enabling further write accesses by thehost PC. While not Host Data Ready is LOW, if the host PCwrites to this board CHRDY is pulled LOW and wait states areinserted in the ISA cycle until this board de-asserts CHRDY.

The flag not Host Data Ready is preset HIGH on power-up, hostreset, and reset in the Reset register, so enabling data transfer.


Data Transfers

5-9

5.5 FPGA to Host PC Data Transfers

The sequence of operations for transferring data from the FPGA tothe host PC is as follows. The waveforms and timings in nS areshown in figure 7.

not FPGA Write

FPGA Data Ready

not Host Read

FPGA Data bus

Figure 7. FPGA to Host PC Data Transfers

1. The FPGA polls the flag ‘FPGA Data Ready’ on its pin 39 tocheck that it is LOW signifying that any previous data written bythe FPGA has been read by the host PC.

2. The FPGA clocks data into the registered transceiver using notFPGA Write on its pin 36, automatically setting the flag FPGAData Ready HIGH. There is no address information to send tothe ISA bus. not FPGA Write must be LOW for at least 5.0nS tosatisfy the registered transceiver clock timing.

The FPGA data outputs must be enabled during writecycles and at no other time. Otherwise there could be aclash with the registered transceiver data outputs.

To ensure that data is valid on the rising edge of not FPGA Write atthe transceiver register, FPGA data outputs must be enabled withvalid data for at least 10.0nS after the rising edge of not FPGAWrite (8.5nS for delay through CPLD plus 1.5nS for transceiverregister data hold).

3. OPTIONAL. The host PC polls the flag FPGA Data Ready in bit1 of the Flags register to check that it is HIGH. This is optionalbecause if this flag is LOW CHRDY (ISA bus signal ChannelReady) will be pulled LOW when the host PC attempts a read,thus inserting wait states until the flag is set HIGH by the FPGA

>5.0

> 0.0 > 10.0


5-10

performing a write. Setting of FPGA Data Ready also causes aninterrupt to the host PC according to the position of JP3.

4. The host PC reads the data from the registered transceiver. Therising edge of signal not Host Read clears the flag FPGA DataReady which is sensed by the FPGA on pin 39. The FPGA canthen write another data word.

The flag FPGA Data Ready is reset LOW on power-up, host reset,and reset in the Reset register, so enabling data transfer.


Data Transfers

5-11

5.6 Data Transfers without Clocking of Data

The registered transceiver can be set to transparent mode in whichdata is not registered but simply passes straight through. In thiscase decoupling of the ISA and FPGA clock domains should bedone in the FPGA. Registered or transparent mode is selected byJP1 as in Table 12.

JP1A not fitted registeredFPGA to ISA fitted transparentJP1B not fitted registeredISA to FPGA fitted transparent

Table 12. Selection of Registered or Transparent DataTransfers

The address register can also be set to transparent mode in whichthe address bits 1-3 are not registered but simply passes straightthrough. Registered or transparent mode is selected by JP6 as inTable 13.

JP6 not fitted registeredISA to FPGA fitted transparent

Table 13. Selection of Registered or Transparent AddressTransfers


5-12

6. FPGA


6-2

6.1 Introduction

The FPGA is a Xilinx XC4010E-4PC84C. The physical package isthe 84-pin PLCC and the 4010E is the largest Xilinx FPGA availablein this package. For full information including timing characteristicsplease see ref. 3.

The FPGA pin connections are shown in Appendix A.

It can be programmed from any one of three possible sourcessummarized below.

1. A Xilinx .bit file can be downloaded from the Host PC at anytime.

2. On power-up, host reset, and whenever not PROGRAM ispulsed by the host PC, the FPGA can be configured with aprogram stored in the serial PROM.

3. The Xilinx XChecker cable can be connected to any computerrunning the XChecker software and configurations can bedownloaded.

Two pins of the FPGA are connected to clocks. These aresummarized below.

1. Primary Global Clock 2 (pin 35) is connected to: either theprogrammable clock which is programmed by the host PC to bein the range 400KHz to 100MHz; or the ISA bus clock which isapprox. 8MHz depending on the PC.

2. Primary Global Clock 4 (pin 78) is connected to the IndustryPack clock which is either 8MHz or 32 MHz.

FPGA

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6.2 Configuration

The FPGA configuration program must have the following optionsselected by the Xilinx XACTstep Makebits or Xilinx M1 Bitgenutilities.

• CMOS outputs, this is for the Industry Pack interface which isCMOS compatible.

• TTL inputs for compatibility with the TTL and CMOS devicesconnected to the FPGA.

• I/O pull-ups so that Industry Pack signals cannot float and causeoscillation, or all signals must be driven by the FPGA when notbeing driven by the Industry Pack e.g. the data lines.

• the startup sequence should be DONE goes HIGH, then GSR isinactive, then I/O are active.

Handel-C programs can be configured to initialize allvariables to zero. So when the not FPGA Write strobe isfirst set HIGH in the program a write to the host will beperformed. The host program must perform a read toclear the FPGA Data Ready flag. Similarly when not FPGARead is first set HIGH any data which has been written bythe host to the FPGA will be read and the not Host DataReady flag cleared. Hence care must be taken ininitializing communications between the host and theFPGA.

The FPGA can be configured from one of three sources:• host PC,• on-board serial PROM• XChecker cable

The selection is made by JP11 (FPGA Configuration Mode) andJP13 (serial PROM Chip Enable) as shown in Table 14. JP11A ispins 1 and 2, JP11B is pins 3 and 4, and JP11C is pins 5 and 6.The mode numbers refer to the FPGA mode pins 0-2.

ConfigurationSource

JP11C,mode 2

JP11B,mode 1

JP11A,mode 0

JP13

Host PC orXChecker

not fitted not fitted not fitted not fitted

Serial PROM fitted fitted fitted fitted



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If the configuration source is selected to be the serialPROM but configuration from the host PC or XChecker isattempted, the configuration signals will clash which maydamage the chips on the board.

6.2.1 Configuration from Host PC

1. Make sure that JP11 and JP13 are set correctly as in table 14.2. In the Reset register set the Reset bit HIGH for at least 100nS

and then LOW, this is necessary before any accesses to theboard can be made.

3. In the Control register set not PROGRAM LOW, and DONE andnotINIT HIGH.

4. In the Reset register set Configure HIGH. This enables theoutputs DONE, notINIT and notPROGRAM from the Controlregister. DONE and notINIT are quasi open-drain signals sothey are driven LOW to the FPGA when the relevant Controlregister bit is LOW, otherwise they are tri-state so that the FPGAcan drive them.

5. After at least 300nS set notPROGRAM HIGH.6. Poll the Status register until the FPGA drives notINIT HIGH.7. Configuration can then begin by writing the bit stream to the

Configuration register data bit 0. The FPGA holds DONE LOWuntil configuration is complete, and if there is an error duringconfiguration, the FPGA will pull notINIT LOW.

8. At the end of the configuration bit stream, at least 3 extra writesto the Configuration register (with dummy data) must be made toclock the FPGA through the start-up phase.

9. Poll the Status register until the FPGA either sets notINIT LOW,indicating a configuration error, or sets DONE HIGH, indicatingsuccessful configuration.

10. In the Reset register set Configure LOW.

6.2.2 Configuration from XChecker

1. Make sure that JP11 and JP13 are set correctly as in table 14.2. The Xilinx XChecker cable can be connected from any computer

running the Xilinx XChecker software to JP10.

When connecting the XChecker cable to JP10 make surethat you discharge any static from yourself e.g. bytouching some earthed bare metal.

Connect the XChecker cable to JP10 as in Table 15.

FPGA

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XChecker Signal JP10 pin numberVCC 1CCLK 2D/P 3DIN 4PROG 5INIT 6GND 7

Table 15. XChecker Cable Connections to JP10

3. Follow the instructions from Xilinx for using the XCheckersoftware.

6.2.3 Configuration from Serial PROM

If the serial PROM is selected, the FPGA will configure from theserial PROM automatically after power-up, host reset, or after notPROGRAM is pulsed LOW.

1. Make sure that JP11 and JP13 are set correctly as in table 14.2. In the Reset register set the Reset bit HIGH and then LOW, this

is necessary before any accesses to the board can be made3. In the Control register set not PROGRAM LOW.4. Poll the Status register until not INIT is driven LOW by the

FPGA.5. In the Control register set not PROGRAM HIGH, and

configuration will start 30 to 300uS later.6. Poll the Status register until DONE is driven HIGH by the FPGA

indicating that configuration is complete.


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6.3 Clocks

There are two clocks connected to the FPGA, the FPGA internallogic can use either or both clocks. FPGA pin 35 is its PrimaryGlobal Clock 2 and this is selected by JP9 to be either theprogrammable clock or the ISA Bus Clock. FPGA pin 78 is itsPrimary Global Clock 4 and this is connected to the Industry Packclock.

6.3.1 Primary Global Clock 2

JP9 selects PGCK2 on pin 35 as in Table 16.

JP9A programmableclock

JP9B ISA Bus Clock

Table 16. FPGA PGCK2 Selection

The programmable clock is the Cypress ICD2053B which has anoutput range from 391KHz to 100MHz. The frequency can bechanged glitch-free on the fly. To program it, the host PC writes aserial bit stream (starting with the LSB) on data bit 15 of theProgrammable Clock register. Data bit 15 is used rather than bit 0to minimize electrical loading on bit 0 which is used for otherpurposes.

The bit stream is calculated by the Cypress BitCalc program whichis available for downloading from the Cypress web sitewww.cypress.com. For programming details please see theICD2053B data sheet, ref. 4. Note that pin 7 (OE or /MUXREF) isleft floating so the chip’s internal pull-up enables CLKOUT. Thereference frequency driving the chip is 20MHz. The output shouldbe configured to be TTL which is compatible with the Xilinx inputsbeing configured for TTL. This also gives a higher upper frequencylimit of 100MHz c.f. 90MHz with CMOS output.

The RC1000-II support software (ref. 1 and ref. 2) includesfunctions for programming the clock.

The ISA Bus Clock is approximately 8MHz, the exact frequencydepending on the machine.

FPGA

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6.3.2 Primary Global Clock 4

PGCK4 on pin 78 of the FPGA is the Industry Pack clock. This iseither 8MHz or 32MHz selected by JP8 as in Table 17.

JP8A 8MHzJP8B 32MHz

Table 17. FPGA PGCK4/Industry Pack Clock Selection


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7. Industry Pack Interface


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7.1 Introduction

The FPGA interfaces directly to the IP module, there is no buffering.Appendix A lists the pins of the FPGA, including those which areconnected to the Industry Pack module.

The IP specification (ref. 5) requires CMOS drive levels so theFPGA must be configured in the Xilinx XACTstep Makebits or XilinxM1 Bitgen utilities for CMOS outputs.

Example macros for interfacing to the IP module are included in theRC1000-II support software (see ref. 1 and ref. 2). These macrosare written in Handel-C.

Industry Pack Interface

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7.2 Implementation of Industry Pack Specification Features

The implementation has been limited slightly by the number of I/Opins available on the Xilinx 4000 series PC84 package. Someoptional features have been omitted, and are listed below.

1. DMA is not implemented.2. Interrupt 0 only is implemented (not Interrupt 1).3. Full conformance to the 32MHz IP specification is not achieved.

The specification requires sink and source currents of 15mA and5mA respectively, while this board has sink and source currentsof 12mA and 4mA respectively.


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7.3 Byte Ordering

IP documentation uses big endian byte ordering to be compatiblewith Motorola CPUs and VME systems. However the ISA bus islittle endian and this carrier board uses the little endian convention.This means that both 16-bit and 8-bit modules are on even byteaddresses, byte select 0 refers to even bytes D0-7, and byte select1 refers to odd bytes D8-15. IP D0-15 map directly to ISA D0-15.

Industry Pack Interface

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7.4 Custom FPGA IP Modules

The FPGA configuration signals can be connected to the IPconnector via JP7 so that a custom IP with an FPGA on it can beconfigured. The default for standard IP modules is that the JP7jumpers are not inserted, they should only be inserted for a customIP module with FPGA needing configuration. The IP signals usedfor configuration are shown in Table 18. Note that DIN/Data15 arepermanently connected anyway, they are not jumpered by JP7. Thefirst JP7 pin number in each pair refers to the configuration signal.

Configuration Signal Industry Pack Signal JP7 pinsCCLK notDMAReq0 2-1DONE notDMAReq1 4-3notPROGRAM notDMAck 6-5notINIT notDMAEnd 8-7DIN Data15 X

Table 18. IP Signals used for Configuration on Custom IndustryPacks


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8. Reset


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The whole board apart from the IP module is reset by the host resetsignal on power-up and whenever the host PC is rebooted, and bythe Reset bit in the Reset register. The states of the registers after areset are as follows.

Control register• notPROGRAM HIGH• notINIT HIGH• DONE HIGH

Reset register• Reset HIGH• Configure LOW

Flags register• not Host Data Ready HIGH• FPGA Data Ready LOW

The Reset bit in the Reset register is preset HIGH on power-up andhost reset. It must be set LOW before any accesses to the boardcan be made.

The reset input to the FPGA is on pin 71 which is also DIN. Thissignal can be used by the FPGA application in whatever way isrequired. It does not reset directly the FPGA logic because theXilinx 4000 series does not have a dedicated reset pin.

The IP module active-low reset is controlled by FPGA pin 38.Industry Pack Reset must be driven for at least 200mS, assertedasynchronously, but de-asserted synchronously with the IP clock.

Reset

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9. Miscellaneous Jumpers


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JP12 is the JTAG connector for programming the Xilinx 9536 CPLDwhich implements all the control logic of the board. The jumper isreserved for the use of Embedded Solutions Ltd only.

JP4 and 5 are also reserved for the use of Embedded Solutions Ltdonly. By default they should not be inserted. If they are inserted thewhole ISA bus is connected to the FPGA using the Industry Packsignals. Hence an Industry Pack module must NOT be inserted ifJP4 and 5 are inserted otherwise the IP and ISA signals will clash.

Miscellaneous Jumpers

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10. Power Consumption


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Using the component data sheets, the approximate maximumpower consumption excluding the dynamic power consumption ofthe FPGA has been calculated to be:

1400 mW with worst-case component figures,500 to 700 mW with typical component figures which are 1/3 to

1/2 worst-case figures.

These figures include 50mW for quiescent power consumption ofthe FPGA. Dynamic power consumption of the FPGA variesenormously according to the application’s clock rate and amount oflogic used. This is explained in references 6 and 7.

Power Consumption

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11. Appendix A - FPGA Pin Connections


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The allocation of signals to pins is based on data flow between theISA interface on the left-hand side of the chip and the Industry PackInterface on the right-hand side of the chip. Also to take mostadvantage of the fast-carry support within the Xilinx 4000 series theordering of bits within data and address buses is from bottom to topand from left to right. The clocks are connected to Primary GlobalClock pins.

Table 19 lists the FPGA connections, Industry Pack signals areprefixed by IP_, signals with names prefixed by ‘not’ are active low,and all others are active-high.

FPGA PinNumber

Signal

3 IP_notIDSel4 IP_notError5 ISA Address 16 ISA Address 27 ISA Address 38 notSBHE9 ISA Data 15

10 Unused*13 ISA Data 1414 ISA Data 1315 ISA Data 1216 ISA Data 1117 ISA Data 1018 ISA Data 919 ISA Data 820 ISA Data 723 ISA Data 624 ISA Data 525 ISA Data 426 ISA Data 327 ISA Data 228 ISA Data 129 ISA Data 035 Programmable Clock input to FPGA36 not FPGA Write, Xilinx write strobe to ISA37 not FPGA Read, Xilinx read strobe from ISA38 IP_notReset, low lights LED D1, connected

to test point TP1

FPGA Pin Connections

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39 FPGA Data Ready, flag set automaticallywhen FPGA writes to host, clearedautomatically when host reads the data, canbe connected to ISA interrupt by JP3.

40 IP_notIntReq041 notINIT_notHDR, notINIT during

configuration, not Host Data Ready afterconfiguration which is a flag setautomatically when host writes to FPGA,cleared automatically when FPGA reads thedata.

44 IP Address 145 IP Address 246 IP Address 347 IP Address 448 IP Address 549 IP Address 650 IP Data 051 IP Data 153 DONE55 notPROGRAM56 IP Data 257 IP Data 358 IP Data 459 IP Data 560 IP Data 661 IP Data 762 IP Data 865 IP Data 966 IP Data 1067 IP Data 1168 IP Data 1269 IP Data 1370 IP Data 1471 DIN_RESET, DIN during configuration,

RESET input from host after configuration72 IP Data 15, DOUT during configuration73 CCLK75 IP_notStrobe77 IP_notBS078 IP_CLOCK1, 8MHz or 32 MHz input

selected by JP879 IP_notBS180 IP_Read_notWrite81 IP_notAck


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82 IP_notIOSel83 IP_notMemSel84 IP_notIntSel

Table 19. FPGA Signal Connections

* FPGA pin 10 is connected to CPLD pin 25 for future possible usesuch as decoded ISA address or a secondary global clock. CPLDpin 25 is currently one of the two base address select pinsconnected to JP2, so two of the four base addresses would not beusable, and J2B should not be fitted.

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