RCU Status

1. RCU design

2. RCU prototypes

3. Firmware/software• FEE-board test

• TPC sector test

• Towards final version

HiB, UiB, UiO

1. RCU design – control flow

• State machines

RCUresource

& priority manager

TTCrxFEE bus controller

SIUcontroller DDL

commanddecoder

FEESC

DCS low level

Watchdog 1:health agentDebugger

PCI core

Huffman encoder

DCS high level

Watchdog 2

RCU design - data flow

TTCrx registers

Event memory 1

Event fragment pointer list

TTC controller

FEE bus controller

FEE bus controller

Configuration memoryFEE bus controller

DCS

SIU controller fifoSIU

Huffman encoder

• Shared memory modules

Event memory 2

2. RCU prototypes• Prototype I

– Commercial OEM-PCI board– FEE-board test (ALTRO + FEE bus)– SIU integration– Qtr 3, 2001 – Qtr 2(3), 2002

• Prototype II– Custom design– All functional blocks– PCB: Qtr 2, 2002– Implementation of basic functionality (FEE-board-> SIU): Qtr 3, 2002– Implementation of essential functionality: Qtr 2, 2003

• (Prototype III) – SRAM FPGA -> masked version or Antifuse FPGA (if needed)

• RCU production– Qtr 2, 2003

RCU prototype II

• Implementation of essential functionality– Custom design

– All functional blocks

PCI core

SIU-CMCinterface

SIU

PCI busFPGA

internalSRAM

Memory D32

> 8 MB

FLASH EEPROM

DCS TTCrx

FEE-bus

FEE-bus

DCS FEE SC

RCU prototype II - layout• Motherboard

– FPGA

– memory data buffer

– memory work space

– ethernet

– PCI interface

– CMC connectors

• Mezzanine card I– SIU

• Mezzanine card II– FEE bus A and B

– TTCrx

– Profibus interface

RCU prototype II - motherboard

JN

1

JN

2J

N4

JN

3

JN

2A

JN

5

APEX

Flash

Flash

Flash

SRAM SRAM

SRAM SRAM

SDRAM

Po

wer

(1.8

V G

en.)

SRAM SRAM

SRAM SRAM

Co

nn

ecto

rs

RCU prototype II – mezzanine cards

RCU Mezzanine CardComponents on top side

No maximum height restriction

Front-End Bus Conn 1

Front-End Bus Conn 2

SIU mezzanine card (1/2 CMC)

• Floor plan of PCI board• Status motherboard (in collab. with HD)

• design and layout done

• PCB production in May • mounting of components in May/June

• testing debugging

RCU prototype II - status

314 mm

107 mm

• Status mezzanine boards• SIU (needs adapter)• FEE-bus, TTCrx, Profibus

• design done• layout and PCB production in May

RCU prototype II - status

RCU prototype II - status • TTCrx

RCU prototype II - status • Profibus

RCU prototype II - status

• FEE-bus

• two branches

• external multiplexing

• internal (inside FPGA) multiplexing (modified mezzanine board)

3. Firmware/software – status and plans

• Test environment for FEE-boards

• TPC sector test

• Towards the final version

FEE test environment• ”Special RCU”: not TTCrx, no DCS, no SIU

PCLINUX RH7.2

PCI coremailboxmemory

tester FEE buscontroller

FEE bus

FEE-board(ALTRO)

RCU/ALTRO test tool

RCU-APIdevice driver

PCI FPGA board

Signal generator

GUI?

• Application program:

• C/C++

• GUI?

RCU system for TPC test 2002/2003• Readout of 4 FEE-bus branches

– 2 RCU prototypes II– fallback solution: 4 (2) RCU prototypes I (3 boards are available)

• Basic RCU functionality – configure FEE (done)– readout event (being debugged)– develop logics for readout of all FEE cards on FEE-bus

(design in progress)– include external SRAM (designed, simulated, being tested)– develop RPM for controlling data transfer from FEE-bus to SIU

(design started)

– Include simple trigger and event-ID

• Interface to DATE– DAQ via DDL

• 2 pRORC (including SIU + DIU)• Integration of pRORC: DATE 4 (June 2002)

– fallback solution: DAQ via RCU-PCI

RCU system for TPC test

2002/2003FEE-bus controller

SIU controller

PCI core

SIUinterface

PCI bus

FPGA

SRAM

LINUX RH7.2FEE configuratorPLDA/PCI-tools

RCU-APIdevice driver SIU

PCI bridge Glue logicDIU

interface

PCI bus

LINUX RH7.2DATE 4

DDL/PCI-toolspRORC-APIdevice driver

DIU

DDL

RCU prototype II/I

pRORC

ext. SRAM FLASH

Manager

FEE-bus

Trigger

FEE-boards

Towards the final version

• Radiation induced corruption of SRAM– SEE in configuration SRAM of FPGA will happen– monitor system state and detect such effects

-> reset FPGA

– two watchdogs• FPGA self-detection• detection by Profibus slave ASIC

• DCS– two level interface

• Profibus slave controller (ASIC) • ethernet chip

• Trigger– one TTCrx per RCU