Authored by Andrew Olney, Brad Gifford, John Guravage, Alan Righter - Analog Devices Presented by Jay Hamlin – Medtronic (with Andrew’s authorization) Real-World Charged Board Model (CBM) ESD Failures Purpose of this Presentation Document damage on real-world ESD failures Describe a CBM test method for replicating damage on real-world failures Explore relationship between PCB design and IC CBM robustness Discuss corrective actions for CBM failures Provide guidelines for minimizing real-world CBM damage
Transcript
Authored by Andrew Olney, Brad Gifford,
John Guravage, Alan Righter - Analog Devices
Presented by Jay Hamlin – Medtronic
(with Andrew’s authorization)
Real-World Charged Board
Model (CBM) ESD Failures
Purpose of this Presentation
Document damage on real-world ESD failures
Describe a CBM test method for replicating damage on real-world failures
Explore relationship between PCB design and IC CBM robustness
Discuss corrective actions for CBM failures
Provide guidelines for minimizing real-world CBM damage
Outline Causes of Real-World ESD Failures
Background on Charged Board Model
2 Case StudiesReal-world failure signaturesCBM test methodCBM simulation resultsEffects of varying PCB parametersFixes for case study failuresDiscussion of results
Conclusions
Prevalence of EOS / ESD FailuresReview of ADI’s ’99-’08 Failure Analysis Database:
Excluding No Trouble Found, #1 Cause of Customer Returns is EOS / ESD damage
<1% of ESD failures due to HBM!
>99% of ESD failures due to CDM & CBM
~50% of “EOS” failures may be CBM damage!
HBM Becoming Legacy ESD ModelEffective controls by IC manufacturers & users
Highly automated PCB mf’g lines
Latest packages have mm-range dimensions
- mBGAs, SOTs, SC70s, LFCSPs, Bumped Die, etc.
- Effectively too small to touch just one pin / solder ball
55-Ball3.6 x 2.6mm Bumped Die
Background Causes of most real-world IC ESD failures
Charged Device Model
Charged Strip Model [Olney 2002] – now rare
Charged Board Model [Olney 2003]
HBM & CDM robustness ≠ CBM robustness
CBM damage more severe than CDM damage
May be mistaken for EOS damage
Field-Induced Charged Device Model
Replace IC (Device Under Test) with Printed Wiring Assembly
Real-World CDM Damage Same subtle damage simulated by 700V FICDM testing
•Fix: Redesign IC so capacitors are not tied directly to
package corner pins; increase customer use of ionizers
Charged Board Model (CBM)Similar to the CDM, but discharge occurs on PCB
Assumes the PCB is charged either:
(1) Directly via the triboelectric effect (frictional charging between the PCB & another object) or
(2) Indirectly due to an external electric field
Metal on the PCB (pins, edge connectors, etc.) subsequently contacts a conductive surface at or near ground potential
Result: Charge stored by the relatively large PCB capacitance is dissipated in an ultra-fast, high-energy spark discharge
Case Study 1 – Dual Op Amp IC 6.7% customer PCB failure rate
Five Dual Op Amp ICs per boardSubmicron CMOS; 2-level metal 8-lead SOIC package
All ICs operated within Absolute Max. Ratings
Failures always occurred at IC Position #5
Failure Mode: <100 short Pin 2 (-IN A) to Pin 4 (V- / substrate)Could not simulate this via HBM or CDM
Case Study 1 – Dual Op Amp IC
Customer board failure
- Damage at anode of input protection diode
CBM Test Results – Case Study 1Evaluation Board Pad 2 CBM stressed at -500 V
- Damage at anode of input protection diode
CBM Test Results – Case Study 1
Evaluation Board Pad 2 CBM stressed at -625 V
- Catastrophic damage at same protection diode
Effect of Smaller PCB Power Planes Full-size Evaluation Board for Dual Op Amp
- 3” x 3” ground plane
- CBM ESD withstand voltage = ±250 V
Half-size Evaluation Board for Dual Op Amp
- 1.5” x 3” ground plane
- CBM ESD withstand voltage = ±375 V
IC CBM ESD withstand voltage
- Inversely related to power plane area
- Inversely related to charge on power plane
Fix for Case Study 1 – Dual Op Amp Plastic CPU socket next to IC Position #5
- Charged up to 1400 V
- Induced charge on adjacent Dual Op Amp
- Subsequent IR reflow caused CBM damage
Customer PCB production line fix
- Added ionizer just before IR reflow
Result
- No more Dual Op Amp IC failures
Results Discussion – Case Study 1
FICBM vs. FICDM discharge waveforms
375 V charge voltage
Case Study 2 – DSP IC
~200 PPM customer PCB failure rate
One DSP IC per board Deep-submicron CMOS; 4-level metal 208-lead Plastic Quad Flat Pack 35 GND pins & 33 Vdd pins
DSP operated within Absolute Max. Ratings
DSP located at corner of PCB
Failure Mode: typically functional failures
Could not simulate this via HBM or CDM
Case Study 2 – DSP IC
Customer board failure
- Cracked glassivation (optical view)
Case Study 2 – DSP IC
MET4 AlCu melt / reflow “fingers” (FIB view)
Similar damage to [Banerjee et al. 2000]
CBM Test Method - Case Study 2
Cut-down customer PCB with DSP IC
Test pad discharged in ±125 V increments
CBM Test Results – Case Study 2
Cut-down customer PCB CBM stressed at -250 V
- MET4 AlCu melt / reflow “finger” (FIB view)
CBM Test Results – Case Study 2Cut-down customer PCB CBM stressed at 1 kV
- Catastrophic damage at supply buses & pads
- Most FA Engr’s would incorrectly conclude EOS
Fix for Case Study 2 – DSP IC
Large plastic edge connector on PCB
- Some connectors charged to >1000 V
- Induced charge up to ±300 V on DSP IC
- Subsequent wave solder caused CBM damage
Customer PCB production line fix
- Added ionizer just before wave solder
Result
- No more DSP IC failures
Results Discussion – Case Study 2
FICBM vs. FICDM discharge waveforms
- 250 V charge voltage
g g
-2
0
2
4
6
8
10
0.00
0.25
0.50
0.75
1.00
1.25
1.50
Time (nanoseconds)
Pe
ak
Cu
rre
nt
(Am
ps
) GND test pad FICBM
GND pin FICDM
PCB-Level EOS/ESD Protection
CBM testing was repeated on a customer PCB with a TVS + Schottky Diode across the 3.3V supply planes
No CBM damage occurred to the DSP when zapped up to 2000VNo CBM damage occurred to the DSP when zapped up to 2000V
[Without[Without T VS + Schottky, damage occurred at 250V.]
Conclusions - 1
Charged Board Model testing conducted
Test method similar to FICDM
However, higher energy & faster discharges
Successfully replicates real-world failures
CBM ESD damage
More severe than CDM damage
Occurs at lower voltages than CDM damage
Can be easily mistaken for EOS damage
Conclusions - 2
CBM ESD withstand voltages Inversely proportional to PCB capacitance
Larger power planes higher capacitance Inversely proportional to # of IC supply pins
More connections lower R & L
Minimizing real-world CBM discharges Use ionizers at key PCB assembly steps
e.g., just prior to wave solder / reflow
Device-level robustness ≠ board-level robustness DSP: Pass 2000 V CDM; fail 250 V CBM
Conclusions - 3• ADI data on real-world EOS/ESD failures:
