Recent Trends of Package Warpage
Project leader: Wei Keat Loh – IntelCo-leaders: Ron Kulterman - Flextronics
Tim Purdie - Akrometrix
Presenter: Masahiro Tsuriya
IMPACT 2015 ConferenceOctober 22, 2015Taipei, Taiwan
Content
• Package Technology
• Warpage Attribute
• Warpage Specification
• Phase 2
– Objective, Samples, Measurement Technique, Thermal Profile
• Measurement Results
– PoP
• Effect of “As Is”, “Bake”, “MET9 Days”
– PoP Memory
– FCBGA
– PBGA
• Effect of “As Is”, “Bake”, “MET9 Days”
– Warpage Results vs. Existing Guideline
• Summary
• Next Step
2
Direct connection
between dice
Inter-
connection
via
substrate
Embedded
Horizontal
BGA Package Flip Chip Module
Wire BondingDie Stacked
Package on Package
Through Silicon Via
Chip Embedded + Package on Surface
3D Chip Embedded type
Package in Package
Wire Bonding +Flip Chip (CoC)
Wire Bonding +Flip Chip
SiP structures
Sta
ck
ed
QFP Package
EEPROMV850(DB1)
QFP Type
EEPROM
V850(DB1)
EEPROM
EEPROM
Stacked SOP
QFP Type
Package Technology
3
3D
Packaging3D IC Integration 3D Si Integration
3D Stacking
(wirebonds)
PoP
CMOS image sensor
with TSV
Memory (50μm) with
TSV and microbump
2.5D interposer to support
high-performance chips
CMOS image
sensor with DSP
and TSV
32 memory (20μm)
stacked
Active TSV Interposer
(e.g., Memory on Logic
with TSVs)
Cu-Cu bonding
SiO2-SiO2 bonding
3D MEMS; 3D LEDBumpless
Bumpless
3D Package Technology
4
Technology Trends
• Thinner devices = thinner board and packages
• More disruptive packaging technology – POP, 2.5D, 3D, SIP.
• Packages continue to get thinner with more I/Os and tighter ball pitch
• Lead free solder is driving higher reflow temperature
• Board assembly/SMT parameters becomes part of key equation in yield.
5
Warpage Attributes
6
Package Warpage CharacteristicBoard Warpage Characteristic
Board Assembly Parameters
Material selections: solder paste, flux
Project Phase 2
8
Objective:
1. To characterize the package warpage with respect to
existing warpage allowable
2. To understand the impact of bake and moisture exposure
Thermal Shadow Moiré Apparatus Convention and Preconditioning
Preconditioning Description
“As Is”Units used for board assembly immediately after
taken out from seal bag.
“Bake”Mimic condition where package moisture level being
reset by baking it for 24hrs at 125˚C
“MET 9 Days”
Mimic 7 days component board assembly staging
time + 2 days of unforeseen delays. Exposed to 30
˚C and 60%RH prior to warpage measurement
Metrology
10
JEDEC Standard No. 22-B112A
Package on Package (POP) Warpage
12
• POP Package dynamic warpage varies in behavior and form.
• Majority are convex at room temperature and transition to concave at high temperature.
• The construction of the package and the material used can modulate the dynamic warpage behavior.
• All these samples have low warpage within the allowable guideline stipulated in Jedec.
Effect of “As Is”, Bake & MET 9 Days
13
• Based on the available sample size, the effect of moisture associated with “As Is” vs. “Bake” on package
warpage is insignificant.
• This could be due to these reasons:
• moisture can absorb and desorb easily thru the thin package
• The amount of stress relaxation is not apparent after exposure to baking temperature.
POP Memory Warpage
14
• POP Memory package dynamic warpage varies in form and behavior.
• It is crucial to ensure the POP Memory dynamic warpage (shape) is compatible to POP Bottom Package.
FCBGA Package Warpage Characteristics
15
• FCBGA and FCBGA MCP: Package warpage started off convex at room temperature, then transitions
towards concave at elevated temperature
• FCBGA with Lid: Dynamic warpage depends on the way the lid was attached either fully or partially
coupled to the substrate
• In general, larger package size gives higher dynamic warpage.
Thicker substrateLarger Package size
PBGA Package Warpage Characteristics
16
• In PBGA package construction, mold properties play a significant role in controlling the package warpage
due to the dominant ratio of the mold volume.
• The different range of warpage depends on the material and geometry used.
• All meet the Jedec guideline in reflow temperature warpage. Depending on the solder system or mold
material used, the high temperature warpage can refer to 183C-220C for PbSn or 220C-260C for Pb-free
Different mold
PBGA Package Warpage Characteristics
17
• For larger PBGA packages, the magnitude of warpage can be significantly higher.
• If the solder system is Pb free, some of the package warpage magnitude shown exceeds the Jedec
guideline.
• If the solder system is PbSn, all of the PBGA meet the Jedec guideline.
Different mold
Effect of “As Is”, Bake, MET 9 Days
18
• In some cases, impact of Bake and MET on PBGA warpage magnitude is apparent at both room and reflow
temperatures.
• Bake process reduces the reflow temperature warpage,
• Exposure to a moist environment increases the warpage.
• The impact can be 20-50um.
High Temperature Warpage VS. Existing Guideline
19
POP
Technology
FCBGAs
PBGAs (Pb-Free)
PBGAs (PbSn)
PBGAs (Smaller
Package)
Fine pitch BGA technologies
faced significant challenge to
ensure the package warpage is
low enough for SMT
Summary
• POP
– Dynamic warpage of POP package varies according the construction.
– There is insignificant dynamic warpage difference between As Is vs Bake and MET.
– Majority of the POP package received kept the high temperature warpage below 100um.
• POP Memory:
– There is insignificant dynamic warpage difference between As Is vs Bake and MET.
– Majority of the POP package received kept the dynamic warpage below 100um.
• FCBGA:
– There is no observable dynamic warpage difference between As Is vs Bake.
– Different Lid attachments can yield different dynamic warpage characteristic.
– Ceramic substrate with Lid demonstrate similar dynamic warpage behavior as like organic
substrate but with lower magnitude for the package size considered.
• PBGA
– The effect of “Bake” and “MET” on dynamic warpage is more apparent in PBGA package.
– The “Bake” generally shows lower high temperature while “As Is” and “MET” shows the tendency
to elevate the warpage by 20-50um. Take note that this depends on the mold material used.
20
Next Steps
• Phase 3:
– Measure the advanced package technology (eg: TSV, Heterogeneous, SIP packages)
– Explore other warpage measurement tool as stipulated in JESD22-B112A or newer techniques
– Understand the key factors in packaging assembly that modulates package warpage.
• Other Project: SMT/Component board assembly evaluation
– Solder paste supplier, ODM, component suppliers, Board suppliers.
– Advanced materials for Packages. eg: Ultra Low CTE Package Materials or Low Temp Solders
21