Recognition of Logic Blocks in CMOS circuits · a library of functional blocks is maintained....

Recognition of Logic Blocks

in CMOS circuits

by

lnderpreet Bhasin

Thesis submitted to the Faculty of the

Virginia Polytechnic Institute and State University

in partial fulfillment of the requirements for the degree of

Master of Science

Dr. S. F. Midkiff

in

Electrical Engineering

APPROVED:

Pt. J. G. Tront (Chairman)

August, 1988

Blacksburg, Virginia

Dr. D.S. Ha


In CMOS circuits

by

lnderpreet Bhasin

Dr. J. G. Tront (Chairman)

Electrical Engineering

(ABSTRACT)

A Prolog based approach towards the recognition of logic functional blocks in CMOS

circuits is described in this thesis. A transistor level description of the circuit is as-

sumed to be available. Predefined gates and logic blocks are extracted from such a

description. This recognition procedure is a step towards raising the level· of de-

scription of a network. An extracted block level description can be used to verify the

correctness of the implemented logic. The approach described here uses a circuit

partitioning technique to divide a given circuit into smaller subcircuits. This is fol-

lowed by the extraction of logic expressions at the output nodes of subcircuits. From

these logic expressions, gates are recognized. Functional blocks in the circuit are

recognized based on rules which define such blocks in terms of their structural con-

figuration.

Prologue

This thesis has waxed and waned And suffered from nonchalance Quite often, on wakeful nights It was revived from alarming plights Now, hopefully, it stands arranged Shed of much ambivalence

Even so, it dare not boast or shout Of work unparalleled in academia In fact it spurs many a doubt Of a kind that leads to insomnia

To what end our relentless endeavour, This meditation upon the logical behaviour Of electronic worlds? What if all our microcircuitry Should be a piece in a war machinery ?

And lo, this flash of corporate money That drives eager eyed graduates To talk with a Lisp, Strive to C (Just shrunken chips and timeless gates ?)

Never mind. Its just a career. 'Write an algorithm. Have a beer.' They say it wouldn't be quite so bad If one could connect Quanta with CAD.

I apologise for such cynicism Perhaps, I need better vision (I wonder why I spend my time Striking strains of feminine rhyme) Besides, why should electrical engineers essay To write verse? It doesn't pay.

Ill

Acknowledgements

I thank Dr Tront, my advisor For his continued help and guidance And for having provided wiser Counsel, in times of trying patience

For their willingness to be Judges of my Master's degree My thankfulness is due To Ors Ha and Midkiff too

I am indebted to each friend Who did partake my curious blend Of poetry and E.E. And helped my spirits run free

If my thoughts flow out in song I should credit Dylan and Simon Their soulful tunes, hours long Of painful tedium, did enliven

On days, when my technicality Seemed to border on triviality It was Milind who (unknowingly) consoled By his stand, so shocking and bold: These are mediocre times. Who can dare To assume an Einsteinian air?

Acknowledgements iv

Table of Contents

Chapter 1. Introduction . . . . . . . . . . . . . . . • • . . . . • . • . . . . • • • . . . • • . . • • . . • . • . . . . • . 1

Chapter 2. A Survey of Verification Techniques for VLSI • . . . . • • • • • • • • • • • • . • . • . . • . • 4

2.1 Circuit Verification ................................................... 5

2.2 Logic Level Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.2.1 The Graph Isomorphism Problem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.3 Verification through Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.4 Symbolic Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.5 Formal Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.6 Rule Based Verification Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2. 7 Functional Abstraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.8 Functional Block Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Chapter 3. The Block Recognition Approach • • . . • . • . . . . . • • . . . • . . . . • . • . . . . . • • • . 17

3.1 The Recognition Problem ............................................. 18

3.2 Circuit Description and Verification Using Prolog . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.3 The Block Extraction And Recognition System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.4 A Recognition Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table of Contents v

Chapter 4. The Extraction of Logic Blocks . . . • • . • . • . . . . • . . . . . . • . . • • . . . . . • • . • . . 32

4.1 Circuit Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.2 Input to the Block Extraction Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4.2.1 Node Labelling Convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4.3 Recognition of Inverters and Transmission Gates . . . . . . . . . . . . . . . . . . . . . . . . . . 38

4.4 Deriving a Node-Oriented Data Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

4.5 Node Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

4.6 Circuit Partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4.6.1 The Partitioning Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

4.6.2 A Partitioning Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

4.7 Derivation of Logical Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

4.7.1 A Note on the Representation of Boolean Equations ..................... 52

4.7.2 Handling Complements of Boolean Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

4.7.3 Forming Logic Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

4.7.4 The Path Tracing Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

4.7.5 Rules for forming logic expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

4.8 Load-Driver logic blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

4.9 Pass and Transmission Blocks .............................. ·. . . . . . . . . . . 61

Chapter 5. Recognition of Logic Blocks • • • . . . . . . . • • • . . . . . . . . . . . . • . . . • . . . . . . . . 66

5.1 Recognition of Gates through Logical Equivalence . . . . . . . . . . . . . . . . . . . . . . . . . . 68

5.1.1 An Example .................................................... 70

5.2 A Rule for Establishing Equivalence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

5.3 Recognition of Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

5.4 The Specification of Rules for Gates and Functional Blocks . . . . . . . . . . . . . . . . . . . 81

Chapter 6. Conclusions ...... ·. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

6.1 A Discussion of Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Table of Contents vi

6.2 Extensions to the Work Done . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . 91

Vita . I •• I I •• I •• I I •••••• I I ••• I ••• I I I • I I • I I I • I I I ••• I I I ••• I •• I I ••• I I I I • • 95

Table of Contents vii

List of Illustrations

Figure 1. Topological Nonequivalence of The Same Logic ................. 8

Figure 2. CMOS Static d flip-flops .................................. 19

Figure 3. A Block Extraction and Recognition System ................... 25

Figure 4. Transmission-Gate Adder ................................. 27

Figure 5. Input Description of Transmission-Gate Adder ................. 28

Figure 6. Blocks Extracted in the Circuit of Figure 4. . ................... 31

Figure 7. An Example Output of Magic's Circuit Extractor ................ 34

Figure 8. Classification of Nodes ................................... 41

Figure 9. A CMOS Circuit ......................................... 47

Figure 10. Partitioned Blocks for the Circuit of Figure 9 ................... 48

Figure 11. Examples of Load-Driver and Pass Blocks .................... 60

Figure 12. Tally Circuit ........................................... 64

Figure 13. Logic Expressions Generated for the Tally Circuit ............... 65

Figure 14. An Example of a Composite Gate ........................... 71

Figure 15. A CMOS Exclusive-Or Circuit .............................. 74

Figure 16. A Transmission-Gate Exclusive-Or Circuit ..................... 76

Figure 17. A Full-Adder Circuit ..................................... 78

Figure 18. A Multiplier Circuit ...................................... 79

Figure 19. D Flip-Flop Circuit with Reset .............................. 80

Figure 20. Gates and Blocks Recognized in the Multiplier Circuit ........... 82

List of Illustrations viii

List of Tables

Table 1. Load, Driver and Pass Blocks in the Circuit of Figure 9 ............ 50

Table 2. Sample Run Times ....................................... 87

List of Tables Ix

Chapter I

Introduction

An important aspect of VLSI CAD is verification of the design. Verification ensures

that the final layout correctly represents the intended logic. The design process is

error prone because the design of digital systems is not as yet a fully automated

procedure. Topological design errors in the layout can cause the intended logic not

to be realized. We therefore need to verify that the final layout will implement the

desired function. Broadly, the verification process consists of establishing the cor-

rectness of two design features. One needs to check that the correct logic is imple-

mented and that the desired timing behaviour is obtained. In this thesis we deal with

the first kind of verification, that of logic.

Digital circuits have an implicit hierarchy in their description. At the lowest level,

transistors can be configured in different arrangements, to form basic gates such as

nand, nor, exor, transmission gates and inverters. These basic gates may be com-

bined to obtain more complex gates such as adders and shift registers, which in turn

could be the building blocks of larger logic modules. Given such a hierarchy in the

description of a circuit, verification is possible at several levels. However, it is easier

Introduction 1

to verify a circuit at a higher level of description when it is pruned of details. A de-

sirable approach in verifying a design would therefore be to transform a detailed de-

scription into a less detailed one. In a sense, this is a reversal of the forward design

process where a designer goes step by step from a highly abstract notion of the

function to be implemented to a detailed layout on silicon.

A system has been implemented to automatically extract logic blocks from a CMOS

transistor level description. This process of block extraction is a positive step toward

translating the circuit description to a higher level.

The description of the circuit is assumed to be available at the transistor level. Se-

veral schemes already exist to extract the transistor level interconnectivity informa-

tion from the mask level layout [1,2]. Starting with the description generated by a

circuit extractor, we derive a higher level description in the form of an intercon-

nection of functional blocks. Previous work of a related nature has concentrated on

the extraction of very basic gates, based purely on topological comparison with ref-

erence gates [4,5,17]. In the program to be described, an array of predefined gates

can be recognized from a transistor level description of the circuit, based on the

symbolic boolean expressions at the output nodes of the gates. The extraction of

these boolean expressions is part of the program. Following the recognition of basic

gates, functional blocks composed of these gates can be recognized. In the program,

a library of functional blocks is maintained. Within this library, a logic block is defined

as a set of Prolog clauses. More than one description of the same type of logic block

is possible. The recognition of a functional block becomes equivalent to satisfying a

goal subject to the constraints specified in the rules for that block. These constraints

Introduction 2

take a structural form wherein a block is defined as a composition of lower level

blocks and gates.

The program is written in Prolog. Prolog is a logic programming language well suited

to the structural description of digital circuits.

The next chapter is an overview of existing verification techniques for VLSI. In Chap-

ter 3 the block recognition approach is outlined. Chapter 4 deals with the partitioning

of a CMOS circuit into logic blocks and the extraction of logic expressions at the

output nodes of blocks. In Chapter 5 the recognition of gates from the derived logic

expressions and the subsequent recognition of functional blocks composed of these

gates is described. Chapter 6 is a summary which includes a discussion on possible

extensions to the work done in this thesis.

Introduction 3

Chapter II

A Survey of Verification Techniques for VLSI

In this chapter, we review a number of approaches to the problem of verifying that

an implemented layout performs correctly, the logic function desired of it.

The design process consists of translating through a sequence of steps, a relatively

abstract behavioural description of a circuit, to a detailed layout which can be imple-

mented on silicon. The final layout must be checked for features such as conformity

to geometrical design rules, electrical connectivity, functional correctness and timing

performance.

Design rule checkers perform the basic task of checking for violations of rules that

govern geometrical aspects such as minimum widths of layers and the clearance

between layers. An electrical connectivity check could consist of determining the

nodes in a layout and their interconnections. Knowing these, one can detect shorted

and open nodes and missing contacts. A check for functional correctness seeks to

A Survey of Verification Techniques for VLSI 4

determine a correspondence between the intended logic and the logic realizable with

the implemented design. A physical layout may obey design rules and realize the

correct logical function, but it could still fail to give the desired electrical performance

in terms of timing. Timing verification is the process of checking to determine that the

signal path delays are within acceptable limits.

The term verification in the rest of this chapter will imply logic verification or the

process of checking for functional correctness.

The first step in the verification of a layout consists of reconstructing the transistor

level interconnection description from the mask level layout. This step is carried out

by circuit extracting programs [1,2] which operate on the layout description to gen-

erate a list of circuit nodes, resistances, parasitic capacitances and transistors.

In the sections that follow, a survey is made of some of the verification techniques

developed so far.

2.1 Circuit Verification

Once the circuit information has been extracted from a layout, a direct comparison

can be made between the extracted circuit and the reference or desired circuit. In

order to do so, the reference connectivity information must be provided. The com-

parison process in most cases, is one of proving a graph isomorphism [3,4]. One

such approach described in [3], derives a matrix representation of the extracted cir-

cuit. Rows of the matrix represent circuit elements such as transistors, resistors and

capacitors while columns represent nodes of the circuit. A matrix representation of


the intended circuit is also prepared and the two matrices are tested for

isomorphism. The isomorphism test involves permutations of the rows and columns

of the extracted circuit matrix and then a check with the reference matrix. To improve

performance, 'weights' can be assigned to the matrix elements depending on the el-

ement connectivity.

An alternative comparison technique is to employ labels on the layout corresponding

to node names in the reference circuit [4]. In this case, a one to one correspondence

can be attempted between the nodes of the designed circuit and the reference circuit

to check for correctness.

For large circuits, circuit level verification is infeasible because the amount of data

to be handled would be voluminous and preparing the reference connectivity would

be a tedious task. This approach is limited to small circuits and cells.

2.2 Logic Level Verification

An improvement can be made on the previous method if groups of transistors are

replaced by the logic gates they implement. A graph can then be made to represent

a gate level circuit, reducing the amou:it of data. A program is described in [5] for

logic level verification, in which a limited category of primitive logic gates are con-

structed from the transistor level description. Gates belonging to this category are

inverters, nands, nors, ands, ors, transmission gates, nand/nor latches and wired-or

gates. Circuits which cannot be resolved into this primitive logic gate category are left

as collections of transistors. In the graph representing the gate level circuit, vertices

in the graph stand for logic gates and input/output terminals. Gates are identified by


placing labels on the vertices. Interconnecting wires are converted into directed

graph edges, where the direction is that of the signal flow. Bidirectional paths are

replaced by two edges which have opposite directions.

A point to note in these methods of verification is that a test for isomorphism estab-

lishes topological, not functional equivalence. In the approach described above, two

implementations of the same logic, as shown in Figure 1, would be considered dif-

ferent. Several papers have described the graph isomorphism approach. This ap-

proach however, imposes a restriction on the designer to create designs which retain

a topological correspondence with the original designs.

A second shortcoming of the above approaches is the limited number of logic gates

which are recognized. Designers frequently use non standard logic gates and not all

logic blocks are describable as combinations of simple primitive gates.

2.2.1 The Graph Isomorphism Problem

All techniques that use a graph theoretical technique must contend with the fact that

efficient methods for the general problem of proving the isomorphism of two graphs

do not exist [28]. Heuristic algorithms rely on partitioning the vertices of the graph

into groups of similar topological features. An example of such a feature would be the

degree of a vertex, that is, the number of edges incident upon it. A mapping is at-

tempted between the partitioned vertices of the two graphs which are being tested for

isomorphism. In the worst case there will be N I mappings where N is the number

of vertices in the graph. For particular problems the timing complexity of the algo-

rithm depends on the criterion used for grouping vertices.


vdd vdd 0 0

I

c-4~94 c-4 ~ d-4 ~

I I d-4 ~ ~ a-4 a_j

I

a~ b~ d~

c~ a I 11 c~

d~ b~

e~ e~

Figure 1. Topological Nonequivalence of The Same Logic


2.3 Verification through Simulation

Verification can be accomplished through simulation of the designed circuit and

comparison of the resu Its with expected input/output responses. At present, simu-

lation is the most widely used method for verifying the design of a chip prior to fab-

rication. Logic simulation started mainly as gate level simulation using the three

states: '1' (logical high), 'O' (logical low) and 'X' (don't care). Since gate level simu-

lation could not be applied to a large class of logic circuits which used pass transistor

logic and non standard gates, logic simulation at the transistor level, switch level

simulation [6], was developed. Switch level simulators view transistors as switches

with no assigned direction of signal flow. Circuit nodes can be sources of strong

signals or they can hold charge dynamically. A switch level simulator is used after the

circuit extraction phase when verifying a layout. The extracted circuit is fed a series

of test patterns and the output response is compared with the expected response.

This method has the advantage that it does not impose any restrictions on the de-

signer. However, it has its drawbacks. Since complete verification would mean sim-

ulation with all possible input patterns, complete verification of large circuits is not

practical. Usually, a set of random patterns is used. Moreover, when partial circuits

rather than a complete design has to be verified, it may be a tedious task to prepare

test patterns for each part of the circuit.


2.4 Symbolic Verification

The symbolic verification approach is based on the idea that one can symbolically

verify the behaviour of a circuit by computing the boolean expressions at the outputs

of the circuit. Symbolic simulation which falls in this class of verification techniques

is a conceptual extension of the switch level simulation method to a case where the

inputs to a circuit can be set not just to '1', 'O' and 'X' but also to a boolean variable.

The simulation then becomes symbolic and requires boolean function manipulation

techniques. Since a symbolic simulator can accept input patterns consisting of

boolean variables, it can compute the boolean function describing the behaviour of

the circuit for the entire range of input vectors (in terms of '1's and 'O's) represented

by this set of variables. Symbolic simulation would therefore have greater power than

conventional simulation, which in fact becomes a special case where all the inputs

are set to constants, either '1', 'O' or 'X'. Attempts at symbolic verification and auto-

matic generation of logic expressions for MOS circuits have been described in [7-10].

Symbolic verification requires the ability to extract boolean expressions at specified

nodes in the network and then to operate on these expressions. However, finding the

logic expression at the output of a logic block, the inputs to which are logic ex-

pressions produced as outputs of other logic blocks, is not a straightforward problem.

Also, certain operations such as the complementation of a boolean expression are

computationally time consuming. Moreover, for sequential systems, the behaviour

cannot always be represented in terms of boolean equations.


2.5 Formal Verification

Formal verification is a suggested approach which attempts to overcome the short-

comings of simulation by considering the verification of digital behaviour as a prob-

lem of mathematical proof [11).

In essence, the idea is to formally prove, as is done with a theorem in mathematics,

that a proposed logic design does implement the desired function. Within the frame-

work of this approach, the VLSI design process is viewed as a series of translations

between levels, starting from a functional level to a mask artwork level. Each trans-

lation between two levels has to be accompanied by a validation or proof that it is

correct. An example of this could be proving that the functions expected from ele-

ments such as adders and shift registers are indeed realized, when these elements

are translated in the design process to a composition of lower level elements such

as nands, inverters, flip-flops and multiplexers.

A formal verification system is described in (12). The system is a theorem proving

program which uses the axioms of boolean algebra and signals in transition and has

the ability to manipulate symbols. The logic network is described at gate level. The

function to be implemented is viewed as a possible theorem which expresses the

desired behaviour of the network at a logic level, one level above the level of the

described network. The axioms and manipulation rules are then applied to the logic

circuit description to prove the theorem.

In order to be a useful alternative to simulation, the formal verification approach

needs to develop far enough to verify translations between all levels in a design.


2.6 Rule Based Verification Systems

Another alternative to simulation has been the suggested use of expert systems for

verifying the correctness of a design [13, 14]. These systems conduct a static analysis

of the circuit using design methodology rules. The rules are dependent on the design

style and form the knowledge-base of the system. The program invokes rules to

check for violations of design aspects such as logic levels, race-free operation and

timing constraints.

This approach is essentially an extension of the geometric design rule checker con-

cept to a higher level. Such systems do not establish functional correctness. Rather,

they indicate whether a given circuit violates any design rules from a predefined set

of such rules. Hence, they do not substitute for simulation.

2.7 Functional Abstraction

The objective of a design verification system is to insure that the final design meets

the specifications which the designer developed at the outset of the design process.

It should be noted though, that the final design (layout) is in the form of a static

structural description whereas the initial design is usually in the form of a functional

behavioural description. Thus, a comparison needs to be made between descriptions

of a design at two different levels.

There are three possible ways to approach this problem: [15]


1. An alternative correct design could be generated from the original specifications

and a comparison made with the design to be verified at a low level of ab-

straction.

2. From the final detailed design, the behaviour is automatically extracted and a

comparison is made at a high level of abstraction.

3. A combination of the above methods in which both the original functional de-

scription and the final structural description are brought to a common intermedi-

ate level of abstraction.

In practice, approach (3) is commonly used. For instance, the method of logic verifi-

cation using the graphical approach employs a reference graph made from the ori-

ginal logic level design and a graph derived from the actual layout. However,

approach (2) is theoretically the most desirable for the following reasons: [15]

1. By abstracting the final design to a higher level only relevant features are re-

tained, resulting in a minimal amount of data in the comparison process.

2. The same original specifications can result in different implementations. This

problem has been mentioned before in relation to logic level verification based

on recognition of primitive gates. A purely graphical approach in that case, can-

not determine the functional equivalence of two different implementations of the

same logic design. By raising the level of abstraction, different implementations

are abstracted to the same behaviour.

The process of extracting the behaviour of a design from a lower level detailed de-

scription is termed functional abstraction.


A method is outlined in [15] for deriving RTL expressions for gate level designs. For

this purpose, an extension of boolean algebra called 'dynamic boolean algebra'

which can handle signals in transition is used. The system accepts as input a struc-

tural definition of the design to be verified. This structural definition is in terms of

predefined basic elements such as adders and flip-flops and their interconnections.

The design to be verified is a logic module composed of these basic elements. The

behaviour of these elements is defined in a catalog. The generated output contains

a list of interface signals, a list of internal state signals in the case of sequential cir-

cuits and the behaviour of each interface signal of interest given in a RTL like fashion.

Abstraction of behaviour to a higher level is only the first step in the verification

process. The extracted behaviour has to be compared with the intended behaviour.

It is not yet clear how the comparison can be done automatically. However, at this

point, the extracted behaviour facilitates a by-hand comparison for lower complexity

circuits.

An application of the functional abstraction approach is described in [16] where an

attempt is made to automatically generate the program code for a higher level func-

tional simulation model. The objective here is to allow a designer to create a design

and then abstract it to a higher level where it can be simulated more efficiently. The

circuit could be described in terms of basic logic blocks and their interconnections.

The simulation models for these basic blocks are defined in a library. The program

produces a high level simulation model for a circuit from the models of its compo-

nents. The assumption in this method is that the behaviour of a large circuit is implicit

in the behaviour of its parts and their structural interconnections.


Ideally speaking, a reverse process of going from a detailed description of a design

to a high level abstract description can be envisioned as one that would accept as

an input, the layout data of a design and produce as an output the underlying algo-

rithm which describes the digital behaviour of the design. The task involves bridging

several levels of abstraction and is difficult.

2.8 Functional Block Recognition

We have observed that the task of verification would be considerably easier if per-

formed at a higher level in the hierarchy. Although the conceptual outline for trans-

lating descriptions from a lower level to a higher level exists, there has been little

work in attempting to bridge levels of abstraction. Recognition of logic function blocks

from a transistor level description is a step in this direction.

Some logic verification techniques (4,5, 17] incorporate the extraction of very basic

gates from the transistor level description of a circuit. However, the range of logic

gates recognized is very limited. In [18] a more general block extraction scheme

based on a graph theoretical approach is described. But, the recognition of blocks is

purely on the basis of circuit topology and is accomplished through comparison of

reference graphs of logic functions with derived graphs in a circuit. A generalised

approach is outlined in [19,20] for checking the logical correctness of FET designs

through circuit recognition.

In the following chapters we describe an approach for the recognition of functional

blocks in CMOS circuits. The basis of recognition is the circuit topology as well as the

deduced logical behaviour of circuit blocks. Unlike previous methods which take a


purely graphical approach, we use the symbolic features of Prolog to define func-

tional blocks. The instances of these blocks in a circuit are then recognized using the

pattern matching ability inherent in Prolog.


Chapter Ill

The Block Recognition Approach

Having reviewed a number of verification techniques, we can make the following ob-

servations:

1. Alternatives to the simulation approach for verification are desirable and are be-

ing pursued by researchers.

2. In the absence of simulation, the functional correctness of a circuit has to be de-

duced from a purely static analysis. Such an analysis would be based on the

physical connectivity of the circuit components.

3. The task of establishing the functional correctness of a circuit is easier when the

description of the circuit is available at a higher level in the abstraction hierarchy.

We describe a method to recognize logic functional blocks from a transistor level

description of a circuit. The motivation for doing so stems from the observations

above. Translating a circuit description consisting of an interconnection of transistors

to a description consisting of an interconnection of logic blocks is a step toward

raising the level of abstraction. We may observe how such a recognition process can

The Block Recognition Approach 17

enable verification at a higher level. Assume that a circuit is specified as a composi-

tion of subcircuits. A recognition procedure operating on the implemented design

identifies each subcircuit that makes up the larger circuit. Now, we can check

whether these subcircuits are configured in a way that realizes the intended circuit.

The terms logic blocks and subcircuits are used interchangeably in this writing and

have a loose definition. They imply logic components reconstructed from a transistor

level description. As shall be apparent in later sections, the recognition process itself

follows a hierarchy. Thus, the term logic block can stand for an and gate, an exor

gate, an adder, a flip-flop or even a multiplier composed of previously recognized

adders and flip-flops.

Given a network described at the transistor level, the recognition program would

seek to identify collections of transistors which constitute defined logic blocks. Hav-

ing identified some of the basic blocks directly from the transistor level, the next step

would be to identify other blocks which are defined as being composed of blocks al-

ready identified and possibly, transistors. The block recognition procedure moves up

in steps, identifying larger blocks from smaller blocks and their interconnection.

However, their is no clear division between the levels of logic blocks.

3.1 The Recognition Problem

Consider the problem of recognizing the logic qf a circuit block from a description of

its constituent transistors. Figure 2(a) shows the transistor level circuit of one ver-

sion of a 2 phase static D flip-flop. The gate level circuit is shown in Figure 2(b). A


vdd vdd

r vdd r

D

Ca) Cb)

D ¢

Q -¢ ¢

¢

Cc)

Figure 2. CMOS Static d flip-flops


human designer attempting to interpret the logic described by this circuit would

identify the nodes Q and Q1 as the output nodes and also conclude that it is a cross

coupled structure. Next, the logic equations at the output nodes would be derived as:

Q=(</JD +01)

Q1 =(</JD+Q)

Substituting Q1 in the expression for Q, a simplification would yield:

Q =</JD+ </JQ

This equation would lead to the interpretation that the circuit is an instance of a D

flip-flop with an input D and a clock signal </J.

Now, consider Figure 2(c). which shows another version of a two phase static D flip-

flop. In this case, a designer with previous knowledge of circuit structures, observing

the feedback paths, would note two clocked latches cascaded in series. A further

observation that the clock inputs to the two latches are complementary would lead to

the conclusion that the circuit is a 2 phase D flip-flop.

We conclude then, that an intelligent program attempting to recognize logic blocks in

a circuit would need a knowledge-base which enables it to do the following:

• Correlate derived boolean expressions with defined functions.

• Match particular circuit topologies to defined functions.


The recognition process then, is based on both, the topology of the circuit and the

logical behaviour of the circuit.

The broad outline of the recognition and verification procedure can now be stated as

follows:

1. Circuit recognition rules are maintained in a library. These rules define logic

blocks in terms of transistor interconnections, lower level logic blocks or in a

behavioural form in terms of boolean logic expressions.

2. The transistor level description of the circuit is processed to a form where the

application of recognition rules can proceed. This processing step involves par-

titioning a circuit into smaller subcircuits and extracting logic expressions at

output nodes of these subcircuits. This forms the subject of the next chapter.

3. The circuit to be verified is specified as an interconnection of its constituent logic

blocks. Rules describing each of these logic blocks should be present in the rule

library.

4. Using the recognition rules, an attempt is made to find an instance of each logic

block in the original circuit, within the designed circuit. The recognition proce-

dure is constrained by a need to preserve the connectivity between logic blocks

as specified in the original circuit. This connectivity pattern is implicit in the input

and output node names of the logic blocks.

5. If an instance of each constituent logic block is found, one can conclude that the

circuit reflects the desired logic.


In order to implement the described approach, a programming language is desired

which facilitates an easy description of logic circuits as well as the manipulation of

boolean expressions. Pro log fu lfi Is these needs. The next section reviews the use of

Prolog in describing digital circuits.

3.2 Circuit Description and Verification Using Prolog

Prolog is considered a logic programming language, suitable for symbolic, non-

numeric computation [21]. The use of Prolog has been suggested of late for the de-

scription and verification of digital circuits [22, 23]. A Prolog program consists of

clauses. A clause may be a fact or a rule. Facts describe relations on objects. For

example, a 2-input nand gate with inputs a and b and output y, can be represented

as a Prolog clause in the following manner:

nand2(a, b, y).

In the above expression, nand2 is the predicate and a, band y are arguments.

A rule in Prolog relates objects. A rule has the form :

G :-

G1,

G2,

Gn.


where G, G1, G2, ... Gn are logic expressions. G is the head or goal of the rule. Each

of G1, G2, ... Gn may in turn be another rule in which case it is a subgoal. The goal

G is true if each of its subgoals is true.

As an illustration, a nand latch consisting of two cross-coupled nand gates can be

described in rule form as follows :

nand_latch(S,R,Q,Q_) :-

nand_gate2(S,Q,Q_),

nand_gate2(R,Q_,Q).

In the example above, it should be noted that the input terminals of a nand gate are

interchangeable. This could be taken care of by defining another rule as follows :

nand_gate2(A, B, Y):-

nand2(A, B, Y);

nand2(B,A,Y).

Note the semicolon in the rule above. It implies the or operation. Thus, a nand with

inputs s and q_ and output q is found if either of the two facts: nand2(s,q_,q) or

nand2(q_,s,q) are present in the database. Prolog follows a pattern matching proce-

dure when searching for a clause in the database. The order of arguments is there-

fore important. A clause nand2(a,b,y) would be different from nand2(b,a,y).


A Prolog program is invoked by framing a query which could consist of one or more

goals. Prolog responds to the query by attempting to prove the specified goal(s). For

instance, assume that we have extracted all the basic gates from the transistor level

description of a circuit and we wish to check for the presence of an exor gate. We

could do so by framing the query:

exorgate(A, B, Y).

If we assume that the knowledge-base of the program contains rules which enable

the identification of exclusive-or gates in a circuit, then Prolog will attempt to find an

instance of such a gate. If it succeeds, the variables A, B and Y are instantiated to

actual node names in the circuit.

In [24], a Prolog based approach is described for verifying gate level circuits through

symbolic simulation. Prolog allows a circuit to be described in a manner which is

easy to understand. This is particularly advantageous when we consider the framing

of rules for the recognition of logic blocks. If a new logic block is used in a design,

the user can add the rule describing the block, to the rule library with relative ease.

There are two major features of Prolog which are very useful in verification. These

are the pattern matching ability and automatic backtracking.

3.3 The Block Extraction And Recognition System

The overall scheme for the extraction of gates, blocks and logic expressions from a

layout description such as the Caltech Intermediate Form (CIF file) is shown in

Figure 3. In this scheme, the Magic system [29} is shown, used in conjunction with

the block extraction and recognition system devised in this thesis. Any other circuit


I

lt'IGIC SYSTEM

Cif" FILE

.mag FILE

.ext FILE

l .slm FILE

PREPROCESSOR IC - f'ROGRA'!)

l I

PROLOG DATABASE AND

PROGRR1

l l l gate• logic logic

block• expres•lon•

BLOCK EXTRACTION AND RECOGNITION SYSTEM

Figure 3. A Block Extraction and Recognition System


extraction procedure which produces a transistor level description of a layout in the

.sim format, can be used instead.

In the Magic system, a CIF file is read and converted into a .mag file which is in

Magic's own format. Magic's circuit extractor operates on a file in this format to

produce a .ext file which consists of a heirarchical circuit level description. The pro-

gram ext2sim converts a heirarchical description of a circuit into a flat form which is

called the .sim format. A C preprocessing program which forms a part of the block

recognition system, converts a file in the .sim format into a list of Prolog clauses

which form the input to the recognition program written in Prolog.

3.4 A Recognition Example

To illustrate the ideas outlined in this chapter, consider the recognition of a functional

block such as a full-adder which occurs in a larger circuit. One form of a full-adder

known as the transmission-gate adder [26] is shown in Figure 4. The transistor level

description of a circuit which forms the input to the recognition system, can be ob-

tained through a circuit extractor operating on a mask level layout description. (The

next chapter reviews circuit extraction.) The input description of this full-adder circuit,

which is given to the recognition system, is in the form of the netlist connectivity in-

formation of the circuit and consists of a list of transistors contained in the circuit

along with the list of primary input and output nodes in the circuit. This description

is shown in Figure 5. Circuit recognition rules are then used to identify the logic

blocks in the circuit. Simple structures such as inverters and transmission gates can


vdd

sl s

vdd

q carry

Figure 4. Transmission-Gate Adder


input_list([a, b, c]). output_list([s, carry]). trans(p, c, vdd, c1). trans(n, c, c1, gND). trans(p, y1, c1, s1). trans(n, y2, c1, s1). trans(p, y2, c, s1). trans(n, y1, c, s1). trans(p, b, vdd, b1). trans(n, b, b1, gND). trans(p, y1, b1, q). trans(n, y2, b1, q). trans(p, y2, c1, q). trans(n, y1, c1, q). trans(p, s1, vdd, s). trans(n, s1, gND, s). trans(p, q, vdd, carry). trans(n, q, gND, carry). trans(p, a, vdd, a1). trans(n, a, gND, a1). trans(p, b, a, a1). trans(n, b, y1, a1). trans(p, b, a1 ,y2). trans(n, b, a, y2). trans(p, a, y1, b). trans(n, a1, y1 ,b). trans(p, a1, y2, b). trans(n, a, y2, b).

Figure 5. Input Description of Transmission-Gate Adder


be recognized directly from the transistor level description. For instance, an inverter

with input X and output Z can structurally be described by the following rule:

inv(X,Z):-

(trans(p, X, vdd, Z);

trans(p, X, Z, vdd)),

(trans(n, X, gND, Z);

trans(n, X, Z, gND)).

where a clause such as trans(p, X, vdd, Z) represents a p-type transistor with gate

signal X, source node vdd and drain node Z.

The repeated application of the rule above, will lead to the identification of all

inverters in the circuit. This is accomplished by utilising the automatic backtracking

facility in Prolog which causes all possible solutions for a given goal to be explored.

In order to identify more complex logic blocks, the circuit is partitioned into smaller

subcircuits as described in the next chapter. The logical behaviour of each subcircuit

is then determined in terms of boolean expressions at the output nodes of the sub-

circuit. Logic gates are recognized on the basis of these boolean expressions. The

exor and exnor gates in the full-adder circuit of Figure 4 would be recognized by such

a process.

The structural description of the transmission-gate adder is expressed by the follow-

ing rule:

fu nction(fu I I_ adder, [[i nputs,A, B,C],[su m,S],[carryout,Carry]]):-

exorgate(A, B, Y1 ),

exnorgate(A, B, Y2),

transmission(B_, Carry_, Y2, Y1),


transmission(C_, Carry_, Y1, Y2),

inv(A, A_),

inv(B, B_),

inv(C, C_),

transmission(C, S_, Y1, Y2),

transmission(C_, S_, Y2, Y1),

inv(S_, S),

inv(Carry_, Carry),

assert(full_adder(A, B, C, S, Carry)).

By the recognition process, first all the basic gates in the circuit are identified. Next,

predefined functional blocks are identified. The output generated by the recognition

process for the circuit of Figure 4 is shown in Figure 6.

In the next chapter we consider the extraction of logic blocks from a description of a

circuit which is in the form of a list of transistors.


GATE: transmission input b output yl gate_inputs al a

GATE: transmission input b output y2 gate_inputs a al

GATE: transmission input c output s gate_inputs yl y2

GATE: transmission input bl output q gate_inputs y2 yl

GATE: transmission input cl output s gate_inputs y2 yl

GATE: transmission input cl output q gate_inputs yl y2

~ATE: transmission input yl output b gate_inputs al a

GATE: transmission input y2 output b gate_inputs a al

GATE: transmission input s output c gate_inputs yl y2

GATE: transmission input q output bl gate_inputs y2 yl

GATE: transmission input s output cl gate_inputs y2 yl

GATE: transmission input q output cl gate_inputs yl y2

GATE: exor input [a, b] output yl

GATE: exnor input [a, b] output y2

Function: full_adder inputs a b c sum sum carryout carry

*****

Figure 6. Blocks Extracted in the Circuit of Figure 4.


Chapter IV

The Extraction of Logic Blocks

It was mentioned in the previous chapter that the recognition of logic blocks in a cir-

cuit is a step toward raising the level of description of a circuit. In particular, such a

recognition process can eventually enable verification at a higher level in the hierar-

chy.

To facilitate the recognition procedure, the circuit has to be divided into its constitu-

ent logic blocks. A program to automatically extract logic blocks in CMOS circuits is

described in this chapter.

The input to the program is a transistor level description of the circuit. We are not

concerned here with the extraction of the transistor level interconnectivity information

from a mask-level layout description. Several circuit extraction schemes are in ex-

istence for accomplishing this task. The next section is .a brief overview of circuit

extraction.

The Extraction of Logic Blocks 32

4.1 Circuit Extraction

A circuit extractor accepts as an input, the geometric layout description of a circuit

and produces as an output, a network of interconnected electrical devices. The input

description given to an extractor could be a CIF file. Such a description conveys

purely geometric information of the mask-level layout. Based on the pattern of layers,

the extractor derives a list of nodes in the circuit as well as a list of circuit elements

such as transistors, resistors and parasitic capacitances. Circuit elements are re-

cognized by considering the intersection of layers. The structure of the circuit ele-

ments depends on the technology used. Most extractors include a technology file to

incorporate technology dependent information. This information is preprocessed

prior to the extraction phase. A circuit extractor also determines the connectivity be-

tween electrically equivalent regions. Polygons which touch or intersect on the same

conducting layer are electrically equivalent. Electrical equivalence between polygons

on different layers depends on the technology.

We consider as an example, Magic's circuit extractor [2]. This is a hierarchical circuit

extractor which operates on a layout to produce a list of transistors as well as

parasitic capacitances and resistances. If a layout is created hierarchically, a cell

would consist of layer descriptions, calls to smaller subcells, and interconnection

layers. The extracted circuit preserves the hierarchy and contains calls to smaller

subcircuits.

An example of the output generated by the M?gic extractor is shown in Figure 7.

Since we are concerned only with the logical behaviour of the network we can ignore

the resistance and capacitance information generated by the extractor. The Magic


Vdd

A B

GND

(a)

node GND 12 21 node B 150 50 node 3_ 4_6# 30 8 node A 150 50

Out Node:Vdd R = 22 C = 20

---++------1 R = 150 C = 50 1-----

Node: A 1 C=2

-~1------lR = 150 C = 50 1----"---

Node:B node Out 113 25 node Vdd 22 20

Node:GND R=12 C=21

cap BA 2 fet efet 12 16 GND B 4 3_4_6# 6 GND 6 fet efet 1216 GND A 4 Out 6 3 3_4_6# 6 let diet 1216 GND Out 12 Vdd 2 Out 2

(c)

(b)

Figure 7. An Example Output of Magic's Circuit Extractor: Figure 7 (a) shows an NMOS inverter. Shown in (b) is the extracted connectivity information. The actual output of the extractor is shown in (c). (2).


layout system enables the user to ascribe labels to the layers when they are created.

These labels are retained in the extracted circuit description. In the case where no

labels are ascribed, the extractor generates its own node names. For ease of analy-

sis, one can standardise global node labels like Vdd and GND. Further, the user can

affix attributes to layers which would allow an extracted node to be identified as a

user defined input or output node.

Magic's extractor produces a separate file for each cell in a hierarchical design. A file

consists of a series of lines, each starting with a keyword. A line describing a tran-

sistor has the following format:

fet type xi yl xh yh area perim sub GATE T1 T2 ....

where,

type denotes the kind of transistor, that is p or n,

and

xi, y/, xh, yh, area and perim give geometrical information about the gate region of

the transistor.

The remainder of the fet line describes the three terminals of the transistor, that is,

gate, source and drain. The description of a terminal includes its name, its perimeter

and an attribute list which might identify the terminal as a chip input or output.

4.2 Input to the Block Extraction Program

The input to the block extraction program consists of a list of transistors which com-

prise the circuit. Along with the list of transistors, a list of input and output nodes of

the circuit is also specified. It was mentioned in the previous section, that a node


could be identified as a primary input or output node, by means of attributes affixed

to the layer corresponding to the node. Each transistor in the input description is

represented as a Prolog clause in the database. The connectivity of a transistor is

specified in the format

trans(Type, Gate, T1, T2).

where

Type indicates the transistor type, namely n or p

Gate stands for the gate node of the transistor

and T1 and T2 represent the end terminals of the transistor, namely source and

drain.

A generalised form of the input file to the block extraction program is as follows:

input_list([/1, /2, ... In]).

output_list([01, 02, ... Omll·

trans(Type, Gate, T1, T2).

The input description consists of a list of primary input nodes to the circuit, 11, 12 .. ln,

a list of primary output nodes of the circuit, 0 1, o2 .. 0m , followed by a list of transis-

tors in the circuit, specified in the format discussed before.

The system at present does not make use of the hierarchical information provided

by a circuit extractor. The input description should be in a flat form. The Magic sys-

tem includes a tool, 'Ext2Sim' which converts the output of the extractor into a non-

hierarchical flat form known as the .sim format.


A transistor in the .sim file is described in the following manner:

type gs d I w x y g=gattr s=sattr d=dattr

For CMOS, the type may be porn. The names of the nodes to which the gate, source

and drain of the transistor are connected are given by g, s and d respectively. The

length and width of the transistor are denoted by I and w. The parameters, x and y

are optional and give the location of a point inside the gate region. The last three to-

kens comprise the attribute lists for the gate, source and drain nodes of the transistor.

If a particular terminal has no associated attributes, its attribute list may be absent.

The attribute lists, gattr, sattr and dattr are comma separated lists of labels.

A program has been written in C to convert the information in a .sim file to a list of

Prolog clauses forming the input to the block extraction program, in the format de-

scribed earlier in this section. This preprocessing program is called sim2pro and

converts a transistor in the .sim format to the following Prolog clause:

trans(type, g, s, d).

In addition, the program searches through the attribute lists of terminals to identify

nodes which are primary inputs and outputs of the circuit. To enable the program to

extract this information, the designer when creating a layout needs to affix the labels

input and output to the layers associated with the input and output nodes.

4.2.1 Node Labelling Convention

The Prolog program treats node names in the circuit as symbolic constants. In the

version of Prolog used, constants begin with lower-case letters and may contain only


alphanumeric characters and the character '_'. This places the requirement that the

circuit description given as an input to the Prolog program have all node names be-

ginning with lower-case letters. The preprocessor sim2pro accomplishes the con-

version of node names from the .sim format to a form compatible with Prolog. A '-' if

occuring within a node name is converted to '_'. Any non-alphanumeric character, in

a node name other than '_' is deleted. If a node name begins with a digit, an 'a' is

appended before the digit. If a node name begins with an upper-case letter, the letter

is made lower-case. For example, the node names PULL_5/3_ 15_51, q2-bar, 12 and

Out in the .sim file are converted into the node names pULL_53_15_51, q2_bar, a12

and out in the Prolog file. The recognition system assumes the global node names,

Vdd and GND to be standardised. They are extracted by sim2pro as vdd and gND.

4.3 Recognition of Inverters and Transmission Gates

As mentioned in the last chapter, inverters and transmission gates can be recognized

directly from their transistor structure. The first step therefore, consists of recognizing

all the inverters and transmission gates in the circuit. The early recognition of

inverters is necessary to identify complementary signals in the circuit. This informa-

tion is useful in later steps when logic expressions are derived at the output nodes

of partitioned blocks.

Inverters are identified by looking for a pair of p and n type transistors having the

same gate input and forming a direct path fron:i vdd to ground. CMOS transmission

gates are recognized by identifying a pair of nodes connected to both p and n type

edges and having complementary gate inputs. The recognized inverters and trans-


mission gates are inserted into the database. The transistors forming these are then

deleted from the database.

4.4 Deriving a Node-Oriented Data Structure

The input to the program containing a list of transistors in the circuit describes the

circuit in the form of an implicit graph. Transistors in the circuit correspond to edges

in the graph. The drain and source terminals of transistors correspond to vertices in

the graph. In order to recognize logic blocks, we need to partition the network de-

scribed by the transistor netlist. The partitioning step converts the network into

smaller subnetworks, the behaviour of which can be derived independently.

Each transistor in the circuit stands for an edge in the circuit graph. The input de-

scription of the circuit is therefore, a list of edges. Prior to the partitioning procedure,

a node-oriented data structure for the graph, consisting of a list of nodes in the circuit

along with the connectivity information for each node is derived. This facilitates par-

titioning.

A node is represented in the following format after processing the transistor list :

node(Nodename, Nodetype, Edge/isl, Gate/isl).

where

Nodename is the name of the node in the circuit.

Nodetype is a variable instantiated in a later step to one of the node categories.

Edgelist is the list of edges incident with the node.

Gate/isl is the list of edges to which the given node is a gate input.


4.5 Node Classification

Preceding the partitioning of the circuit into smaller subcircuits, the nodes in the cir-

cuit are classified into one of the four categories : input, pullup, external and normal.

The terminology has been borrowed from Nmos partitioning techniques. In the case

of CMOS circuits, we proceed to define the classification of nodes as follows:

1. Pullup Nodes: A pullup node is defined as a node which is a drain or source node

of both a p and an n type transistor, in the circuit which results after all transis-

tors forming CMOS transmission gates have been removed. See Figure 8(a). The

need to identify all the transmission gates in the circuit in the first step is evident

here. This definition of pullup nodes is merely intended to enable partitioning. It

does not always conform to the usual notion of a pullup node in a CMOS circuit

as a node connected to vdd via a p block.

2. Input Nodes : An input node is defined as one of the following:

(a) A primary input node in the circuit.

(b) A primary output of the circuit which is not also a pullup node.

(c) A node which is a drain or source node of a transistor, but is not a pullup

node and is connected to an end terminal of a transmission gate. (Figure 8 (b)).

3. External Node : An external node is defined as one of the following:

(a) A node which is connected only to gates of transistors and is an end terminal

of a transmission gate. (Figure 8 (c)).


pul lup node

external node Cc)

Figure 8. Classification of Nodes


~ '1

Cb)

external node

(d)

normal node

Ce)

41

(b) A node which is not a pullup or input node and is connected to the gate of a

transistor. (Figure 8 (d)).

4. Normal Node: A normal node is one which does not fall into any of the categories

above. (Figure 8 (e)).

4.6 Circuit Partitioning

The circuit partitioning technique formulated here is similar to the partitioning meth-

ods used in the pre-simulation phase in switch-level simulators. One such partition-

ing method for Nmos circuits is described in [25]. In a CMOS circuit the broad idea

behind the partitioning procedure is to divide the set of transistors in the circuit into

driver, load and pass transistors. Driver transistors are a group of n type transistors

which could form the n block of a CMOS logic block. Load transistors are a group of

p type transistors which could form the p block of a CMOS logic block. The remaining

transistors are grouped into pass transistor blocks.

Partitioning is accomplished by splitting the circuit graph at boundary nodes. These

boundary nodes consist of vdd, ground, input nodes and pullup nodes. Splitting the

graph at a vertex means dividing the vertex into two or more vertices, so that all the

edges incident with the vertex become mutually disconnected at that vertex.


4.6.1 The Partitioning Procedure

The steps followed in partitioning a circuit are described in this section. We seek

groups of transistors bounded by boundary nodes. The procedure is implemented as

a search starting at a boundary node and terminating at all boundary nodes reachable

from the starting node.

The following symbols are defined :

Ni = set of input nodes

Ne = set of external nodes

NP = set of pullup nodes

Ns=NiU NP

Adj(n) = set of edges incident with the node n.

An edge incident with a node n is represented as [n, t, g, nal• where t is the transistor

type of the transistor corresponding to the edge, g is the gate node of the transistor

and na is the other end node of the edge.

For each node n8 e N8 steps 1 to 4 are followed:

1. Construct the set Adj(n8 ) from the current circuit graph. (The circuit graph

changes during the partitioning procedure because some edges are deleted.)

For each edge Ea e Adj(n8 ), steps 2 to 4 are followed.

Maintain three lists : (1) Pathlist: which will contain the list of edges in the par-

titioned component at the termination of the. partitioning procedure. (2) Nodelist:

to contain the nodes in the partitioned component. and (3) Front: to contain the

edges to be traversed in the partitioning procedure.


2. Initialize Pathlist to [ ], the empty list.

Node/ist to [n5 ].

Front to [Eal·

3. If Front is empty go to 4, otherwise examine the first element E; in Front where

E; = [n;,t. g, n,J

Check for the following cases:

a. If n, = n5 where n5 is the starting node in the search, then we have looped

back. In this case add the edge E; to Pathlist and delete it from the circuit

graph as well as from Front. Go to 3.

b. If n, e {vdd, gND} or n, e N5 , add n5 to Nodelist, add E; to Path list and delete

it from the circuit graph and from Front. Go to 3.

c. If n, e Nodelist, then it is a node previously visited. Check if E; e Pathlist. If

so, delete E; from the Front and go to 3. Otherwise, we have a new path to a

previously visited node. Add E; to Pathlist, delete it from Front and go to 3.

d. If the above cases do not hold, n, is an internal node not visited before. In this

case add n, to Node list. Add E; to Path list and delete it from Front. Next, add

to Front the set of edges Adj(n,) - [n,, t, g, n;]. that is, all the edges incident

with nr except the edge which leads back to the node n; from which we have

moved to n,. Go to 3.

4. When Front becomes empty, the list of edges collected in Pathlist form a parti-

tioned component. The steps below are followed to identify the load, driver or


pass block to which the component belongs. The input and output nodes of the

block are determined.

a. Initialize Inputs to [ ], the empty list. Initialize Outputs to [ ].

b. If Nodelist contains only one pullup node np and includes vdd, but has no

external or input nodes, the component is a load component.

Outputs = [np]

Inputs = set of gate nodes in Pathlist.

If there exists a previously formed load block Ci with list of edges Pi, input

nodes Ii and output np , then remove the block Ci and form a new load block

c, with

list of transistor edges Pr= Pathlist U Pi

inputs 1, =Inputs U Ii

and output o, = [np]

Otherwise assert this component as a new load block.

c. If Nodelist contains only one pullup node np and includes gND, but has no

external or input nodes, the component is a driver component.

Outputs = [np]

Inputs = set of gate nodes in Pathlist.

If there exists a previously formed driver block Ci with list of edges Pi input '

nodes Ii and output np ,then remove the block Ci and form a new driver block

c, with


list of transistor edges Pr= Path/isl UP;

inputs Ir= Inputs U I;

and output Or= [np]

Otherwise assert this component as a new driver block.

d. If Nodelist contains more than one pullup node or has a nonzero number of

input and external nodes, the component is a pass component. Add the set

of gate inputs in Pathlist to Inputs. Add each pullup, input and external node

to both Inputs and Outputs.

If there exists already a pass component C; with list of edges P;, input nodes

I; and output nodes O; and further if

Outputs n O; =I= [ ]

then, remove C; and form a new pass block Cr with:

list of edges Pr= Pathlist UP;

input nodes Ir= Inputs U I;

output nodes Or= Outputs U O; .

Otherwise, assert this component as a new pass block.

4.6.2 A Partitioning Example

Figure 9 shows a CMOS circuit. In the first step, the three inverters (numbered 8, 9

and 12) and the transmission gate (11) are recognized. The sets of input, pullup and

normal nodes are listed below


vdd

n7

nl

rl nS

T

vdd Vdd

n3

J_ r2

y

n9

Figure 9. A CMOS Circuit


?dd ~n4

rl -1~ nl n2 n2 n5

~--L_J~

X~ ( 1 )

,,~O~n· n6 n4

(5)

(2)

n5 -{:>on7

rd (8)

~n2 n6-{:>on8 n8

n3 r2 -11n4 n7~ (9)

y

(3)

,2 ~~>~n2 n9

(10)

(4)

Figure 10. Partitioned Blocks for the Circuit of Figure 9


nS~vdd

T (6)

__l_ nS~vdd

(7)

n8

n6

( 11)

(12)

48

Input nodes: [r1, r2]

Pullup nodes: [n2, n4, n5, n6, n7, n8, n9, y]

Normal nodes: [n1, n3]

There are no external nodes in the circuit.

The partitioning procedure, followed by the classification of blocks yields the blocks

shown in Table 1.

4.7 Derivation of Logical Expressions

Once the partitioning is complete, transistors in the circuit have been grouped into

sets of load, driver and pass blocks. Load and Driver blocks are multi-input-single-

output logic blocks, whereas pass blocks may be multi-input-multi-output logic

blocks. The next step consists of deriving the logical expressions at output nodes of

logic blocks in terms of the inputs to the blocks. The description of this step entails

the use of terminology which is discussed next.

A path between nodes ni and nj in the circuit graph is a connected sequence of tran-

sistor edges with end nodes ni and nj. A path expression is a logic expression which

when true causes the path between ni and nj to become conducting.

A path expression is represented as:

p = [v1 V2 ....••. vnJ ' '


Table 1. Load, Driver and Pass Blocks In the Circuit of Figure 9

Number Block Inputs Outputs

1 Load r1, n4 n2

2 Driver r1, n4 n2

3 Load r2, n2 n4

4 Driver r2, n2 n4

5 Pass n2, n4, n5, n6 n2, n4, n5,n6

6 Load gND n5

7 Load gND n6

10 Pass n7, n8, n9, y nB, n9, y


where each of v1 .... vn is a symbolic constant associated with the gate input of a

transistor in the path. For an n type transistor, vi is the gate input whereas for a p

type transistor vi is the complement of the gate input.

We define an interface node in the partitioned circuit as a node which is either an

input or output node of a logic block. With each interface node n, we associate an

expression set of the form :

En= [n_1,n_O]

where n_ 1 and n_O represent the logical high and low values respectively of the

node n. For vdd and ground the expression sets are defined as:

Evdd = [1,0]

Egnd = [O, 1] .

For a primary input node n,

En= [n, i1].

If we let P(ni,nj) denote the path expression between nodes ni and nj, then:

n n· 1 = ~ Pk(n· n·)n· 1 1- i...J ,, J J-

k=1

n

n· 0 = ~ Pk(n· n·)n· 0 I- i...J I' J j-k=1

where there are n paths between nodes ni and nj and 2: denotes logical OR.


4.7 .1 A Note on the Representation of Boolean Equations

We derive boolean expressions of nodes in the circuit in the sum of products form.

A boolean equation in the sum of products form is represented as a list, each element

of which is a product term. Each product term in turn is in the form of a list of boolean

variables. For example the equation:

abc + abc + abc

is represented as :

[[a, b, C],[a, b, C],[a, b, c]J.

4.7.2 Handling Complements of Boolean Variables

The program treats the node names in the circuit as symbolic constants. The gate

input of a transistor is synonymous with the node name of the gate. In order to han-

dle complements of boolean variables within the program we define a relation:

complement(N, Ne) where Ne is the complement of the boolean variable N, and as-

sumes a value according to one of the following relationships:

1. NC = 1 if N = gND.

2. Ne = 0 if N = vdd.

3. Ne = the output node name of an inverter if the input to the inverter is N.

4. Ne = the input node name of an inverter if the output of the inverter is N.


5. · If N is neither vdd nor gND and is not the input or output of an inverter in the

circuit, then a new constant is generated by the program to stand for the com-

plement of N. In this case, if N is a node name ending in ' _ ', such as a_, Ne is

assigned the constant value which results if the '_'at the end of N is deleted. ff

N does not end in ' _ ', a _ is appended to the constant value represented by N

and Ne is assigned the resultant constant. Thus, if N is a_, Ne is a and if N is a,

Ne is a_. The program treats such node names as complements.

4.7.3 Forming Logic Expressions

A logic expression at an output node of a logic block is formed by tracing paths from

the node to all reachable input signal nodes of the block. A node nj is reachable from

a node n; if there is a path in the circuit graph that connects the two. Nodes that fall

into the category of input signal nodes are vdd, ground and input nodes to the block.

Let n0 be the output node of a logic block and let (n1, ..• , nn) be the input signal nodes

of the logic block, reachable from n0 . Further, let

denote the path expressions which connect n0 to n; .

At each output node of a block, two logic expressions are generated to represent the

logical high and logical low value at that node. The logical expression at n0 is derived

as:


n0 _low can be derived likewise by substituting ni _ 1 with ni _O in the expression

above.

In formal notation :

n k1

n high = '\"' '\"' p .. n· 1 0- L...ii....i ij l-

i=1 }=1

n k;

n low= '\"' '\"' p .. n· 0 0- f....i f....i IJ 1-

i= 1 }=1

In the case of a load block the only input signal node is vdd and

k

n0 _high =LP; }=1

where P; , j = (1 ... k) are the path expressions leading to vdd.

For a driver block the only input signal node is gND. In this case we have :

k

n0 _/ow= LP; }=1

where P1, j = (1 ... k) are the path expressions leading to gND.


[1]

[2]

54

For a pass block the logic expressions at an output node are given by equations [1]

and [2].

4.7 .4 The Path Tracing Procedure

The path tracing procedure is implemented as a depth-first search on the circuit

graph. The starting node in the search is the output node for which the logic ex-

pressions have to be derived. A terminal node in the search is one which is an input

signal node to the block.

The following notation is used in describing the search procedure:

n0 = the output node

n; = node currently being visited in the search procedure.

Npar = set of nodes already visited.

P; = path expression which connects n0 to n;.

N; = set of input signal nodes to the block.

The following rules guide the search:

1. If n; e N;, then it is a terminal node in the search. If [n;_O, n;_ 1 ] is the expression

set associated with n;. then P;.n;_O and P;.n;_ 1 are added to the logic expressions

for n0 _/ow and n0 _high respectively according to rules described in the next

section.

2. If n; is not a terminal node, the nodes adjacent to n; are examined. Let nj be a

node adjacent to n; and let s;j denote the gate signal for the transistor edge be-


tween n; and ni. (s;j is the gate input if the transistor is n type and the complement

of the gate input if the transistor is p type.)

The node ni is visited if the following conditions are met :

a. ni ¢ Npar• that is, it has not been previously visited in the search. (This avoids

loops.)

b. (sij) ¢ P;. This ensures that redundant paths, (those yielding a 0 term) are not

traced.

If node ni is visited, it becomes the current node in the search and the path ex-

pression Pi becomes P;.sij .

4.7 .5 Rules for forming logic expressions

The logic expressions at the output node of a logic block are derived in the sum of

products form. Each path traced from the output node to a reachable input signal

node yields a product term and the OR of all such terms gives the sum of products

form for the expression.

A logic expression at an output node is of the form:

where P; is a product term.


The product terms P; are formed one at a time and are added to the list L using the

following rules :

( Denote L' as the expression list which results after the addition of P; to L.)

1. If L = [],the empty list and P;=I= [],then L' = [ P; ] •

2. If P; = [ ] , a 0 term, then L' L .

3. If there is a term

Pje L

such that

PjcP;.

then L' = L.

For example adding the term [a ,b ,c] to the equation [[a ,b], [d ,e]] does not

change the equation, since a b + d e + a b c = a b + d e .

4. If there are terms

Pj1 .... Pjn e L

such that P;cPj1,

P;cPj2,

P;cPjn.

then L' = L - [Pj1, .. .Pjn ] + [P; ].

For example if :

P; = [a , b]

and L = [[a, b, c ], [a, b, d ]],

then L' = [[a, b]]


because a b + a b c + a b d = a b .

Rules 3 and 4 are intended to simplify the expression. These rules are not exhaustive.

We do not attempt to minimize the derived expression but only reduce the number

of redundant terms. In a later step, we recognise gates in the circuit based on these

derived boolean expressions. The process is one of establishing the functional

equivalence of two sets of boolean expressions and involves proving that the product

of two expressions is zero. This step would take less time if the boolean expressions

were available in their minimal forms. However, deriving the minimal form of a

boolean expression is itself a computationally time consuming problem. As a trade-

off we allow for some redundancy in the expressions.

4.8 Load-Driver logic blocks

A load-driver logic block is formed by combining a load block and a driver block

which have the same output node. In order to derive the logic expressions at the

output node V of a load-driver block, we need to consider all the paths leading from

V to vdd and gND.

We represent the generated logic expressions for a load block output as :

va/ue(V, 1, 11, T1)

and for a driver block output as :

va/ue(V, 0, Id, Td)

where T1 and Td are the derived logic expressions V _ 1 and V _O respectively and

11(/d) are the inputs to the load (driver) block.


A load-driver block is recognized by identifying a pair of clauses as above, which

have the same first argument V, (the same output node) and complementary second

arguments (1 and 0).

Shown in Figure 11 (a) are two load-driver blocks formed from the partitioned blocks

of Figure 9.

Three classes of logic, namely pseudo - NMOS , clocked CMOS and fully comple-

mentary CMOS are recognized. The rules for recognizing the logic category are

listed below:

1. If T1 = [[ 1 ]], the load block consists of a single p type transistor with a grounded

gate, and the logic is pseudo - NMOS. In this case, V_low = Td and V_high =

(Td). The logic expression for the output node V is asserted into the database in

the form:

value( V, I , V _low, V _high )

where I= Id.

2. If there is a boolean variable c present in each product term in Td and its com-

plement c is present in each product term in T1, then we have clocked logic. In

this case c is removed from each product term in Td to get Td1 and c from each

product term in T1 to get T11 . The logic expression at the output node V is asserted

as:

value( V , clocked , c , I , V _low , V _high )

where I= Id- [c], V _low= Td1 and V _high= T11 .


vdd vdd

~n4 ~n2

rl--4 n2

r2-4 n4

r~ ~ n4 r2~ ~2

(a)

vdd

hrl n5 n6

n2 n4

( b)

Figure 11. Examples of Load-Driver and Pass Blocks


3. If 11 =Id, we consider the logic to be fully complementary. In this case

V _low= Td and V _high = T1. The logic expression at V is represented as:

value( V , I , V _low, V _high )

where I= Id.

In case 1 above, the complement of a boolean expression has to be derived. The

program has the capability to find the complements of boolean expressions. The

procedure however, is exponential in time complexity with the number of variables

in the expression to be complemented. This means that load-driver blocks with a

large number of inputs would restrict the program speed.

4.9 Pass and Transmission Blocks

Transmission gates and pass blocks in the circuit have nodes which have been la-

belled as both inputs as well as outputs of these blocks. Such nodes are denoted as

io nodes. After all the load-driver logic blocks have been identified, there is a pos-

sibility that unpaired load and driver blocks remain in the circuit. As an example

consider Figure 9. The load blocks numbered 6 and 7 in Figure 10 remain unpaired

after load-driver blocks are formed. Such unpaired load or driver blocks are consid-

ered as pass blocks. They are merged with other pass blocks according to the fol-

lowing rule.

If the output node of an unpaired load or driver block is v, and there exists a pass

block such that v is an io node of this pass block, then the load or driver block is

merged with this pass block.


In the example of Figure 9 the load blocks 6 and 7 are merged with the pass block 5

to form the block shown in Figure 11 (b).

Nodes which are labelled as io nodes of pass blocks and transmission gates have to

be resolved as either input or output nodes of these blocks and gates. We do this

by tracing the fan-in and fan-out of nodes which form the interface nodes between

blocks.

The following rules are useful in resolving io nodes as either input or output nodes.

1. If a primary input to the circuit is an io node of a transmission gate, it is consid-

ered as the input node of the transmission gate and the other end node of the

transmission gate becomes its output node.

2. If a primary input to the circuit is an io node of a pass block, it is removed from

the list of output nodes of the pass block.

3. If the output of a load-driver logic block is an io node N1 of a transmission gate

and the other end node N2 of the transmission gate is an input node (but not an

io node) of some other block, then N1 is considered the input and N2 the output

of the transmission gate.

4. If the output node of a load-driver block is an io node of a pass block it is removed

from the list of output nodes of the pass block.

5. If an io node of a transmission gate is an input (but not an io node) of another

block, it is considered the output node of the transmission gate and the other end

node of the transmission gate becomes its input.


After steps 1 to 5 above have been carried out for every pass block in the circuit

having an input list I and an output list 0, the new input list I' is set to be equal to I -

0. In this way all the nodes which have been resolved as output nodes of a pass

block are removed from the list of its input nodes.

The rules stated above may not resolve the directionality of a transmission gate in

all possible cases. Further, these rules are of an empirical nature and may have ex-

ceptions. In particular, the case where the output of one pass block is an input to

another pass block, the two pass blocks may be considered as one large pass block

by the program. This could cause the logic not to be recognized.

In the case where the directionality of a transmission gate is unresolved, it is left as

bidirectional.

The logic expressions at output nodes of pass blocks are derived according to the

path tracing procedure described earlier. Shown in Figure 12 is the tally circuit from

[27] with the depletion mode load transistors replaced by p transistors with gates

connected to ground, to give pseudo Nmos logic. The logic expressions generated for

the output nodes are shown in Figure 13. Notice, that in the case of the output node

zO, the logic expression is recognized as the nor of the inputs x1, x2 and x3, by the

gate recognition procedure to be described in the next chapter. For the other three

output nodes, the system could not find equivalent gate functions in the data base.

The gate names for these logic expressions are left unassigned as shown.

In the next chapter we consider the recognition of gates and functional blocks in the

partitioned circuit.


Vdd

Figure 12. Tally Circuit


GATl1 inverter input xl output xl_bar

GAT11 inverter input x2 output x2_bar

GATI: inverter input x3 output x3_bar

output_node: z3 inputa1 [x3, x2, xl] V_hiqh.: [[xl, x2, x3]] V low: [[X3 bar], [xl bar, x2, x3], (x2_bar, x3]] ***** - -GATI: 4606 input [x3, x2, xl] outp~ z3

output_node: z2 inputs: [x3, x2, xl] V hiqh: [[xl bar, x2, x3], [xl, x2, x3 bar], [xl, x2 bar, x3]] v:1ow: [[xl,-x2, X3], [x2_bar, x3_bar]~ [xl_bar~ x2,-x3_bar], [xl_bar, x2_bar, x3]J ***** GATI: 4606 input [x3, x2, xl] output z2

output_node: zl inputa: [x3, x2, xl] V_hiqh: ([xl_bar, x2_bar, xJ], [xl, x2 bar, x3 bar], (xl bar, x2, x3 bar]] V_low: [[x2, x3], [xl, x2, xJ_bar], [xl_bar, x2_bar, x3_bar], (xl, x2_bar, x3]] ***** GATI: 4606 input [x3, x2, xl] output zl

GATI: nor3 input [x3, x2, xl] output zo

Figure 13. Logic Expressions Generated for the Tally Circuit


Chapter V


In the last chapter, the partitioning of a circuit into subcircuits and the extraction of

logic expressions at output nodes of subcircuits was described. In the next step, an

attempt is made to recognize the logic implied by a derived boolean expression. In

order to do so, we maintain a library of rules for correlating the derived expressions

with defined gates.

The term gate as used here implies a collection of transistors with one or more inputs

and only one output. Each gate defined in the library has an associated set of attri-

butes. These attributes include the name by which the gate is referred to in the pro-

gram, the inputs and output of the gate and two boolean equations which express the

logical high and logical low values at the gate output in terms of the inputs. An addi-

tional attribute may be present describing the gate as being clocked, in which case

the clock signal would also be specified.

The reference boolean equations associated with a gate are in terms of Prolog vari-

ables. (In the version of Prolog used, variables begin with upper-case letters. Vari-

Recognition of Logic Blocks 66

ables may be instantiated to constants which begin with lower-case letters.) The

derived expressions at the output node of a logic block are in terms of Prolog con-

stants. These constants are, in effect, the node names of the inputs to the logic block.

As an illustration, the logic at the output node y of a block implementing the exor

function and having inputs a and b is represented as:

value(y, [a , b], [(a_, b_],(a, b]], [[a_, b],(a, b_]]).

where the format is :

value(Output, Inputs, Low_expression, High_expression).

In the example above, the boolean variables: a, a_, b, and b_ are all constants. In the

program database, a two i.nput exor gate may be defined using the following attri-

butes:

gatename : exor2

Inputs : [A, B]

High expression : [[A_ ,B],[A, B_]]

Low expression : [[A_, B_],[A, B]]

where A and B are Prolog variables representing the two inputs to the exor gate. The

variables A_ and B_ would be related within the rule to A and B by the clauses below:

complement(A, A_).

and complement(B, B_).

The identification of a gate in the circuit becomes a problem of finding a corre-

spondence between an extracted logic expression set- (v_low, v_high) for an output

node v and a gate in the library with an associated set of iogic expressions. In order

to do so, the definitions in the library of n input gates are examined, where n is the

number of inputs in the expressions for the output v. An equivalence is sought to be


established between the derived logic expression set and the reference logic ex-

pression set of an n input gate in the library. The next section expands this notion.

5.1 Recognition of Gates through Logical Equivalence

In order to recognize the gate represented by a boolean equation we need to match

a reference equation with a derived equation. Consider the two boolean equations:

F(x) = f(x1, x2, ..... xn) and G(x) = g(x1, x2, ..... xn)·

where x1 ... xn represent primary input variables.

We make use of the following equivalence relationship:

F(x) and G(x) represent the same boolean function if:

F(x)G(x) + F(x)G(x) = O

Or in other words

F(x)G(X) = 0 and

F(x)G(x) = 0.

The above equations imply that if F(x) = 1, then G(x) = 1 and if G(x) = 1 then

F(x) = 1. This in turn implies that the truth tables for the two functions match. The

stated equivalence is valid however, only in the case when the truth tables for F and

G contain no 'don't cares' in the output column. The presence of don't cares leaves

the function incompletely specified . In that case there would be a likelihood of the

function being recognized wrongly. This is a restriction on the method.

The equivalence relationship described above is applied in the recognition proce-

dure. Assume that in the gate library we have a gate 'f' defined by the boolean ex-


pressions f_O and f_ 1 which represent the logical low and high values respectively

of the gate output. An extracted expression 'g' represents gate 'f' if:

f_O*g_1=0 (1)

and f_ 1 " g_O = 0 ( 2 )

As stated before, the boolean expressions describing a gate in the library are in

terms of Prolog variables. Before we can attempt an equivalence through Equations

1 and 2, these variables have to be instantiated to symbolic constants in the logic

expression which we wish to recognize.

As an illustration, the exor gate in the last section uses the Prolog variables A and

B. The derived expression is in terms of Prolog constants a and b. A one to one as-

signment from the set {a, b} to the set {A, B} has to be made. In this case, since the

inputs to an exor are symmetric, either of the assignments (A = a, B = b) or (A =

b, B = a) would prove or disprove the equivalence. In the general case we have a

derived expression which is in terms of the n constants (a1, a2, ... an)· The boolean

expressions for n input gates in the library are in terms of the n variables

(A1, A2, .... An)· We seek a one-one assignment of the set {a1, ... an} to the set

{A1, .... An}· There are n ! such assignments. This means that in the worst case there

will be n I steps to prove equivalence before an equivalence test fails. As the number

of gate inputs grows, the process of recognition becomes more time consuming.

However, it is to be noted that the definition of a 'gate' as applied here refers to a

partitioned block within a larger circuit. We can expect that the number of inputs n to

a partitioned block would, barring exceptional cases, be a small value. Further, for a

large class of gates, we can put the symmetricity or interchangeability of inputs to


advantage here. If p of the n gate inputs are interchangeable, then effectively, the

number of assignments in the discussion above reduces to ;:

5.1.1 An Example

For the circuit block shown in Figure 14 (a), the following expressions are derived for

the output node y:

y_high = ac +"be

y_low= ab+ c

The gate level circuit for this block is shown in Figure 14 (b). We assign the name

'and2_nor' to this composite of a 2 input and gate and a 2 input nor gate. The defi-

nition of an and2_nor would have the attributes:

Inputs: [A, 8, CJ

Output: [Y]

Y_high: AC+ BC

Y low : AB + C.

In the recognition process, an assignment of the set {a, b, c} to the set {A, B, C} has

to be made. The inputs a and b are interchangeable. There are three possible as-

signments for c, namely A = c, B = c and C = c. The last assignment C = c would

lead to the equivalence being established.


vdd

c y

(a)

y

Cb)

Figure 14. An Example of a Composite Gate: Shown in (b) is the gate level circuit for the circuit in (a).


5.2 A Rule for Establishing Equivalence

In Equations 1 and 2, we attempt to prove that the product of two boolean equations

is zero. In other words if E1 and E2 are two boolean equations we need a means to

test for the truth of the following statement:

E1 x E2 = 0 ( 3)

Both E1 and E2 are in the sum-of-products form and can be expressed as :

and

where Ti (i = 1 .. n) and Uj (j = 1 .. m ) are the product terms.

The product E1 x E2 is zero only in the case when each of the products of the form

Tix Uj is equal to zero.

A rule for testing whether Equation 3 holds can be written as follows :

E1 x E2 = 0 if for every pair of product terms Tix Uj (i = 1 .. n, j = 1 .. m ), there

is a boolean variable x e Ti such that the complement of x, x e Uj.

The test for equivalence fails at the very first instance of a pair of product terms

Tix Uj for which the above rule is not satisfied. This is useful when we consider the


fact that there may be a number of n input gates defined in the library and a recog-

nition step may involve searching through these gates. The early elimination of in-

correct gates in the search procedure is desirable.

In the worst case m x n steps are followed if Equation 3 is not satisfied. When

Equation 3 is satisfied, exactly m x n instances of the rule have been invoked.

The method described above can be used to recognize all the logic blocks in a circuit

for which corresponding gates exist in the gate library. In this approach we recognize

a gate by the logic it implements rather than by the topology as is done in previous

gate recognition programs which use graphical techniques. This is an advantage be-

cause different implementations of the same gate can be recognized without having

to store knowledge of all the different forms.

5.3 Recognition of Functional Blocks

Once all the gates have been recognized, the program proceeds to recognize all the

functional blocks which may be composed of these gates. At this level, recognition

is through the connectivity of the basic gates. We do not attempt to derive the

behaviour of higher level logic blocks.

The descriptions of functional blocks used in a design are present in the program

database in the form of rules. A functional block is defined in rule form in terms of the

gates it contains and their interconnections. More than one description of the same

function is possible.


vdd

a vdd

b

y

(a)

c

b==D--b~:__-=c;sv 0 y

(b)

Figure 15. A CMOS Exclusive-Or Circuit


In Prolog terms, a functional block is defined as a set of clauses. Figure 15 shows

one version of a CMOS exor gate. The gate recognition procedure would identify two

separate gates: a 2 input nor and the and2_nor of the previous section. To recognize

the combination as an exor, we could have a rule in the library as follows:

function(exorgate, [[inputs A, B], [output Y]]):-

and2_norgate(A, B, C, Y),

norgate_2(A, B, C),

assert(exorgate(A, B, Y)).

This is only one possible definition of an exor gate. Figure 16 shows another version

of an exor called a transmission-gate exor. In this case, the gate if occuring in a larger

circuit forms a pass block after the partitioning stage. The logic at the output node y

wou Id be derived as :

value(y, [a,b], [[a_,b_],[a,b]], [[a_,b],[a,b_]]).

By the gate recognition procedure described earlier, this block would be recognized

as an exor.


vdd

a

gnd b

y a exor b

Figure 16. A Transmission-Gate Exclusive-Or Circuit


In Chapter 2, the structural description of a transmission gate adder was stated as a

Prolog rule. The following rule for a functional block describes another form of a

full-adder which is shown in Figure 17.

fu nction(fu I l_adder,[[i nputs,A, B,Ci n],[su m,Su m],[ carryout,Cout]]):-

exorgate(A, B,S 1 ),

exorgate(S 1,Cin,Sum),

nandgate_2(A,B,S2),

nandgate_2(A,Cin,S3),

nandgate_2(B,Cin,S4),

nandgate_3(S2,S3,S4,Cout).

The recognition of a functional block is equivalent to satisfying a goal subject to the

constraints specified in the rules for that block. In the case above, this particular

full-adder is found in the designed circuit if all the gates that compose it are found

and are interconnected in the manner specified in the rule.

The recognition process involves a search in the database, for components which are

specified in the description of a functional block. A functional block may be described

both in terms of basic gates as well as other functional blocks. For instance, the

multiplier cell of Figure 18 uses the full-adder of Figure 17 and d flip-flops of the kind

shown in Figure 19 and is described as follows:

fu nction(mu lt_cell,[[inputs,M 1,M2,Pin,Rb],[clocks,Clk 1,Clk2],

[outputs,M 1 out,Pout]]):-

dffr(M 1 ,Rb,Clk1 ,M1out,Q1 b),

dffr(Pin,Rb,Clk2,S4,Q2b),

dffr(Cout,Rb,Clk2,S5,Q3b),


exor a 0--

~r b 0 s Cin

nand2

nand2 nand3

o---° Cout

nand2

Figure 17. A Full-Adder Circuit


d flip-flop

ml 0---------tD

Cl k 1 o--.r-------1Clk

Xl~---iCik

INV

R nii.nd2

d flip-flop

PlnG----------+------iD

Clk2 Clk

XJ--+-....--t---1 Cik R

INV

INV

d fl Ip-flop

rb

D

'-----+--+----! Clk

'-----+---t----1 Cik

Figure 18. A Multiplier Circuit


01------'

R

full adder Pout

a

Cin Cout

79

reset

Clk Clk

d a

Clk Clk

Clk Clk

a

Clk Clk

Figure 19. D Flip-Flop Circuit with Reset


nandgate_2(M 1 out,M2,S2),

inv(S2,S3),

fu I l_adder(S3,S4,S5, Pout,Cout).

The gates and functional blocks recognized from the transistor level description of the

multiplier circuit are shown in Figure 20.

The search during the recognition of a functional block is successful when the last

clause in its rule is satisfied. In other words a block is recognized when the last

component contained in its structural description is identified in the given circuit.

A clause in the rule for a functional block is constrained by the node interconnection

assignments made in previous clauses in the rule. If the search procedure in the

recognition of a particular block fails, all the node interconnection assignments done

prior to the step at which failure occurs must be undone and alternative assignments

explored. The advantage of automatic backtracking is realized here. The procedure

seeks all the possible alternatives in terms of the component interconnections to

satisfy the recognition rule. If the rule fails completely, an instance of that particular

functional block does not exist in the circuit and all node assignments are undone.

5.4 The Specification of Rules for Gates and Functional Blocks

In the program database a library of gates and functional blocks is maintained. Rules

describing new gates and functional blocks can be added to the library.


GATE: transmission input ml output dtll 9ate_inputs clklb clkl

GATE: transmission input pin output df2l 9ate_inputs clk2b clk2

GATE: transmission input dtl3 output dfll 9ate_inputs clkl clklb

GATE: transmission input df23 output df2l 9ate_inputs clk2 clk2b

GATE: transmission input df33 output df3l 9ata_inputs clk2 clk2b

GATE: transmission input cout output df3l 9ate_inputs clk2b clk2

GATE: transmission input df3qb output df34 9ate_inputs clk2b clk2

GATE: transmission input df32 output df34 9ate_inputs clk2 clk2b

GATE: transmission input df2qb output df24 9ate_inputs clk2b clk2

GATE: transmission input df22 output df24 9ate_inputs clk2 clk2b

GATE: transmission input df lqb output dfl4 9ate_inputs clklb clkl

GATE: transmission input dtl2 output dtl4 9ate_inputs clkl clklb

GATE: inverter input clkl output clklb

GATE: inverter input s2 output s3

GATE: inverter input clk2 output clk2b

GATE: inverter input dtl2 output dtl3

GATE: inverter input df 14 output mlout

GATE: inverter input df22 output df23

GATE: inverter input df24 output s4

GATE: inverter input df32 output df33

GATE: inverter input df34 output s5

GATE: nand2 input (s5, s4) output ad4


GATE: nand3 input (ad4, ad3, ad2) output cout


GATE: and2 nor input [x22~ s5, adl] output pout

GATE: and2 nor input (xl2~ s4, s3) output adl

GATE: nor2 input [adl, s5J output x22

GATE: nor2 input [&3, &4) output xl2

GATE: nand2 input [rb, s5) output df 3qb

GATE: nand2 input (df3l, rbJ output df32

GATE: nand2 input [rb, s4J output df2qb

GATE: nand2 input [df2l, rbJ output df22

GATE: nand2 input [m2, mlout] output s2

GATE: nand2 input [rb, mlout] output dflqb

GATE: nand2 input [dfll, rb] output dfl2

GATE: and2 input (df3l, rbJ output df33

GATE: and2 input [df2l, rb] output df23

GATE: and2 input [m2, mlout] output s3

GATE: and2 input [dfll, rb] output dfl3

Figure 20. Gates and Blocks Recognized in the Multiplier Circuit


Function: exorgate inputs s5 adl output pout

***** Function: exorgata inputa s4 s3 output adl

***** Function: exor9ate inputa adl a5 output pout

***** Function: exor9ate inputs a3 a4 output adl

***** Function: full adder inputs s4 s3 ss sum pout carryout cout

***** Function: full adder inputs s3 s4 ss sum pout carryout cout

***** Function: dffr input cout reset_input rb outputs s5 df3qb clock clk2

***** Function: dffr input pin reset_input rb outputs s4 df2qb clock clk2

***** Function: dffr input ml reset_input rb outputs mlout dflqb clock clkl

***** Function: mult cell inputs ml m2 pin rb clocks clkl clk2 outputs mlout pout

•••••

82

The description of gates is in a behavioural form. The gates are grouped in the library

by the number of inputs they have. The description of functional blocks is in a struc-

tural form. When automatically recognizing gates and functional blocks in a circuit,

the program first attempts to find a corresponding gate in the database for each de-

rived logic expression set. After the recognition of gates, the program checks for the

possible invocations within the circuit, of each functional block defined in the data-

base. Each recognised instance of a functional block is then asserted as a clause in

the database.

The recognition of functional blocks proceeds sequentially according to the order in

which rules for functional blocks appear in the database. A functional block may be

composed of other lower level functional blocks. For recognition to proceed correctly,

a block which is a component of another functional block should be defined before

the latter. For this reason the order in which rules for functional blocks appear in the

database should be such that lower complexity blocks are defined before higher

complexity blocks.

The order in which the input and output nodes are listed within the attributes for a

functional block is important. In particular if two or more of the inputs of a functional

block are interchangeable, through backtracking, the program may report more than

one instance of the same functional block with the same set of inputs but a different

order. For example, the output generated for the multiplier circuit of Figure 18 shows

two instances of the same full adder with the order of inputs changed.


Chapter VI

Conclusions

In this thesis an approach has been outlined for translating a physical description of

a CMOS circuit which is in terms of transistor interconnections, to a logic level de-

scription which is in terms of interconnections of logic functional blocks. The de-

scribed system operates on a circuit to produce a list of gates and logic blocks in the

circuit along with their input and output terminals.

The system is an aid in checking the physical design of a circuit against the intended

logic level description. It facilitates the task of network comparison by translating it

to a higher level in the circuit hierarchy. Rules describing the logic blocks used in a

design should be present in the program database. If an instance of each logic block

present in the original design is found in the circuit by the circuit recognition proce-

dure, and the recognized blocks are interconnected correctly, the physical design can

be assumed to be logically correct.

The system can also be used to check for the presence of a particular circuit block

in the designed circuit. In this case, the structural description of the circuit block is

Conclusions 84

provided and contains actual node names in the circuit. The program then checks for

a specific circuit block with the given input and output terminals. If the node names

in the description of the circuit block are left as variables, the program would check

for all invocations of that block within the design.

Since the system extracts logic expressions at output nodes of blocks, it has a further

application. It can be used to verify the logical behaviour of a cell which is composed

of a single load-driver block or a pass block. In this case, the cell is described in

terms of the boolean equations at its output nodes. Using the equivalence rule de-

scribed earlier, the program can be made to check for an equivalence between the

extracted boolean expressions and the reference expressions.

Lastly, the system can be used to arrive at logical expressions at output nodes of

blocks in the circuit.

6.1 A Discussion of Results

Apart from the C preprocessor, which consists of 200 lines of code and converts a file

in the .sim format to a list of Prolog clauses, the work done in this thesis can broadly

be divided into three stages which are relatively independent of each other. The first

stage is the circuit partitioning stage, in which a CMOS circuit is partitioned into

smaller subcircuits. The second stage consists of extracting logic expressions at

output nodes of circuit blocks. In the third stage circuit recognition rules are used to

identify logic blocks within a circuit. The program consists of about 2300 lines of

Prolog code and has been implemented in the dialect of Prolog known as the

Conclusions 85

Edinburgh syntax, on the MV/10000 Data General computer running under the

AOS-VS operating system.

Major concerns in a system of this kind would be the size of the circuit handled and

the run time of the program. Logic blocks in a number of circuits were recognized

using the approach described in this thesis. Sample results for three different circuits

are shown in Table 2.

It should be mentioned at this point that the program run time contains a factor which

is dependent on the computer system used. The implementation of Prolog on the

system which was used here is not the most efficient one. Prolog runs on this system

through a Pascal interpreter. The first two stages of the program described in this

thesis involve partitioning a circuit into smaller blocks followed by the extraction of

logic expressions at the output nodes of these blocks. The computation involved is

purely of a symbolic nature. Hence, Prolog was considered a suitable language for

this purpose. In the absence of a Prolog compiler, the program runs on an interpreter.

This could be a disadvantage with regard to the run time of the program. The third

stage of the program involves circuit recognition based on rules. This stage makes

use of the symbolic features of Prolog and would be difficult to carry out in a language

such as Pascal or C.

The run times in the examples above should be viewed with the above discussion in

mind. Conceivably, the run times would be much lower using a more efficient imple-

mentation of Prolog.

Conclusions 86

Table 2. Sample Run Times

Circuit Circuit 1 Circuit 2 Circuit 3

number of transistors 9 22 108

number of nodes 8 14 61

number of gates and blocks extracted 4 9 47

CPU time in seconds 7.4 22 134

Conclusions 87

The run time is also dependent on the size of the program database. As more rules

for recognising logic blocks are added to the database, the time taken to recognize

a logic block increases.

It is not possible to give a simple measure of the time complexity of the recognition

procedure because backtracking is involved. There is a restriction on the size of

gates which can be recognized. This restriction arises from the fact that the number

of input assignments to be considered in a gate is nl where n is the number of gate

inputs. (Refer the discussion on page 69.) The recognition time is dependent not only

on the size of the circuit, that is the number of transistors present within the circuit,

but also on the complexity of gates and logic blocks in the circuit. A large circuit with

a number of simple gates (having a small number of inputs) would take proportionally

less time than a smaller circuit containing a few complex gates (having a large num-

ber of inputs).

The time taken to recognize functional blocks depends to some degree on the way

the rules for functional blocks are framed. In recognizing blocks in a circuit, the pro-

gram attempts to find instances of each block, the rules for which are stated in the

database. A block is not reported in a circuit if the constraints specified in its rules

are not met. A rule for a functional block is a structural description of the block, con-

sisting of a sequence of clauses, each of which represents a component within the

block. The failure of a rule can occur at any stage in the sequence of clauses. Ideally,

if a block is not going to be reported in a circuit, we would want the rule for that block

to fail as early as possible. The sequence in whi~h the clauses within a rule are listed

affects the recognition time. Clauses with a higher likelihood of failure should occur

earlier in the sequence. Since clauses represent components in the circuit, the like-

Conclusions 88

Ii hood of failure of a clause is related to the probability of occurrence of a component

within a circuit. For instance, one could say that, in general, a large circuit would

contain more inverters than full-adders or D flip-flops. If there is a choice, the rule for

the multiplier-cell stated in Chapter S should take precedence over the following rule

for the same circuit even though both are correct.

function(mult_cell, [[inputs, M 1, M2, Pin, Rb],

[clocks, Clk1, Clk2], [outputs, M1out, Pout]]):-

inv(S2, S3),

nandgate_2(M 1 out, M2, S2),

dffr(M1, Rb, Clk1, M1out, Q1b),

dffr(Pin, Rb, Clk2, S4, Q2B),

dffr(Cout, Rb, Clk2, SS, Q3b),

full_adder(S3, S4, SS, Pout, Cout),

assert( multiplier _cell(M 1,M2,Pin,Rb,Clk1,Clk2,M1 out, Pout).

6.2 Extensions to the Work Done

As mentioned in earlier chapters, the final aim behind a translation of the level of

description of a circuit from a lower to a higher level is to enable the derivation of an

algorithmic description of the behaviour of a network from its mask-level layout de-

scription. The recognition of transistors from a layout description, as performed by

a circuit extractor is the first step in raising the level of description of a circuit. The

recognition of gates and functional blocks is a further step in that direction.

Possible extensions to the block recognition system are mentioned below.

Conclusions 89

1. Connectivity comparison at a higher level: If a reference description of the circuit

is provided in the form of an interconnection of gates and logic blocks, it can be

compared with the extracted list of gates and logic blocks to check for the cor-

rectness of the circuit. The present recognition procedure reports the presence

or absence of blocks within a circuit. It does not have the ability to report dis-

crepancies between a reference circuit description and the extracted block level

description.

2. Simulation at a higher level: The recognition of logic blocks could enable sym-

bolic or logic simulation at the functional block level.

3. Extraction of higher level behaviour: Given an interconnection of logic blocks in

a circuit, an attempt could be made to derive the behavioural description of the

circuit. For this purpose, the behaviour of each functional block would be stored

in a suitable format. The behaviour of the circuit would then be extracted from the

behaviour of its components and a description of their interconnection.

4. Exploitation of circuit hierarchy: The block recognition approach at present does

not take advantage of the circuit hierarchy in the layout description of a circuit.

A circuit may contain several instances of the same subcircuit which could arise

out of repeated calls to a subcell during the creation of the layout. A possible

extension within the system would be the incorporation of the ability to recognize

repeated logic blocks only once during the recognition procedure.

Conclusions 90

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