Reconfigurable Computing

Josh Bilger, Richard Collins

What is it?Reconfigurable computing is the idea that

you can change the hardware to suit a more specific task than the generic

implementation that presently exists to increase performance.

What makes it useful?Drastic improvements to speed and flexibility

within hardware allow for smaller, faster, better suited, and easier to upgrade

machines

Why dont we use it?Due in large part to reverse compatibility

there doesnt currently exist a good way to implement reconfigurable computing without

forcing the re-write of all programs that presently exist.

Solution One:Suck it up

By re-writing the code, we can quickly eliminate old tech

and move foward.

Solution Two:New tech

Create a whole new type of machine that only runs

reconfigurable code

Solution Three:Hybrid

A new machine that can run old code but is optimized to run new code that changes

hardware during runtime

Proposed Idea:Annotations talk to

translators and compilers that decide

when and how to reconfigure hardware

Pre-configured Place and Route, size,

I/O Requirements

Old Code:

Old code has a default annotations

associated with every file / method

etc.

XP

Our Examples:

Bottom up:Radio Communication Technology

Top down:Automatic Message Dissemination

Reconfigurable Hardware Based Radio Expands on Software Defined Radio (SDR)

Increases Real-Time System development at lower costs Latency between Target Hardware and Host Computer less of an issue Target CPU/FPGA combo can be smaller Standardized Reference Cores vs. Custom Designs each time

Push computationally intensive functions into target HW Already done with expensive LabView and Simulink Packages, but Introduce core-mgmt. and context switching Design your own cores! Start with the dwarfs!

Current Design Methodologies:

Generic Control-System Design with HIL Real-Time Controller

Current Design Methodologies:SDR Tool Chain: NI Lab-View

Current Design Methodologies:SDR Tool Chain: MathWorks

MATLAB and Simulink + Xilinx

Current Design Methodologies:SDR Tool Chain: GNURadio,

Companion

Were already halfway there!Only missing:

Dynamic Reconfigurability

Optimal Coregeneration orselection fromdesign constraints

Example Use Case Multi-User MIMO:

Adaptive Beamforming for Space Division Multiple Access (SDMA) Calculate Direction of Arrival (DoA)

(Computationally Intense, Array Processing) Use with known distance to cell tower (GSM, Timing Advance) Create High-Efficiency Digital Filters on the fly when moving

between co-channel cells. (Parks-McClellan Algorithm on large temporary FPGA core)

Do this on Cell Phone to improve network throughput on same frequency bands

Functional Hierarchy EE Designs FPGA Material Computer Engineer designs Reference Cores

Versions based on: Size, Latency, Throughput, I/O constraints Custom ISA

Software Engineer implements them in dynamic code that chooses best option given current RCPU usage/state/availability

Cores Managed similar to Multiprocessing: Context Switching (Swapping cores, saving machine states)

Task Control Blocks Resource Management (Scheduling, Semaphores)

Most Problems already solved for other purposes? ISA, Drivers, Shared Memory, Heterogenous System Architecture (HSA)

Feasibility?Sure!

Still Needed: Simpler / Unified / Open-Source Toolchain(s) Functional Mapping:

Common Functions / Algorithms to Standardized Reference Cores Reference Cores to varied FPGAs Performance Gains from Implementation

Dynamic Core Management & Interface Standards !!! Security Concerns Addressed

Process-snooping HW through use of emergent EM properties

Reconfigurable Message Sending Software

Presently a message comes in and goes out.

While this seems efficient, reconfigurable computing could allow

this to be so much more efficient.

Information disseminationCurrent Methods:Get informationSend information

Take for example:Decide message communication path, decide message type (all presently done) and send while passing through significantly less gates

Design Principles for Modern Computers

1) Instructions executed directly in HW Reduction of repetitive code (microcode in SW)

but for higher-order operations (MAC, Convolution, Transforms, etc.)2) Maximize rate of Instruction Issuance

Parallelizability maximally taken advantage of If propagation delay too high, add more cores, stagger issuance assuming

no dependencies: do this until rate of instruction issuance meets clock rate3) Instructions should be easy to decode

Change point of view from Load-Store Arch to Stream/VectorProcessing Instructions can be assigned to cores as needed, and removed as well Fallback to default RISC CPU & ISA if custom core not available

Design Principles forModern Computers

4) Only Load/Store Access to Main Mem No processing directly in Main Mem, no problem HSA allows for virtual memory mapping between cpu and cores via PCI-e bus

(& AXI ? or any high-speed interconnect)5) Provide Plenty of Registers

Registers can be loaded and removed just as easily as processing cores When Context Switching between cores dynamically,

Many registers needed to load/store (pipelined) machine states anyway

Other Computing Architecture Concepts Pipelining HW/SW Logically Equivalent

Take Operating System fundamentals to manage new HW Context Switching & Core (CPU) Condition Registers Resource Contention & Deadlock Avoidance Scheduling of Core Loading/Unloading (during IO-Bound or CPU-Bound

tasks?) REGEX ASM HW

Amdahls Law

Conclusions:The fact that the technology isnt in wide use despite clear

benefits proves the challenges faced with using this technology. However using a combination of a new layer

of translation and a new type of software-hardware engineer hybrid, we feel the challenges can not only be overcome, but eventually phase out old code long term

and become a new standard. By hybridizing the technologies we allow the transition to be gradual and not

cause any major hiccups. That is presently the largest obstacle.

QuestionsIn what ways does reconfigurable computing already exist?

Name one proposed solution for implementing reconfigurable computing

What is the @ symbol be used for in our proposed method?