ReconfigurableComputingDavidBoland1,Chung-KuanCheng2,AndrewB.Kahng2,PhilipH.W.Leong1

1SchoolofElectricalandInformationEngineering,TheUniversityofSydney,Australia20062Dept.ofComputerScienceandEngineering,UniversityofCalifornia,LaJolla,California

Abstract:

Reconfigurablecomputingistheapplicationofadaptablefabricstosolvecomputationalproblems,often

takingadvantageoftheflexibilityavailabletoproduceproblem-specificarchitecturesthatachievehigh

performancebecauseofcustomization.Reconfigurablecomputinghasbeensuccessfullyappliedto

fieldsasdiverseasdigitalsignalprocessing,cryptography,bioinformatics,logicemulation,CADtool

acceleration,scientificcomputing,andrapidprototyping.

AlthoughEstrin-firstproposedtheideaofareconfigurablesystemintheformofafixedplusvariable

structurecomputerin1960[1]ithasonlybeeninrecentyearsthatreconfigurablefabrics,intheformof

field-programmablegatearrays(FPGAs),havereachedsufficientdensitytomakethemacompelling

implementationplatformforhighperformanceapplicationsandembeddedsystems.Inthisarticle,

intendedforthenon-specialist,wedescribesomeofthebasicconcepts,toolsandarchitectures

associatedwithreconfigurablecomputing.

Keywords:

reconfigurablecomputing;adaptablefabrics;applicationintegratedcircuits;fieldprogrammablegate

arrays(FPGAs);systemarchitecture;runtime

1Introduction

Althoughreconfigurablefabricscaninprinciplebeconstructedfromanytypeoftechnology,inpractice,

mostcontemporarydesignsaremadeusingcommercialfieldprogrammablegatearrays(FPGAs).An

FPGAisanintegratedcircuitcontaininganarrayoflogicgatesinwhichtheconnectionscanbe

configuredbydownloadingabitstreamtoitsmemory.FPGAscanalsobeembeddedinintegrated

circuitsasintellectualpropertycores.Moredetailedsurveysonreconfigurablecomputingareavailable

intheliterature[2-6].

Microprocessorsofferaneasy-to-use,powerfulandflexibleimplementationmediumfordigital

systems.Theirutilityincomputingapplicationsmakesthemanoverwhelmingfirstchoice.Moreover,it

isrelativelyeasytofindsoftwaredevelopers,andmicroprocessorsarewidelysupportedbyoperating

systems,softwareengineeringtools,andlibraries.However,inthelastdecade,powerconstraintshave

limitedtheperformanceofserialcomputationonmicroprocessors.Thishasledtothedevelopmentof

multi-coreprocessorsandanincreasingimportanceplacedonthepursuitofparallelcomputation[7].

Unfortunately,multi-coreprocessorsarerarelythemostefficientmethodtoperformparallel

computation.Thisinefficiencystemsfromthefactthateachcoremustbegeneralenoughtosupportan

entireinstructionset.Asaresult,themajorityofenergyisusedindecodingtheinstructionandfetching

datainsteadofperformingactualcomputation[8].

Hardwareacceleratorssuchasgraphicsprocessorunits(GPUs)andFPGAsareparallel

computationalarchitecturesthathavedemonstratedsubstantialperformanceandenergyefficiency

improvementsovertraditionalmulti-coreprocessordesignsbymovingthefocusbacktocomputation

[9,10].Intermsofenergyefficiency,theGPUarchitecture,whichconsistsofthousandsofparallel

floating-pointunits,isbestsuitedtoso-calledembarrassinglyparallelcomputationorcomputationally

expensiveproblems.However,manyalgorithmswillnotfallintothisproblemcategory.Incontrast,

usinganFPGAorApplication-SpecificIntegratedCircuit(ASIC),itispossibletocreateafullycustomised

datapathforagivenalgorithm,meaningitispossibletoachieveevengreaterenergyefficiencyusing

thesedevices.

Application-specificintegratedcircuits(ASICs)andFPGAsachievegreaterlevelsofparallelism

thanamicroprocessorbyarrangingcomputationsinaspatialratherthantemporalfashion.Thiscan

resultinperformanceimprovementsofseveralordersofmagnitude.Also,theabsenceofcachesand

instructiondecodingcanresultinthesameamountofworkbeingdonewithlesschipareaandlower

powerconsumption[11].Notableexamplesofapplicationdomainsincludecryptography,NP-hard

optimizationproblems,patternmatching,machinelearning,andmoleculardynamics[6].

Anexampleinvolvingtheimplementationofafiniteimpulseresponse(FIR)filterisshownin

Fig.1.Thereconfigurablecomputingsolutionissignificantlymoreparallelthanthemicroprocessor-

basedone.Inaddition,itshouldbeapparentthatthereconfigurablesolutionavoidstheoverheads

associatedwithinstructiondecoding,caching,registerfiles.Furthermore,speculativeexecution,

unnecessarydatatransfersandcontrolhardwarecanbeomitted.

Figure1.IllustrationofamicroprocessorbasedFIRfiltervs.areconfigurablecomputingsolution.Inthe

microprocessor,operationsareperformedintheALUsequentially.Furthermore,instructiondecoding,

caching,speculativeexecution,controlgenerationandsoonarerequired.Forthereconfigurable

computingapproachusinganFPGA,spatialcompositionisusedtoincreasethedegreeofparallelism.

TheFPGAimplementationcanbefurtherparallelizedthroughpipelining.

ComparedwithASICs,FPGAsofferverylownon-recurrentengineering(NRE)costs,whichis

oftenamoreimportantfactorthanthefactthatFPGAshavehigherunitscosts.Thisisbecausemany

applicationsdonothavetheextremelyhighvolumesrequiredtomakeASICsacheaperproposition.As

integratedcircuitfeaturesizescontinuetodecrease,theNREcostsassociatedwithASICscontinueto

escalate,increasingthevolumeatwhichitbecomescheapertouseanASIC(seeFig.2).Beingmore

specialized,ASICsofferarea,powerandspeedadvantagesoverFPGAs,thisgapbeingreducedasmore

hardblocksareemployed[12].Movingforward,reconfigurablecomputingwillbeusedinincreasingly

moreapplications,asASICsbecomeonlycosteffectiveforthehighestperformanceorhighestvolume

applications.

Figure2.Costoftechnologyvs.volume.ThecrossovervolumeforwhichASICtechnologyischeaper

thanFPGAsincreasesasfeaturesizeisreducedbecauseofincreasednon-recurrentengineeringcosts.

Additionalbenefitsofreconfigurablecomputingarethatitstechnologyprovidesashortertime

tomarketthanASICs(associatedFPGAfabricationtimeisessentiallyzero),makingmanyfabrication

iterationswithinasingledaypossible.Thisbenefitallowsmorecomplexalgorithmstobedeployedand

makesproblem-specificcustomizationsofdesignspossible.FPGA-baseddesignsareinherentlylessrisky

intermsoftechnicalfeasibilityandcost,asshorterdesigntimesandlowerupfrontcostsareinvolved.

Asitsnamesuggests,FPGAsalsoofferthepossibilityofmodificationstothedesigninthefield,which

canbeusedtoprovidebugfixes,modificationstoadapttochangingstandards,ortoaddfunctionality,

allofwhichcanbeachievedbydownloadinganewbitstreamtoanexistingreconfigurablecomputing

platform.Reconfigurationcaneventakeplacewhilethesystemisrunning,thisbeingknownasruntime

reconfiguration(e.g.,[13]).

Inthenextsection,weintroducethebasicarchitectureofcommonreconfigurablefabrics,

followedbyadiscussionofapplicationsofreconfigurablecomputingandsystemarchitectures.Runtime

reconfigurationanddesignmethodsarethencovered.Finally,wediscussmultichipsystemsandend

withaconclusion.

COST

VOLUME

CurrentASIC

OlderASIC

OlderFPGA CurrentFPGA

Crossovervolumeincreases withdecreasingfeaturesize

2ReconfigurableFabrics

Ablockdiagramillustratingagenericfine-grainedisland-styleFPGAisgiveninFig.3[14].Productsfrom

companiessuchasXilinx[15],Altera[16],andMicrosemi[17]arecommercialexamples.TheFPGA

consistsofanumberoflogiccellsthatcanbeinterconnectedtootherlogicandinput/output(I/O)cells

viaprogrammableroutingresources.Logiccellsandroutingresourcesareconfiguredviabit-level

programmingdata,whichisstoredinmemorycellsintheFPGA.Alogiccellconsistsofuser-

programmablecombinatorialelements,withanoptionalregisterattheoutput.Theyareoften

implementedaslookuptables(LUTs)withasmallnumberofinputs,4-inputLUTsbeingshowninFig.3.

Usingsuchanarchitecture,subjecttoFPGA-imposedlimitationsonthecircuit'sspeedanddensity,an

arbitrarycircuitcanbeimplemented.Thecompletedesignisdescribedviatheconfigurationbitstream

whichspecifiesthelogicandI/Ocellfunctionality,andtheirinterconnection.

Figure3.Architectureofabasicislane-styleFPGAwithfour-inputlogiccells.Thelogiccells,shownas

grayrectanglesareconnectedtoprogrammableroutingresources(shownaswires,dots,anddiagonal

switchboxes)(source:Reference[14]and[18]).

Currenttrendsaretoincorporateadditionalembeddedblockssothatdesignerscanintegrate

entiresystemsonasingleFPGAdevice.Apartfromdensity,cost,andboardareabenefits,thisprocess

alsoimprovesperformancebecausemorespecializedlogicandroutingcanbeusedandallcomponents

areonthesamechip.AcontemporaryFPGAcommonlyhasfeaturessuchascarrychainstoenablefast

addition;widedecoders;tristatebuffers;blocksofon-chipmemoryandmultipliers;embedded

microprocessors;programmableI/Ostandardsintheinput/outputcells;delaylockedloops;phase

lockedloopsforclockde-skewing,phaseshiftingandmultiplication;multi-gigabittransceivers(MGTs);

andembeddedmicroprocessors.Embeddedmicroprocessorscanbeimplementedeitherassoftcores

usingtheinternalFPGAresourcesorashardwiredcores.

Inadditiontothearchitecturalfeaturesdescribed,intellectualproperty(IP)cores,implemented

usingthelogiccellresourcesoftheFPGA,areavailablefromvendorsandcanbeincorporatedintoa

design.Thesecoresincludebusinterfaces,networkingcomponents,memoryinterfaces,signal

processingfunctions,microprocessorsandsoonandcansignificantlyreducedevelopmenttimeand

effort.

Thebit-levelorganizationofthelogicandroutingresourcesinisland-styleFPGAsisextremely

flexiblebuthashighimplementationoverheadasaresult.Tradeoffsexistinthegranularityofthelogic

cellsandroutingresources.Fine-graineddeviceshavethebestflexibility;however,coarse-grained

elementscantradesomeflexibilityforhigherperformanceanddensity[19].

Withmoderntechnologies,thespeedoftheroutingresourceisalimitingfactor.Trendshave

beentoincreasethefunctionalityofthelogiccellse.g.,uselogiccellswithlargernumbersofinputs

whichcanalsobeconfiguredassmallerLUTs[20]andtoaddpipelineregisterstotheroutingfabric[21].

Fordatapathorientedapplicationssuchasindigitalsignalprocessing,coarse-grainedarchitectures[22]

suchasPipewrench[23]andRaPID[24]employbus-basedroutingandword-basedfunctionalunitsto

utilizesiliconresourcesmoreefficiently.

3Applications

Reconfigurablecomputinghasfoundwidespreadapplicationintheformof“customcomputing-

machines”toacceleratecomputationoveralgorithmsimplementedonaCPU.Applicationdomains

includehigh-energyphysics[25],genomeanalysis[26],signalprocessing[27,28],computervision[29],

cryptography[30,31],financialengineering[10,32],scientificcomputing[33],machinelearning[34]

andsecurity[35].

Inmanyoftheseproblemdomains,ageneralpurposeGPUhasalsodemonstratedconsiderable

accelerationoveraCPUandwilloftenoutperformanFPGAaswellintermsofrawperformance.Thisis

becauseitisaparallelarchitecturewithmanyhardenedfloating-pointunitsandsubstantiallygreater

memorybandwidth,meaningitisanidealarchitectureprovidedalgorithmsthatcanbebrokendown

intoalargenumberofparallelthreads.However,outrightperformanceisnolongertheonly

benchmark;energyconsumptionisalsoimportant.Intermsofhighperformancecomputing,

supercomputingclustersanddatacentersnowconsumevastamountsofenergy,notonlyon

computation,butalsooncoolinginordertomaintainperformanceandreliability.Itfollowsthat

reducingenergyconsumptionprovidesbothenvironmentalandeconomicbenefits.Energyminimization

isalsoimportantforembeddedapplications;forexample,reducingpowerconsumptionon

smartphonesorotherbattery-powereddevicesisdesirablefromanenduserperspective.Asaresult,

FPGAandGPUvendorsarefocusingtheirengineeringeffortstowardsmakingfuturearchitecturesmore

energyefficient.ThisisreflectedinthemostrecentFPGAandGPUarchitectures:Nvidia’sP100claimsa

peakperformanceof10.6TFLOPs(singleprecision)withaTDPofonly300W[36],whileAlteraclaims

performanceofupto9.3TFLOPs(singleprecision)at80GFLOPs/wattisachievableontheirupcoming

Stratix10device[16].

ManyexperimentalstudieshavebeenperformedcomparingtheenergyefficiencyofFPGAs,

GPUsandCPUs;arecentsurveyisprovided[37].BothFPGAsandGPUstypicallyoutperformCPUs

accordingtothismetric.GPUshavebeenshowntobemoreenergyefficientthanFPGAsforcertain

applicationssuchasmatrixmultiplication.Tosomeextent,thisisaresultofthedecisiontooptimizethe

GPUarchitectureforthisproblem[38].However,theflexibilityofanFPGAhasseenitoutperforma

GPU,intermsofenergy-efficiencyorperformance-per-watt,acrossabroaderspectrumofapplications.

Examplesinclude:2-DFIR(finite-impulseresponse)filters,Viola-Jonesfacedetection,K-means

clustering,Monte-Carlooptionspricing,randomnumbergeneration,Smith-Waterman,3-Dultrasound

computertomography[37].EnergyefficiencygainsusingFPGAshavealsobeenclaimedoncommercial

systems.Forexample,Microsoftreporteda3xenergyefficiencygain,andareducedlatency,whenusing

FPGAsinsteadofGPUsontheirCatapultmachine[39],whichisdiscussedlaterinSection4.

WhilemostoftheseperformancecomparisonshavebeenperformedusingIEEEstandardsingle

ordoubleprecisionarithmetic,thisisnotnecessarilythemostenergy-efficientdesignpossibleonan

FPGA.ThisisbecauseFPGAshavethefreedomtoimplementanyprecision,soitmaybepossibleto

createaworkingdesignusingacustom(reducedprecision)fixedorfloating-pointnumberformatthatis

sufficienttosatisfyadesignspecification.Thiswillavoidunnecessarycomputationandcanimprovethe

energy-efficiencyandperformanceofanFPGAimplementationdramatically[40,41].

Toadegree,theflexibilityofanFPGAisevenbeyondthatpossibleinanASIC.Forexample,inan

FPGA-basedimplementationofRSAcryptography[30],adifferenthardwaremodularmultiplierforeach

primemoduluswasemployed(i.e.,themoduluswashardwiredinthelogicequationsofthedesign).

SuchanapproachwouldnotbepracticalinanASICasthedesigneffortandcostistoohightodevelopa

differentchipfordifferentmoduli.Thisledtogreatlyreducedhardwareandimprovedperformance,the

implementationbeinganorderofmagnitudefasterthananyreportedimplementationinany

technologyatthetime.

Anotherimportantapplicationislogicemulation[42,43]wherereconfigurablecomputingisnot

onlyusedforsimulationacceleration,butalsoforprototypingofASICsandin-circuitemulation.In-

circuitemulationallowsthepossibilityoftestingprototypesatfullornear-fullspeed,allowingmore

thoroughtestingoftime-dependentapplicationssuchasnetworks.Italsoremovesmanyofthe

dependenciesbetweenASICandfirmwaredevelopment,allowingthemtoproceedinparallelandhence

shorteningdevelopmenttime.Asanexample,itwasusedin[44]forthedevelopmentofatwo-million-

gateASICcontaininganIEEE802.11mediumaccesscontrollerandIEEE802.1la/b/gphysicallayer

processor.UsingareconfigurableprototypeoftheASIConacommodityFPGAboard,theASICwent

throughonecompletepassofreal-timebetatestingbeforetape-out.

Digitallogic,ofcourse,mapsextremelywelltofine-grainedFPGAdevices.Themaindesign

issuesforsuchsystemslieinpartitioningofadesignamongmultipleFPGAsanddealingwiththe

interconnectbottleneckbetweenchips.TheCadenceProtiumRapidPrototypingPlatform[45]isa

commercialexampleofalogicemulationsystemandhas100million-gatelogiccapacityandfast

compilationandpartitioningalgorithms.Furtherdiscussionofinterconnecttime-multiplexingand

systemdecompositionisgivenlaterinthisarticle.Someexamplesofapplicationsacceleratedusing

earlymultipleFPGAsystemsarediscussedbelow.

Hoang[26]implementedalgorithmstofindminimumeditdistancesforproteinandDNA

sequencesontheSplash2architecture.Splash2canbemodeledintermsofbothbidirectionaland

unidirectionalsystolicarrays.Inthebidirectionalalgorithm,thesourcecharacterstreamisfedtothe

leftmostprocessingelement(PE),whereasthetargetstreamisfedtotherightmostPE.Comparingtwo

sequencesoflengthmandnrequiresatleast2´max(m+1,n+1)processors,andthenumberofsteps

requiredtocomputetheeditdistanceisproportionaltothesizeofthearray.Theunidirectional

algorithmissuitedforcomparingasinglesourcesequenceagainstmultipletargetsequences.The

sourcesequenceisfirstloadedasinthebidirectionalcase,andthetargetsequencesarefedinoneafter

theotherandprocessedastheypassthroughthePEs(whichresultsinvirtually100%utilizationof

processors,sothattheunidirectionalmodelisbettersuitedforlargedatabasesearches).

Acommonapplicationdomainforreconfigurablecomputingisinreal-timedataacquisitionand

signalprocessing.TheBEE2system[27],describedinthenextsection,wasappliedtotheradio

astronomysignalprocessingdomain,whichincludeddevelopmentofabillion-channelspectrometer,a

1024-channelpolyphasefilterbank,andatwo-input,1024-channelcorrelator.TheFPGA-basedsystem

useda130-nmtechnologyFPGAandperformancewascomparedwith130-and90-nmDSPchipsaswell

asa90-nmmicroprocessor.Performanceintermsofcomputationalthroughputperchipwasfoundto

beafactorof10to34overtheDSPchipin130-nmtechnologyand4to13timesbetterthanthe

microprocessor.Intermsofpowerefficiency,theFPGAwasoneorderofmagnitudebetterthantheDSP

andtwoordersofmagnitudebetterthanthemicroprocessor.Computethroughputperunitchipcost

was20–307%betterthanthe90-nmDSPand50–500%betterthanthemicroprocessor.

Onefinalemergingapplicationdomainismachinelearning.Reconfigurableimplementations

showgreatpromiseforaddressingtheirheavycomputationaldemands,andreconfigurablecomputing

isparticularlystronginembeddedandlow-precisionscenarios.Tridgellet.al.demonstratedregression,

classificationandnoveltydetectionusingonlinekernelmethods.Theirfullypipelinedimplementation

couldprocesscontinuousdataatrateshigherthan1Gbpsandperformsimultaneouslearningand

predictionwithalatencyof100ns[46].Zhanget.al.appliedarooflinemodeltobalanceresource

utilizationandmemorybandwidthintheaccelerationofadeepconvolutionalneuralnetwork(CNN).

Theyachieved62GFLOPSonasingleXilinxVirtexVC707board,thisbeinga4.8Xspeedupovera16

threadimplementationonanIntelXeonE5-2430processor[47].

4SystemArchitectures

ReconfigurablecomputingmachinesareconstructedbyutilizingoneormoreFPGAs.Mostsystems

includeotherelements,suchasmicroprocessorsandstorage,andcanbetreatedasprocessing

elementsandmemorythatareinterconnected.Obviously,thearrangementoftheseelementsaffects

thesystemperformanceandroutability,andsomeexamplesaregiveninthissection.

TheAvnetZedboardisadevelopmentboardwhichintegratesasingleXilinxZynqXC7Z020FPGA

(whichcontainsFPGAlogicandadual-coreARMCortex-A9processor),DDRmemory,SDcard,Ethernet,

USBandvideointerfaces.ThissingleboardcomputercanruntheLinuxoperatingsystem,andit

providesalow-costentrypointforteachingandresearchinreconfigurablecomputing[48].

ThesimplesttopologyforconnectingmultipleFPGAsinvolvesaring,mesh,orotherfixed

pattern.FPGAsserveasbothlogicandinterconnect,providingdirectcommunicationbetweenadjacent

devices.Suchanarchitectureispredicatedonlocalityinthecircuitdesignandfurtherassumesthatthe

circuitdesignmapswelltotheplanarmesh.Thisarchitecturefitswellforapplicationswithregularlocal

communications[49].However,ingeneral,highperformanceishardtoobtainforarbitrary

communicationpatternsbecausethearchitectureonlyprovidesdirectcommunicationsbetween

neighboringFPGAsandtwodistantFPGAsmayneedmanyotherdevicesas“hops”tocommunicate,

resultinginlongandwidelyvariabledelays.Furthermore,FPGAs,whenusedasinterconnects,often

resultinpoortimingcharacteristics.

Figure4depictstheSPLASH2architecture[50]publishedin1990.Eachboardcontains16

FPGAs,X1throughX16.TheblocksM1throughM16arelocalmemoriesoftheFPGAs.Asimplified36-

bitbuscrossbar,withnopermutationofthebit-lineswithineachbus,interconnectsthe16FPGAs.

Another36-bitbusconnectstheFPGAsinalinearsystolicfashion.Thelocalmemoriesaredualported

withoneportconnectingtotheFPGAsandtheotherportconnectingtotheexternalbus.Itis

interestingtonotethatthecrossbarwasaddedtotheSPLASH2machine,theoriginalSPLASH1machine

onlyhavingthelinearconnections.SPLASH2hasbeensuccessfullyusedforcustomcomputing

applicationssuchassearchingeneticdatabasesandstringmatching[26].

Figure4.SPLASH2architecture.Eachboardcontains16FPGAs,XIthroughXI6.TheblocksMlthrough

Ml6arelocalmemoriesoftheFPGAs.Asimplified36-bitbuscrossbar,withnopermutationofthebit-

lineswithineachbus,interconnectsthe16FPGAs.Another36-bitbusconnectstheFPGAsindaisy-chain

fashion.ThelocalmemoriesaredualportedwithoneportconnectingtotheFPGAsandtheotherport

connectingtotheexternalbus.

Otherdesignshaveusedahierarchyofinterconnectschemes,differinginperformance.Theuse

ofmulti-gigabittransceivers(MGT)availableoncontemporaryFPGAsallowshighbandwidth

interconnectionusingcommoditycomponents.AnexampleistheBerkeleyEmulationEngine2(BEE2)

[27],designedforreconfigurablecomputingandillustratedinFig.5.Eachcomputemoduleconsistsof

fiveFPGAs(XilinxXC2VP70)connectedtofourdoubledatarate2(DDR2)dualinlinememorymodules

(DIMMs)withamaximumcapacityof4GBperFPGA.FourFPGAsareusedforcomputationandonefor

control.EachPPGAhastwoPowerPC405processorcores.Alocalmeshconnectsthecomputation

FPGAsina2-Dgridusinglow-voltageCMOS(LVCMOS)parallelsignaling.Off-modulecommunications

areofvia18(twofromthecontrolFPGAandfourfromeachofthecomputeFPGAs)Infiniband4X

channel-bonded2.5-Gbpsconnectorsthatoperatefull-duplex,whichcorrespondstoa180-Gbpsoff-

modulefull-duplexcommunicationbandwidth.Modulescanbeinterconnectedindifferenttopologies

includingtree,3-Dmesh,orcrossbar.Theuseofstandardinterfacesallowsstandardnetworkswitches

suchasInfinibandand10-GigabitEthernettobeused.Finally,a100base-TEthernetconnectiontothe

controlFPGAispresentforout-of-bandcommunications,monitoring,andcontrol.

Figure5.BEE2ComputeModuleblockdiagram.Computemodulescanbeinterconnectedviathe

InfinibandIB4Xconnectors,eitherdirectlyorviaa10-GigabitEthernetswitch.The100-BaseTEthernet

canbeusedforcontrol,monitoring,ordataarchiving.

Commercialmachines,suchastheMaxelerMPC-X2000system[51],haveasimilarinterconnect

structuretotheBEE2inthattheyareparallelmachinesemployinghighperformancemicroprocessors

tightlycoupledtoarelativelysmallnumberofFPGAdevicespernode.TheMPC-X2000isa1Userver

witheightlargeFPGAs,calleddataflowengines(DFEs),interconnectedinaringarrangement.Atotalof

384GBofdynamicRAMissupportedandmultiplehostprocessorscancommunicatewitheachDFEvia

ahigh-speedInfinibandswitchedinterconnectnetwork.Suchmachinescanhaveordersofmagnitude

performanceimprovementoverconventionalarchitecturesandswitchingtopologiescanbealteredvia

configurationoftheswitchingfabric.

MicrosofttookadifferentapproachintheirCatapultmachine,choosingasingledaughtercard

perserverovermulti-FPGAboardsforthereasonsofscalability,capacity,power,spaceandreliability

[52].EachFPGAcardoperatesunder20W,ishostedbyaserverviaPCIExpressandcontains8GBof

dynamicRAM.TheFPGAboardsareorganizedina24Uarrangementof48Uhalf-width1Uservers,

directlyconnectedtogetherwithSAScables.Atestsystemcontaining1,632serverswasshownto

reducethetaillatencyoftheMicrosoftBingsearchengineby29%andimproverankingthroughputof

eachserverby95%.

TheIntel-AlteraHeterogeneousArchitectureResearchPlatform(HARP)utilizesIntelQuickpath

Interconnect(QPI)inadualsocketmotherboardwiththeprocessorandFPGAresidingeachoccupyinga

socket[53].Thisoffershigherbandwidthandlowerlatencyoverconventionaldaughtercards.A

coherentsharedmemorybetweentheprocessorandFPGAgivesthepromiseofagreatlysimplified

programmingmodelandtighterprocessor-FPGAcouplingwhichwillbenefitirregulardataaccess

patterns.

5RuntimeReconfiguration

Areconfigurablecomputingsystemcanhaveitsfunctionalityupdatedduringexecution,

resultinginreducedresourcerequirements.Aruntimereconfigurablesystempartitionsadesign

temporallysothattheentiredesigndoesnotneedtoberesidentintheFPGAatanygivenmoment[54,

55].Instead,theFPGAfabricistime-sharedbetweenspecializedhardwareacceleratorsatruntime.

Usingthistechnique,designslargerthantheavailablehardwareresourcescanberealized,or

alternatively,anexistingdesignmaybeimplementedonasmallerorcheaperdevice.Furthermore,

energyefficiencycanbeincreasedbecausetheentirefabriccanbeusedmoreeffectively.

Singlecontext,multiplecontextarchitecturesandpartiallyreconfigurableFPGAsbeen

developed.Inasinglecontextsystem,anychangestothefunctionalityoftheFPGAinvolvereloadingthe

entirebitstream;earlyFPGAswereofthistype.Thisschemehasthedisadvantageoflong

reconfigurationtime.Multiplecontextortime-sharingarchitectures,lieattheotherextreme.These

allowanumberofcompleteconfigurationstobestoredinthefabricsimultaneouslyandthus

reconfigurationcanbeachievedinasmallnumberofcycles.Thesearchitectureswerealsoproposedfor

earlyFPGAs.Asanexample,anarchitecturenamedDharma,wasproposedthatcontainsafunctional

blockandaninterconnectnetwork[56].Bybreakingalargedesignintolevelsinafoldedpipeline,the

logicmodulesandinterconnectcanbetime-sharedbydynamicallyreconfiguringeachlevel.This

topologysimplifiesthearchitectureandprovidespredictableinterconnectdelay(Fig.6).Multiple

contextarchitectures,suchasNEC'sDynamicallyReconfigurableProcessor(DRP)[57],werelater

developed.Sucharchitectureshavetheshortestcontextswitchtime,however,alargerareaoverheadis

associatedwithimplementationofthisscheme.

Figure6.DynamicArchitectureforFPGA-basedsystems.Thearchitecturecontainsafunctionalblock

andaninterconnectnetwork.Theinterconnectandthelogiccanbetimeshared.Theemulateddesign

topologyislevelizedinafoldedpipelinemanner.Thelevelizedtopologysimplifiesthearchitecturewith

predictableinterconnectdelay.

PartiallyreconfigurableFPGAs,assupportedbythemajorFPGAvendorsinXilinxVirtex[15]and

AlteraStratix[16]architectures,havebeguntodominatethemarket.Thesearchitecturesallowportions

oftheFPGAtobechangedviaamemorymappedschemewhilsttheotherportionsoftheFPGA

continuefunctioning.Incomparisontoasinglecontextscheme,thereissomeareaoverheadassociated

inprovidingthisfeature;ideallythisiscompensatedforbymoreefficientuseofthefabric.

Manytoolshavebeendevelopedtohelpsupportruntimereconfiguration.Commercialtools,

providedbythemainFPGAvendorsXilinxandAlteraaimtoabstractthelowlevelimplementation

detailsfromtheengineer.However,otheropensourcetoolshavebeendevelopedtoenablemore

flexiblesystems.Forexample,ReCoBus-Builderintroducedasimpleinterfaceforcommunication

betweenthestaticpartofasystemandthedynamicmodules,aswellastheabilitytoplaceandroute

partialmodulesseparately,beforelinkingthesecompiledbitstreamsatrun-time[58].Thismakes

modulesinterchangeableandspeedsupthecompilationprocess.TheGoAheadtooltakesthisfurther,

allowingtheFPGAfabrictobeseparatedintodifferentregions,withindividualmodulescompiledtofit

intooneormoreoftheseregions[59].Italsoprovidessupportformodulestocommunicatebetweenor

acrossregions.Thisimprovesflexibilityinplacementofmodulesandpromotessharingacrossregions.

Toolstohelpdeterminetheoptimumnumberofregionshavealsobeengenerated[60].

Theaforementionedtoolsarealsoabletosupporthierarchicaldesigns,whereapartialregion

doesnotneedtobefullyreconfigured;insteadasmallerregionwithinthisareacanbereconfigured.

Thishasmultipleadvantages.Firstly,storingafewdifferentmodulesateachhierarchicallevelprovides

ahugeamountofflexibility,savingsignificantconfigurationmemoryincomparisontostoringall

differentmodulesatthehighestlevel.Furthermore,sinceonlyasmallregionneedstobereconfigured,

thereconfigurationtimeisreduced[61].

Toolsalsoexisttohelpoverlapre-configurationandcomputationtomaximizetheperformance

ofthedevice.ForexampleZyCAP,whichisbasedontheXilinxZynqarchitecturewithanembedded

ARMCPU,providessoftwaredriverstohelpreconfigurationbeoverlappedwithcomputationby

controllingallthereconfigurationprocesses[62].Itcanalertthesoftwarethatconfigurationis

complete,andalsomanageshowpartialbitstreamsarestoredinmemory.Thisisimportanttohelp

maximizeperformance,forexample,thistoolofferstheabilitytocachepartialbitstreamsinDRAMto

speedupthereconfigurationprocess.Finally,therearealsoeffortstoverifythepartialbitstreams

performthedesiredfunctionality[63].

Therearemanyexamplesofrun-timereconfiguration,withthelogicalunitofreconfiguration

rangingfromapplication-leveldowntoasub-instruction.Thesearediscussedbelow:

Attheapplicationlevel,examplesincludeadaptingthebitstreamaccordingtochangesin

environmentalconditions.Forexample,Clausetal.discussedhowhardwareacceleratorsmaybe

neededforreal-timevideoprocessing,butinthecontextdriverassistance,adaptingthemaccordingto

changinglightconditionscouldimproveperformance.Theydemonstratedthatthiscanprove

worthwhilesincemodulescanbequicklyreconfiguredbetweenframes[64].

Tasklevelreconfigurationiscommonforsoftwaredefinedradio,forexamplewhenswitching

betweenencodingschemes.Thetrade-offsbetweenfullorpartialreconfigurationinthisproblem

domainarediscussedbyDelahayeetal.[65].Similarly,Feillenetal.discussedhowdifferentstagesof

digitalvideodecodingdonotneedstooperateconcurrently,meaningthesamehardwarecouldbere-

usedinthisexample[66].Tasklevelreconfigurationforanoperatingsystemhasalsobeenproposed

[67].Undercontrolofsoftwarerunningonamicroprocessor,taskcircuitscanbescheduledonlineand

placedinasuitablefreespaceinahardwaretaskarea.CommunicationsbetweentasksandI/Oaredone

throughataskcommunicationbus,andterminationofataskfreesthereconfigurableresourcesused.It

wasshownthathardwareinthehardwaretaskareacanbesharedbytasksandtheoverheads

associatedwithitsimplementationonapartiallyconfigurableplatformwereacceptablylow.Thishelps

improveschedulingofreal-timetasks.

Instructionlevelreconfigurationhasbeendemonstratedforhardwareaccelerateddatabase

queries.DifferenthardwaremodulesforSQLqueriescouldbedynamicallyconfiguredtoimprove

performance[68]andenergyefficiency[69].ACPUsystemwithcustominstructionsisanothercommon

candidateforinstructionlevelreconfiguration.AnearlyexampleincludestheDynamicInstructionSet

Computer(DISC)[70],whichsupporteddemand-drivenmodificationoftheinstructionsetthrough

partialreconfiguration.ThecommercialStretchprocessor[71]combinesreconfigurablefabricwitha

processortosupporttheexecutionofcustominstructionsimplementedonareconfigurablefabric.

Furthermore,thefabriccanbereconfiguredatruntimeandthedesignenvironmentissoftware-centric,

withprogrammingoftheprocessorbeinginStretchC.

Finally,partialreconfigurationhasalsobeenshownforsub-instructions.Forexample,apipeline

stagecouldbeaconvenientunitofreconfiguration,asdemonstratedbyincrementalpipeline

reconfiguration[72].AssumeanFPGAthathasenoughsiliconareaforNphysicalpipelinestages,but

thedesigncontainsMpipelinestages(whereM>>N).Throughaddingonepipelinestageandremoving

thetrailingpipelinestageineachstageofthecomputation,executionandcomputationcanbe

overlapped.SuchacircuitwillimplementapipelineofdepthNandfullyutilizetheFPGAatanygiven

pointintime.Runtimereconfigurationcanbedoneatevenlowerlevels.Examplesincludethose

supportinghierarchicaldesignsforaCPUwithgreaternumbersofcustominstructions[61]anda

crossbarswitchwhichemploysruntimereconfigurationoftheFPGA'sroutingresources[73].Bypartially

reconfiguringroutingmultiplexers,thisschemewasabletoachievedensity,switchupdatelatencyand

performancehigherthanpossibleusingconventionalmeans.

6Designmethods

Hardwaredescriptionlanguages(HDLs)suchastheVeryHighSpeedIntegratedCircuitHardware

DescriptionLanguage(VHDL)andVerilogarecommonlyusedtospecifythelogicofareconfigurable

system.Descriptionsintheselanguageshavetheadvantageofbeingvendorneutral,sothesame

descriptioncanbesynthesizedfordifferenttargetssuchasdifferentFPGAdevices,differentFPGA

vendors,andASICs.Forthisreason,theselanguagesareoftenthetargetlanguageforhigherleveltools

thatofferhigherlevelsofabstraction.

Modulegeneratorsandlibrariesarecommonlydeployedtopromotereuse.Forexample,

vendorssuchasAlteraandXilinxhaveparameterizedlibrariesofcomponentsthatcanbeusedina

design.Theselibrariesaregeneratedsothatacircuitoptimizedfortheparticularapplicationcanbe

produced.Asanexample,aparameterizedfloatingpointlibrarymightallowthewordlengthofthe

exponentandsignificandtobespecifiedaswellaswhetherdenormalizednumbersaresupported.The

modulegeneratorthengeneratesanetlistorVHDL-basedfloatingpointadderthatcanbeincludedina

design.Opensourcealternatives,suchastheFloPoColibraryalsoprovidevendorneutralalternativesto

generatemanykeycomponents[74].

InanefforttohelpmakeFPGAsmoremainstream,effortshavebeenplacedintohigh-level

synthesis,whichistheprocessofcompilingatraditionalhighlevellanguagedowntoanetlistorHDL.

Theuseoftraditionalprogramminglanguagesimprovesproductivityaslowleveldetailsarehandledby

thecompiler.ThisisanalogoustoCversusassemblylanguageforsoftwaredevelopment.Another

differencewithpotentiallylargeimplicationsisthat,usingthesetools,softwaredeveloperscanalso

designreconfigurablecomputingapplications

Asanearlyexample,LukandPagedescribedasimplecompilationprocess[75,76]fromahigh

levellanguagewithexplicitparallelextensionstoaregistertransferlanguage(RTL)description.Parallel

executionofstatementsisimplementedviaparallelprocesses,andthesecancommunicateviachannels

throughwhichasingle-wordmessagecanbepassed.Variablesintheuserprogramaremappedto

registers,allexpressionsareimplementedascombinationallogic,andmultiplexersareusedinthecase

aregisterhasmultiplesources.Adatapaththatmatchesthedataflowgraphoftheinputsource

descriptionisgeneratedusingthisstrategy.Theclockingschemeemployedisaglobal,synchronousone,

andaconventionthateachassignmenttakesexactlyoneclockcycleisfollowed.Astartsignalisusedto

feedtheclockandtoenableeachregisterthatcorrespondstoavariable,andafinishsignalisgenerated

fortheassignmentinthefollowingclockcycle.Toexecutestatementssequentially,thestartandfinish

signalsofadjacentstatementsaresimplyconnectedtogether,creatingaone-hotdistributedcontrol

scheme.Conditionalstatementsandloopsareformedbyassertingoneofseveralpossiblestartsignals

thatcorrespondtoalternativebasicblocksinaprogram.Completionofconditionalorloopconstructs

andsynchronizationofparallelblocksareimplementedbycombiningrelevantfinishsignalsusingthe

appropriatecombinatoriallogic.Anexampleshowingthetranslationofasimplecodefragmentto

controlanddatapathisshowninFig.7.

Figure7.Hardwarecompilationexample.TheCprogramistranslatedintoadatapath(top)andcontrol

(bottom).Executionofstatementsinthewhilelooparecontrolledbys1ands2;s0ands3correspondto

thestartsignalsofthestatementsbeforeandafterthewhileloop.

High-levelsynthesistoolshavesincemovedbeyondsimplytranslatingahigh-levellanguagetoa

hardwaredesign;insteadtheyfocusoncreatinganoptimizedhardwaredesign.Straightforward

examplesmayincludeextractingparallelismthroughloopunrollingorcreatingdeeplypipelineddesigns

tomaximizeclockfrequency.However,finer-grainedoptimisationsarealsopossible.Forexample,since

movingdataontotheFPGAcanbeexpensive,storingdatalocallyonthechipandre-usingthedatacan

havesubstantialperformanceimplications[77].Whiletheideaissimilartothatofcachingona

microprocessor,onanFPGAthelocalbufferscanbesizedaccordingtotheneedsofaparticular

algorithm,savingresources.Alternatively,thememorycanbearrangedinafashionthatprovidesa

largememorybandwidth,whichmaybenecessarytofeedaparalleldatapath.Moreoever,theinterface

withtheDRAMcanalsobecontrolledtoensurethatmemoryreadsoccurfaster,forexampleby

‘activating’rowsthataresoontoberead[78].Anotheroptimizationistofinetunetheprecisionused

throughoutcomputations,i.e.touseaslittleprecisionasisnecessarytomeetyourdesignspecification.

UnlikeaCPUimplementation,anFPGAdesignhasthefreedomtoimplementanyprecision.Since

arithmeticoperatorswithlessprecisionuselesssiliconarea,usingtheminimumprecisionnecessary

freesresources,allowingforgreaterparallelperformance.Toolstosupportthisdesignmethodology,

bothinfixedandfloatingpointarithmeticarebeingsupported[79,80].

Variousotherissueswiththemappingofalgorithmstohardwarearemoregenerallydiscussed

byIsshikiandDai[81],whofocusonthedifferencesbetweenimplementingbit-serialversusbit-parallel

modules(e.g.,addersandmultipliers)onFPGAarchitectures.Althoughlatencyislargerforbit-serial

modules,thereductioninareafrequentlymakesarea-timeproductssignificantlylowerforsuch

implementations.Morespecifically,suchadvantagesasthefollowingcanbeobtained:1)Forbit-parallel

modules,theI/Opinlimitationisamajorproblem,andthelargesizeofthemoduleclustercanresultin

unusedspaceandunderutilizedlogicresources;2)bit-serialmodulesareeasiertopartitionascell-to-

cellconnectionsaresparseanddonotcauseI/Oproblems;and3)highfanoutnetscanimpair

routabilityofbit-parallelmodules.LeongandLeong[82]generalizedfurtherwithadesignmethodology

thatcantranslateadataflowdescriptionwithsignalsofdifferentwordlengthstoadigitserialdesign.

CommercialtoolsthatcancompilestandardprogramminglanguagessuchasJava,C,orC++

(e.g.,[76])areavailable.ExamplesincludeXilinx’sVivadoHLS[15],Maxeler’sMaxCompiler[83]and

CatapultCfromMentorGraphics[84].Domain-specificlanguagessuchasMATLAB/Simulinkoffereven

greaterimprovementsinproductivitybecausetheyareinteractive,includealargelibraryofprimitive

routinesandtoolkits,andhavegoodgraphingcapabilities.Indeed,manydesignsforcommunications

andsignalprocessingarefirstprototypedinMATLABandthenconvertedtootherlanguagesfor

implementation.ToolssuchastheMATCHcompiler[85]andXilinxSystemGenerator[15],AlteraDSP

builder[16]andMathwork’sHDLcoder[86]cantranslateasubsetofMATLAB/Simulinkdirectlytoan

FPGAdesign.ThereisalsointerestinsupportingmoreparallelC-to-gatesflows.Supportformore

recentparallelprogramminglanguagesisgainingtraction,forexampleAlteraSDKforOpenCL[16]and

effortstosupportNVidia’sCUDAusingFPGAs[87].

Duetothedifficultyincreatingafull-customdesign,thereisalsosupportforcreating

hardware/softwareco-designs.TheavailabilityofembeddedoperatingsystemssuchasLinuxfor

microprocessorsonanFPGAprovideafamiliarsoftwaredevelopmentenvironmentforprogrammers,

greatlyfacilitatingprogramdevelopmentthroughtheavailabilityofalargerangeofopen-source

librariesaswellashighqualitydevelopmenttools.Suchtoolscangreatlyspeedupthedevelopment

timeandimprovethequalityofembeddedsystems.Forexample,Altera'sNiosIIC-to-Hardware

accelerationcompilerenabletime-criticalfunctionsinaCprogramtobeconvertedtoahardware

acceleratorthatistightlycoupledtoamicroprocessorwithintheFPGA[88].Thesetoolswillsupportsoft

processors,suchastheAlteraNIOSorXilinxMicroblaze,andembeddedprocessors,suchasthoseon

theXilinxZynqorAlteraSoCs.Withthelatter,foroptimalperformance,thepartsofanalgorithmthat

areeasilyparallelizableshouldmakeuseoftheparallelFPGAfabric,whereasserialpartsofthe

algorithmshouldberunonaprocessor[89].

AfinaldesignapproachtoallowforfastFPGAprototypingistheuseofoverlayarchitectures.

Thesearecoarse-grainedarchitectureswithsoftware-likeprogrammability,withtheaimofsacrificing

someperformanceinexchangeforeaseofimplementation.Forexample,VectorBloxextendsthe

hardware-softwareparadigmbyusingtheFPGAfabrictoprovideparallelvectorinstructionsthatcanbe

easilyexecuted[90].Atypicaldesignflowusingthistechnologywouldbetocreateaninitialsoftware

design,addvectorinstructionswithinasoftwarestyledevelopmenttoobtainsomeaccelerationand

finallycreatecustomhardwareinstructionsforthemosttimeconsumingpartsofanalgorithm.Thismay

provideafastertimetomarket.Manyoverlaysarchitectureshavebeencreated,includingsomefor

specificapplications,suchasforefficientnetworkonchip(NOC)interconnectionsofprocessors[91]or

dataflowgraphs[92],andsomedesignedtomakeuseofspecifichardenedcomponentsonFPGAssuch

asDSPs[93].

7MultichipSystems

Specialcaremustbetakeninthedesignoflargeandmultichipreconfigurablesystems.Inthissection,

wedescribesometheoreticresultsrelevanttothemajorarchitecturalandissuesassociatedwithsuch

designs.

7.1InterconnectOrganization

AclassicClosnetwork[94]containsthreestages:inputs,intermediateswitches,andoutputs,asshown

inFig.8.Itcanbeusedtointerconnectpinsinareconfigurablecomputingsystem,anditsinputand

outputstagesaresymmetric.Supposethefirststagehasrn×mcrossbarswitches,thesecondstagehas

mr×rswitches,andthethirdstagehasrm×nswitches,letusdenotethenetworkasc(n,m,r).Forany

two-pinnetinterconnectrequirement,thenetworkc(n,m,r)canachievecompleteroutabilityifmis

notlessthann.Theroutingmethodcanbedescribedbyrecursiveoperations[95].Inthefirstiteration,

wereducethenetworktoc(n-1,m-1,r).Intheithiteration,wereducethenetworktoc(n-i,m-i,r).

Whenn-i=1,wehaver1×(m-n+1)switchesinthefirststage,m-n+1r×rswitchesinthesecondstage,and

r(m-n+1)×1switchesinthethirdstage.Inotherwords,onlyoneinputexistsineachfirst-stageswitch

andoneoutputineachthird-stageswitch.Inthiscase,onesecond-stager×rswitchisenoughtoroute

therinputsofrfirst-stageswitchestotheroutputsofrthird-stageswitches,thuscompletingthe

interconnect.

Figure8.Closnetwork.AClosnetworkcontainsthreestages:inputs,intermediateswitches,and

outputs.Theinputandoutputstagesaresymmetric.Inthefigure,thefirst-stagehasrn×mswitches,

thesecond-stagehasmr×rswitches,andthethird-stagehasrm×nswitches.

Thereductionfromc(n-i,m-i,r)toc(n-i-1,m-i-1,r)canbederivedbyamaximummatching

algorithm.Thematchingalgorithmselectsdisjointsignalsfromdifferentinputswitchestodifferent

outputswitches.Onesecond-stageswitchisthenusedtoroutetheselectedsignals.FromHall's

theorem,themaximummatchingandroutingcanalwaysreducethenetworktoc(n-i-1,m-i-1,r).

Conceptually,theroutingproblemcanalsobeformulatedasedgecoloringonabipartitegraph

G(V1,V2,E)[96].ThenodesetsV1andV2representtheswitchesintheinputandoutputstages,

respectively.AnedgeinErepresentsatwo-pinnetinterconnectrequirementbetweenthe

correspondinginputandoutputswitches.InReference[96],ChanandSchlagassignedcolorstothe

edgesofthebipartitegraph.Edgesofthesamecolorarebundledintoonegroupandthecorresponding

setofnetsareroutedbyoneswitchinthesecondstage.TheworkofReference[97]wasthenusedto

findaminimumedgecoloringsolutioninO(|E|logn).

Thethree-stageClosnetworkcanbefoldedintoatwo-stagenetwork(Fig.9)sothattheinputs

andoutputsaremixedinthefirststage.Thus,thecorrespondingbipartitegraphG(V1,V2,E)constructed

aboveforedgecoloringisalsofoldedwithV1andV2mergedintooneset.

Figure9.FoldedClosnetwork.Thethree-stageClosnetworkisfoldedintoatwo-stagenetworksothat

theinputsandoutputsaremixedinthefirststage.

Tofindtheroutingassignment,thefoldededgecoloringgraphcanbeunfoldedbacktoa

bipartitegraphusinganEulerpathsearch.TheEulerpathtraverseseveryedgeexactlyonceanddefines

theedgedirectionaccordingtothedirectionofthetraversal.Wethenrecovertheoriginalbipartite

graphbysplittingthenodesetbackintotwosetsV1andV2andunfoldtheedgessuchthatalledgesare

directedfromV1toV2.Wecanfindtheminimumedgecoloringsolutionoftheunfoldedbipartitegraph

andapplythesolutionbacktothefoldedroutingproblem.

Inpractice,thefirst-levelcrossbaroftheClosnetworkisreplacedwithFPGAstosaveboard

space(Fig.10).RoutabilityisworsethananidealClosnetwork.EvenwithatrueClosnetwork,complete

routabilityofmultipinnetsisnotguaranteed,whichisanimportantpracticalconsiderationbecausein

microelectronicdesign,manymultipinnetstypicallyexist.

Figure10.VariationsoftheClosnetwork.ThefirstlevelcrossbaroftheClosnetworkisreplacedwith

FPGAstosaveboardspace.RoutabilityisworsethananidealClosnetwork.

Inanattempttosolvethemultipinnetandroutabilityproblem,wecanintroduceextra

connectionsamongFPIDsasshowninFig.11.However,extraFPIDinterconnectionsalsoincurextra

delay.WecanalsoexpandthefanoutwidthofFPGAssothateachFPGAI/Opinisconnectedtomore

thanoneFPIC[98,99].Thefanoutwidthexpansionimprovesroutabilitywithoutsignificantadditional

delay.ThemultipleappearancesofI/Opinsincreasetheprobabilitythatasignalconnectioncanbe

madeinasinglestage,whichisespeciallycriticalformultipinnets.However,theadditionalfanouts

increasetheneededpincountofFPICs.Thus,weneedtofindabalancedfanoutdistributionthat

reducestheinterconnectdelaywithaminimalpinrequirement.

Figure11.VariationsofClosnetwork.ThefanoutwidthofFPGAsisexpandedsothateachFPGAI/Opin

isconnectedtomorethanoneFPIC.Thefanoutwidthexpansionimprovesroutabilitywithoutsignificant

additionaldelay.

Atree-structurednetworkcansimplifythemappingprocessforcertainapplications.In

Reference[100],anexampleofatree-structurednetworkisillustratedforaVeryLargeScaleSimulator

(VLSS).TheVLSStreestructurehasalllogiccomponentslocatedattheleavesandinterconnectswitches

attheinternalnodes.Themachinecoversacapacityofeightmilliongates.Eachbranchisan8-bitbus.

Thehigherupthelevelofthetree,thelessparallelismthesignaldistributioncanachieve.Therefore,a

partitioningprocessisdesignedtominimizethehighlevelinterconnectandmaximizetheparallel

operation.

7.2InterconnectMultiplexing

Timemultiplexingisaneffectivemethodfortacklingthescalabilityproblemininterconnectinglarge

designs.Thetime-sharingmethodcanbeextendedfromtraditionalbusorganization[42,100]to

networksharing[101]andfurthertofunctionblocksharing[56].

Interconnectcanbetimesharedasabus[42,100].Ifncommunicationlinesexistbetweentwo

FPGAs,theycanbereducedtoasinglelinebystoringlogicaloutputsinshiftregistersandtime-

multiplexingthecommunicationinphases.Suchaschemewasemployedinthevirtualwireslogic

emulationsystem[42],whichisefficientbecauseinterconnectsarenormallycapableofbeingclockedat

muchhigherratesthanthecriticalpathoftherestofthesystem,andalllogicalwiresarenot

simultaneouslyactive.Thisschemecangreatlyreducethecomplexityoftheinterconnectingnetworkor

printedcircuitboardinamulti-FPGAsystem.

LiandCheng[101]proposedthatadynamicnetworkbeviewedasoverlappingLconventional

FPICstogetherbutsharingthesameI/Opins.Adynamicroutingarchitecturecanincreasetheroutability

andshorteninterconnectlength.Eachswitchingnetworkisafullcrossbar,whichcanbereconfiguredto

provideanyconnectionsamongI/Opins.Theselectlinesareusedtoactivateonlyoneswitching

networkatatime;thustheI/Opinsaredynamicallyconnectedaccordingtotheconfigurationofthis

activeswitchingnetwork.BydynamicallyreconfiguringtheFPICs,Llogicsignalscantime-sharethesame

interconnectresources.

7.3MemoryAllocation

InterconnectschemesshouldalsoconsiderhowmemoryisconnectedtotheFPGAs.Although

combiningmemorywithlogicinthesameFPGAisthemostdesirablemethodforreducingrouting

congestionandsignaldelay,separatecomponentscansupplymuchlargercapacityathigherdensityand

lowerprice.Figure12demonstratesthreedifferentwaysofallocatingthememoriesinaClosnetwork

[96,102].ThememorymaybeattacheddirectlytoalocalFPGA(Fig.12a),attachedtothesecond-stage

switchesoftheClosnetworkviaahostinterface(Fig.12b),orattachedtothefirst-stageswitchesofthe

Closnetwork(Fig.12c).Thefirstmethodprovidesgoodperformanceforlocalmemoryaccess.However,

forthecaseofnonlocalmemoryaccess,theroutabilityanddelayareconcerns.Thesecondmethodis

slowerthanthefirstmethodforlocalmemoryaccessesbutprovidesbetterroutability.Thethirdisthe

mostflexibleasthememoryisattachedtothenetworkandtheroutabilityishigh.However,everylogic-

to-memorycommunicationmustgothroughthesecondinterconnectstage.

Figure12.Memoryorganization,(a)MemoryisattacheddirectlytoalocalFPGA.(b)Memoryis

attachedtothesecond-stageswitchesoftheClosnetworkviaahostinterface,(c)Memoryisattached

tothefirst-stageswitchesoftheClosnetwork.

7.4BusBufferInsertion

InFPGAs,signalpropagationisinherentlyslowbecauseofitsprogrammableinterconnectfeature.

However,thedelayoflongroutingwirescanbedrasticallyreducedbybufferinsertion.Theprincipleat

workisthatbyinsertingbufferswecandecouplecapacitiveeffectsofcomponentsandinterconnect

drivenbythebuffersandtherebyimproveRCdelay.

Givenaroutingtopologyforanetandtimingrequirementsforitssinks,anefficientoptimal

bufferinsertionalgorithmwasproposedin[103].Experimentalresultsshowdramaticimprovement

versustheunbufferedsolution.Thus,itisadvantageoustohaveabundantbuffersinFPGAs.However,

eachpossiblebufferanditsprogrammableswitchaddscapacitancetothewires,whichinturnwill

contributetodelay.Thus,abalancepointneedstobeidentifiedtotradeoffbetweentheadditional

delayandcapacitanceofthebuffersversustheimprovementtheycanprovide.

Foramultisourcedbus,theproblemofbufferinsertionbecomesmorecomplicated,because

theoptimizationforonesourcemaysacrificethedelayofothers.Furthermore,thedirectionofthe

bufferneedstobearbitratedbyacontroller.Insteadofusingsuchacontroller,anovelapproachisto

useapatentedopencollectorbusrepeater[104].Whenidle,thetwoendsoftherepeateraresetto

high.Whentherepeatersensesthepull-downactionononeside,itpresentsthesignalontheother

sideuntilthepull-downactionisreleasedfromtheoriginatedsignal.Thebusrepeatereliminatesthe

needforadirectioncontrolsignal,resultinginasimplerdesignandbetteruseofresources.

7.5SystemDecomposition

Todecomposeasystemintomultipledevices,Yehetal.[105]proposedanalgorithmbasedonthe

relationshipbetweenuniformmulti-commodityflowandmin-cutpartitioning.Yehetal.constructaflow

networkwhereineachnetinitiallycorrespondedanedgewithflowcostone.Tworandommodulesin

thenetworkwerechosenandtheshortestpath(i.e.,pathwithlowestcost)betweenthemwas

computed.AconstantΔ<1wasaddedtotheflowforeachnetintheshortestpath,andthecostfor

everynetinthepathwasincremented.Adjustingthecostpenalizespathsthroughcongestedareasand

forcesalternativeshortestpaths.Thisrandomshortestpathcomputationisrepeateduntileverypath

betweenthechosenpairofmodulespassesthroughatleastone“saturated”net.Thesetofsaturated

netsinducesamulti-waypartitioninginwhichtwomodulesbelongtothesameclusterifandonlyif

thereisapathofunsaturatednetsbetweenthem.

Foreachoftheseclusters,theflux(definedasthecutsizebetweentheclusterandits

complement,dividedbythesizeofthecluster)iscomputedandtheclustersaresortedbasedontheir

fluxvalue.Yehetal.beganwithasingleclusterequaltotheentirenetlist,andthenpeeledoffthe

clusterswithlowestflux.Thisapproachwasattractivebecausethesaturatednetsaregoodcandidates

tobecutinapartitioningsolution.Aspeeledclusterscanbeverysmall,asecondphasemaybeusedto

makethemulti-waypartitioningmorebalanced.Thisapproach,withitssubsequentspeedupbyYeh

[106],iswell-suitedforlarge-scalemulti-waypartitioninginstances.

Thesystemprototypingphasemayalsoexplorenetlisttransformationssuchaslogicreplication

andretimingtominimizecutsize(I/Ousage)orsystemcycletime.Suchtransformationsareneededas

inter-devicedelayscanberelativelylargeandbecausedevicesareoftenI/O-limited.InReference[107],

Liuetal.proposedapartitioningalgorithmthatpermitslogicreplicationtominimizebothcutsizeand

clockcycleofsequentialcircuits.GivenanetlistG=(V,E),theirapproachchoosestwomodulesasseeds

sandt,thenconstructsa“replicationgraph”thatistwicethesizeoftheoriginalcircuit.Thisgraphhas

thespecialpropertythatatypeofdirectedminimumcutyieldsthereplicationcut(i.e.,adecomposition

ofVintoS,T,andR=V-S-TwheresÎS,tÎTandRisthereplicatedlogic)thatisoptimal.Adirected

versionoftheFiduccia-Mattheysesalgorithmisusedtofindaheuristicdirectedminimumcutinthe

replicationgraph.Congetal.[108]presentanefficientalgorithmfortheperformance-drivenmulti-way

circuitpartitioningproblemthatconsidersthedifferentlocalandglobalinterconnectdelayintroduced

bythepartitioning.

AlpertandKahng[109]surveytheFPGApartitioningliteratureinthecontextofmajorgraph

partitioningparadigms.Thecurrentpartitioningproblemsare(i)lowusagerateofFPGAgatecapacity

becauseI/Opinlimit,(ii)lowclockratebecauseofinterconnectdelaybetweenmultipleFPGAsand(iii)

longCPUtimeforthemappingprocess.

7.6SystemPlanningandDesignChanges

Foragivensystemdecompositiontobeimplementedonamulti-FPGAprototypingarchitecture,all

connectionswithineachdeviceandbetweendevicesmustberoutable.Chanetal.[110]invokemuch

literatureonroutabilitypredictioningatearrays,aswellastheoreticalconcepts,suchastheRent

parameter,toobtainafastroutabilityestimateforarbitrarynetlistsandFPGAarchitectures.Their

methodascribesoneofthreelevelsofroutable(easilyroutable,marginallyroutable,orunroutable)toa

netlistbasedonvariousparameters.Specifically,combiningawirelengthestimatorduetoFeuer,the

averagenumberofpins-per-cell,andtheestimatedRentparameteryieldsarelativelyaccurate

routabilitypredictor.TheutilityoftheseparametersiscontrastedwiththatofothercriteriasuchasEl

Gamal'schannelwidthrequirement[111]ortheaveragepins-per-netratio.

Inadditiontoroutability,connectionsmustalsomeetsystemtimingconstraints.Selvidgeetal.

[112]extendtheoriginalvirtualwires[42]conceptintheirTIERS(Topology-IndEpendentRoutingand

Scheduling)approach.Theproblemformulationassumesthatanassignmentfromamultiple-FPGA

partitioning(i.e.,adesigngraph)toatargettopologygraphhasalreadybeenmade.Theobjectiveisto

assign“links”(i.e.,signalnets)tochannelsbetweendevices;aswiththeVirtualWiresconcept,specific

timeslicesforachannelcanbeassignedtomultiplelinksaslongasnotwolinksneedtotransmitsignals

atthesametime.TheTIERSalgorithmusesagreedymethodtoorderthelinksandthenrouteseachlink

inthescheduledorderwhilereservingchannelresources;factorsofupto2.5improvementinsystem

cycletimeareachieved.

Chang,etal.[113]addressthecombinedissuesofroutabilityandsystemtimingbyapplying

layout-drivenlogicresynthesistechniques.Foragivenwirethatcannotberouted,“alternativewires”

andalternativefunctionsareidentified,suchthatthegivenunroutablewirecanberemovedfromthe

circuitandreplacedwithanewwire(orwires)ornewlogicwithoutaffectingfunctionality.Chengetal.

estimatethatbetween30%and50%ofwireshaveso-called“triple-wirealternatives”(i.e.,

replacementsconsistingofthreeorfewerwires).Theirmethodfirstroutesthewiresthatdonothave

anyalternativesthenreplacesanyunroutablewirewithavailablealternatives.Systemtimingcanbe

improvedbyreplacinglongwireswithshorteralternatives.

8Conclusions

Reconfigurablecomputingoffersamiddlegroundbetweensoftware-basedsystemsandASIC

implementations,andisoftenabletocombineimportantbenefitsofboth.Implementationsareableto

avoidoverheadssuchasunnecessarydatatransfers,decodingandcontrolmandatoryin

microprocessors,anddesignscanbeoptimizedonabasisspecifictoanapplication,aprobleminstance

orevenanexecution.Usingthistechnology,itispossibletoachievesize,performance,cost,orpower

improvementsovermoreconventionalcomputingtechnologies.

9Acknowledgments

TheauthorswouldliketothankYM.LamforhishelpinpreparingthismanuscriptandProf.WayneLuk

(ImperialCollege)forhisproofreadingofthisarticle.

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