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Reconfigurable Hardware SpaceCube & Beyond
by Gordon Seagrave
Chief Architect and Inventor
Agenda
Introduction to Reconfigurable Hardware
My background The “AHA” moments SpaceCube Details Beyond SpaceCube
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Introducing SpaceCubeImagine validated off-the-shelf hardware With common interfaces Instantly configurable to any mission requirements
Configurable via GSE or while in Flight Inexpensive Easy to develop on (IP Reuse) 4” X 4”
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MAPLD 2009 Gordonicus LLC 4
Xilinx In SpaceA Quantum Leap
High Speed DSP Algorithm Processing Image Processing Pose Estimation Algorithms Communications / Radio Data Encryption / Decryption Waveform Processing Instrument Data Validation and Compression Application Reconfigurable While in Flight
Reconfigurable Hardware Platforms
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Dual Xilinx QV4 FX60
PIC
Controller Reconfigurable Fabric
Flexible I/O
Bus I/O
SpaceCube
16 High Speed Serial
Stacking Connector Custom
Xilinx QV4 FX60
LEON3FT
12 SpaceWire Ports
3U cPCI w / HighSpeed Serial I/O
Next Generation Reconfigurable ComputerPCI-104 Reconfigurable Computer
Xilinx SiRF
LEON3FT
Stacking Connector
Stacking Connector PCI & High Speed Serdes
Born on a mission to deliver reconfigurable hardware
6
Background Education Phase
Drexel – computer engineering Corporation while in College: Abyss Microcontroller phase 8051 & mc 68hc11
DSP Phase TI and Analog Devices
FPGA Phase Schematic Entry then VHDL & Verilog
SPACE Orbital Sciences – FPGA & SDRAM JHUAPL – 5 FPGAs for MRO , stackable architecture DPU Goddard -- HRV - classic design with v2 1000 new arch. QuikTOMs,OV4,OV3,Messenger,NewHorizons,MRO,LRO,NewStar GEO, COTS etc.
7
The “AHA” Moments
8
9
Xilinx Architectures
HRV - Classic Voter Scheme
SpaceCube
Conservation of Space
10
Championing the Development of SpaceCube
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The “Secret” SpaceCube Brass Boards
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Important Features Xilinx Brings to Space
Operates internally > 400Mhz Core 1.2VDC IBM PowerPC RISC processor
PPC405 Auxiliary processor unit
interface (co processor) Multiple Ethernet MACs Reconfigurablity
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PPC405 Supported Operating Systems
VxWORKS BlueCat Linux RTEMS
Mixed operating system scheme supported
14
SpaceCube Approach Dual Back to Back Xilinx takes
advantage of symmetric architecture
128M x 16 SDRAM
128M x 16 SDRAM
PPC405
PPC405
V4 FX60
128M x 16 SDRAM
128M x 16 SDRAM
PPC405
PPC405
V4 FX60
Top side
Bottom side
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Processor Board Dataflow
Xilinx V4 FX60
Node 4 = QUAD 4
IBM PowerPC405
450MHz
Node 3 = QUAD 3
IBM PowerPC405
450MHz
Node 2 = QUAD 2
IBM PowerPC405
450MHz
128M x 16
SDRAM256MB
3DPlus
Node 1 = QUAD 1
IBM PowerPC405
450MHz
External Connectors
Internal Stacking Connector
8 SpaceWire Ports or 16 LVDS / RS422 LVDS
Xilinx V4 FX60
Radiation Immune RISC Microcontroller
Housekeeping
Data Validation
512MB FLASH
3DPlus
32kB RAM
Honeywell
32kB PROM
3DPlus
External Connectors
Internal Stacking Connector
8 SpaceWire Ports or 16 LVDS / RS422 LVDS
DATA IN
QuadDATA OUT
DATA OUT
512MB FLASH
3DPlus
128M x 16
SDRAM256MB
3DPlus
128M x 16
SDRAM256MB
3DPlus
128M x 16
SDRAM256MB
3DPlus
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Data IN: Shared Nodes
Top Xilinx
Bottom Xilinx
Data IN
“shared via”
Common input to 4 processing nodes.
Nodes physically separated
Provides maximum protection from multi-bit single event upsets (SEUs).
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Node Links
PPC
Top Xilinx
Bottom Xilinx
Quad 1
PPC
Quad 2
PPC
Quad 3
PPC
Quad 4
4 Processing Nodes are divided into Quads
The Quads have high speed Intra-connections
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Voted Data Out
Top Xilinx
Bottom Xilinx
Matched Length
VOTER
Data OUT
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Data Validation : Quad redundancy mode
Top Xilinx
Bottom Xilinx
Voting
AeroFlex FPGA
ResultMVO_C
MVO_A
MVO_D
MVO_B
Quad 1 Quad 2
Quad 2 Quad 1
Stacking Connector (LVDM & LVTTL)
External Inputs (LVDS / RS422)
To other boards in box
To external devices
A small, radiation hardened, microcontroller provides the synchronization to allow for voting in this multiprocessor system when operating in the quadruple mode redundancy approach
The PPCs may be configured for Quad redundancy processing where the outputs are voted
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Top Xilinx
Bottom Xilinx
PPC1 PPC2
PPC3 PPC4
AeroFlex FPGA
Left Side Signals
Right Side Signals
(Left and Right Side Signal directions are user configurable)
The PPCs may act as 4 unique engines performing 4 unique tasks where the outputs are not voted.
Four independent parallel processing nodes
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RISC Microcontroller Housekeeping
PPC
Top Xilinx
Bottom Xilinx
RISC Micro
controller
AeroFlex FPGA
Quad 3
PPC
Quad 4
Quad 1 Quad 2
PPCPPC
Each Xilinx Virtex 4 houses (2) PPCs
Xilinx FPGAs are monitored, programmed and synchronized by a RISC microcontroller in the Aeroflex FPGA
The Xilinx FPGAs implement self-scrubbing, monitored by the RISC Microcontroller
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SpaceCube Node Partial or Full Reconfiguration
A Singe Node can be reconfigured with•PPC Operating system•PPC application code or •Xilinx fabric reconfiguration
WITHOUT disruption to the other nodes
FLASH
PPC
Top Xilinx
Bottom Xilinx
RISC Micro
controller
AeroFlex FPGA
Quad 1
PPC
Quad 2
PPC
Quad 3
PPC
Quad 4
Serial Port
SelectMap
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RISC MicrocontrollerSoftware Modification
New RISC Microcontroller software is loaded into a specific section of RAM
RAM
RISC Micro
controller
AeroFlex FPGAFLASHROM
FLASH
Uplink
•After reset, ROM is loaded into RAM•Processor boots from top half of RAM•Software looks to FLASH for updates•Loads updates into bottom half of RAM•Processor jumps to bottom half of RAM•New code patches can be received via uplink
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INTERNAL INTERFACES
Mission Module
text
I2C (pri & redun)
400kbps2.5 SW
1.5V 2.5V 3.3V
3.3 SW
+/- 12V
5 SW
LVDM 8 Channels
>100 Mbps
Xilinx Data In: 12 per PPC Node
RISC Microcontroller I/O (30)
Power Supply Module
POR_N
RISC I/OLVTTL (30)
Bir-DirLVDM(8)
Power
I2C x 2 PWR
Xilinx INLVTTL (48)
Processor Module
PWR
STACKING CONNECTOR
• Slice to Slice communications are handled via a combination of configurable high and low speed serial links.
– Redundant I2C Busses (400 Kb/S) provide for low speed command and telemetry functions
– High Speed LVDM busses such as Ethernet or SpaceWire provide for high speed communications (125Mb/s – 250 Mb/s per bus)
• 8 high speed busses and two low speed busses on the stack.
• I2C Communication is from hard microcontroller to hard microcontroller for critical functions
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4 x 4 inch Processor Board
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Stacked Architecture Allows Endless Flexibility
•SpaceCube uses a stacked architecture
composed of cards or “slices” connected via a connector running the length of the stack
•Slices can be made redundant and the stacking architecture allows any slice to communicate with any other slice – thus allowing card level redundancy.
•Custom Slices Stack onto the SpaceCube Processor and LVPS Slices
•Small card size (4x4 inches) means mass is minimal. (<2Kg for minimum configuration)
LVPC
Processor
Project Module
Processor
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Stackable Architecture
LVPC 2
SCuP 1
SCuP 2RNS
BD
LVPC 1
Minimum Configuration = 4 x 4 x 3 inches• Scup • LVPC
• SpaceCube uses a stacked architecture composed of cards or “slices” connected via a connector running the length of the stack
• Slices can be made redundant and the stacking architecture allows any slice to communicate with any other slice – thus allowing card level redundancy.
• Each slice has an individual enclosure which encloses it on 5 sides.
• Slices are stacked in whatever order desired and covered by a top plate.
• Up to two Power slices can be combined in a stack (one on the top, one on the bottom) to allow for a complete “warm back-up” system.
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MiniCube Facilitates AeroFlex FPGA Development
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SpaceCube PackagingProcessor Slice and CCA
•External interface thru two MIL-DTL-83518 (Micro-D) connectors
•The Processor board is supported by 2 stiffeners and 2 integral stand-offs.
PROCESSOR PWB EDU, 2098673
Primary Side
Secondary Side
•Designed per IPC-2222 and Fabricated per IPC-6012
•Multi-layer (18 layers) board material construction per IPC-4101
•PWB, 2098673, size 4.00W x 4.00L x .093T (inch) (Polyimide-glass laminate)
•Up to 2 oz top & bottom, and internal signal & ground planes utilized for thermal management of components.
•Maximum component heights: 0.79 inch (primary side), and 0.21 inch (secondary side)
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CENTRAL PROCESSORS
4 x 450 MHz PowerPC™ 405, 32-bit RISC processors:
2 x Xilinx XC4VFX60
Redundant to handle SEFI
32K bytes of secondary (L2) on-die cache
Common Processor Features are:-
700+ DMIPS RISC core
32-bit Harvard architecture
16 KB 2-way set-associative instruction and data caches
Auxiliary Processor Unit (APU) controller
1.2V core voltage
RECONFIGURABLE RESOURCES
2 x 56,880 logic cells
2 x 25,280 slices
2 x 4,176 Kb block RAM
232 18K block RAMs
Example: Helion AES core
447 slices, 10 block RAM, 2548Mbps performance
SDRAM
3Dplus stacked SDRAM
8 Gbit 75 MHz
Each PPC processor has 2 Gbit dedicated.
ETHERNET CAPACITY
2 x 10-Base-T Ethernet Interfaces
Physical Interface is Hardened/Transformer coupled
IEEE 802.3 compatible
Ethernet MACS are built in to Virtex
DIGITAL SIGNAL PROCESSING
128 XtremeDSP Slices
18-bit by 18-bit, two's complement multiplier with full precision 36-bit result, sign extended to 48 bits.
FLASH
256 Mbyte of Flash
application storage
Flash has separate power switching.
Allows Flash to be powered off when not in use.
BOOT PROM
32 Kbyte of Rad-Hard Boot PROM for SpaceRISC Microcontroller
Utilized at startup/reconfiguration as a “Hard” source of code
SOFTWARE SUPPORT
Support for Linux, VxWorks
WindRiver
MontaVista, BlueCat
GNU GCC Compiler
SpaceCube Specifications
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SERIAL INTERFACES32 x LVDS serial pairs:
Support DS Ethernet, SpaceWire, or custom interface.
16550 compatible UARTs
Aeroflex LVDS drivers and Receivers
RS422 can be substituted for LVDS if desired
STACKING CONNECTOR INTERFACE122 pins ICI Solder-mount Stacking Connector
Design uses no backplane or motherboard.
Low speed internal bus – 400Kbps Redundant I2C
High speed LVDM bus – 8 Bidirectional Pairs
Power Pins 3.3V, 5V
RAD-HARD SCRUBBER2 UT6325 RadHard Eclipse FPGAs
320,000 usable system gates
Incorporates a SpaceRISC Microcontroller to monitor Xilinx Devices
RadHard to 300K rad(Si)/sec
OTHER PERIPHERAL INTERFACESAvailable through stacking connector by additional card slices
Low Voltage Power Converter card sliceSame board size as processor
Provides low voltages from spacecraft bus voltage
Has 1553 interface, transformers and signal drivers
ELECTRICAL SPECIFICATION21V to 35V voltage input through optional low voltage power
converter card slice
Power Slice can provide:
+5V@ 2 Amps
+3.3V@ 6 Amps
+2.5V@ 4 Amps
all voltages are tolerant to +10% / -10%
SAFETYCore Voltage power is switched separately to handle any potential
latchup conditions.
ENVIRONMENTAL SPECIFICATION-20°C to +55°C (operating Baseplate temperature)
-40°C to +85°C (storage baseplate temperature)
10% to 90% Relative Humidity, non-condensing (storage)
MECHANICAL SPECIFICATION4 inches x 4 inches (PCB)
Box slice 4.25 inches x 4.25 inches x 1.25 inches/slice
single board, double sided
I/O connectors:122 pin, Stacking
2 x 51 pin MDM LVDS/Debug (Processor)
1x 37 pin MDM 422/Debug (Power)
SpaceCube Specifications
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RNS SpaceCube Stacks
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NASA Rover in Antarctica
First Flight SpaceCube
Processor Card Flight Box
Mechanical: 7.5-lbs, 5”x5”x7”Power: 37W (STS-125 Application)
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• Successful flight demonstration on STS-125
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SpaceCube on Shuttle Mule
2nd Mission 9 mo. Later MISSE-7
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• Launched November 2009
Reconfigurable Hardware Platform 2nd Generation
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• Reconfigurable State-of-the-Art High Speed Data Processing Capabilities
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Features
STS125 Mission
No blind and buried viasFlight Board meets NASA and IPC 6012 class 3 standards
• 1553• 100 Mb Ethernet • 200 Mb Spacewire routers• COTs Interfaces: cPCI (33MHz) & High Speed SERDES on P2
This hardware platform provides these needs by combining:
• A Rad Hard LEON3FT Processor• 1 Gbyte protected SDRAM
Aeroflex
LEON3FT
UT699
Aeroflex
LEON3FT
UT699
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SPECIFICATIONS5 PROCESSORS
LEON3FT ASIC AeroFlex UT699 SPARCTM V8/LEON
3FT 66 MHz Up to 52.8 MIPS Floating Point and MMU TID: 300 krad (Si) SEL Immune >110 MeV-cm2/mg
4 x 350 MHz PowerPC™ 405 Heritage Implementation Dual Xilinx QV4 FX60 32 bit RISC processors 700+ DMIPS TID: 250 krad (Si) SEL Immune >110 MeV-cm2/mg SEFI: 1.5E-6 Upsets/device/day (GEO)
STANDARD I/O INTERFACES
10 SPACEWIRE PORTS Up to 200Mbps (Configurable) Supports Cross stapping Multiple configurations
CompactPCI 32 Bit, 33MHz Master and Slave Mode Supported PCI 2.2 Compliant NASA Hypertronics connectors
Mil-Std-1553 A/B Mil-Std-1553 BC/RT/MT Based on the Actel Core1553 IP
CONSOLE PORT LEON3FT UART Rate configurable
FRONT PANEL DEVELOPMENT / DEBUG PORTS
DEVELOPMENT LEON3FT 10T/100 Ethernet port Xilinx 10T/100 Ethernet portDEBUG LEON Debug Serial Port RTAX Debug Serial Port Xilinx Debug Serial Port JTAG
MEMORY
1 GByte SDRAM Reed Solomon Protected corrects for 2
nibble upsets8 GByte FLASH stored in two banks16 Gbit SDRAM 4Gbits per PPC4052 MBbyte SRAM Protected (Self Scrubbing)32 KByte PROM
CONFIGURABLE I/O
10 RS422/LVDS Transmit Ports Xilinx configured (Quad redundant)
10 RS422/LVDS Receive Ports Xilinx configured (Quad redundant)
39 Xilinx Backplane I/O12 Actel I/O2 LEON GPIO2 Backplane Spacewire Backplane Ethernet
SMALL SIZE
DIMENSIONS
Standard 3U cPCI Single slot front panel configuration
supports: 4 SpaceWire, 1553 A/B , Console port and Debug.
Dual slot front panel configuration supports additional SpaceWire ports.
LOW POWER
LEON3FT 2.5Volt CoreXilinx 1.2Volt Core
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SPECIFICATIONS5 PROCESSORS
LEON3FT ASIC AeroFlex UT699 SPARCTM V8/LEON
3FT 66 MHz Up to 52.8 MIPS Floating Point and MMU TID: 300 krad (Si) SEL Immune >110 MeV-cm2/mg
4 x 350 MHz PowerPC™ 405 Heritage Implementation Dual Xilinx QV4 FX60 32 bit RISC processors 700+ DMIPS TID: 250 krad (Si) SEL Immune >110 MeV-cm2/mg SEFI: 1.5E-6 Upsets/device/day (GEO)
STANDARD I/O INTERFACES
10 SPACEWIRE PORTS Up to 200Mbps (Configurable) Supports Cross stapping Multiple configurations
CompactPCI 32 Bit, 33MHz Master and Slave Mode Supported PCI 2.2 Compliant NASA Hypertronics connectors
Mil-Std-1553 A/B Mil-Std-1553 BC/RT/MT Based on the Actel Core1553 IP
CONSOLE PORT LEON3FT UART Rate configurable
FRONT PANEL DEVELOPMENT / DEBUG PORTS
DEVELOPMENT LEON3FT 10T/100 Ethernet port Xilinx 10T/100 Ethernet portDEBUG LEON Debug Serial Port RTAX Debug Serial Port Xilinx Debug Serial Port JTAG
MEMORY
1 GByte SDRAM Reed Solomon Protected corrects for 2
nibble upsets8 GByte FLASH stored in two banks16 Gbit SDRAM 4Gbits per PPC4052 MBbyte SRAM Protected (Self Scrubbing)32 KByte PROM
CONFIGURABLE I/O
10 RS422/LVDS Transmit Ports Xilinx configured (Quad redundant)
10 RS422/LVDS Receive Ports Xilinx configured (Quad redundant)
39 Xilinx Backplane I/O12 Actel I/O2 LEON GPIO2 Backplane Spacewire Backplane Ethernet
SMALL SIZE
DIMENSIONS
Standard 3U cPCI Single slot front panel configuration
supports: 4 SpaceWire, 1553 A/B , Console port and Debug.
Dual slot front panel configuration supports additional SpaceWire ports.
LOW POWER
LEON3FT 2.5Volt CoreXilinx 1.2Volt Core
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LEON3FT PROCESSOR & MEMORY
LEON3FTAeroflex UT699
2MByte SRAM(Internal EDAC)
32KB PROM
1GByte SDRAM(Reed Solomon)
4GByte FLASH
Actel RTAX
TID: 300 krad (Si)SEL Immune >110 MeV-cm2/mg
52.8 MIPS
4GByte FLASH
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Xilinx QV4 FX60
PPC405
PPC405
Xilinx QV4 FX60
XILINX PPC405 PROCESSORS & MEMORY
PPC405
512MByte SDRAM
200Mbps SpaceWire(4)
Dual Xilinx QV4 FX60
PPC405700 DMIPs
TID: 250 krad (Si) SEL Immune >110 MeV-cm2/mgSEFI: 1.5E-6 Upsets/device/day (GEO)
512MByte SDRAM
512MByte SDRAM
512MByte SDRAM
LEON3FTAeroflex UT699
Based on Heritage Architecture Implementation
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STANDARD INTERFACES
CompactPCI Console Port Async UART 1553 SpaceWire
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CompactPCIMIL-STD-1553 A/B LEON3FT Console Port
Actel RTAX2000
LEON3FT
AMBA BUS AMBA BUS
1553 A/BTransceiver
Aeroflex UT63M143
AMBA 1553 Core
FRONT
PANEL
MIL-STD-1553 A/B
cP
CI
CO
NN
EC
TO
RS
32 Bit 33 MHz
CompactPCI
LEON RS422 Console Port
AMBA Bus Bridge via
LEON Memory Bus
READY
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SpaceWire Ports
LEON3FT
SpW Router 5 Port
SpW Router 5 Port
RTAX
200Mbps Configurable
200/100/50 Mbps200Mbps
Front Panel Conn. Thru-hole Jumpers
FRONT PANEL
CPCI
P2
Xilinx
200Mbps
10 Front Panel
4 Backplane
2 Backplane via Jumpers
200Mbps Configurable
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RADCLK
33MHz66MHz
100MHz
LEON_3FT66MHz
Ethernet MII
SpaceWire
SpaceWire
SelectMAP
4 GByteFLASH
2MB_ EDACSRAM
ACTELRTAX2000
CG624
4 GByteFLASH
Data
cPC
I
DebugSerial Port & JTAG
32KROM
23Kx8
512MB
SDRAM256Mx16
Xilinx1a Xilinx1b Xilinx2a Xilinx2b
RS 422 Outputs
RS 422 Inputs
66MHz33MHz
Addr
1553Driver
1553Transformer
1553Transformer
1GB_ EDACSDRAM
256Mx48
RS 422 Console Port5 Port SpW
Router
5 Port SpW Router
SpaceWire
LVDS / RS422 Front Panel Transceivers
8 RX8 TX
2 Backplane GPIO
200MHz
12 Backplane GPIO
512MB
SDRAM256Mx16
512MB
SDRAM256Mx16
512MB
SDRAM256Mx16
(Front Panel)
(Front Panel)
(Front Panel)
(Front Panel)
(Front Panel)
(Front Panel)
(Front Panel)
Eth
erne
t MII
(P2) 39 Backplane I /O
Front Panel & Backplane
(2 Backplane)
PPC 405uP
512MB PPC 405uP
512MB PPC 405uP
512MB
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Application
LEON3FT RTAX SpW Router
DownLink0
PPC 405uP
512MB
SpaceWire
SpaceWireSpW Router
DownLink1
MissionCrd0
MissionCrd1
MissionCrd2
MissionCrd3
PC/104 Design
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FUTURE
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Dawn of a New Era in Spacecraft Computing
Most spacecraft flying today have less computing power than cheapest laptop in the market.
We can no longer afford this scenario. Spacecraft computing needs to advance to allow
continuation of our vision of space exploration and to understand and protect Earth.
Reconfigurable computing is the solution. The Radiation Hard By Design FPGA by Xilinx (SIRF
chip) enables a new business model. We are committed to pioneer this new era of spacecraft
computing.
MetamorfX New company will bring together best in industry. It will shape a new computing paradigm in space.
Standard spacecraft super computing platform. Robust application development process. Recognized quality assurance methods. New development tools and libraries. Training
Extreme computing in space will push the envelope in high performance computing.
MetamorfX – The New Shape of Spacecraft Computing