Reducing memory latency using MRAM

Suzanne ReedLisa Trova

Outline● Problems with existing memory

○ DRAM○ SRAM

● MRAM - Mechanics● Read/Write Strategies● Benefits/Cons of MRAM● Alternatives to MRAM

DRAM● Created with a

single transistor and capacitor

● Small area -> densely packed

http://fourier.eng.hmc.edu/e85_old/lectures/memory/node1.html

DRAM● Capacitor holds data, but needs to be

refreshed as capacitance degrades (approx. 8 ms)

● High power consumption on refreshing

SRAM● Created with 6, 8,

or 12 transistors ● Large area in layout● Buffering on

signals to prevent degradation due to large capacitances

http://upload.wikimedia.org/wikipedia/commons/3/31/SRAM_Cell_%286_Transistors%29.svg

SRAM● Used in cache● Single clock cycle access, with addressing

overhead● Power hungry during switching● Volatile

Problems with DRAM/SRAM● Volatile memory does not save state after

power off● Speed / layout size tradeoff● Modern designs are limited by memory

speed, size, and address computation

Universal Memory● Currently, DRAM, SRAM, and

Flash Memory are combined to provide optimal performance

● The goal is to have one memory type that is cost-effective, high-speed, high-density, and low-power. http://spectrum.ieee.org/img/unime

m02r-1337284470946.jpg

Origin of MRAM1955 - Magnetic core memory1988 - Albert Fert and Peter Gruenberg: discovered Giant Magnetoresistance 1995 - Motorola/Freescale started work on MRAM2000 - IBM and Infineon started MRAM development together2003 - first MRAM chip (128kbit)

MRAM● Data is stored as

magnetic charges● Reference layer

holds fixed magnetic polarity

● Storage layer changes polarity to store data.

http://www.crocus-technology.com/images_crocus/tech-figure-mram.jpg

Anatomy of MRAM

http://upload.wikimedia.org/wikipedia/commons/f/f9/MRAM-Cell-Simplified.svg

MRAM Read Strategy● Bit values are read by

comparing the resistance value of a cell to midway reference value

● Resistance measurement is taken by measuring current through the cell http://www.crocus-

technology.com/pdf/MRAM_CR_v5a.pdf

MRAM Write Strategies● Stoner-Wohlfarth theory of coherent

rotation● Toggling ● Current Line Cladding● Thermally Assisted● Precessional Switching● Current Induced Magnetic Switching● Spin Transfer Torque

Toggle MRAM● Freescale● A pulse sequence to alternate data in

memory● Only bits at the intersection of two write

lines will be written● Uses Savtchenko switching for toggle

Savtchenko Switching● Savtchenko switching

provides free synthetic antiferromagnet and a 45 degree orientation to prevent “half-disturb” problem

● Discs orient themselves to be orthogonal Freescale

Spin Transfer Torque MRAM● Current is passed

through the MTJ● Current becomes

polarized● Conserves angular

momentum by using first layer to exert spin on free layer

http://www.eetimes.com/author.asp?section_id=36&doc_id=1323466

ComparisonDRAM SRAM (6T) Flash MRAM

Cell Size [F2] 8-12 50-80 4-11 6-20

Non-Volatile No No Yes Yes

Endurance write/read ∞/∞ ∞/∞ 106/∞ >1015/∞

Non Destructive Read No Partial Yes Yes

Direct Overwrite Yes Yes No Yes

Signal Margin 100-200mV 100-200 mV Δ current 60-200% R

Write/Read 50 ns/50 ns 8 ns/8 ns 200 μs/60 ns 30 ns/30 ns

Erase 50 ns 8 ns 1-100 ms (blocks) 30 ns

Transistor Performance Low High High Voltage (HV) High

Scalability Limits Capacitor 6 Transistors Tunnel Oxide/HV Current Density

http://www.crocus-technology.com/pdf/MRAM_CR_v5a.pdf

Benefits of MRAM● Very low power consumption● Unlimited endurance● Long data retention (non volatile)● Compromise for speed and area

Limitations of MRAM● Slower than SRAM● Lower cell density than DRAM● No proven way to fabricate that is fast,

reliable, and inexpensive

D-MRAM● Improved DRAM by

adding MRAM elements

● Removes need to refresh all data, reducing high power consumption of DRAM http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&ar

number=6513809

*RAM● Ferroelectric - FRAM ● Phase-change - PRAM● Nano - NRAM● Strain-Mediated Magnetoelectric - SME -

RAM● Thyristor - TRAM● Zero-Capacitor - ZRAM

FRAM vs. MRAM● Smaller memory size● Faster Write time● Slower Read time than MRAM and DRAM● Write power consumption 2333 times

smaller○ FRAM: 0.03 pJ per bit○ MRAM: 70 pJ per bit

SME-RAM vs. MRAM● Significantly larger size of memory >> 1 GB

compared to 16 Mb● Half of the write time of MRAM● Equivalent Read time● 4,375,000 times smaller write power

consumption○ SME-RAM : 0.00016 pJ per bit○ MRAM : 70 pJ per bit

MRAM Market Timeline2004 - Freescale begins selling MRAM2006 - 4-Mbit MRAM developed by Freescale2008 - 1 Gbit MRAM by Toshiba2008 - $6M DARPA grant for STT-RAM research2011 - Toshiba uses MRAM as Cache

Recent Developments2013 - first STT-MRAM chip by Buffalo Memory2014 - January - ARM uses Magnetic Logic Unit technology to utilize MRAM2014 June - STT-MRAM based microprocessor cache memory

Current MRAM● Produced by Everspin● Uses Spin Torque writing● 1600 MT/s at a 800 MHz clock● used by Buffalo Memory in SATA III SSD

chip to improve access time and power consumption

Conclusion● Currently being used in some new chips● Lot of room for use in market● Experts predict will flood the market in

2015-2016● Some of the newer alternatives have better

performance

Resources1. Freescale, 2006. Magnetoresistive Random Access Memory [Online]. Available:

http://www.signallake.com/innovation/MRAMWP.pdf2. Future Electronics. What is MRAM? [Online]. Available: http://www.futureelectronics.com/en/memory/mram.aspx3. J. L. Hennessy, D. A. Patterson, “Memory Hierarchy Design,” in Computer Architecture: A Quantitative Approach, 5th ed.

Waltham, MA: Elsevier, 2012, ch. 2, sec.3, pp 96-103.4. J. M. Hu, “High-density magnetoresistive random access memory operating at ultralow voltage at room temperature,” in

Nature Communications, 2011.5. J. M. Slaughter, et al.“Toggle and Spin-Torque MRAM : Status and Outlook” in Magnetic Society of Japan, 2010, pp. 171-

176.6. MRAM history, 2014. MRAM-Info [Online]. Available: www.mram-info.com/history7. N. H. Weste, D. M. Harris, “Array Subsystems,” in CMOS VLSI Design: A Circuits and Systems Perspective, 4th ed.

Boston, MA; Addison-Wesley, 2011, ch. 12, sec 2-3, pp 498-526.8. G. Lee. (2012, May 17). The Quest for a Universal Memory [Online]. Available:

http://spectrum.ieee.org/semiconductors/memory/the-quest-for-a-universal-memory9. CROCUS Technology. (2013). MRAM Basics [online]. Available: http://www.crocus-

technology.com/crocus_technology_MRAM_basics.php10. R.C. Sousa, I.L. Prejbeanu, C. R. Physique 6 (2005). Non-volatile magnetic random access memories (MRAM) [Online].

Available: http://www.crocus-technology.com/pdf/MRAM_CR_v5a.pdf11. H. Noguchi, K. Nomura. D–MRAM Cache: Enhancing Energy Efficiency with 3T–1MTJ DRAM / MRAM Hybrid Memory

[Online]. Available: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6513809&tag=1.