Redundant Representations 1 Redundant Representations Ivor Page 1 6.1 The Binary Signed Digit Representation (BSD) Conventional unsigned binary is a positional number system with radix two and digit set {0, 1}. In any redundant system the digit set has larger cardinality (more values) than the radix. In the BSD system, the digit set is [−1, 1] = {−1, 0, 1}, usually written { 1, 0, 1}. Each number in a BSD system is represented by two binary vectors, where each digit of the number A is represented by its positive and negative components, A + = a + k-1 ,a + k-2 , ··· ,a + 1 ,a + 0 A - = a - k-1 ,a - k-2 , ··· ,a - 1 ,a - 0 1 University of Texas at Dallas
Transcript
Redundant Representations 1
Redundant Representations
Ivor Page1
6.1 The Binary Signed Digit Representation (BSD)
Conventional unsigned binary is a positional number system with radixtwo and digit set {0, 1}. In any redundant system the digit set has largercardinality (more values) than the radix. In the BSD system, the digitset is [−1, 1] = {−1, 0, 1}, usually written {1, 0, 1}. Each number in aBSD system is represented by two binary vectors, where each digit ofthe number A is represented by its positive and negative components,
A+ = a+k−1, a
+k−2, · · · , a+
1 , a+0
A− = a−k−1, a−k−2, · · · , a−1 , a−0
1University of Texas at Dallas
Redundant Representations 2
The following table shows the most common assignment of values tothese bits:
Value a+ a−
1 1 00 0 01 0 1
It is easy to see that the system is redundant. For example, the dec-imal value +5 can be represented by 000101, 000111, 001011, 001101,001111, etc.
The range of a k digit BSD system is symmetrical: +2k −1 to −2k −1.
Conversion from 2’s complement to BSD is trivial. Recall the value ofa 2’s complement number:
Value of A = −ak−12k−1 +k−2∑
i=0ai2
i
Redundant Representations 3
The equivalent BSD number X has x−k−1 = ak−1, x+
k+1 = 0 and, for all0 ≤ i < k−1, x+
i = ai and x−i = 0: the sign digit of the 2’s complement
number is copied into the negative part of the corresponding positionin the BSD number and the remaining bits of the 2’s complement num-ber are copied into the corresponding positive components of the BSDnumber. Figure 1 illustrates the process.
ak-1 ak-2 ak-3 ak-4 ai a1 a0
x-k-1 0 0 0 0 0 0
0 x+k-2 x+
k-3 x+k-4 x+
i x+1 x+
0X+
X-
A
Figure 1: Conversion of 2’s complement value A to BSD value X
Redundant Representations 4
Conversion of the BSD number X to 2’s complement binary requiresthe subtraction of the bit vectors X− and X+ using a standard 2’scomplement adder. This is usually performed by a carry-look-aheadadder having O(logk) processing time.
6.2 Carry Ripple Elimination
Redundant systems limit the carry propagation path to only 2 bits andenable constant time addition, independent of the number of bits beingadded.
The adder for two BSD numbers, X and Y , comprises two stages. Inthe first stage of digit position i, input bits xi and yi are combined toform an intermediate sum si and an intermediate carry ci+1. These areBSD values. In the second stage, the sum bit si is combined with thecarry-in from the previous stage, ci, to generate the result bit zi.
Redundant Representations 5
Figure 2 shows the block diagram of the adder. Note that, in the text,the adder is shown as having three stages.
xi+1 yi+1 xi yi xi-1 yi-1
si
ci+1
ei
ci
zi+1 zi
Stage 1
Stage 2
ei+1
Figure 2: Two stage BSD Adder
Redundant Representations 6
Redundancy enables us to choose the values of the intermediate sumand carry so that the second stage can absorb the carry from the po-sition to the right. Below is a table of possible intermediate values forthe 9 values of xi and yi.
Inputs Intermediate Results Intermediate Resultsfor ci ∈ {0, 1} for ci ∈ {0, 1}
Consider the case where the expected carry into this position is knownto be either a 0 or a 1. This corresponds to the first column of inter-mediate results in the table above. There are four cases in which theredundancy gives us a choice of intermediate results.
In all nine cases, if a carry-in of 1 occurs, the intermediate results in thefirst column enable the carry-in to be absorbed without further carrypropagation since the intermediate sum in each case is in {0, 1}.
Similarly, if the carry-in is known to be either a 0 or a 1, the interme-diate results from the second column enable the carry to be absorbedwithout further carry propagation.
In general, we cannot know the exact value of the carry input to anystage until it is generated, but we can bound its value into one of thetwo subsets, {1, 0} or {0, 1}, simply by examining the values of theinputs of the position to the immediate right:
In three cases the carry out of any digit position is in {0, 1}, in threeothers it is in {0, 1}. In the remaining three, the carry must be zero.The logic signal ei passes between the first stages of neighboring pairsof digit positions in the BSD adder to inform position i of the carry-insubset. This signal does not propagate along the adder.
Redundant Representations 9
The longest paths through the adder are shown in bold in Figure 3.
xi+1 yi+1 xi yi
xi-1 yi-1
si
ci+1
ei
ci
zi+1 zi
Stage 1
Stage 2
ei+1
Figure 3: Longest Paths in BSD Adder
Redundant Representations 10
The three cases where the carry is zero can be assigned to either subsetin the form of don’t care input vectors to the logic circuit.
The e and c signals have been left-shifted so each column of e, s andc values, are the inputs to a digit position. The redundancy is usedin the 21, 25, and 28 positions, where the e signals are used to selectthe appropriate intermediate sum and carry signals for those stages. Ineach case the carry is absorbed in the second stage.
Redundant Representations 11
It is instructive to carry out such an example on paper by dealing withthe digit positions in random order. Doing so illustrates the fact thatthe addition process takes constant time.
Since BSD representation requires double the number of bits used in the2’s complement scheme, it is impractical to consider its use for storingall values within a computer. Values must therefore be converted toBSD before calculations are performed, and results must be convertedback to 2’s complement. Since conversion from BSD to 2’s complementrequires a log-time addition, nothing is gained by using BSD if onlypairs of values are operated on.
The real advantage of BSD, and other competing redundant numbersystems, comes when many arithmetic operations must be performedwithin the system before results must be converted back to 2’s comple-ment. One such case is the multiplication of integers. If two k bit valuesare to be multiplied, the two arguments can be converted in constanttime (actually only one of them needs to be converted) and the BSDscheme can be used to sum the k partial products.
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If we have k/2 BSD adders, then pairs of partial products can be added,giving k/2 intermediate results. These can then be added in pairs, andso on. The result of such a scheme is obtained in O(log k) time. Con-version back to 2’s complement also takes O(log k) time, so multiply isachieved in log time.
Further details of this multiplier will be considered when we get to thesection on multiply. By using techniques invented by Booth the numberof partial products can be reduced by a factor of 2 or 4 without undulycomplicating the logic of the multiplier.
Redundant Representations 13
6.3 General Redundant Systems
6.3.1 Digit Sets
We have seen the BSD system which uses the digit set {1, 0, 1}, alsowritten [−1, 1]. Many other digit sets are possible, including both non-redundant and redundant number systems. Avizienis defined a class ofnumber systems, known as Ordinary Sign Digit (OSD) systems, whichhave symmetrical digit sets, [−α, α]. and radix r > 2, where �r/2�+1 <α < r − 1. These number systems allow at least �r/2� + 3 differentdigit values and are therefore redundant (non-redundant systems haveexactly r digit values).
More general redundant systems have been studied more recently withdigit sets, [−α, β]. These are known as Generalized Sign-Digit (GSD)representations. Examples are the radix 2 BSD system with digit set[−1, 1], the high redundancy radix 2 system with digit set [−7, 7], andthe radix 2 system with digit set [0, 2]. None of these is an OSD system.
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The Redundancy Index is defined as ρ = α + β + 1− r, which gives theamount by which the cardinality of the digit set exceeds the radix.
6.3.2 Carry-Free Addition Algorithms
Unlike the BSD system studied earlier, which only has a Limited Carry-Free Addition Algorithm, we shall first study a generalized system thatis not limited. In an unlimited system, the redundancy in the numbersystem enables carry-free addition without each stage requiring anyknowledge of the input carry. Recall that in the BSD system, in eachdigit position, the first stage of the adder received a logic signal fromthe cell to its right specifying whether the carry from that stage wouldbe in {1, 0} or {0, 1}.
For unlimited carry-free addition, certain constraints must be observed.The addition process is as follows:
• In the first stage, compute the interim sum and carry, pi = xi +yi.
Redundant Representations 15
• Separate pi into components ti+1, wi such that pi = ti+1r + wi.
• In the second stage, add wi to ti to produce the sum digit si.
Clearly −2α ≤ pi ≤ 2β since xi, yi have digit set [−α, β].
The next step is to decide on the minimum range of the digit set forthe transfer digit. Minimizing the cardinality of this transfer digit setwill minimize the number of logic signals needed for ti.
Assume that the carry signal ti has the digit set [−λ, µ]. If a carry-inof ti = −λ occurs, the result after the second stage is si = wi − λ.The result must be in the range [−α, β], meaning −α ≤ wi − λ, or,−α + λ ≤ wi. This condition enables the most negative possible valueof ti to be absorbed in the second stage.
Similar reasoning leads to the result that, for a carry-in of β to beabsorbed, wi ≤ β − µ. Combining these, we get:
−α + λ ≤ pi − rtt+1 ≤ β − µ
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To find the smallest value of λ allowed, we take the first inequality,−α + λ ≤ pi − rtt+1, and substitute the most negative values for thetransfer digit, ti+1 = −λ, and for the interim sum digit, pi = −2α:
−α + λ ≤ −2α + rλ
α ≤ λ(r − 1)
λ ≥ α
r − 1
By similar reasoning,
µ ≥ β
r − 1
The next step is to choose the transfer digit ti+1 by comparing theposition sum pi with λ + µ + 1 constants. Call these constants breakpoints, Cj for −λ ≤ j ≤ µ + 1. The transfer digit is chosen to be j ifand only if Cj ≤ pi < Cj+1. For ti ∈ [−λ,mu] the break points willbe C−λ · · ·Cµ We will illustrate how these constants are chosen by anexample.
Redundant Representations 17
Example:
For r = 10 and digit set [−5, 9], we need λ ≥ 5/9 and µ ≤ 1. Wechoose the minimal values, λmin = µmin = 1 so that the transfer signal,ti ∈ [−1, 1] can be implemented using only two logic signals.
Note that pi ∈ [−10, 18]. For each value in this range, we must select theinterim sum and carry signals, wi and ti+1 such that si = wi+ti ∈ [−5, 9]for any ti ∈ [−1, 1].
Consider the restrictions on the values of the carry-out, ti+1, for eachof the values of pi + ti.
ti = 0pi + ti [-11,-6] [-5,-1] [0,4] [5,9] [10,19]ti+1 -1 {-1,0} 0 {0,1} 1
Then adjust the ranges for all values of pi to accommodate all valuesof the carry-in, such that the final sum digit, si ∈ [−5, 9]
The redundancy gives us choices for the value of ti+1 for pi ∈ [−4,−2]and pi ∈ [6, 8]. This enables us to choose the break points in betweenthe ranges to minimize the number of bits needed to store them andto also simplify the logic in comparing pi values against these breakpoints. C0 = −4 and C1 = 8 would be suitable choices. The tablebecomes:
ti ∈ [−1, 1]pi [-10,-5] [-4,8] [9,18]ti+1 -1 0 1
With these break points, the logic for choosing the carry-out is simple:
Redundant Representations 19
If pi is a 6 bit 2’s complement value with bit vector < abcdef >,
g−1 = a(c + d) carry = -1
g1 = a(b + c) carry = 1
The result is an addition algorithm that is carry-free without the needfor estimation of the carry-in from the previous stage. Figure 4 showsthe block diagram of the adder. Note the missing signals connectingthe first stages.
Redundant Representations 20
xi+1 yi+1 xi yi xi-1 yi-1
wi
ti
si+1 si
Stage 1
Stage 2
ti+1
Figure 4: Unlimited Carry-Free General Sign Digit Adder
