Registers and Counters

byDr. Amin Danial Asham

References

Digital Design 5th Edition, Morris Mano

Registers are group of FF’s.

Each FF stores a binary bit .

Therefore, n-bits registers has n-

FF’s.

4-bits Register.

This register has a clear signal to reset all FF’s.

This register is positive edge trigger.

Each input is mapped to output at the clock positive edge.

Shift Register Data is injected serially in serial input SI into the register with each

clock pulse.

Sine the data is shifted inside the register it comes out serially as well from serial output SO

SI SO

Counters A counter is a register that goes though a predetermined

sequence of binary states upon the applications of input pulses.

An n-bits binary counter has states that count from 0 up to .

An n bits counter has n FF’s. There are two categories of counters:o Ripple Counterso Synchronous counters

Ripple Counters (Asynchronous)with JK-FF’s Two-bit asynchronous

counter Each FF is connected as a toggle FF triggered by the previous FF. That is:

• Q0 is complemented each time clock goes from 1 to 0.

• Q1 is complemented each time Q0 goes from 1 to 0.

• That means the trigger is propagated through the counter as a ripple fashion from the clock to the most significant bit through FF’s.

• Therefore the transition od from01 to 10 is as follows:

10

Ripple Counters (Asynchronous)with D-FF’s

Ripple Counters (Asynchronous)with T-FF’s

2-bits Ripple countdown counter.

3 2 1 0 3

2-bits ripple count down counter which counter from 3 to 0

All FF’s are positive edge trigger.

The polarity of the clock is essential for ripple counter counter

3 -BCD Ripple Counter (0-999) Noting that BCD counters here are triggered by the

negative edge.

Synchronous counters

A FF in any position is complemented if all the lower significant bits are all 1’a.o For example for output , then the next

count is is complemented by the next count when all the lower significant bits are ones.

When count enable is 0 all J’s and K’s are zeros and hence the clock does not affect the counter state.

The polarity of the clock is not essential for synchronous counters

Up-Down Binary Counter

When the Up enable signal is 1 the counter acts as count-up counter.o A FF in any position is

complemented if all the lower significant bits are all 1’a.

When the Down enable signal is 1 and UP signal is 0 the counter acts as count-Down counter.

o A FF in any position is complemented if all the lower significant bits are all 0’a.

Up-Down Binary Counter (continue)

0 1 2 3 0 3 2 1 0

Binary O/P=

Logic 1

Thanks