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1964 Short Notes 741 a = .X1X2X3 . . = *YlY2 . . YkZ1Z2 . . . ZlZiZ2 . . . Z, Regular Expressions from Sequential Circuits namely, the base-a expansion of a has period 1. A tape 6l22 . . . (n is J. A. BRZOZOWSKI, MEMBER, IEEE in Ua if and only if there exists a non-negative integer m <n such that SUMMARY X1X2 . . Xm-1 = 4142 . . . (m-AR and In this paper the relation between a sequential circuit and its regular expression is investigated. The circuits are without special Xm > m starting units. One method of analysis of a circuit leads to a set of or equations whose solutions are regular expressions related to the state diagram of the circuit. In another approach, a set of regular XJX2 * * * Xn-41t2* *.* &. equations, identical in form to the next state equations, is obtained Utilizing this fact, an automaton with k+l+2 states can be con- directly from the circuit. By reversing the regular equations and structed to define Un as shown in the following diagram, (Fig. 1). SI is using derivatives, the regular equations are transformed to a form the initial state, and R is the rejection state. All of the states except R related to the reverse state diagram. The discussion clarifies the rela- are accepting states. The label <yl stands for all letters of the alpha- tionship among circuits, regular expressions and state diagrams. bet which are smaller than yi. Moreover, further insight is obtained into the solution of equations with regular expressions as unknowns. INTRODUCTION A sequential circuit [2]-[4] is constructed from unit delay ele- ments and logical gates. It has state variables yi, Y2, - yiM, where <y \Z >each yj is an output of a unit delay element. For simplicity we con- sider circuits with a single input x and a single output z; the results are easily generalized later. The next state and output functions are Yj3'= fi(y, * Y2 . my x), j = 1,*2m.,gm (1) z = g(yl, Y2, Y Yn.), (2) where fj and g are Boolean functions. We are using here the Moore [] model where the output is a function of the state variables only; a Mealy [2] model can be treated in a similar way. For example, for 'Y2 . //,k the Moore circuit of Fig. 1 (a) we have Y x & Y ~~~~~~~~(3) z =y. (4) Logical connectives and gate symbols are defined in Fig. 1 (b). Fig. 1. AND Now, assume that a is irrational. We shall prove that Ua is not X2 regular by Nerode's Theorem.' The following statement shall be used. x xi V x2 An event U is regular if and only if the equivalence relation - Inclusive OR (defined by the condition that for tapes X and Y, X- Y if and only x Y' if for all tapes Z, whenever XZ is in U, then YZ is in U) is of finite Xi) Exclusive OR index. Consider the set S of tapes Xi =xlx2*.. xi. Let Xi and Xi be 2 two distinct tapes of S. Thus, i7f j. It follows that (4 - Inverter XlX2 . . . XiXi+lXi+2 . .. '- XIX2 . . . XjXi+lXi+2 ... or the infinite fraction representing a is periodic. Let h be the least x(t Unit delay integer such that (b) X1X2 . . . XjXj+1 . . . Xj+h = X1X2 . . . XjXi+lXi+2 . . . Xi+h and ° Xi+h+l Xi+h-1. 0 and let Z = xi+lx+2. . Xi+h+l. If Xj+h+l <Xi+A+l, then XiZ2 Ua 6> and XiZC-Ua whence Xi"-Xj. If XJ+h+±>Xi+h&l, then for 1l ) every positive integer g, XjZ(oa-1)gC U5; but for some g, XiZ(c-_1)5EUa, and again Xi,r*Xj. This implies that no two ele- (c) ments of S are equivalent and, therefore, that the index of - is (p) - 0 infinite. By Nerode's Theorem U5 is not regular.2 Q.E.D. ACKNOWLEDGMENT(d Fig. 1-(a) Circuit Cl. (b) Gate symbols. (c) State diagram. (d) Reverse The author wishes to thank Dr. M. Cohn of the Sperry Rand state diagram. Research Center who criticized the manuscript. Manuscript received March 30, 1964; revised July 13, 1964. The research re- ported was supported by the National Research Council of Canada under grant 1 M. 0. Rabin and D. Scott, "Finite Automata and their Decision Problems," No. A-1617. Previously available from the Electrical Engineering Department. Uni- IBM J. Res. anzd DeeU., vol. 3, pp. 114-125; April, 1959. versity of Ottawa, Canada, Tech. Rept. No. 64-3; January, 1964. 2 One can also use Nerode's Theorem to prove the first part, but the construction The author is with the Dept. of Electrical Engineering, University of Ottawa, of the automaton is easier to describe. Ontario, Canada.
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Page 1: Regular Expressions from Sequential Circuits

1964 Short Notes 741

a = .X1X2X3 . . = *YlY2 . . YkZ1Z2 . . . ZlZiZ2 . . . Z, Regular Expressions from Sequential Circuitsnamely, the base-a expansion of a has period 1. A tape 6l22 . . . (n is J. A. BRZOZOWSKI, MEMBER, IEEEin Ua if and only if there exists a non-negative integer m <n such that

SUMMARYX1X2 . . Xm-1 = 4142 . . . (m-AR

and In this paper the relation between a sequential circuit and itsregular expression is investigated. The circuits are without special

Xm > m starting units. One method of analysis of a circuit leads to a set of

or equations whose solutions are regular expressions related to thestate diagram of the circuit. In another approach, a set of regular

XJX2 * * * Xn-41t2* *.* &. equations, identical in form to the next state equations, is obtained

Utilizing this fact, an automaton with k+l+2 states can be con- directly from the circuit. By reversing the regular equations andstructed to define Un as shown in the following diagram, (Fig. 1). SI is using derivatives, the regular equations are transformed to a formthe initial state, and R is the rejection state. All of the states except R related to the reverse state diagram. The discussion clarifies the rela-are accepting states. The label <yl stands for all letters of the alpha- tionship among circuits, regular expressions and state diagrams.bet which are smaller than yi. Moreover, further insight is obtained into the solution of equations

with regular expressions as unknowns.

INTRODUCTION

A sequential circuit [2]-[4] is constructed from unit delay ele-ments and logical gates. It has state variables yi, Y2, - yiM, where

<y\Z >each yj is an output of a unit delay element. For simplicity we con-sider circuits with a single input x and a single output z; the resultsare easily generalized later. The next state and output functions are

Yj3'= fi(y, *Y2 . my x), j = 1,*2m.,gm (1)z = g(yl, Y2, YYn.), (2)

where fj and g are Boolean functions. We are using here the Moore[] model where the output is a function of the state variables only;a Mealy [2] model can be treated in a similar way. For example, for

'Y2 .//,k the Moore circuit of Fig. 1 (a) we have

Yx&Y ~~~~~~~~(3)z =y. (4)

Logical connectives and gate symbols are defined in Fig. 1 (b).

Fig. 1.

ANDNow, assume that a is irrational. We shall prove that Ua is not X2

regular by Nerode's Theorem.' The following statement shall be used. x xi V x2An event U is regular if and only if the equivalence relation - Inclusive OR

(defined by the condition that for tapes X and Y, X- Y if and only x Y'if for all tapes Z, whenever XZ is in U, then YZ is in U) is of finite Xi) Exclusive ORindex.

Consider the set S of tapes Xi =xlx2*.. xi. Let Xi and Xi be 2two distinct tapes of S. Thus, i7f j. It follows that (4 - Inverter

XlX2 . . . XiXi+lXi+2 . ..'- XIX2 . . . XjXi+lXi+2 . . .

or the infinite fraction representing a is periodic. Let h be the least x(t Unit delayinteger such that

(b)X1X2 . . . XjXj+1 . . . Xj+h = X1X2 . . . XjXi+lXi+2 . . . Xi+h

and °

Xi+h+l Xi+h-1.0

and let Z=xi+lx+2. . Xi+h+l. If Xj+h+l <Xi+A+l, then XiZ2 Ua 6>and XiZC-Ua whence Xi"-Xj. If XJ+h+±>Xi+h&l, then for 1l )every positive integer g, XjZ(oa-1)gC U5; but for some g,XiZ(c-_1)5EUa, and again Xi,r*Xj. This implies that no two ele- (c)ments of S are equivalent and, therefore, that the index of - is (p) - 0infinite. By Nerode's Theorem U5 is not regular.2 Q.E.D.

ACKNOWLEDGMENT(dFig. 1-(a) Circuit Cl. (b) Gate symbols. (c) State diagram. (d) Reverse

The author wishes to thank Dr. M. Cohn of the Sperry Rand state diagram.Research Center who criticized the manuscript.

Manuscript received March 30, 1964; revised July 13, 1964. The research re-ported was supported by the National Research Council of Canada under grant1 M. 0. Rabin and D. Scott, "Finite Automata and their Decision Problems," No. A-1617. Previously available from the Electrical Engineering Department. Uni-

IBM J. Res. anzd DeeU., vol. 3, pp. 114-125; April, 1959. versity of Ottawa, Canada, Tech. Rept. No. 64-3; January, 1964.2 One can also use Nerode's Theorem to prove the first part, but the construction The author is with the Dept. of Electrical Engineering, University of Ottawa,

of the automaton is easier to describe. Ontario, Canada.

Page 2: Regular Expressions from Sequential Circuits

742 IEEE TRANSACTIONS ON ELECTRONIC COMPUTERS December

The circuits considered operate synchronously, but there are no diagram of the circuit first, and then proceed to find a regular expres-special starting signals [3], [4]. At t=1, the outputs of the delay sion using well-known methods.elements are set to some arbitrary initial values; these values deter- The state diagram for the example is shown in Fig. 1 (c). Anmine the starting state q(1). At times 1, 2, - - *, t an input sequence incoming arrow indicates the starting state and a double circle de-s=x(1), x(2), * *, x(t) of length L(s) =t is applied. This results in notes a state with an output z=1.a state sequence q(2), q(3), - * * , q(t+1), and an output sequence The objection to finding a regular expression from the state dia-z(2), z(3), * * , z(t+1) [z(1) depends on the initial state btit not gram is that the expression is not at all directly related to the circuit.on s]. Previously we have shown [10] that for linear sequential circuits

there is another point of view in which the regular expressions areDefinitions 1: A sequential circuit C is said to accept [9] an input mr ietyrltdt h ici.Sc on fve snxsequence s of length t>0 from initial state q(1) if and only if, when applied to the general case.C is started in q(1) and s is applied, the output at time t+1 is z=1.If z = 1 for the initial state q(1) at time 1, C is said to accept the set REGULAR CIRCUIT EQUATIONSX consisting of the sequence of zero length. (Further discussion of X

may~~ ~be fon in[] 4. As will be seen, when dealing directly with a sequential circuit, itmay~~~be fon in.3] [4s more convenient to consider whether a sequence s of length t pro-The set of sequences accepted by a sequential circuit may be ismr onvenieatto consider whether th tepro-described by a regular expression, [3]- [12] and our problem here is to duces an output at time t rather than to ask whether the sequencefind such a regular expression for a given circuit. A basic knowledge is accepted (i.e, produces an output at time t+1). For this reasonof regular expressions is assumed; the minimum required background we make the following definition.material is summarized in the Appendix, which also defines the sym- Definition 2: An input sequence s of length t>0 energizes a point Abols used in this paper. in a sequential circuit C started in state q, if and only if, the signal

at A is 1 at time t. The sequence of zero length energizes all pointswith 1 signals at time 1.

One can look at the problem of finding a regular expression for a The reader can easily verify the following properties of sequentialcircuit in two ways: circuits:

1) Given a circuit C in initial state q at time 1, what is the set of 1) The set of sequences energizing the input lead is the set of allsequences which, when applied to C in state q, will leave C in sequences ending in a 1 which is denoted by the regular expres-a state with z= 1 ? In this case we must examine the sequences sion I1. (By convention, assume that X does not energize thein the forward direction, as time increases. input lead.)

2) Given a circuit C with z = 1 at time t+1, what sequences could 2) Let the set of sequences energizing the jth input j= 1, 2, *have been applied to C started in the initial state at some n, of a logical gate performing the Boolean function f, beearlier time in order to produce this condition? Here the denoted by Sy. Then the set of sequences energizing the outputsequences are examined in the reverse direction. of that gate is given by f(Si, S2, * * *, Sn). (The gate is

assumed to have no delay.)In this section we shall illustrate the forward approach by the 3) If R is the set of sequences energizing the input of a unit

example of Fig. 1(a). Let R. be the set of all sequences accepted by delay, then its output is energized by RiV8(y(1)), wherethe circuit from initial state q, i.e., the sequences resulting in z=1. a(0) (the empty set of sequences) and 6(1) =X.Suppose y=0 at t=1; then the required regular expression is Ro.Now, if an input x = 0 is applied at t = 1, the state at t =2 is still The above properties are illustrated in Fig. 2.y = 0; hence the expression applicable at t =2, after a 0 has beenreceived, is still R(. However, if x = 1 is applied at t = 1, the state att =2 will be y= 1; hence, after a 1 is received, the applicable expres- X - ITsion is R1. Since the output is 1 for the state y =0, Ro must also con- SItain X. Thus S2 I'S s )

Ro = ORoV1R V X. (5)

Similarly we obtain for R1: n

R, = (0 V l)Ro = iRo. (6) RiV &(y (l)

Equations of this type have been described in detail in the litera- Fig. 2-Effects of circuit elements.ture [3], [4] and can be solved using the fact that X=AXVB,where A p) X and A and B are regular expressions, has the solutionX=A*B. Solving for Ro we have Consider a general sequential circuit C characterized by (1) and

(2). Let the set of sequences energizing the input of the jth delay ofRo =ORo V haR0 V X C be called the jth delay (regular) set, and be denoted by Rj. Let the= (OV li)RoV X set of sequences energizing the output lead be called the output= (0 V li)*. (7) (regular) set and be denoted by Q. Then we can state:

Hence Theorem 1: The delay and output sets of a sequential circuit C char-

RI = i(O V li)*. (8) acterized by (1) and (2), must obey the equations:

Thus, if y=O is the starting state the sequences accepted are denoted Ri = f1[R1i V 6(yi(1)), R2i V B(Y2(1)), , RijV 5(Ym(l)), II],by (7), and if y=1 is the starting state the sequences accepted are j =1, 2, * * ,m, (9)denoted by (8).Q= Ri\(y() iV(())***R \/y(l]. 10

It is clear that, in the analysis, the states of the circuit play the = '[iV (il) 2 (2l) m (m1). (0key role. Now several techniques are available for finding regular If in the initial state all delay outputs are 0, then a simpler form ofexpressions from state diagrams and we shall not dwell on this (9) and (10) resultsmethod. We merely wanted to point out that the forward approachapplied to a circuit involves the states of the circuit and the transi- Rs = fy[R0i, R2i, Rm2j 11], j = 1, 2, , m (9a)tions among the states. Thus it is most efficient to construct the state Q-=g[Rsi, R2i, * *., Rmi]. (lOa)

Page 3: Regular Expressions from Sequential Circuits

1964 Short Notes 743

The theorem follows directly from Properties 1)-3). Note the One can verify that P is equivalent to RO of (7) found by the forwardone-to-one correspondence of (9a) and (lOa) to (1) and (2), respec- approach.tively, when Rj is identified with yj', Rji with yj, I1 with x, and Q Returning to p= r, we see that the derivatives of pwith z. For simplicity we shall deal with the case of zero initial condi- Dxp = p, Dop = I, Dip Diop =tions. Eqs. (9a) and (10a) will be called the regular circuit equationsand our problem is to solve these equations. However, in order to define a state diagram [Fig. 1(d)] which is the reverse of that ofconform with the previous literature, we must find P, the set of Fig. 1(c).sequences accepted by the circuit. This can be done as a result of the In summary the reader can verify thatfollowing corollary. 1) For every one-input, one-output sequential circuit, one can

Corollary: If the delay and output sets of a sequential circuit are write a set of regular equations directly related to the circuitgiven by (9a) and (lOa), then the set P of sequences accepted by the structure (Theorem 1).circuit is 2) The equations can be reversed as in (14).

P = g(R1, R2, - * * Rm). (11) 3) The derivatives of rj with respect to sequences of length 1 are

This is evident from the definitions of accepted and energizing Boolean functions of the rj as in (15) and (16).sequences. 4) The reverse of the set of sequences accepted by the circuit is

As an example consider the circuit of Fig. 1(a) started with given byy = 0 at t = 1. Then R, the set of sequences energizing the delay p = g(ri, r2, *, m).input, must satisfy the following equation: 5) Since for aCAk, DP=g(Darl, Dar2, Da7m), the deriva-

R = (I1) & Ri, (12) tives of p with respect to sequences of length 1 are Boolean

and P, the set accepted by the circuit is given by functions of the rj.6) Conequently, all derivatives of p are Boolean functions of the

P= R. (13) ri.REVERSE APPROACH 7) To find the derivatives of p it is necessary to know the deriva-

We have shown that the analysis of a circuit gives rise to a set of tives of the r2 only with respect to sequences of length 1.euinwApresent it is 8) The distinct derivatives of p can be found in a finite numbereqainswt reuaexrsinasnko s.A of steps. Hence the characteristic equations [11], [121]forp

known [3], [4] how to solve equations of the type X=AXVB or an itsd ertie canterfound.X=XAVB and equations arising from the analysis of linear circuits[10]. It will be shown that the method of derivatives [12]- [15], also 9) The characteristic equations can be solved for p using the

called quotients [151 (see Appendix), allows us to obtain a solution solution of the general form X =AXVB.for any set of equations from a general circuit. 10) The regular expression p obtained in this way is related to the

l, ~~~reverse state diagram of the circuit.In order to apply derivatives it is necessary to reverse [Ii1 (see reverse ate diar e ircuit.Appendix) the regular equations for the circuit. Let rj =Rj- for nota-tional convenience. Then (9a) becomes GENERALIZATIONS

r; = f,(iri, iT2, * - *, ir,m 11), j = 1, 2, * *, m. (14) The example that we used was chosen for the sake of simplicity

Note what happens when we take derivatives with respect to 0 and 1 but was rather restricted. If there is more than one input the exten-

Dorj = fi(ri, r2, , Tm, 0) (15) sion is straightforward. Suppose a next state equation has the form

D1ri = f,(ri, r2, - r, Tm, 1). (16) yl = (XI & yl) V (XI & x2 & yI & Y2). (26)

Thus the derivatives of the reverse expressions rj with respect to Now each function of the inputs represents, in general, several inputsequences of length one are simply Boolean functions of the r,. Con- combinations; for example xi = (xi&x2)V(xl&x2). Represent each in-sequently all derivatives with respect to longer sequences are also put combination by its decimal equivalent: (xI, x2) = (0, O) by 0,Boolean functions of the rj. Now it is known [12 ]-[15] that rj has a (xl, x2) = (1, 0) by 2, etc. Then xi is represented by 2V3. Thus R, cor-finite number of distinct derivatives; since there is a finite number of responding to (26) isBoolean functions of the ry, the process of constructing the deriva- RI = (I(2 V 3)) & (R,i) V (Il) & Rli & (R2i).tives will terminate without difficulty.

Consider the simple circuit of Fig. 1 (a) again. Here If there are r outputs Zk, then we must find r regular expressions

r= (11) &r (17) Pk, or we can treat Pk as components of a regular vector [12]P.Dor O&F 0 (18)

At any rate the extension is again straightforward.Dor = k & r = ¢ (18) It is felt that an example with more than one delay should be givenDir = I & r = r, (19) to illustrate a more general case. For the circuit of Fig. 3 we haveDior = Dor 5 = I, (20) R1 5I1&(Rii+R2i)D1ir = lr = r= r. (21)

R2 = Rii & (I1 V R2i)The process terminates here because no new derivatives are found P = R1 & R2.for sequences of length 3. At this point we can write r in terms of its Reversing we obtainderivatives [12] (see Appendix):

r = ODor V 1Dir V 6(r) = 04V lDir = lDir, (22) r1 = Il & (irn + in)Dir = ODiorVl1DuirV5(Dir) = OIVlrV=/X-r. (23) r2-= & (1IV iru)

p =Tri&T2.Now, since we are really interested in r =p=P-, we can solve for p:

p = XV01Vin = XV 01 ~~ Now in order to construct derivatives of p we require the derivativesP =XV01Vlr = X V OI V llpof ri and r2 with respect to sequences of length one. Thus:

=(11)*(XV\tOI)- (24)Donl = Ti + r2 Dor2 = 71& r2

Finally, reversing p we obtain another valid expression for the cir- D1l= Dir2 = Ti.CUit of Fig. 1 (a):

P = (10 V x)(11)*. (25) This is sufficient to construct derivatives of p

Page 4: Regular Expressions from Sequential Circuits

744 IEEE TRANSACTIONS ON ELECTRONIC COMPUTERS December

x lb) Da(P*) = (DaP)P*3WnD.(PQ) = (DaP)QV6(P) D.Q

D.(f(P, Q)) =f(DaP, DaQ)where 6 (P) = X if PDX, 6(P) = 0 otherwise.

2) D,a2aP= Da2(Da,P)Daa2 .. arP= Dar(Daja2 ...ar-P)

L DxP = P.

The reverse [I1i R of a regular expression R is defined recursively:

Fig. 3-Circuit C2. x- x for xe A, or x = X or x =(PQ)- = Q-P-

P = r. &r2 (P*)- (P-)*

Dsp ri+ri&(rs&r2) I/S ((P, Q)) = (P-, Q&).Dop = Y1+ri & (r, & r2)=Dip = I &F, = F,REFERENCES

--r~ + r2[1] E. F. Moore, "Gedanken-experiments on sequential machines," in "Automata

DTop = ri + r2= + ri + r2 Studies, Annals of Math. Studies," C. E. Shannon and J. McCarthy, Eds.,Princeton University Press, Princeton, N. J., No. 34, pp. 129-153; 1956.

DliP = I [21 G. H. Mealy, " A method for synthesizing sequential circuits," Bell. Sys. Tech.J., vol. 34, pp. 1045-1079: September, 1955.

Dioop = I + ri + r2 + (il & r2) P, V r2 [31 D. N. Arden, "Delayed Logic and Finite State Machines," Proc. 2nd Ann.Symp. on Switching Circuit Theory and Logical Design, pp. 133-151; September,DioiP = I + + fi = ri, etc. 1961. Also in "Theory of Computing Machine Design," University of MichiganEngineering Summer Conferences, Ann Arbor, Mich., pp. 1-35; 1960.

As a final point, consider the effect of a starting state different [4] J. A. Brzozowski, "A survey of regular expressions and their applications,"IRE TRANS. ON ELECTRONIC COMPUTERS, VOl. EC-11, pp. 324-335; June, 1962,from 0, on the reverse approach. This can be illustrated by the ex- and Dept. of Elec. Engrg., Digital Systems Lab., Princeton University, Prince-

ton, N. J., Tech. Rept. No. 4; April, 1961.ample of Fig. I (a). If y-1 at t = 1, the proper equation for R iS [5] S. C. Kleene, "Representation of events in nerve nets and finite automata," in

"Automata Studies, Annals of Math. Studies, " C. E. Shannon and J. McCarthyR = (It) & Ri V X Eds., Princeton University Press, Princeton, N. J., No. 34, pp. 3-41, 1956.[6] R. McNaughton and H. Yamada, "Regular expressions and state graphs for

automata," IRE TRANS. ON ELECTRONIC COMPUTERS, vol. EC-9, pp. 39-47;The remainder of the procedure is the same. March, 1960.

[7] J. A. Brzozowski and E. J. McCluskey, Jr., "Signal flow graph techniqules forsequential circuit state diagrams," IEEE TRANS. ON ELECTRONIC COM-

CONCLUSIONS PUTERS, vol. EC-12, pp. 67-76; April, 1963.[8] I. M. Copi, C. C. Elgot, and J. B. Wright, "Realization of events by logical

We have investigated the possibility of obtaining a reguilar expres- nets," J. ACM, vol. 5, pp. 181-196; April, 1958.9]M. 0. Rabin and D. Scott, "Finite automata and their decision problems,"

sion directly from a sequential circuit. We have shown that both the IBM J. Res. and Dev., vol. 3, pp. 114-125; April, 1959.[10] J. A. Brzozowski, "Regular expressions for linear sequential circuits," Proc.direct and the reverse approach make use of a state diagram. It First Annual Allerton Conf. on Circuit and System Theory, pp. 406-426; Novem-

appears that the only more direct method would be to solve the her, 1963.[11J. A. Brzozowski, "Canonical regular expressions and minimal state graphs for

regular circuit equations without using derivatives (which in effect definite events," Proc. Symp. on the Mathematical Theory of Automata, Poly-technic Press of the Microwave Research Institute Symposia Ser., Polytechnicconstitute a state diagram). Before this can be done we must learn Inst. of Brooklyn, N. Y., vol. 12pp.529-561; 1963.

more about the regular algebra. However, it appears unlikely that a [121 J. A. Brzozowski, 'Derivatives of regular expressions," J. ACM, vol. 11, pp.481-494; October, 1964. See also "Properties of Regular Expressions and State

much simpler method can be found. Diagrams," Dept. of Elec. Engrg., Digital Systems Lab., Princeton University,Princeton, N. J.; Tech. Rept. No. 15; March, 1962.

[13] C. C. Elgot and J. D. Rultledge, "Operations on finite automata," Proc. 2ndAPPENDIX Ann. Symp. on Switching Theory and Logical Design, pp. 129-132; October,

1961.Regular expression [31- [12] is defined recursively: [14] R. E. Stearns and J. Hartmanis, "Regularity preserving modifications of

regular expressions," Information and Control, vol. 6, pp. 55-69; September,1) and a (in Ak) are regular expressions. [1]1963.1) X, ¢s and a (in A e) are regular expressions. [t5] S. Ginsburg and G. F. Rose, "Operations which preserve definability in lan-

2) If P and Q are regular expresssions then so are PQ, P*, f(P, Q), guages," J. ACM, vol. 10, pp. 175-195; 1963.where f(P, Q) denotes any Boolean expression in P and Q.The symbols for common Boolean functions are shown in Fig.1(b).

3) Only expressions obtained from Rules 1) and 2) by a finitenumber of applications are regular.

We use the same symbol for a sequence as for the set of sequencesconsisting of only that sequence. Regular expressions denote sets of A Sampled-Data Analog of Neuron Propertiessequences. Above Ak is the input alphabet, A*= { 0, 1, * - -, (k-1) 1, E. E. NELSON, MEMBER, IEEE, AND H. F. WOLFX is the set consisting of the sequence of zero length and is the empty A mathematical neuron model is discussed that can be used inset of sequences. Also PQ denotes concatenation, and Amteaia ernmdli icse htcnb sdi

investigating neural net activity. This model incorporates many of00

P* =U pn the data processing capabilities of biological neurons in a simple,n=O iterative set of equations. The neuron properties simulated are linear,

where p2=pp, etc., and PO.=X. Furthermore we let the set of all weighted summation of inputs, standard signal shape, threshold fir-sequences be I, and the set of all sequences of length 1 be ing, refractory recovery, signal delay, and temporal summation. Thei=OVlV . . . V(k-1). necessary equations are derived by dissecting these characteristics

The dersvats-e [12]-[15] D+R of a regular set R with respect to a into small and separate entities and then generating a sampled-datasequence s is a regular set defined by model that conveniently combines their effects. A flow chart that

diagrams the necessary program to implement this neuron analogDsR = {l slf R}, on a digital computer is developed.

In recent years, the tempo of activity in the area of neural model-and iS found recursively. If a, a3As, and P Q are regular expressions in ha'hwakdices.Tishihee neethsbethen the regular expressions for derivatives are found as follows:

la) Daa = X Manuscript received February 14, 1964.The authors are with Douglas Missile and Space Systems Div., Newvport Beach.

D b=I/ for b=X or b=/S orbftAs and b#a Calif.


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