Regular Structures

Regular Regular StructuresStructures

Levelized Levelized StructuresStructures

Standard Lattice Standard Lattice Diagrams for Diagrams for continuous, continuous,

multiple-valued and multiple-valued and binary logicbinary logic

Patented by Pierzchala and Perkowski 1994/1999

Lattice Structure for Multivalued and Binary Logic

•Realizes every binary symmetric function

•Realizes every non-symmetric function by repeating variables

•Realizes piece-wise linear multivalued functions

Lattice Structure for Multivalued and Binary Logic•Cell has three inputs and two outputs

•Both outputs have the same function

0 1red nose

beard

red eyes

PerkowskiJeske ZakrevskijAl-Rabadi

Multivalued variables

Binar

y in

put v

ariab

les

Multi-valued output variable


0 1

Redness of nose in interval [3,4]

Length of beard an odd number

Redness of eyes in intervals [2,4] or [7,9]


Multivalued variables

Multi-valued output variablebinary


0 1A>B

C<D

E=G


Multivalued input variables

Multi-valued output variablebinary

Mul

tivalu

ed in

put v

ariab

les


0 1A>B

C<D

E=G




Mul

tivalu

ed in

put v

ariab

les

A B

C>0

E<Gor G>0

E<G and G<0

C D

E G

Cell has 4 inputs and 2 outputsCell has 4 inputs and 2 outputs

Can we make the cell reversible?Can we make the cell reversible?

Control left right output

0 value - value

1 - value value

YZ

X 00 01

0

1

0 1

54

3 2

67

11 10Control

left

right

0 0 1 1

0 1 1 0

Control

right

left

We want to make this cell reversible

output

output

Values not separated

YZ

X 00 01

0

1

0 1

54

3 2

67

11 10Control

left

right

00 00 10 10

01 11 11 01

Control right

left

Let us try to repeat control variable in output

output

output

output1

output1

Still not separated

YZ

X 00 01

0

1

0 1

54

3 2

67

11 10Control

left

right

000 001 101 100

010 110 111 010

Control right

left

Repeating variables will not help

output

output

output1

output1

Now it works!

output2

YZ

X 00 01

0

1

0 1

54

3 2

67

11 10

This means that we added another MUX

leftControl

right

outputoutput1

Control

right

000 001 101 100

010 110 111 010

left

output output1

output2

…. And we reinvented the Fredkin Gate ….!!!

• But how to use it in a Lattice?

Lattice Structure for Binary Logic

0 1A

B

C

0 1 0 1

F = S 1,3 (A,B,C)

S0 S1 S2 S3

0 1 2 0 1 20 1 2

A

PSRQ

BCD

A P

Q R S

D C B

D

C

B

Q

S

R

A

P

(a)

(b)

(c)

x1

x2

x3

1

2 43

8 7 6 5

D R

S

Q

B

C

A

P

x1

x2

x3x1

x2

x3

1

2

3

4

7

8

6

5

Notation for Fredkin Gates

0 1

A

0 1 0 1

C B

PQ R

A P

B C

Q R (a)

(b)

Three Types of General Expansions

0 1A

f

f0 f1

f and A f0 and f1g,h and A g1A+h0A’

10 1 0

g1

h

A

g1A+h0A’

g1A+h0A’

A

g h

10

g0A’+h1A

g, h, and A g0A’+h1A and g1A+h0A’

Forward Shannon Reverse Shannon

Reversible Shannon

(a)

(b)

(c)

ho

g

*+

*+

*+

*+

…...

…...

…...

ci

f1 f2 f3

f4

k1k2 k3

k4 k5 k6

Previous levels

next levels

Other same level

*

+

*

+

*

+

*

+

…...

…...

…...

f1 f2 f3

k1k2 k3

k4 k5 k6

Previous levels

next levels

Other same level

f4

ci

0 1X

Y

Z

1 01

fgarbage

YZ

X 00 01

0

1

0 1

54

3 2

67

11 10

1 1

1

1

00

0

1

YZ

X 00 01

0

1

0 1

54

3 2

67

11 10

- - - -

- - - -

YZ

X 00 01

0

1

0 1

54

3 2

67

11 10

1 0 1 0

- - - -

YZ

X 00 01

0

1

0 1

54

3 2

67

11 10

- - - -

0 1 1 1

100 1

1

0

g

garbagegarbage

garbage

garbage

garbage

garbage

fg gfh i

hfg fgh

YZ

YZ

X

YZ

X

X

YZX

00 01 11 10

0 1

YZ

X 00 01

0

1

0 1

54

3 2

67

11 10

YZ

X 00 01

0

1

0 1

54

3 2

67

11 10

1 0 1 0

0 1 1 1

- - - -- - - -

YZ

X 00 01

0

1

0 1

54

3 2

67

11 10

YZ

X 00 01

0

1

0 1

54

3 2

67

11 10

- - - -0 1 1 1

- - - -- - - -

YZ

X 00 01

0

1

0 1

54

3 2

67

11 10

YZ

X 00 01

0

1

0 1

54

3 2

67

11 10

- - - -- - - -

1 0 1 0- - - -

X

Y

Z

YZ

X 00 01

0

1

0 1

54

3 2

67

11 10

- - - -- - 1 1

YZ

X 00 01

0

1

0 1

54

3 2

67

11 10

YZ

X 00 01

0

1

0 1

54

3 2

67

11 10

- - - -- - - -

- - 1 0- - - -

YZ

X 00 01

0

1

0 1

54

3 2

67

11 10

YZ

X 00 01

0

1

0 1

54

3 2

67

11 10

1 - - -- 1 - -

- 0 - -0 - - -

=1

= 1

YZ

X 00 01

0

1

0 1

54

3 2

67

11 10

YZ

X 00 01

0

1

0 1

54

3 2

67

11 10

1 0 - -- - - -

- - - -0 1 - -

=0=1 =0

YZ

X 00 01

0

1

0 1

54

3 2

67

11 10

YZ

X 00 01

0

1

0 1

54

3 2

67

11 10

- - 1 -

- - - -

- - - 0- - - -

XYZ

Reversible Lattice Structure for Binary Logic

0 1A

B

C

0 1 0 1

F = S 1,3 (A,B,C)

S0 S1 S2 S3

G waste

F waste

F waste

F waste

F waste

Two-DimensionalTwo-Dimensional Lattice Diagrams Lattice Diagrams

for reversible logicfor reversible logic


f

0 1A

f0 f1

f and A f0 and f1

Forward Shannon


g,h and A g1A+h0A’

10 1 0

g1

h

A

g1A+h0A’

Reverse Shannon

(b)ho

g


g1A+h0A’

A

g h

10

g0A’+h1A

g, h, and A g0A’+h1A and g1A+h0A’

Reversible Shannon

0

0

1

1

a

+

+

a

c

b

x

yb

c ab

c ab

a

a

Third stage of decomposition: Feynman gate

Second stage of decomposition: Reversible Expansion for Fredkin gate

First stage of decomposition: Feynman gate

Realization of Toffoli Realization of Toffoli Gate from Fredkin and Gate from Fredkin and Feynman GatesFeynman Gates

0

0

1

1

a

+

+

a

c

b

x

yb

c ab

c ab

a

a

First stage of composition: Feynman gate

Second stage of composition: Reversible Expansion for Fredkin gate

Third stage of composition: Feynman gate

Realization of Toffoli Realization of Toffoli Gate from Fredkin and Gate from Fredkin and Feynman GatesFeynman Gates

0 1

YZ

X 00 01

0

1

0 1

54

3 2

67

11 10

1 0 1 0

- - - -

YZ

X 00 01

0

1

0 1

54

3 2

67

11 10

- - - -

0 1 1 1

100 1

fgarbageg

garbage

garbage

1 010

Z

garbage

fg

X

garbagegarbage gfh i

Y

1

garbagehfg fgh

YZ

X

YZ

YZ

X 00 01

0

1

0 1

54

3 2

67

11 10

- - - -

- - - -

X

YZX

YZ

X 00 01

0

1

0 1

54

3 2

67

11 10

1 1

1

1

00

0

1

YZX

00 01 11 10

0 1

cofactor permutercofactor permuter

To distinguish this new general decomposition from the well-known decompositions of Ashenhurst, Curtis or Shannon, we call it the Multi-purpose Portland Decomposition, the MP-decomposition for short.

GeneralizationGeneralization• We mapped the logic function to a lattice

structure of geometrical connections

• there is nothing in our method to map to only this kind of structure

• we can map to any selected regular structure

• we can also map to a irregular structure with arbitrary connections

Generalizations of Fredkin gateGeneralizations of Fredkin gate

• Observe, that this definition of the gate does not specify the type of signals.

• Thus they can be binary, multi-valued, fuzzy, continuous or complex.

• The only requirement is that the relation of order (<) is defined on them

• It is interesting and important that a single reversible gate in binary logic has many generalizations in multiple-valued logic.


• Because it has been shown in [1] that there are many multiple-valued and multi-output (k>3) generalizations of Fredkin gate, the name “modified” assigned by Picton is not correct.

• The generalization invented by him we will call the Picton Gate, while generalization of Fredkin-like gates we call “new gates”.

Generalizations of Fredkin gateGeneralizations of Fredkin gate• The exhaustive list of families of all such

permutative multi-valued gates (both Shannon-like and Davio-like) has been presented in [1] and even more families in [18].

• These of the “new gates” that use multiplexers only are similar to the original Fredkin gate but they use multiple-valued multiplexers.

• Such multiplexers have been already realized in many technologies, including super-pass transistors [9], so building these new gates should be also possible.


• We believe therefore that they are good candidates for future reversible multiple-valued nano-technologies. The new generalization of Fredkin gate using multi-valued logic has additional advantages and is simpler. Let us observe, that equations for the binary 4 * 4 binary Fredkin gate can be rewritten as follows:

• P = A , Q = if A=1 then C else if A=0 then B , R = if A=1 then B else if A=0 then D , S = if A=1 then D else if A=0 then C

• Now, it can be easily generalized to a 4 * 4 ternary gate as follows: P = A, Q = if A=2 then B else if A=1 then C else if A=0 then D, R = if A=2 then C else if A=1 then D else if A=0 then B, S = if A=2 then D else if A=1 then B else if A=0 then C

Reversible Lattice Structure for Binary Logic

•Advantages

•regular structure

•binary Fredkin Gate

•planar structure (good for Quantum Logic)

•Easy algorithmic creation

•Reasonable waste

•Disadvantages

• Variable ordering?

• Symmetrization?

• Waste still exist

Should be patented!

Do you remember that there are other binary expansions?

•All Binary Expansions

•Shannon - S

•Flipped Shannon - fS

•Positive Davio - pD

•Negative Davio - nD

•Flipped Positive Davio - fpD

•Flipped Negative Davio - fnD

•Ideas

• Fredkin = <Var, S, fS>

•what about these?

• <Var, pD, fpD>

• <Var, nD, fnD>

•<Var, nD, pD>

•….

I checked some of them to work

Do you remember that there are other component functions of reversible gates

•All Binary Balanced Expansions:

•…..

•Linear functions - L

•Negations - N

•Majorities - M

•Ideas

• Fredkin = <Var, S, fS>

•what about these?

• <N, pD, fpD>

• <Var, M, fnD>

•<Var, nD, L>

•….

I checked some of them to work

As you see, this opens a very broad area of research that will lead to invention of new reversible gates and regular structures that use them

•Easy way to become a pioneer:

• Investigate all combinations

• Use genetic programming or other search methods to build structures and map functions to them

•There is a place for many researchers

•Nobody does this research

But this was only for binary

What about What about multivalued, multivalued, fuzzy, arithmetic fuzzy, arithmetic or other logics?or other logics?

…. And we reinvented the Fredkin Gate ….!!!

• But what about the variant with two control signals?

Multi-valued Fredkin Gate• MVFG is described by equations:

P = A

Q = B

R = C if A < B else R = D

S = D if A < B else S = C

A B C D

P Q R S

>=

A B C D

P Q R S

< A < B


0 1




Mul

tivalu

ed in

put v

ariab

les

A BC

D

E G

Cell has 4 inputs and 4 outputsCell has 4 inputs and 4 outputs

Cell is reversible!Cell is reversible!

MV and Generalized MV MV and Generalized MV FredkinFredkin

waste

waste

Multi-valued logic generates less signals

Hence it generates less Hence it generates less wastewaste

Of course, it generates also less Of course, it generates also less power, less connections and is power, less connections and is easier to testeasier to test

•The real-life functions are multi-output.

•Thus, there exists an opportunity to re-use some waste functions in other output functions

•This is a tough problem.

•I do not know now how to solve it!

The main open research problemThe main open research problem

We need some We need some group creativitygroup creativity

Generalized Multi-valued Fredkin GateGeneralized Multi-valued Fredkin Gate

A B C D

P Q R S

< A < B

Select other pairs of MUX-type functions

Select other pairs of VAR-type and NOT-type functions

Select other function of two variables

Generalized Multi-valued Fredkin GateGeneralized Multi-valued Fredkin Gate

•The number of these gates is astronomical

•We need both computer generation and some intelligence, simply generating them all would be a nonsense

•Very wide area of research

•It will give hints to gate designers what to look for

Let us go back to our fundamental invention…..

•What if we resign from oblique buses?

Buses are removed and each cell is programmed individually…..

•Some regularity is lost!

D’

C

B

A

3

3*A*B*C*D’

X

Y

Z

V

2

2*Z*V

B

B1

A

1 * A’ * B’

• The general levelized method can assume any structure of the layout, thus any order and choice of input signals of successive Reversible Shannon expansions.

• Assuming other type of structure, cascade or non-planar lattice with intersecting signals, this other type of structure would be created.

• For arbitrary structures, however, the method requires small modification: if the structure is too constrained, the structural equations have no solutions or the algorithm loops.

• This happens, for instance, when a Maitra Cascade structure is assumed for a function that is not Maitra-realizable.

• It happens also when we assume a levelized circuit of too narrow a bandwidth

• Thus the algorithm must be modified to deal with these special cases.

• Finally, our general approach will work also for irregular structures. In such case, any pair of signals can be the inputs to the Reversible Shannon Expansion, regardless of their order. The signals are paired to give the smallest evaluated total complexity for the level.

• Arbitrary symmetric function can be realized in a lattice without repeated variables.

• Arbitrary (non-symmetric) function can be realized in a lattice with repeated variables (so-called symmetrization).

• Similar property exist for the presented method. This method terminates for arbitrary function, assuming that the variables are repeated in levels. Thus, if the leafs of the lattice are not constants after expanding for all input variables, some of these variables are used again in new levels of expansions, which we call variable repetition.

• Interestingly, the functions that do not require variable repetition in the Reversible Shannon Lattices are not symmetric functions.

• We work on the characterization of the functions realizable in these structures without repetitions and respective synthesis algorithms.

• We can impose during joining the structure of the three dimensional lattice. Such lattice is typical for some crystals.

• There are also several other three-dimensional structures corresponding to other types of bonds or constraints that exist in Nature (for example, quantum dot computers).

• This leads to very many new circuit types, which are reversible and multi-valued generalizations of Shannon Lattices, Kronecker Lattices, Fat Trees, and many other structures introduced in the past.

Future Work

• Several realizations of reversible and quantum logic, such as for instance quantum dots, involve a geometrical space. – For instance, in the quantum dot model this space is two-

dimensional.

• Here we propose to create three-dimensional regular structures, because our physical world is three dimensional. Layout-driven synthesis

• We plan to design these structures in CMOS and Optical technologies.

• Software

Date post:	15-Jan-2016
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Regular Structures

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