Page 1
Reiner Hartenstein (invited paper): Trends in Reconfigurable Logic and Reconfigurable Computing; 9th IEEE International Conference on Electronics, Circuits and Systems - ICECS 2002, September 15-18, 2002, Dubrovnik, Croatia
Reiner Hartenstein, University of Kaiserslautern, Germany http://hartenstein.de
1
ICECS 2002 IEEE 9th International Conference
on Electronics, Circuits and Systems
Trends in Reconfigurable Logic and Reconfigurable Computing
(invited paper)
Reiner Hartenstein
University of Kaiserslautern
viewgraph downloading, see:
http://kressarray.de
Dubrovnik, Croatia
September 15-18, 2002
© 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
2
>> Outline
• The Computer Architecture Crisis
• The Impact of Reconfigurable Platforms
• The Dichotomy of Models
• Parallelism
• Conclusions
http://www.uni-kl.de
© 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
3
Flag ship example: annual IEEE ISCA conference series
Resignation?
taken over by the opposition:
Interconnect Fabrics:
vN Parallelism:
the Datenflow Machine is dead
Statistics [David Padua, John Hennessy, et al.]
Reconfigurable Computing
© 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
4
Dead Supercomputer Society
•ACRI •Alliant •American Supercomputer
•Ametek •Applied Dynamics •Astronautics •BBN •CDC •Convex •Cray Computer •Cray Research •Culler-Harris •Culler Scientific •Cydrome •Dana/Ardent/ Stellar/Stardent
•DAPP •Denelcor •Elexsi •ETA Systems •Evans and Sutherland •Computer •Floating Point Systems •Galaxy YH-1 •Goodyear Aerospace MPP •Gould NPL •Guiltech •ICL •Intel Scientific Computers •International Parallel Machines
•Kendall Square Research •Key Computer Laboratories
[Gordon Bell, keynote at ISCA 2000].
•MasPar •Meiko •Multiflow •Myrias •Numerix •Prisma •Tera •Thinking Machines •Saxpy •Scientific Computer •Systems (SCS) •Soviet Supercomputers •Supertek •Supercomputer Systems •Suprenum •Vitesse Electronics
© 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
5
CS: young ? dynamic?
.. but the von Neumann Paradigm is still the dominant doctrine ...
Microelectronics is ignored (except falling cost
of computational effort)
... still pushing he basic models from the times of mainframe dinosaurs
after >10 technology generations ...
• 1th 4004 • 2nd 8008 • 3rd 8086 • 4th 80286 • 5th 80386 • 6th 80486 • 7th P5 (Pentium) • 8th P6 (Pentium Pro / Pentium II) • 9th Pentium III • 10th .... • 11th
• .......
... the vN Microprocessor is a methusela, the steam engine of the silicon age.
© 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
6
>> Paradigm Shifts
• The Computer Architecture Crisis
• The Impact of Reconfigurable Platforms
• The Dichotomy of Models
• Parallelism
• Conclusions
http://www.uni-kl.de
Page 2
Reiner Hartenstein (invited paper): Trends in Reconfigurable Logic and Reconfigurable Computing; 9th IEEE International Conference on Electronics, Circuits and Systems - ICECS 2002, September 15-18, 2002, Dubrovnik, Croatia
Reiner Hartenstein, University of Kaiserslautern, Germany http://hartenstein.de
2
© 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
7
better to go for reconfigurable platforms
• [Dataquest] PLD market > $7 billion by 2003.
• fastest growing segment of semiconductor market
• IP reuse and silicon reuse
• FPGAs are going into every type of application
© 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
8
Why coarse grain ?
© 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
9
Throughput vs. Efficiency
1000
100
10
1
0.1
0.01
0.001 2 1 0.5 0.25 0.13 0.1 0,07
MOPS / mW
µ feature size
S S
S S
resources needed for
reconfigurability
L
L L
L L
L
L L L
area used by application
1 Bit CLB
T. Claasen et al.: ISSCC 1999
Wiring by abutment: 32 Bit example
*) R. Hartenstein: ISIS 1997
© 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
10
Throughput vs. Flexibility
flexibility
throughput 1000
100
10
1
0.1
0.01
0.001 2 1 0.5 0.25 0.13 0.1 0,07
MOPS / mW
µ feature size
T. Claasen et al.: ISSCC 1999
hard- wired
von Neumann
FPGAs
the anti machine goes far beyond bridging the gap
anti machine
*) R. Hartenstein: ISIS 1997
© 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
11
Terminology
DPU data path unit rDPU reconfigurable DPU DPA data path array (DPU array) rDPA reconfigurable DPA RA reconfigurable array ISP instruction set processor AM anti machine AMP data stream processor* rAMP reconfigurable AMP
*) no “dataflow machine”
platform category
programming source
machine paradigm
hardware (not programmable) none
ISP software von Neumann
• morphware configware FPGA: none
data stream processor (AMP)
streamware
anti machine reconfigurable
AMP (rAMP)
streamware &
configware
digital system platforms:
morphware use granularity (path width) (re)configurable blocks
reconfigurable logic • fine grain (~1 bit) CLBs
reconfigurable computing coarse grain (e.g. 32 bits) rDPUs (e.g. ALU-like)
multi granular: by slice bundling rDPU slices (e.g. 4 bits)
categories of morphware:
consensus is near
FPGA field-programmable gate array FPL field-programmable logic PLD programmable logic device CPLD complex PLD
instruction set processor
© 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
12
Paradigm Shifts: Nick Tredennick‘s view
algorithms variable
resources fixed
instruction-stream-based computing:
algorithms variable
resources variable
reconfigurable computing:
programmable
Page 3
Reiner Hartenstein (invited paper): Trends in Reconfigurable Logic and Reconfigurable Computing; 9th IEEE International Conference on Electronics, Circuits and Systems - ICECS 2002, September 15-18, 2002, Dubrovnik, Croatia
Reiner Hartenstein, University of Kaiserslautern, Germany http://hartenstein.de
3
© 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
13
Compilation for (r)DPA of anti machine
mapper
scheduler
expressionmorphware
configware
streamware
tree
high level source program
wrapperparameters
codegenerators
DPU library
(software notation)
Data
Path
Array
DPA
streamware
streamware © 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
14
Why fine grain ?
•no specific silicon: low production volume (aerospace, automotive, military, industrial controllers, et al.)
•the spare part problem
•design flow
© 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
15
Evolution of FPGA and its design flow
User Code Compiler Executable
Netlister Netlist
Place
and
Route . .
Bitstream
Schematics/
HDL
HLL Compiler
Compiler HLL
[à la S. Guccione]
CPU core
FPGA core
Memory core Compiler
HLL
soft
CPU
© 2002, [email protected] http://KressArray.de
inter face
s
CPU core
FPGA core
Memory core
rDPA
core
inter face
s
soft
rDPA
as soon as Giga FPGA is available
© 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
16
Some soft CPU core examples
Spartan-II 16 bit DSP DSPuva16
FLEX10K30 or EPF6016
i8080A My80
32-bit gr1050
16-bit gr1040
Altera – Mercury
8 bit Nios
Altera
22 D-MIPS
32-bit instr. set
Nios 50 MHz
Altera
Mercury
16-bit instr. set
Nios
Xilinx up to 100 on one FPGA
32 bit standard RISC
32 reg. by 32 LUT RAM-based reg.
MicroBlaze 125 MHz 70 D-MIPS
platform architecture core
SpartanXL RISC integer C xr16
old Xilinx FPGA Board
16-bit RISC, 2 opd. Instr.
YARD-1A
1 Flex 10K20 Acorn-1
Altera, Lattice, Xilinx
8 bit CISC 1Popcorn-1
Lattice 4 isp30256, 4 isp1016
12 bit DSP Reliance-1
2 XILINX 3020 LCA
8 bits Instr. + ext. ROM
REGIS
200 XC4000E CLBs
CISC, 32 reg. uP1232 8-bit
ARM ARM7 clone
SPARC Leon
25 Mhz
platform architecture core
© 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
17
soft CPUs in academic teaching
• UCSC: 1990!
• Märaldalen University
• Chalmers University
• Cornell University
• Gray Research
• Georgia Tech
• Hiroshima City Univ.
• Michigan State
• Univ. de Valladolid
• Virginia Tech
• Washington U. St. Louis
• New Mexico Tech
• UC Riverside • Tokai University
© 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
18
ASIC emulation
• ASIC emulation / Rapid Prototyping: to replace simulation
• Quickturn (Cadence), IKOS (Synopsys), Celaro (Mentor)
• hours of compilation run: inefficient since netlist-based: ...
• ... ASIC emulators will become obsolete soon
• by RTR: in-circuit execution debugging instead of emulation
• new business model: upgradable morphware is the product
• emulation for solving the spare part problem in many areas
Page 4
Reiner Hartenstein (invited paper): Trends in Reconfigurable Logic and Reconfigurable Computing; 9th IEEE International Conference on Electronics, Circuits and Systems - ICECS 2002, September 15-18, 2002, Dubrovnik, Croatia
Reiner Hartenstein, University of Kaiserslautern, Germany http://hartenstein.de
4
© 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
19
The microelectronics spare part problem
•Original fab line is no more existing
•ICs do not survive storage time
•Demand: several decades of availability
2 1 0.5 0.25 0.13 0.1 0,07 µ feature size
[Hartenstein 2002]
• e. g. car price: ~25% electronics
© 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
20
The microelectronics spare part problem
2 1 0.5 0.25 0.13 0.1 0,07 µ feature size
[Hartenstein 2002]
key problem in many application areas: medical, aerospace, automotive, other transportation, military, industrial equipment controllers, et al.
© 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
21
>> The Dichotomy of Models
• The Computer Architecture Crisis
• The Impact of Reconfigurable Platforms
• The Dichotomy of Models
• Parallelism
• Conclusions
http://www.uni-kl.de
© 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
22
Matter & Antimatter
The World of Matter machine paradigm: the Atom
+ + -
The World of Anti Matter machine paradigm: Anti Atom
- - +
© 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
23
Matter & Antimatter of Informatics :
- DPU
+
Anti Machine paradigm
+
CPU
-
nothing central !
© 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
24
computing paradigms and methodologies: instruction-stream-based vs. data-stream-based
1946: machine paradigm (von Neumann) 1980: data streams (Kung, Leiserson) 1989: anti machine paradigm introduced 1990: anti machine implementation methodology 1990: rDPU (Rabaey) 1994: anti machine high level programming language 1995: super systolic rDPA (Kress) 1996+: SCCC (LANL), SCORE, ASPRC, Bee (UCB), ... 1997: configware / software partitioning compiler (Becker) 2000: generator for rDPA with high memory bandwidth
(tutorials and courses available on all this)
Page 5
Reiner Hartenstein (invited paper): Trends in Reconfigurable Logic and Reconfigurable Computing; 9th IEEE International Conference on Electronics, Circuits and Systems - ICECS 2002, September 15-18, 2002, Dubrovnik, Croatia
Reiner Hartenstein, University of Kaiserslautern, Germany http://hartenstein.de
5
© 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
25
Nasty Matter
+
CPU
Data
Path
instruction sequencer
RAM
Address Computation Overhead
Instruction Fetch Overhead
central von Neumann bottleneck
extremely power hungry and area inefficient
reconfigurable?
the wrong machine paradigm
© 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
26
- DPU
Data
Path
Unit
DPU
Data
Path
instruction sequencer
Matter vs. Antimatter: CPU vs. DPU
+
dat
a st
ream
dat
a st
ream
s
+
+
Data
Path
Unit
DPU
© 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
27
heavy anti atoms: DPA = DPU array
- DPA
- DPU
- DPU
- DPU
- DPU
- DPU
- DPU
- DPU
- DPU
- DPU -
DPA
+
+
+
+
+
+
+
+
+
stre
amware
: dat
a st
ream
s sp
inni
ng a
roun
d
© 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
28
+
CPU
Data
Path
instruction sequencer
+ simple machine paradigm + scalability
+ relocatability + compatibility
= secret of success of software industry
RAM
RAM-based CPU:
© 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
29
Success Factors
property instruction
stream based
data stream based
reconfigurable
hardwired fine grain (FPGA)
coarse grain
RAM-based yes yes yes (hardwired)
machine paradigm yes no available available
compatibility yes limited feasible feasible
scalability yes no good* (hardwired)
code relocatability yes no good* (hardwired)
*) if KressArray used
**) mapping coarse grain onto FPGA
good**
good**
feasible**
available**
success of software industry
• for configware industry is missing: – FPGA compatibility, – fully scalable FPGA, – relocatable configuration code • rDPUs and rDPAs do
much better than FPGAs
© 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
30
>>> Problems with Concurrency
• The Computer Architecture Crisis
• The Impact of Reconfigurable Platforms
• The Dichotomy of Models
• Parallelism
• Conclusions http://www.uni-kl.de
Page 6
Reiner Hartenstein (invited paper): Trends in Reconfigurable Logic and Reconfigurable Computing; 9th IEEE International Conference on Electronics, Circuits and Systems - ICECS 2002, September 15-18, 2002, Dubrovnik, Croatia
Reiner Hartenstein, University of Kaiserslautern, Germany http://hartenstein.de
6
© 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
31
Parallelism by Concurrency
independent instruction streams
....
Bus(es) or switch box
Data
Path
instruction sequencer
Data
Path
instruction sequencer
Data
Path
instruction sequencer
Data
Path
instruction sequencer
+ -
+
-
- +
+
+
-
+
- +
-
-
difficult coordination
massive run time overhead © 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
32
Data-stream-based Parallelism
See my other talk
ICECS 2002 IEEE 9th International Conference
on Electronics, Circuits and Systems
Memory Organisation for Datastream-based Reconfigurable Computing
(invited paper)
Michael Herz, Agilent Technologies
Reiner Hartenstein, University of Kaiserslautern Miguel Miranda, Erik Brockmeyer, Francky Catthoor, IMEC, Leuven
Dubrovnik, Croatia September 15-18, 2002
© 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
33
>> The Dominance of Embedded Systems
• The Computer Architecture Crisis
• The Impact of Reconfigurable Platforms
• The Dichotomy of Models
• Parallelism
• Conclusions
http://www.uni-kl.de
© 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
34
Summary of the Anti Machine Paradigm
• anti language primitives are almost the same (slightly extended)
• anti machine execution potential is dramatically more powerful
• provides drastically more flexibility
• not always replacing von Neumann
© 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
35
Conclusions
•the anti machine is the way to go for massive parallelism, also data-intensive applications
•reconfigurable anti machine for high performance with short product life cycles, unstable standards
•reconfigurable for low cost low volume production
•Giga FPGAs highly promising - only by a new design flow: configware could repeat the success of software industry
•sparepart problem: needs new infrastructures
© 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
36 © 2001, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab>>> thank you
thank you for your patience
Page 7
Reiner Hartenstein (invited paper): Trends in Reconfigurable Logic and Reconfigurable Computing; 9th IEEE International Conference on Electronics, Circuits and Systems - ICECS 2002, September 15-18, 2002, Dubrovnik, Croatia
Reiner Hartenstein, University of Kaiserslautern, Germany http://hartenstein.de
7
© 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
37 © 2001, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab>>> END
END © 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
38 © 2001, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab>>> Appendix
Appendix
for discussion
© 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
39
>> Problems to be solved
• Configware Market
• FPGA Market
• Embedded Systems (Co-Design)
• Hardwired IP Cores on Board
• Run-Time Reconfiguration (RTR)
• Rapid Prototyping & ASIC Emulation
• Evolvable Hardware (EH)
• Academic Expertise
• ASICs dead
• Soft CPU
• HLLs
• Problems to be solved
© 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
40
EDA industry shift into CS mentality [Wojciech Maly]
• patches instead of engineering
• innovation stalled many years ago
• 85% users hate their tools
• netlist-based: do not care about efficiency, ...
• ... do not care about transistor density
© 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
41
[Jonathan Rose] FPGAs Give You
• Instant Fabrication – Get to Market Fast – Fix ‘em quick
• Zero NRE Charges – Low Risk
– Low Cost at good volume
© 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
42
Machine Paradigms
machine category Computer (the Machine:
“v. Neumann”) The Anti Machine
driven by: Instruction streams data streams (no “dataflow”)
engine principles instruction sequencing sequencing data streams
state register single program counter (multiple) data counter(s)
Communication path set-up .
at run time at load time
resource DPU (e.g. single ALU) DPU or DPA (DPU array) etc. data path
operation sequential parallel pipe network etc.
( “instruction fetch” )
also hardwired implementations* *) e g. Bee project Prof. Broderson
Page 8
Reiner Hartenstein (invited paper): Trends in Reconfigurable Logic and Reconfigurable Computing; 9th IEEE International Conference on Electronics, Circuits and Systems - ICECS 2002, September 15-18, 2002, Dubrovnik, Croatia
Reiner Hartenstein, University of Kaiserslautern, Germany http://hartenstein.de
8
© 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
43
Machine Paradigms
machine category Computer (the Machine:
“v. Neumann”) The Anti Machine
driven by: Instruction streams data streams (no “dataflow”)
engine principles instruction sequencing sequencing data streams
state register single program counter (multiple) data counter(s)
Communication path set-up .
at run time at load time
resource DPU (e.g. single ALU) DPU or DPA (DPU array) etc. data path
operation sequential parallel pipe network etc.
( “instruction fetch” )
also hardwired implementations* *) e g. Bee project Prof. Broderson
© 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
44
The Crisis of Computing Sciences
• Computing Sciences are in a severe crisis
• Computing curricula are obsolete because of strictly enforced „procedural-only“ blinders
• Computer Architecture and related areas have lost leadership in digital system implementation
• CS ignores > 90% µprocessors in embedded systems: 10 times more programmers will write embedded applications than computer software by 2010
• A disruptive promising therapy introduced by new approaches coming with Reconfigurable Computing
© 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
45
Programming Language Paradigms
language category Computer Languages Languages f. Anti Machine
both deterministic procedural sequencing: traceable, checkpointable
operation sequence driven by:
read next instruction, goto (instr. addr.),
jump (to instr. addr.), instr. loop, loop nesting
no parallel loops, escapes, instruction stream branching
read next data item, goto (data addr.),
jump (to data addr.), data loop, loop nesting, parallel loops, escapes, data stream branching
state register program counter data counter(s)
address computation
massive memory cycle overhead overhead avoided
Instruction fetch memory cycle overhead overhead avoided
parallel memory bank access interleaving only no restrictions
© 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
46
Programming Language Paradigms
language category Computer Languages Languages f. Anti Machine
both deterministic procedural sequencing: traceable, checkpointable
operation sequence driven by:
read next instruction, goto (instr. addr.),
jump (to instr. addr.), instr. loop, loop nesting
no parallel loops, escapes, instruction stream branching
read next data item, goto (data addr.),
jump (to data addr.), data loop, loop nesting, parallel loops, escapes, data stream branching
state register program counter data counter(s)
address computation
massive memory cycle overhead overhead avoided
Instruction fetch memory cycle overhead overhead avoided
parallel memory bank access interleaving only no restrictions
© 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
47
Conclusion: all knowledge needed is available
• languages
• machine paradigm
• compilation techniques
• anti architectural resources
• sequencing methodology: hw & sw
• hw / sw partitioning methodology
• parallel memory IP core and module generator vendors
courses / embedded tutorials: • DATE. Munich, 2001
• ASP-DAC, Yokohama, 2001 • SBCCI, Brasilia, 2001
full day:
Univ. Montpellier 1998 Nokia / Univ. Tampere, Finland, 2002
CNRS Paris France, 2002
• keynotes 2001 / 2002
• invited talks 2001 / 2002
• anything else needed
© 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
48
Ubiquitous embedded systems
20 billion µprocessors (2001)
> 90% in embedded systems
10 times more programmers will write embedded applications than computer software by 2010
That’s where our graduates will go
Embedded systems means:
• hardware / software co-design
• configware / software co-design
• hardware / configware / software co-design
Page 9
Reiner Hartenstein (invited paper): Trends in Reconfigurable Logic and Reconfigurable Computing; 9th IEEE International Conference on Electronics, Circuits and Systems - ICECS 2002, September 15-18, 2002, Dubrovnik, Croatia
Reiner Hartenstein, University of Kaiserslautern, Germany http://hartenstein.de
9
© 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
49
The Situation in Computing Sciences
• Computing Sciences are in a severe crisis
• New fundamentals and R&D directions are inevitable
• my mission: getting you involved
• All knowledge needed is readily available ...
• ... even from Computing Sciences
• Silicon application and EDA provide useful concepts
• Reconfigurable Computing has the remedy
© 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
50
the edu gap has dramatic consequences
•Key R&D scenes are drying out or dying
•because of a lack of qualified researchers
•the embedded system design crisis gets worse
•because of a lack of qualified designers
•many innovative products cannot be sold
•because of a lack of qualified customers
•the edu gap is widening dramatically
•because of a lack of qualified educators
© 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
51
Super Pipe Networks
pipeline properties array applications
shape resources
mapping scheduling
(data stream formation)
systolic array
regular data
dependencies only
linear only
uniform only
linear projection or algebraic synthesis
super-systolic DPA
no restrictions simulated
annealing or P&R algorithm
(e.g. force-directed) scheduling algorithm
*) KressArray [ASP-DAC-1995]
© 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
52
.... it‘s an alternative culture ....
• now the area is going mainstream: a rapidly widening audience of non-specialists gets interested ...
• severe communication gaps due to educational deficits
• not only to users: still many hardware and EDA experts ask: isn’t it just logic design on a strange platform ?
• it is time to clarify and popularize fundamental aspects and to explain, that it is a fundamentally different culture
© 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
53 © 2001, [email protected] http://www.fpl.uni-kl.de
University of Kaiserslautern
Xputer Lab
Jürgen Becker’s Co-DE-X Co-Compiler
Analyzer / Profiler
Host Software
GNU C compiler
para d igm Computer machine
DPSS KressArray Configware
X-C compiler
Xputer machine paradigm
Partitioner
X-C is C language extended by MoPL X-C
Resource Parameters
supporting different platforms
supporting platform-based design
© 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
54
Impact of Makimoto’s wave
TTL µproc., memory
custom
standard
ASICs, accel’s
LSI, MSI
1957
1967
1977
1987
1997
2007
Procedural personalization via RAM-based
Machine Paradigm
Personalization (CAD) before fabrication
structural personalization:
RAM-based before run time
Software Industry’s Secret of Success
Repeat Success Story by new Machine Paradigm !
Configware Industry
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Reiner Hartenstein (invited paper): Trends in Reconfigurable Logic and Reconfigurable Computing; 9th IEEE International Conference on Electronics, Circuits and Systems - ICECS 2002, September 15-18, 2002, Dubrovnik, Croatia
Reiner Hartenstein, University of Kaiserslautern, Germany http://hartenstein.de
10
© 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
55 © 2001, [email protected]
University of Kaiserslautern
Xputer Lab
instructions
program cou n ter:
state register
Compiler RAM
Datapath
har dw ired
Sequencer
Computer tightly coupled
by compact instruction code
“von Neumann” does not support
soft data paths
Datapath
Xputer
Scheduler
Compiler
RAM
(multiple) sequencer
Datapath Array
“instructions”
University of Kaiserslautern
Xputer Lab
loosely coupled by decision data bits only
Xputer: The Soft
Machine
Paradigm reconfigurable
also for hardwired
Computer: the wrong Machine Paradigm
“von Neumann”
s
d a ta cou n ter
(anti machine) © 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
56
Reconfigurable semiconductor market
Xilinx 42%
Altera 37%
Lattice 15%
Actel 6%
Top 4 PLD Manufacturers 2000
total: $3.7 Bio
• [Dataquest] > $7 billion by 2003.
• PLD vendors’ and their alliances provide libraries of “soft IPs”
Configware Market
• fastest growing semiconductor market segment
coarse-grained:
rDPUs: configurable functional blocks
fine-grained:
cLBs, rLBs: configurable logic blocks
PACT AG, Munich, Germany http://pactcorp.com
Quicksilver, San Jose http://quicksilver-tech.com
© 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
57
Semiconductor Revolutions
“Mainstream Silicon Application is switching every 10 Years”
TTL µproc., memory
custom
standard
1957
1967
1977
1987
1997
2007
ASICs, accel’s
LSI, MSI
“The Programmable System-on-a-Chip is the next wave“
Tredennick’s Paradigm Shifts
hardwired
algorithm: fixed
resources: fixed
procedural programming
algorithm: variable
resources: fixed
structural programming
algorithm: variable
resources: variable
vN machine paradigm
anti machine paradigm
© 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
58
Impact of Makimoto’s wave
TTL µproc., memory
custom
standard
ASICs, accel’s
LSI, MSI
1957
1967
1977
1987
1997
2007
Procedural personalization via RAM-based
Machine Paradigm
Software Industry’s Secret of Success
© 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
59
Impact of Makimoto’s wave
TTL µproc., memory
custom
standard
ASICs, accel’s
LSI, MSI
1957
1967
1977
1987
1997
2007
structural personalization:
RAM-based before run time
Repeat Success Story by new Machine Paradigm !
Configware Industry
© 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
60
Impact of Data-stream-based ...
TTL µproc., memory
custom
standard
ASICs, accel’s
LSI, MSI
1957
1967
1977
1987
1997
2007
structural personalization:
hardwired before fabrication
Repeat Success Story by new Machine Paradigm !
Embedded Hardware/ Configware Industry
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Reiner Hartenstein (invited paper): Trends in Reconfigurable Logic and Reconfigurable Computing; 9th IEEE International Conference on Electronics, Circuits and Systems - ICECS 2002, September 15-18, 2002, Dubrovnik, Croatia
Reiner Hartenstein, University of Kaiserslautern, Germany http://hartenstein.de
11
© 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
61
Rapidly growing CS education gap
•Our computing curricula are obsolete
• introduction is strictly „procedural-only“
•vN-only use of terms like „computer organisation“, „ computer structures“, „ computer architecture
•graduates are not prepared to the real world
– most applications for embedded systems (>90% by 2010)
•our graduates are unable to compete with EE graduates
•only a few % curricula need to be changed
•my mission: getting you involved
© 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
62
Binding Time vs. Computing Domain
time domain (procedural)
Binding time: (Set-up of Communication Channels)
at run time microprocessor parallel computer
time & space (hybrid)
later fabrication step ASICs
space domain (structural)
before fabrication full custom ICs
at loading time
at compile time
Reconfigurable Computing
array processor
programming domain:
supersystolic arrays systolic
arrays
© 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
63
Sources: Proc ISSCC, ICSPAT, DAC, DSPWorld
Why Coarse Grain instead of FPGA ?
physical logical
FPGA logical
1980 1990 2000 2010
FPGA physical
100 000 000 000
10 000 000 000
1000 000 000
100 000 000
10 000 000
1000 000
100 000
10 000
1000
Tra
nsis
tors
/ c
hip
~ 10
~ 10 000
drastically smaller configuration memory
a lot of more benefits
much faster loading
FPGA routed
reduced reconfigurability overhead by up to ~ 1000
© 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
64
What are the differences ?
vN* computing:
• computing in time
• instruction fetch at run time
• procedural programming
• instruction scheduling
Reconfigurable Computing:
• computing in space and time
• “instruction” fetch at compile time
• structural programming
• data scheduling
• i. e. Data-stream-based
• also hardwired implementations**
• “instruction” fetch before fabrication
**) e g. Bee project Prof. Broderson *) vN stands for “von Neumann”
© 2002, [email protected] http://KressArray.de
University of Kaiserslautern
Xputer Lab
65
Basics of Binding Time
run time
loading time
compile time
time of “Instruction Fetch”
microprocessor parallel computer
Reconfigurable Computing
“Instruction” generalized: including complex expressions and other datapaths
strong impact on the machine paradigm !
