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Reliability studies of Hf-doped and NH3-nitrided gate dielectric for advanced CMOS application

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Reliability studies of Hf-doped and NH 3 -nitrided gate dielectric for advanced CMOS application C.W. Yang, Y.K. Fang, S.F. Chen, C.S. Lin, C.Y. Lin, W.D. Wang, T.H. Chou, P.J. Lin, M.F. Wang, T.H. Hou, L.G. Yao, S.C. Chen and M.S. Liang Abstract: A novel technique is proposed for forming high-K dielectric of HfSiON by sequentially doping base oxide with Hf and nitridation with NH 3 . The HfSiON gate dielectric demonstrates excellent device performances such as only 10% degradation of saturation drain current and almost 45 times of magnitude reduction in gate leakage compared to conventional SiO 2 gate dielectric at the same equivalent oxide thickness (EOT). Additionally, negligible flatband voltage shift is achieved with this technique. Excellent performances in electrical stressing are also demonstrated by the dielectric. 1 Introduction Recently, high-K gate dielectric films have been widely studied to replace SiO 2 for low power and small leakage current CMOS technology applications [1–3] . Among the reported high-K dielectrics, HfO 2 has attracted much attention as a promising candidate due to high dielectric constant, wide band-gap, and compatibility with poly–Si [4] . However, some techniques have been proposed [1–3, 5] to improve the properties of high-K film, some critical issues such as obvious mobility degradation and large flatband voltage shift still existed, thus impeding its real applications for device and circuit. The mobility degradation is due to the surface states or defects at the HfO 2 /Si interface and the large positive flatband voltage shift to the existed negative charges in HfO 2 dielectric. Hence, in this study, we developed a novel method for preparation of high-K dielectric to solve those issues. First, the base oxide was thermally grown and then doped with hafnium (Hf). Next, the doped oxide was nitrided with NH 3 to form HfSiON high-K dielectric. With the method, the interface states or defects could be reduced or eliminated by the thermally grown base oxide, and the negative charges in dielectric could be compensated with the positive charges induced by the incorporated nitrogen, thus improving the mobility degradation and flatband voltage shift. In comparison to the reported techniques, the proposal possesses the advantages of less degradation of mobility, higher drain current and the negligible flatband voltage shift. 2 Experimental N+ NMOSFETs with polycrystalline-silicon gates were fabricated on p-type (100) silicon wafers using 0.1 mm CMOS technology. After a standard SC1/SC2 wet clean, 1.7 nm base oxides were thermally grown in O 2 ambient. Then, the base oxides were doped with Hf (hafnium) using HfCl 4 at substrate temperature of 3001C by atomic layer chemical vapour deposition (ALCVD), and sequentially annealed in NH 3 under 9501C for 60 seconds to form the HfSiON. Conventionally ALCVD deposited HfO 2 (ALD_HfO 2 ) films were also prepared by using HfCl 4 and H 2 O in cycles. Next, a 150 nm thick undoped poly–Si film was deposited and patterned, followed by phosphorus of 25 keV implantation with dose of 1 10 15 cm 2 to form the N+ poly-Si gate. Then spike activation was carried out at 10501C. In comparison, control oxides were prepared by wet oxidation of the Si substrate directly. Finally, interlayer deposition (ILD), W-plug formation and Cu interconnec- tion were conducted sequentially, followed by forming gas annealing at 4001C for 30 min. Additionally, for the measurement of flatband voltage shift and extraction of equivalent oxide thickness (EOT), capacitors with split dielectrics were also prepared with the same process for NMOSFET samples, except for the larger area of 10000 mm square and the S/D being connected together. Current–voltage (I–V) and capacitance–voltage (C–V) characteristics were obtained from HP 4156B precision semiconductor parameter analyser and HP 4284A precision LCR meter measurements, respectively. On the other hand, a C–V simulator, which took into account both poly-Si depletion and quantum mechanical effects [6] , was used to extract EOT and V FB values. 3 Results and discussions Figure 1 shows the SIMS analysis of the HfSiON sample. The existence of HfSiON layer is identified by the presence of nitrogen, oxygen, and hafnium (Hf). In the Figure, the scale of hafnium (Hf) signal on the right vertical axis was enlarged for the lower sputtering yield of hafnium with heavy atomic mass. Based on the C–V measurement, for various gate dielectrics, i.e. SiO 2 , HfSiON, and ALD_ HfO 2 ., the extracted EOT and V FB for SiO 2 , HfSiON and C.W. Yang, Y.K. Fang, S.F. Chen, C.S. Lin, C.Y. Lin, W.D. Wang, T.H. Chou and P.J. Lin are with the VLSI Technology Laboratory, Institute of Micro- electronics, Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan, Republic of China M.F. Wang, T.H. Hou, L.G. Yao, S.C. Chen and M.S. Liang are with Taiwan Semiconductor Manufacturing Co. Ltd., Hsinchu, Taiwan, Republic of China E-mail: [email protected] r IEE, 2005 IEE Proceedings online no. 20041216 doi:10.1049/ip-cds:20041216 Paper first received 29th March and in revised form 27th October 2004 IEE Proc.-Circuits Devices Syst., Vol. 152, No. 5, October 2005 407
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Page 1: Reliability studies of Hf-doped and NH3-nitrided gate dielectric for advanced CMOS application

Reliability studies of Hf-doped and NH3-nitrided gatedielectric for advanced CMOS application

C.W. Yang, Y.K. Fang, S.F. Chen, C.S. Lin, C.Y. Lin, W.D. Wang, T.H. Chou, P.J. Lin, M.F. Wang, T.H. Hou,L.G. Yao, S.C. Chen and M.S. Liang

Abstract: A novel technique is proposed for forming high-K dielectric of HfSiON by sequentiallydoping base oxide with Hf and nitridation with NH3. The HfSiON gate dielectric demonstratesexcellent device performances such as only 10% degradation of saturation drain current and almost45 times of magnitude reduction in gate leakage compared to conventional SiO2 gate dielectric atthe same equivalent oxide thickness (EOT). Additionally, negligible flatband voltage shift isachieved with this technique. Excellent performances in electrical stressing are also demonstrated bythe dielectric.

1 Introduction

Recently, high-K gate dielectric films have been widelystudied to replace SiO2 for low power and small leakagecurrent CMOS technology applications [1–3]. Among thereported high-K dielectrics, HfO2 has attracted muchattention as a promising candidate due to high dielectricconstant, wide band-gap, and compatibility with poly–Si [4].However, some techniques have been proposed [1–3, 5] toimprove the properties of high-K film, some critical issuessuch as obvious mobility degradation and large flatbandvoltage shift still existed, thus impeding its real applicationsfor device and circuit.

The mobility degradation is due to the surface states ordefects at the HfO2/Si interface and the large positiveflatband voltage shift to the existed negative charges inHfO2 dielectric. Hence, in this study, we developed a novelmethod for preparation of high-K dielectric to solve thoseissues. First, the base oxide was thermally grown and thendoped with hafnium (Hf). Next, the doped oxide wasnitrided with NH3 to form HfSiON high-K dielectric. Withthe method, the interface states or defects could be reducedor eliminated by the thermally grown base oxide, and thenegative charges in dielectric could be compensated with thepositive charges induced by the incorporated nitrogen, thusimproving the mobility degradation and flatband voltageshift. In comparison to the reported techniques, theproposal possesses the advantages of less degradation ofmobility, higher drain current and the negligible flatbandvoltage shift.

2 Experimental

N+ NMOSFETs with polycrystalline-silicon gates werefabricated on p-type (100) silicon wafers using 0.1mmCMOS technology. After a standard SC1/SC2 wet clean,1.7nm base oxides were thermally grown in O2 ambient.Then, the base oxides were doped with Hf (hafnium) usingHfCl4 at substrate temperature of 3001C by atomic layerchemical vapour deposition (ALCVD), and sequentiallyannealed in NH3 under 9501C for 60 seconds to form theHfSiON. Conventionally ALCVD deposited HfO2

(ALD_HfO2) films were also prepared by using HfCl4and H2O in cycles. Next, a 150nm thick undoped poly–Sifilm was deposited and patterned, followed by phosphorusof 25keV implantation with dose of 1� 1015 cm�2 to formthe N+ poly-Si gate. Then spike activation was carried outat 10501C. In comparison, control oxides were prepared bywet oxidation of the Si substrate directly. Finally, interlayerdeposition (ILD), W-plug formation and Cu interconnec-tion were conducted sequentially, followed by forming gasannealing at 4001C for 30min. Additionally, for themeasurement of flatband voltage shift and extraction ofequivalent oxide thickness (EOT), capacitors with splitdielectrics were also prepared with the same process forNMOSFET samples, except for the larger area of 10000mmsquare and the S/D being connected together.

Current–voltage (I–V) and capacitance–voltage (C–V)characteristics were obtained from HP 4156B precisionsemiconductor parameter analyser and HP 4284A precisionLCR meter measurements, respectively. On the other hand,a C–V simulator, which took into account both poly-Sidepletion and quantum mechanical effects [6], was used toextract EOT and VFB values.

3 Results and discussions

Figure 1 shows the SIMS analysis of the HfSiON sample.The existence of HfSiON layer is identified by the presenceof nitrogen, oxygen, and hafnium (Hf). In the Figure, thescale of hafnium (Hf) signal on the right vertical axis wasenlarged for the lower sputtering yield of hafnium withheavy atomic mass. Based on the C–V measurement, forvarious gate dielectrics, i.e. SiO2, HfSiON, and ALD_HfO2., the extracted EOT and VFB for SiO2, HfSiON and

C.W. Yang, Y.K. Fang, S.F. Chen, C.S. Lin, C.Y. Lin, W.D.Wang, T.H. Chouand P.J. Lin are with the VLSI Technology Laboratory, Institute of Micro-electronics, Department of Electrical Engineering, National Cheng KungUniversity, Tainan, Taiwan, Republic of China

M.F. Wang, T.H. Hou, L.G. Yao, S.C. Chen and M.S. Liang are with TaiwanSemiconductor Manufacturing Co. Ltd., Hsinchu, Taiwan, Republic of China

E-mail: [email protected]

r IEE, 2005

IEE Proceedings online no. 20041216

doi:10.1049/ip-cds:20041216

Paper first received 29th March and in revised form 27th October 2004

IEE Proc.-Circuits Devices Syst., Vol. 152, No. 5, October 2005 407

Page 2: Reliability studies of Hf-doped and NH3-nitrided gate dielectric for advanced CMOS application

HfO2 dielectrics are 15.7A( , �1.09V; 16A( , �1.08V and

18A( , �0.8V, respectively. Obviously, the flatband voltageof HfO2 is shifted positively against the SiO2 and implies theexisting of negative charges in HfO2 [1, 2, 5]. On the otherhand, negligible flatband voltage shift against SiO2 is foundin the HfSiON sample. In the past, we found [7] the dopednitrogen will generate positive charges in gate dielectric.Therefore, we attribute the negligible flatband voltage shiftin HfSiON to the compensation of negative charges withthe positive charges generated by the nitrogen incorporatedin HfSiON. The leakage currents measured at 1V are about78mA/cm2, 0.1mA/cm2 and 3.24A/cm2 for HfSiON, HfO2

and SiO2 dielectrics, respectively. The leakage currentthrough HfSiON dielectric is almost 45 times the reductionin magnitude to the SiO2 gate dielectric at same EOT.Because of the physical thickness of HfO2, HfSiON, andSiO2, measured from TEM and shown in the Fig. 2, are

39.2A( , 24A( , and 17.6A( , respectively, it is reasonable toattribute the reduction in leakage of HfSiON and HfO2 totheir thicker physical thickness. Based on the measuredthickness, the extracted k-value is about 5.85 for HfSiONdielectric. Although this value is lower than 10, it could beraised by doping more hafnium into the base oxide andoptimising the nitridation process. Since, the preparation ofHfSiON is doped with hafnium (Hf) and then nitrided with

NH3 on a base oxide (SiO2). The content of Hf andnitrogen in SiO2 should affect the dielectric’s permittivity.

Although even the HfO2 possesses the least leakagecurrent, it also suffers a large number of defects or surfacestates in the HfO2/Si channel interface, thus degrading thedrain current for future CMOS technology applications.The Id–Vgs curves are shown in Fig. 3. It is clear thatthreshold voltage for HfO2 is too large for 0.1mm deviceapplication at this stage. Using our method, well-behavedId–Vg curve can be achieved. Figure 4 presents the draincurrent versus drain voltage (Id–Vds) curves of short channelNMOSFETs with W/L¼ 10/0.1mm under various normal-ised gate biases (Vgs�Vth). The gate voltage has beennormalised with respect to threshold voltage to minimise theeffect of threshold voltage. The measured drain currents atVgs � Vth ¼ 1 V ¼ Vds are about 9.5mA, 10.5mA, and2.6mA for HfSiON, SiO2 and HfO2, respectively. Almostthree-fourths degradation in magnitude of Idsat for HfO2

with respect to SiO2, but only 10% degradation for HfSiONto SiO2 is found. Based on the C–V curves and Id–Vgs

curves, the extracted mobility values at effective field of1MV/cm are 267, 216, and 103cm2/V-s for SiO2, HfSiON,and HfO2, respectively, as shown in Fig. 5. To the best ofour knowledge, this is the least degradation in Idsat forNMOSFET with high-K gate dielectric. We assume thethermally grown 1.7nm base oxide in the proposed HfSiON

0 2 4 6 8 10depth, nm

N, S

i, an

d O

cou

nt, a

rb. u

nits

hafn

ium

(H

f) c

ount

, arb

. uni

ts

NSi

O

Hf

Si

N Hf

O

Fig. 1 SIMS analysis of the HfSiON sample

3nm

HfSiON SiO2

3nm 3nm

HfO2

Fig. 2 TEM pictures of HfSiON, HfO2, and SiO2

Physical thickness for HfO2, HfSiON, and SiO2 measured from the TEM are 39.2A( , 24A( , and 17.6A( , respectively

−0.5 1.51.00.50 2.00

0.5

1.0

1.5

2.0

2.5

3.0

W /L =10/0.1µmVds = 0.1V

SiO2HfSiON

HfO2

I d, m

A

Vgs , V

Fig. 3 Drain current against gate voltage curves (Id–Vgs) at drainbias of 0.1 V

408 IEE Proc.-Circuits Devices Syst., Vol. 152, No. 5, October 2005

Page 3: Reliability studies of Hf-doped and NH3-nitrided gate dielectric for advanced CMOS application

gate dielectric releases the stress at the interface of HfSiON/Si, thus eliminating the interface states or defects andresulting in the large Idsat.

Excellent device performances are obtained using thistechnique. Next, the trapping and reliability characteristicsof the HfSiON gate dielectric are executed and compared toSiO2. Figure 6 shows the C–V measurements (at 100kHz)of NMOS capacitors with HfSiON dielectric before andafter stressing at 1.6V under 1401C for 1 hour. The flatbandvoltage shift is less than 10mV, indicating good stabilityunder stressing. Figure 7 demonstrates the charge-trappingcharacteristics of NMOS capacitors with HfSiON and SiO2

dielectrics at both gate polarities of 2.5V. Less trapgeneration for HfSiON is observed. Figure 8 displays thestress-induced leakage current (SILC) of NMOS capacitorsmeasured at�1V under constant voltage stressing (CVS) of�3V. The SILC of the MOS capacitor with SiO2 increasessignificantly after 100 s stressing, but the SILC of the MOScapacitor with HfSiON increases only after 800 s stressing.

4 Conclusion

The experimental results in this study indicate that a baseoxide doped with hafnium (Hf) and sequentially nitridedwith NH3 forms the HfSiON high-K dielectric caneffectively suppress flatband voltage shift, and significantly

0 2.01.51.00.50

4

8

12

16

20

0.5V

1V

Vgs −Vth =1.5V

W /L =10/0.1µm

SiO2

HfSiON

HfO2I d ,

mA

Vds , V

Fig. 4 Drain current against drain voltage (Id–Vds) curves of theshort channel NMOSFETs with W/L¼ 10/0.1mm under variousnormalised gate biasesMeasured drain current at Vgs�Vth¼Vds¼ 1V are 9.5mA, 10.5mAand 2.6mA for HfSiON, SiO2 and HfO2, respectively

0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.20

100

200

300

400SiO2HfSiONHfO2

effe

ctiv

e m

obili

ty, c

m2 /V

-s

effective field, MV/cm

Fig. 5 Extracted mobility values for SiO2, HfSiON, and HfO2

based on C–V and Id–Vgs measurementsRespective values are 216 and 103cm2/V-s at effective field of 1MV/cm

−3 −2 −1 0 1 2 30

4

8

12

16

20

24

HfSiON dielectric

area =1250 µm2

before stress

after stress

capa

cita

nce,

pF

Vgs , V

Fig. 6 C–V curves of HfSiON gate dielectric before/after stressingat 1.6 V under 1401C for 1 hFrequency of C–V measurement is 100kHz

−4

−2

0

2

4

6

100806040200time, s

∆J

g , µ

A/c

m2

HfSiONsubstrate-injection

gate-injection

SiO2

Fig. 7 Charge trapping characteristics of SiO2 and HfSiON atboth polarities

0

10

20

30

40

0 200 400 600 800 1000

stress time, s

J g, A

/cm

2 , at-

1V

SiO2

HfSiON

Fig. 8 Stress-induced leakage current (SILC) of NMOS capaci-tors measured at �1 V under constant voltage stressing (CVS) of�3 V

IEE Proc.-Circuits Devices Syst., Vol. 152, No. 5, October 2005 409

Page 4: Reliability studies of Hf-doped and NH3-nitrided gate dielectric for advanced CMOS application

improve drain saturation current. The improvements in theHfSiON high-K dielectric are attributed to the chargescompensation induced by the incorporation of nitrogen andthe elimination of surface states or defects in the gatedielectric/channel interface with the thermally grown baseoxide. In addition, excellent performances in electricalstressing demonstrate good film qualities.

5 Acknowledgments

The authors would like to thank the members of R&D inTaiwan Semiconductor Manufacturing Co., Ltd., for waferfabrication and technical supports. The work was finan-cially supported by the National Science Council underContract NSC92-2215–E-006-016.

6 References

1 Gusev, E.P., Buchanan, D.A., Cartier, E., Kumar, A., DiMaria, D.,Guha, S., Callegari, A., Zafar, S., Jamison, P.C., Neumayer, D.A.,Copel, M., Gribelyuk, M.A., Okorn-Schmidt, H., D’Emic, C.,Kozlowski, P., Chan, K., Bojarczuk, N., Ragnarsson, L.-A., Ronsheim,P., Rim, K., Fleming, R.J., Mocuta, A., and Ajmera, A.: ‘Ultrathin

high-K gate stacks for advanced CMOS devices’. IEDM Tech. Dig.,2001, pp. 451–454

2 Kim, Y., Gebara, G., Freiler, M., Barnett, J., Riley, D., Chen, J.,Torres, K., Lim, J.E., Foran, B., Shaapur, F., Agarwal, A., Lysaght, P.,Brown, G.A., Young, C., Borthakur, S., Li, H.J., Nguyen, B., Zeitzoff,P., Bersuker, G., Derro, D., Bergmann, R., Murto, W., Hou, A., Huff,H.R., Shero, E., Pomarede, C., Givens, M., Mazanec, M., andWerkhoven, C.: ‘Conventional n-channel MOSFET devices usingsingle layer HfO2 and ZrO2 as high-K gate dielectrics with polysilicongate electrode’. IEDM Tech. Dig., 2001, pp. 455–458

3 Koyama, M., Suguro, K., Yoshiki, M., Kamimuta, Y., Koike, M.,Ohse, M., Hongo, C., and Nishiyama, A.: ‘Thermally stableultra-thin nitrogen incorporated ZrO2 gate dielectric prepared bylow temperature oxidation of ZrN’. IEDM Tech. Dig., 2001, pp.459–462

4 Hubbard, K.J., and Schlom, D.G.: ‘Thermal stability of binary oxidesin contact with silicon’, J. Mater. Res., 1996, 11, pp. 2757–2776

5 Wilk, G.D., Wallace, R.M., and Anthony, J.M.: ‘ High-K gatedielectrics: Current status and material properties considerations’,J. Appl. Phys., 2001, 89, (10), pp. 5243–5275

6 Lo, S.-H., Buchanan, D.A., and Taur, Y.: ‘Modeling and characteriza-tion of quantization, polysilicon depletion, and direct tunneling effectsin MOSFETs with ultrathin oxides’, IBM J. Res. Develop., 1999, 43,(3), pp. 327–337

7 Ting, S.F., Fang, Y.K., Chen, C.H., Yang, C.W., Hsieh, W.T., Ho, J.J.,Yu, M.C., Liang, M.S., Chen, S., and Shih, R.: ‘The effect of remoteplasma nitridation on the integrity o the ultrathin gate dielectric films in0.13mm CMOS technology and beyond’, IEEE Electron. Device Lett.,2001, 22, (7), pp. 327–329

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