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Remote Firmware Down Load
Xilinx V4LX25Xilinx V4LX25
Xilinx V4LX25Xilinx V4LX25
Altera StratixControl
Altera StratixControl
Xilinx V4FX20Xilinx V4FX20
EPROMXCF08EPROMXCF08
EPROMEPC16EPROMEPC16
EPROMXCF08EPROMXCF08EPROM
XCF08EPROMXCF08
Altera Altera
Atmel uControllerAtmel uController
EPROMEPC16
EPROM
XilinxVirtex 5XilinxVirtex 5
EPROM
XilinxVirtex 5XilinxVirtex 5
EPROM
XilinxVirtex 5XilinxVirtex 5
EPROM
AlteraAltera
CTP SD
TIFADC250ROC
SRAMSRAM
VXS IsquareC
VME
VME
Ethernet
Firmware Files
Firmware Download Diagram for Front-End Readout Modules
VXS IsquareC
FADC-250 Configuration Scheme
JTAG Links
Loading Configurarion During Code Development1) Connect (Altera or Xilinx) JTAG cable2) Set Dip Switch to select JTAG Chain3) Run Altera Quartus or Xilinx Impact program to
config Devices.
Remote ConfigLoading Configurarion After Installation1) Control FPGA receives config. data via VME-64 bus and
temporary stores to SRAM. Config. data for one or more FPGA can be received at once.
2) Control FPGA programs config. data into EPROM.3) Control FPGA read back config data from EPROM to
SRAM.4) VME host (ROC) read and compare data. If OK, issue
config command.5) Control FPGA issues config command to EPROM to load
new config. data to FPGA..
Altera Stratix (control)
Altera Stratix (control)
Altera CPLDAltera CPLD
XilinxLX25XilinxLX25
XilinxFX20XilinxFX20
XilinxLX25XilinxLX25
XilinxXCF08EPROM
XilinxXCF08EPROM
XilinxXCF08EPROM
XilinxXCF08EPROM
XilinxXCF08EPROM
XilinxXCF08EPROM
Altera EPC16EPROM
Altera EPC16EPROM
PC
SRAMSRAMVME
USB
JTAG
FPGA BootFPGA Boot
FADC : Config data size: LX25 = .97744 Mbytes FX20 = .90528 Mbytes Stratix = 1.205 Mbyte VME transfer time (VME 30MByte/Sec): LX25 = .032 sec FX20 = .032 sec Stratix = .042 sec VME transfer for 1 FADC (all FPGA) to Control: .14 sec JTAG transfer time (JTAG clock of 3MHz) LX25 = 3 sec FX20 = 3 sec Stratix = 4 sec Time to erase FLASH: LX25, FX20 = 9 sec Stratix = 20.5 sec Time to program FLASH LX25 = 31.3 sec FX20 = 25.0 sec Straitx = 76.5 sec Total ~= 238 sec. ~= 4 minutes.
FADC-250 Configuration Time
CTP Configuration Scheme
JTAG Links
XilinxLX50XilinxLX50
XilinxLX50XilinxLX50
XilinxLX110XilinxLX110
XilinxXCF16EPROM
XilinxXCF16EPROM
XilinxXCF16EPROM
XilinxXCF16EPROM
XilinxXCF32EPROM
XilinxXCF32EPROM
Remote Config
VXS IsquareC
Loading Configurarion During Code Development1) Connect Xilinx JTAG cable2) Run Xilinx Impact program to config Devices.
Loading Configurarion After Installation1) LX110 config. data via VXS IsquareC and temporary stores
to RAM inside FPGA. Config. Data has to be segmented due to limited RAM.
2) LX110 programs config. data into EPROM.3) LX110 read back config data from EPROM to SRAM.4) VME host (ROC) read and compare data. If OK, send next
segment.5) VME host (ROC) issues config command when all
segments are stored in ROM.6) LX110 issues config command to EPROM to load new
config data to FPGA..
FPGA Boot
CTP Configuration Time
CTP : Config data size: LX50 = 1.57 Mbytes LX110 = 3.64 Mbytes VME transfers to TI (VME 30MByte/Sec): LX50 = .053 sec LX110 = .122 sec TI transfers to CTP (IsquareC 34.43Kbytes/Sec write; 40.08 Kbytes/Sec read (1) ): LX50 = 56 sec (wr); 40 sec (rd) LX110 = 106 sec (wr); 91 sec (rd) JTAG transfer time (JTAG clock of 3MHz) LX50 = 5.2 sec LX110 = 12 sec Time to erase FLASH: LX50 = 16 sec LX110 = 36 sec Time to program FLASH LX50 = 50 sec LX110 = 117 sec Total ~= 720 sec. ~= 12 minutes. (1) Documentation of I2C Protocol Project, Sebouh Paul
VHDL Block Diagram to Remotely Configure FADC-250
VME IFACE
CMD REGS
EPROM OP-CODE TABLE
EPROM OP_CODE SEQUENCER
JTAG IFACE
VHDL Code to Remotely Configure FPGA
AHDL Operating Code
Select
Altera Control FPGA
Altera CPLDAltera CPLD
SRAMSRAM
Select
JTAG
Remote Configurarion Sequence1) VME host (ROC) write configuration data for one or more FPGA to SRAM (memory map TBD). 2) VME host write CMD Registers to initiate EPROM stored.3) VHDL Code takes over control of SRAM. Read config. data from SRAM, send OP-Code to EPROM,
and stores config data to EPROM. After store, read back EPROM data to SRAM.4) VHDL code relinquishes control of SRAM and signals VME host.5) VME host verifies EPROM stored data. If OK, write CMD Register to initiate FPGA config.6) VHDL Code issues config command to EPROM to load new config data to FPGA.
VME BUS
VHDL Block Diagram to Remotely Configure CTP
IsquareC IFACE
CMD REGS
EPROM OP-CODE TABLE
EPROM OP_CODE SEQUENCER
JTAG IFACE
VHDL Code to Remotely Configure FPGA
VHDL Operating Code
Select
LX110 FPGA
JTAG
RAMIsquareCBus
XilinxXCF16EPROM
XilinxXCF16EPROM
XilinxXCF16EPROM
XilinxXCF16EPROM
XilinxXCF32EPROM
XilinxXCF32EPROM
Remote Configurarion Sequence1) VME host (ROC) write configuration data in segments (Host to TI and then TI to LX110).2) VME host write CMD Registers to initiate EPROM stored.3) VHDL Code takes over control of SRAM. Read config. data from SRAM, send OP-Code to EPROM,
and stores config data to EPROM. After store, read back EPROM data to SRAM4) VHDL code relinquishes control of SRAM and signals VME host.5) VME host verifies EPROM stored data. If OK, repeat for all segmens.6) When all segments are done, twrite CMD Register to initiate FPGA config.7) VHDL Code issues config command to EPROM to load new config data to FPGA.