Renesas Electronics America Inc.

Custom SOC Technology and Solutions

AE TrainingJune 18, 2010

Company Confidential2

Statement of Confidentiality

Renesas Confidential Information

The following material contains Renesas confidential and proprietary information. No part of this document may be disclosed, printed, copied, or disseminated in any form or by any means, without prior permission from Renesas Electronics America Inc.

Company Confidential3

Agenda

ASIC Technology Overview Process ASIC Library IP (eDRAM, ARM, SERDES, USB2/3, DDR2/3) Design Flow and Services Packaging

CSOC Product/Solution Gate Array Solutions SOC Solutions

– ARM Platform for Factory Automation – ARM Platform for Smart Grid– ARM Platform for Storage

Mobile ASCP Solutions– IBIC – PMIC

CSOC Organization and Collateral

Summary

ASIC Technology – Process/Libraries

Company Confidential5

Process Roadmap

2008 2009 20112007

2010

2006

High Speed

Generic

Low Leakage

Embedded DRAM

65nm node

65nm node

55nm node 40nm node

UX7LLg=55nmVdd=1.2V

UX9LDCell size

0.041µm2

28nm node

2012

UX7LSeDCell size

0.124µm2

UX7HLg=40nmVdd=1.0V

UX8LDCell size

0.065µm2

UX8LLg=40nmVdd=1.1V

UX7LSLg=50nm

Vdd= 1.0V/1.2V

Ongoing Commitment to Advanced Technology Leadership

UX9LLg=28nm

Vdd=1.0~1.1V

2010

High-k High-k Metal gate/High-k

Toshiba/IBM/RELToshiba/NECEL

Baseline CMOS developmentCommon platform

Company Confidential6

High Performance Transistor with Thin High-k Dielectric

Advantages of High-K Tr

Adoption of High-k gate dielectricAdoption of thin Hf dope silicate dielectric structure

Hf-doped silicate

1. Reduction of Ioff2. High Performance Tr3. Reduction of Vt variation

Cross-section of ultra thinhigh-k dielectric (TEM)

Poly-Si

Si Substrate

Hf content

High density of channel dopant

Conventional Transistor

Low density of channel dopant

Ultra Thin High-k Dielectric Tr.

As+As+

h+

As+ As+As+ As+ As+As+

SiON

S D

Hf-doped silicate

S DAs+

h+

As+As+ As+ As+

High-k Tr. TechnologyDeployed Since 55nm Process

Company Confidential7

40nm Experience (Ex-NEC only ; Feb/2010)

40nm

Wafer fab line Yamagata, Japan

Design experience >13 designs

First MP 2009/July

Manufacturing experience >3Mpcs

Kyushu/Yamaguchi

Kansai

Yamagata

Company Confidential8

Cell Base IC Technology Roadmap

Node 0.50um 0.35um 0.25um 0.18um 0.15um 130nm 90nm 65nm 55nm 40nm

Lpoly 0.50um 0.35um 0.25um 0.18um 0.13um 95nm 60nm 55nm 50nm 40nmPitch 2.08um 1.36um 0.84um 0.56um 0.56um 0.40um 0.28um 0.20um 0.18um 0.132um

2007

CB-8HD

CB-8VX/VM CB-9

CB-10

CB-11

CB-12

CB-130

CB-90

CB-65

CB-9VX/VM

CB-10VX

CB-10VXLIO

CB-130Performance up

CB-90Performance up

1993

19951998

1999

2000

2001

2003

2005

1995

1997

1999

2003

2004

2005

CB-55

CB-40

2008

Multi-oxide technologySignal integrity technology

High-Speed

Low Power Consumption

Low Leak Power

Liquid Immersion,High-K dielectric

UltimateLowPower™Cu routing/LowK technologyPower integrity technology

Delay test technologyLow leak technologyDFY/DFM technology

Multi Vt technology

Node

Lpoly

: Technology node by ITRS (International Technology Roadmap of Semiconductor): Gate length of Tr. On silicon

Company Confidential9999999999999999

0

100

200

300

400

500

600

700

800

900

1000

CB-90M 1.0V MVT

CB-55L1.2V HVT

CB-40 1.1V HVT

Active power

Standby Power

Power Reduction: Advanced Technologies

Power reduction between technologies

40nm power consumption can be reduced by Shrink + High-K.Active Power : 41% of 90nmLeakage Power : 5% of 90nm

100%

78%

41%

5%10%100%

Pow

er C

onsu

mpt

ion

[mW

]

Optimized for low

stand-by power

Reduction of gate capacitance

Frequency : 162MHzOperating ratio : 0.1Tj : 105degUser Logic : 10MGate

Company ConfidentialCompany ConfidentialCompany ConfidentialCompany ConfidentialCompany ConfidentialCompany ConfidentialCompany ConfidentialCompany ConfidentialCompany ConfidentialCompany ConfidentialCompany ConfidentialCompany ConfidentialCompany ConfidentialCompany ConfidentialCompany Confidential

Company Confidential10

CB-12M/UX4M Product Specification

Company Confidential11

CB-90M/UX6M Product Specification

Company Confidential12

CB-55L/UX7L Product Specification

Company Confidential13

CB40L/UX8L Product Specification

ASIC Technology – IP

Company Confidential15

Major CBIC IP Offering Summary

Basic logic libraries, Standard I/O cells

SRAM Compilers 1P, 2P, Dual-Port; Various performance/power options

eDRAM

ARM CPU and peripherals

SERDES (XAUI, PCIe, SATA, …)

USB2.0/USB3.0

Memory I/F (DDR2, DDR3, mDDR, …)

Analog IP (PLL, ADC, DAC) Variety of specifications, performance levels

Company Confidential16

CB-40 (example) SRAM Options

Wide variety of proven SRAM compiler options available

Column

None ○ × WDSRAM001PAA[word]W[bit]C2 C2 128 *2bｗ 2048 *146bｗ 16 / 1bｗ V1.3.0Bit ○ × WDSRAM001PAA[word]W[bit]C2B1 C2 128 *2bｗ 2048 *146bｗ 16 / 1bｗ V1.3.0

None ○ × WDSRAM001PAA[word]W[bit]C3 C3 256 *2bｗ 4096 *74bｗ 32 / 1bｗ V1.3.0

Bit ○ × WDSRAM001PAA[word]W[bit]C3B1 C3 256 *2bｗ 4096 *74bｗ 32 / 1bｗ V1.3.0None ○ × WDREG001PAA[word]W[bit]C1 C1 8 *2bｗ 512 *146bｗ 8 / 2bｗ V1.3.0Bit ○ × WDREG001PAA[word]W[bit]C1B1 C1 8 *2bｗ 512 *146bｗ 8 / 2bｗ V1.3.0

None ○ × WDREG001PAA[word]W[bit]C2 C2 32 *2bｗ 512 *74bｗ 16 / 1bｗ V1.3.0Bit ○ × WDREG001PAA[word]W[bit]C2B1 C2 32 *2bｗ 512 *74bｗ 16 / 1bｗ V1.3.0

None ○ × WDSRAM001PGA[word]W[bit]C3 C3 256w*2b 4096w*74b 32 / 1bｗ CSRBit ○ × WDSRAM001PGA[word]W[bit]C3B1 C3 256w*2b 4096w*74b 32 / 1bｗ CSR

None ○ × WDREG001PGA[word]W[bit]C1 C1 8w*2b 256w*146b 8 / 2bｗ V1.3.0Bit ○ × WDREG001PGA[word]W[bit]C1B1 C1 8w*2b 256w*146b 8 / 2bｗ V1.3.0

None ○ × WDSRAM001PAE[word]W[bit]C3 C3 32 *2bｗ 2048 *74bｗ 32 / 1bｗ V1.3.0Bit ○ × WDSRAM001PAE[word]W[bit]C3B1 C3 32 *2bｗ 2048 *74bｗ 32 / 1bｗ V1.3.0

None ○ × WDSRAM001PDE[word]W[bit]C3 C3 32 *2bｗ 1024 *74bｗ 32 / 1bｗ V1.3.0Bit ○ × WDSRAM001PDE[word]W[bit]C3B1 C3 32 *2bｗ 1024 *74bｗ 32 / 1bｗ V1.3.0

None ○ × WDSRAM110PAA[word]W[bit]C2 C2 128 *2bｗ 1024 *74bｗ 32 / 1bｗ V1.3.0Bit ○ × WDSRAM110PAA[word]W[bit]C2B1 C2 128 *2bｗ 1024 *74bｗ 32 / 1bｗ V1.3.0

None ○ × WDREG110PAA[word]W[bit]C1 C1 16 *2bｗ 512 *74bｗ 8 / 2bｗ V1.3.0Bit ○ × WDREG110PAA[word]W[bit]C1B1 C1 16 *2bｗ 512 *74bｗ 8 / 2bｗ V1.3.0

None ○ × WDSRAM002PAA[word]W[bit]C1 C1 64 *4bｗ 512 *146bｗ 16 / 2bｗ V1.3.0Bit ○ × WDSRAM002PAA[word]W[bit]C1B1 C1 64 *4bｗ 512 *146bｗ 16 / 2bｗ V1.3.0

None ○ × WDSRAM002PAA[word]W[bit]C2 C2 128 *2bｗ 1024 *74bｗ 32 / 1bｗ V1.3.0Bit ○ × WDSRAM002PAA[word]W[bit]C2B1 C2 128 *2bｗ 1024 *74bｗ 32 / 1bｗ V1.3.0

ROM Generic ― ― ― ― WDROMSVDB[word]W[bit]C4 C4 256 *2bｗ 4096 *32bｗ 128 / 2bｗ - Done V1.3.0 334MHz

350MHz

350MHz

1 Port

SHS through - Done 1000MHz

-

-

-

-

-

-

-

-

-

-

HS

PSHD None

PSHD

through

Generic

Generic

Generic(Low Leak)

PSHD(Low Leak)

Dual Port

tRCSpecTEG Eval OPC

Done

359MHz

2 port

PSHD

Done

Done

Done

Done

Done

T.B.D

Done

Generic

Generic None

through

Generic through

Done

359MHz

703MHz

342MHz

Done

342MHz

357MHz

Done

-

UX8LD

Bit WriteWrite DataThrough

typePort Type

OptionMacro Version Info

Macro name

Compile Range Status

Max STEP CSRMin

Redundancy

SoftMacro

HardMacro

through

through

through

through

through

through

Company Confidential17

CB-40 (example) PLL and ADC/DAC Options

Items Application Function VDDLib

TypeASIC Core Name

TentativeRelease

ReleaseSchedule

Status

Multiplying VCO: 800MHz-1600MHz 1.1V L ACPLMPHH38V10 － TBD Under evaluation

VCO: 800MHz-1600MHz 1.1V L ACPLSCHL38V10 － TBD Under evaluation

VCO: 1.6GHz-3.2GHz 1.1V L ACPLSCDR18V10 － Done Released

SSCG VCO: 800MHz-1600MHz 1.1V L ACPLSGHH38V10 － TBD Under evaluation

PLL Skew control

Items Application Function TrLib

TypeASIC Core Name

TentativeRelease

ReleaseSchedule

Status

12bit 200kHz 12ch(MUX) 3.3V L ACAD12B200K12CCR3VV10 Done Done Released10bit 1MHz 8ch(MUX) 3.3V L ACAD10B001M08CCR3VV10 Done TBD Under evaluation10bit 1MHz 1ch 3.3V L ACDA10B001M01CRR3VV10 － TBD Under evaluation10bit 30MHz 1ch 3.3V L ACDA10B030M01CRS3VV10 Done Done Released12bit 170MHz 2ch 3.3V L ACDA12B170M02CCC3VV10 － Done Released12bit 170MHz 3ch 3.3V L ACDA12B170M03CCC3VV10 － Done Released

GeneralPurpose

DACVideo

ADCGeneralPurpose

ASIC Technology – IP/eDRAM

Company Confidential19

eDRAM

Production Proven

>100M units shipped!

>60M units 90 nm shipped

55 nm eDRAM working silicon with >85% pre-repair yield

Technically Differentiated

Full metal MIM-2 >10 fF cap (COB) – Faster speeds – Better data retention – Better SER immunity

Ported to 40 nm

M1

W Bit Line

Nickel Silicide

Hafnium-Silicate Film (high-k) NMOS Cell Transistor

ZrO2 Capacitor

edra

m

Easy to Use

CMOS-compatible

Free orientation

Routing allowed over macro

Pre-configured macros

SRAM-like access

StandardCell ASIC

edram

Company Confidential20

Benefits of Embedded DRAM

• DRAM density with SRAM performance

• Boosts overall system bandwidth by eliminating need to drive I/O signals to separate memory chips

• Lower power consumption and SSO noise due to reduced IO interface

• Smaller pin counts enable use of lower- cost package and PCB

• Lower soft error rate (SER) than SRAM and improved SoC reliability due to eDRAM cells having stable storage capacitor values

• Reduce board space

• Solve impact of standard memory EOL issues

Company Confidential21

① Parasitic resistance reduction using FMD* 　 → high speed, low power consumption② Same structure of cell Tr. as the CMOS Tr 　→ fully CMOS compatible③ MIM* formation at low temperature → fully CMOS compatible④ High-k ZrO2 film implementation → small cell size, high performance

FMD ： Full Metal DRAM

MIM: Metal Insulator Metal

Salicided cell Tr. & full metal structure

DRAM Part Logic Part

STI

M1

NiSi2

MIM Capacitor

M1M1M1M1M1

Bit Line

Feature Description

Cell structure MIM COB

Cell size 0.06µm2

Cell capacitance (capacitor material)

>10 fF /cell (ZrO2)

Cell transistor dielectric

Hafnium-doped silicate

40nm eDRAM Features

eDRAM – Unique Technology

Size Configuration Frequency

64 Mb 256 Kw x 256 b 133 MHz

8 Mb 32 Kw x 256 b 220 MHz

40nm eDRAM Macro Size

Company Confidential22

eDRAM Sub-System (w/controller)

Renesas eDRAM Controller IP (soft) ARM AHB bus interface (32b/64b) Burst mode avoids repeated access, saves pwr Refresh controller

ASIC Technology – IP/ARM Platform

Company Confidential24

Perf

orm

ance

, Fu

nct

ionalit

y

ARM966E-S

ARM926EJ-S

ARM1136J(F)-S

ARM946E-S

ARM7TDMI-S

ARM CPUs – solutions for open platforms

ARM11 MPCore

ARM1156T2-S

ARM968E-S

x1-4

ARM1176JZ(F)-S

Cortex-M3

Cortex-R4

Cortex-A8

Remark planned / t.b.d.available

Cortex-A9 (MPCore)

x1-4

Cortex-R4F

Long-term Strategic Partnership

x1-4

Cortex-A5 (MPCore)

Notes

1. Preliminary roadmap (ref. CCBU-NI-ARM-00056-1V9). Please contact Renesas Electronics for latest releases.

Company Confidential25

ARM SoC Experience

>200M ARM9 SoC’s have shipped to date

100 ARM SoC ASIC designs have been completed CB12, CB130, CB90, CB55, CB40 ARM7, ARM9, ARM11

Cortex A9 Test Chip in 90nm design is complete

Renesas is a leader in ARM based SoC design

Company Confidential26

ARM Platform (ARM PF) Value Proposition

ARM Sub-system (RTL) designed and pre-verified by Renesas Lower customer engineering resources Optimized for customer application

Faster Time-to-market and first silicon success

ARM PF deliverables- Encrypted RTL- Gate Level Netlist- Simulation test bench- Documentation

Pre-verified design by Renesas

CPU Sub

Systems

PeripheralSub

Systems

I/O Sub-Systems

On-chip Bus

Reference Design

Verification environments

I/O Sub-Systemsex: USB, MEM I/F

Customer’s logic

ARM-Platform

Customer’s design

Company Confidential27

ARM Platform Overview

Reference Design (Fully Configured)

Sub-System (SS) = IP + AHB/AXI bridge + test program

• Pre-designed and verified IPs• Automated tool for quick delivery and high quality custom configuration

Customer can pick sub-systems and preferred configuration

AXI AHBAXI AHB AHB AHB AHB

AHB AHBAHBAHBAHB

ARMR4/1176/

1136/926/946/7

PCIe-SS

PCIe

SATA-SS

SATA

USB-SS

H2F2/H1/H2/F2/

DRD

ETHER-SS

MACSUM

MEDIA-SS

SD

SECURE-SS

AESDES

BUS-SS

32/64-bit AHB Bus

DDR2/332/16-bit

DMA-SS

AHB D

MAC

RAM-SS

eSRAMIF

BRIDGE

内蔵SRAM

APB-SS

32-bitAPB3

AHB2APB

TIMER

UART

CSI

PRS

RTC

A/D

UDL(APB3)

UDL(AHB)

SDR

ROM

AXI2AHB

AHB2AXI64/128-bit AXI

AXI

UDL(AXI)

AXI DM

AC I 2C

AXIAHBAXI

AHB

GbE-SS

GMACSUM

AXI

D/A

GPIO

MEM-SS

DDR2/3MEMC

MEM-SS

SDR M

EMC

S RAM

/ROM

M

EMC

S erialFlash

AHB

MEM-SS

Serial Flash M

EMC

Clock/Reset、Controller

Debug VIC

CPU-SS

AXI

STP-SS

DRP

DMA

PWM

WDT

I2S

AHB

RAM-SS

eDRAMIF

BRIDGE

eDRAM

Company Confidential28

Renesas ARM Cortex A9 Dual Core Example

CB40 Dual CPU ARM Cortex-A9 (~600MHz)

NEON NEOND$

I$

DSide

CPUSCU

PL30ISide

PTM

D$

DSide

I$

CPU

PTMISide

Company Confidential29

ARM Cortex-A9 MPCore eval. board

CPU ARM Cortex-A9 MPCore

– 4 Cortex-A9 CPUs at 400MHz– 32KByte L1 cache– 4 NEON Processing Engines

L2 cache with 512KByte Memory

DDR SDRAM 512MByte NOR Flash 64MByte NAND Flash 256MByte

Schedule available

Leverage Renesas’ ARM MPCore expertise for future mobile network infrastructure.

ASIC Technology – IP/High Speed Interface

Company Confidential31

CB-12, 1.5/3.0Gbps(SATA/SAS)

planned

under development

limited release

CB-130, 0.6G~3.2Gbps(GbE, Infiniband, XAUI)

CB-130, 120M~860Mbps(backplane)

CB-12, 2.5Gbps(PCI Express)

2006 2007 20092005 20082004

SerDes Cores and Roadmap

2010

Jedye1,3Jedye3

Linus

Jedye4

Idefix

CB-90, 0.6G~3.2Gbps(GbE, PCIe, XAUI, backplane)

Classic

CB-90, 0.25G~3.4Gbps(HDMI v1.3)

Bright

Jedye7

CB-90, 622M~694Mbps(SFI-4.1e)

CB-130, 622M~694Mbps(SFI-4.1e)

CB-55L, 1.5G/2.5Gbps(SATA, PCI Express)

CB-40L, 0.25G~3.4Gbps(HDMI v1.3)

CB-40L, 1.25G~6.4Gbps(PCIe gen2, SATA gen2, CEI-6G-SR)

CB-65H, 8G~12.8Gbps (backplane)

CB-90, 5G~12.5Gbps(prototype, backplane)

CB-90, 1.5G/3.0Gbps(SATA/SAS)

CB-90, 1.25G/2.5Gbps(GPON/GEPON)

CB-90, 155M~1.25Gbps (SPI-4.2)

CB-65H, 2.5Gbps(PCI Express)

Jedye5,6

CB-130, 2.5Gbps(PCI Express)

CB-90, 0.6G~3.2Gbps(GbE, PCIe, XAUI, backplane)

CB-90, 1.5G/3.0Gbps(SATA/SAS)

CB-90, 1.25G/2.5Gbps(GPON/GEPON)

Apogee

available

CB-90, 1.25G~6.4Gbps(backplane, CEI-6G-LR)

CB-90, 1.25G~6.4Gbps(PCIe gen2, backplane, CEI-6G-SR)

40n6G

CB-40L, 1.25G~6.4Gbps(SATA gen3, USB3.0)

Long-time Supplier of SerDes Macros

6GL-SR

Balsam7

CB-55L, 1.5G/3Gbps(SATA)

CB-28, 1G~12.5Gbps

Company Confidential32

Jitter(p-p) = 27.8psJitter(rms) = 8.22ps

<Conditions> Slowest process : SSL (corner sample), 40N6GTEG001 Sample No=05, Macro B, VDDD=VDDTIO = 1.0V, VDDA=3.0V, Tc= 100deg, Active lane count=4, measured lane No=0, Output pattern = PN-7 PRBS, RefClk=100MHz (20:1 serialize), pre-emphasis setting No = 338

TJ@e-12(p-p) = 34.4psRJ(rms) = 0.88ps

Tx Output Jitter PCI-express Gen2 (5Gbps) Worst Condition

LC tank oscillator in VCO minimizes output jitter

CB40 Serdes evaluation results (1/2)

Company Confidential33

<Conditions> Slowest process : SSL (corner sample), 40N6GTEG001 Sample No=09, Macro B, VDDD=VDDTIO = 1.0V, VDDA=3.0V, Tc= Room Temp, Active lane count=4, measured lane No=0, Output pattern = PN-7 PRBS, RefClk=100MHz (20:1 serialize), pre-emphasis setting No = 496, Equalizer setting No = 3

Rx Bit Error Rate Test PCI-express Gen2 (5Gbps) Worst Condition

CB40 Serdes evaluation results (2/2)

Error Performance Analyzer

CDR +DeMux

MuX

40nm SerDes

Testchip

Agilent86130A

Eye opening Vrx-eye = 40mV (spec: 100mV) Trx-hf-fd-dd = 51ps (spec: 88ps)

Error Free

Less than 6.9E-16 BER Above 2days 14hours 55minutes error

free has been confirmed.

Company Confidential34

USB2.0 IP Core Roadmap

2007 2008 2009 2010

Core

SubSystem

HOST+FUNCTION

Type-H2F2

HOST

Type-F2

Function

CB90M CB55L

UTMI

Type-H1

V1-Type-H2

Type-H2

Type-F2

HOST+FUNCTION

HOST

Function

40nm

Type-H2

Type-F2

Type-H2F2

Renesas also offers USB3.0 device solutions in CB90M

Company Confidential35

2007 2008 2009 20101H 2H 1H 2H 1H 2H 1H 2H

CY

~400MbpsDDR

2009.9

DDR3

DDR2

M-DDR(LPDDR)

~266Mbps

~667Mbps

DDR2/3 Combo DDR2: 600Mbps~1.06Gbps DDR3: 600Mbps~1.3Gbps

UX7LS ~1.06Gbps

DDR2/3Combo

~800Mbps

UX7LS ~667Mbps

90nm

65/55nm

40nm

2009/4

2009/8 （ TEG)

LPDDR/DDR2 Combo~667Mbps

LPDDR2~800Mbps

DDR PHY Roadmap

Company Confidential36

DQ

DQS

CB40 DDR3 1.3Gbps Terminal Controller

PKG(Wire) and PCB model additional.No SSO Noise.

PVT=Worst condition.

DDR3 1.3Gbps DQ/DQS Wave form (40nm)DDR3 1.3Gbps DQ/DQS Wave form (40nm)

ASIC Technology – Design Flow and Service

Company Confidential38

Project Design Phases Overview

Major Topics/Process

Step, metal layers, package,etc.which are mandatory for pricing

Design Level

DR (Design Review)

Ph

ase

Bas

ed V

erif

icat

ion

FN (Floorplan Netlist)

LN (Layout Netlist)

CN (Complete Netlist)

FN1, FN2,…

LN1, LN2,…

CN1

Identify challenges and actions toresolve

Routability estimation based onthe floorplan with the considerationon the timing among blocks andwithin blocks

Timing estimation among blocksand within blocks based onplacement and routing.

Finalize the design including timing fix, SI fix, and LayoutVerification. Entry is 1st hand-off;Exit is 2nd sign-off.

Before Starting LSI Design

TO (Tape Out)

Company Confidential39

Design Interface and Service Flexibility

Complete flow from specification to GDS

Flexible Customer interfaces Placed netlist Interface Gate level netlist interface RTL netlist interface Turnkey design Or practically anything in between

Chip specification handover

RTL/Gate level handover

Physical synthesis / Clock Tree synthesis

Timing Driven Routing

IR Drop Analysis / SI Checking

RC Extraction/Delay Calculation

Physical Verification

Mask Data generation

GDS

Netlist DRC / DFT Insertion

Company Confidential40

SOC – Value Added Design Services

ARM Platform Sub-systems solutions and consultation ARM emulation solutions and consultation IP solutions and consultation SOC project management SOC/EDA tool flow and library support and consultation

Design deliverable quality checking and feedback Signal and power integrity management Power management (power reduction) Design for manufacturing (DFM)

DFT (Design-for-Test) services for MP test program ECO flexible options to minimize rework risk Packaging solution development and support

Company Confidential41

Low Power Design Strategies

To

tal C

hip

Po

we

r(A

ctiv

e+Le

kage

)

Multi Voltage / Multi SupplyMulti Voltage / Multi Supply

Clock GatingClock Gating

Power SwitchPower Switch

System level power supply and Clock ControlSystem level power supply and Clock Control

Layout Design Methodology Layout Design Methodology

Multi Vt TrMulti Vt Tr

No countermeasure for power

No countermeasure for power

Countermeasure by design methodologies and

process technologies

Countermeasure by design methodologies and

process technologies

Low Power Solution byDesign Methodology

Low Power Solution byProcess Technology High-K TrHigh-K Tr

Retention F/FRetention F/F

90nm 65nm 55nm 40nm

Getting low power by both design methodologies and process technologies

Company Confidential42

Leading Edge DSM Design Support

Antenna

Dense

Coarse

Field/Metal density

EM/HE Cross talk

t

t

IR-Drop MSMV

MIN

MA

X

TYP

aa

-+´

11MIN a

a+-´

11MAX

)1( a-´TYP )1( a+´TYP

OCV DFT

Kt Inversion

Vgs

Ids Tj Low

Tj Hi

1.0V

0VTr. Vt

SSTA

Delay library range

Best Typical

Worst

OCV OCV Upper Metal

Lower Metal

D1

D2

T

W

e(Dielectric Constant)

Statistical RC Ext.

Jitter analysis

Lpkg Lchip Rchip

Lpkg

ASIC Technology – Packaging

Company Confidential44

Portable Equipment

Digital AV

Automotive 　　　　　　　　　　

ThinLightsmall

HighPerform-

ance

Heat dissipation Cost

Side by side BGA

Die-stacked SiP

PoP

Die-stacked &Side by Side QFP

Communication Server, Game

FBGA

FCBGA

PBGA

WLBGA

Die-stackede-Die Pad

QFP

FCBGA

PC, Peripheral

HBGA

QFNQFP

Renesas provides a variety of package solutions per application specific.Market Segment and Package Solutions

Company Confidential45

500 2000 2500300

44 376

117 1033

2803

QFN/QFP

PBGA

PKG Pin# 1000 1500

SON/SOP86

FBGA

8

Package Solutions

74525

360

FCBGA

WLBGA

1005

１ 00

SiP solution is available.

Renesas has a variety of package options and is continuously developing advanced packages to meet market demands.

Company Confidential46

Skillful package design incorporation with simultaneous simulation offers lower-cost packages for high-data rate devices.

Narrower Bus

Lower signal frequency

WiderBus

1GHz

5GHz

100MHz

50MHz

64bit32bit 96bit16bit

PBGA

FCBGA

128bit

Signalintegrity

Powerdelivery

500MHz

200MHz

Higher signal frequency

10GHz

QFP

1bit 8bit

FBGA

Electrical Characteristics

Company Confidential47

Thermal ResistancePackage performance generally conflicts with cost requirements.System-level thermal design is inevitable for the critical applications.

QFP

PBGAFCBGA

Package size

Th

erm

al r

es

ista

nce

j-

a

The combination of larger die size and higher conductivity of packaging material, in addition to the use of exposed die pad and heat spreader, lowers thermal resistance.

Large Small

Low

High

QFP with exposed die pad

Company Confidential48

Package Domain

10 20 30 40 500

1000

2000

500

1500

FBGA

PBGA

FCBGA

WLBGA

Renesas provides the best package solutions to meet system requirements.

QFP

Package Size

Pin

Cou

nt

Company Confidential49

Die-stacked SiP PKG-stacked SiP(PoP)

Side-by-side SiP (Wire Bond)

Side-by-side SiP (FC bond)

Major die combination

Logic+Memory Logic+MemoryLogic+MemoryLogic+Analog

Logic+MemoryLogic+Analog

PKG size Small Small Middle Middle

PKG thickness Thin Slightly thin Middle Middle

Yield loss risk High Low High High

Memory capacity flexibility

Low High Good Low

Memory scalability Low High Good Low

Data transfer rate between chips

Good acceptable acceptable Better

Thermal performance

Low Low acceptable Better

Soldering GoodTight warpage management

Good Good

SiP

Item

Select the best SiP solution per specific application. Better

Various SiP Solutions (BGA Type)

CSOC Solutions – Gate Array

Company Confidential51

Customer-designed logicCustomer-designed logic Integrated more efficiently with low-cost custom metalIntegrated more efficiently with low-cost custom metal

Customer-designed logicCustomer-designed logic Integrated more efficiently with low-cost custom metalIntegrated more efficiently with low-cost custom metal

What is a Gate Array?

Customizablemetal layers

SRAM

APLLDLLDLL

APLLDLL DLL

APLL

APLL

SRAMUDL

Gate Area“Sea of Gates”Actually a “sea of transistors” for denser SRAMs, etc.

Embedded Blocks

Cuts costsCuts costs Low price, plus Low price, plus • Eliminates a voltageEliminates a voltage regulator in most designs regulator in most designs • No programming chip No programming chip • Same or smaller footprint Same or smaller footprint • Lowest powerLowest power

Company Confidential52

Why Renesas Electronics Gate Arrays?

No.1 Gate Array supplier worldwide since 1993 Thousands of designs in production now

Gate Array business for over 20 years

Competitive, efficient devices

Direct support of popular supply voltages (5V/3.3V/2.7V/1.5V)

Flexible volume ordering, from 100 pcs to over 1 Mpcs

Wide variety of master slice and package options

Pin-compatible support for many FPGA/CPLD and ASICs

World-class quality and reliability

Company Confidential53

Gate Arrays:Fast-turn, metal-programmable ASICs

Low NRE, Quick TAT.Business Guideline: $1M LTR or greater. Utilize Avnet channel.

Usable Gates5K 10K 20K 50K 100K 200K 500K 1M 2M 5M1K 2K

0.5 µmInterface: 5V/3VCore: 5V/3V

0.35 µm

CMOS-N5CMOS-N5

CMOS-9HDCMOS-9HD

0.35 µm Interface: 5V/3.3VCore: 3.3V EA-9HDEA-9HD

Interface: 5V/3.3VCore: 3.3V

0.15 µmCMOS-12MCMOS-12M

Interface: 3.3V/2.5V/1.8V/1.5VCore: 1.5V

Company Confidential54

Gate Array Product Summary

Renesas Gate Array series CMOS-N5 CMOS-9HD EA-9HD CMOS-12M

No. of master slices 13 22 38 14

No. of packages 27 47 47 16

Metal Layer 2ML 3ML / 4ML 3ML / 4ML 5ML / 6ML

No. of usable ASIC gates

1.5 Kg to120 Kg

11 Kg to1.5 Mg

9.7 Kg to1.4 Mg

63 Kg to2 Mg

Logic performance

60 MHz at 5V33 MHz at 3V

100 MHz 100 MHz 200 MHz

Unit price*1 Starting below $1 Starting Below $2

NRE mask charge*2 $11K

$21K(3ML)

$41K (3ML) $70K

<Note>*1 … Volume pricing*2 … NRE costs based on the simulation netlist hand-off. Other design services are extra. NRE covers all Renesas Electronics proprietary tools, “OPENCAD kits”

Renesas Electronics offers various Gate Array technologies

Company Confidential55

Application and Design Scenarios

Real designs bringing benefits worldwide

5. Conversions

2. SoC Alternative - ASSP Companion

1. SoC Bug Fix

3. SoC Feature-add 8. Piracy protection

9. Reduce EMI

7. Specs Improved

6. Consolidation

4. EOL Extended

Renesas Electronics Gate Arrays just about everywhere

Buggy SoC

Buggy SoC + Gate

ArrayGate Array

WITH BUG FIX

Buggy SoC

Buggy SoC

Gate ArrayGate Array

FPGAFPGA

Gate ArrayGate Array ASSPASSP+

SoCSoC

+SoCSoC Gate ArrayGate Array

WITH NEW FEATURE ROMROM Gate ArrayGate Array

WITH SECURITY KEY

+ FPGA/ CPLD

FPGA/ CPLD

WITH OLD COMPONENTS

System Board

System Board

System Board

System Board

WITH NEW GATE ARRAY

Gate ArrayGate Array

FPGAFPGA+ASSPASSP+ Standard

ProductStandardProductFPGAFPGA

Gate ArrayGate Array

GateArrayGateArrayFPGAFPGA

Company Confidential56

CSOC SolutionsARM Platform Solution – Factory Automation

Company Confidential58

Po

we

r

CP

U

I/O I/O

I/O

CPUCPUCPUCPU

UDLUDLUDLUDL Inter ConnectInter ConnectInter ConnectInter Connect

ARM11/9/7/Coretex

ARM11/9/7/Coretex

AXI/AHB/APBAXI/AHB/APB

Std.IFsUSB/SGMII/LVDS

Std.IFsUSB/SGMII/LVDSStd. IFsStd. IFs

Func.Func.IPsIPs

REL providedPlatform

REL providedPlatform

Customer creating Value

Customer creating Value

+

- Test Bench- Prototype-Board- Doc

- Test Bench- Prototype-Board- Doc

User’s Specific Func.

User’s Specific Func.

MAC/MEMC/MEDIAMAC/MEMC/MEDIA

ASIC Platform for Programmable Logic Controller (PLC)ASIC Platform for Programmable Logic Controller (PLC)

PLC Renesas provides Platform Design for PLC LSI for efficient development

Renesas provides Platform Design for PLC LSI for efficient development

CBIC basedon

platform

CBIC basedon

platform

Company Confidential59

Programmable Logic Controller (PLC) Match with Existing REL ARM-PF

ARM ASIC Platform

AHBAXI AXI AHB AHBAHB AHBAXI AHB

AXI AHB AXI AHB AHBAXI AHBAXI AHB

APB-SS-V2

TIM

ER

DDR2/332/16bitDDR2/332/16bit

MEM-SS 　　　　　

AHB2M x mAHB2M x m

UDL(AXI/AHB)

UDL(AXI/AHB)

AHB2APBAHB2APB

UA

RT

I2C

CS

IP

RS

PW

MR

TC

UDL(APB3)UDL

(APB3)

DMA-SS

AX

I DM

AC

AX

I DM

AC

UDL(MBUS)

UDL(MBUS)

DDR2MEMCDDR2MEMC

RAM-SS

SRAMSRAM

AH

B D

MA

CA

HB

DM

AC

BRIDGEBRIDGE

SRAMIFSRAMIF

DDR2IFDDR2IF

128bit MBUS128bit MBUSS

RO

MS

RO

M

AHB

SATASS

IRDASS

ETHERSS

USBSS

PCIExSS

USB1.1HOST

USB1.1HOST

MACSUMMACSUM

FIRMIRSIR

FIRMIRSIR

CPUSS

SATASATAPCIExPCIEx

VICVIC

GbESS

GMACSUM

GMACSUM

PERIPERI

ARM1176/1136ARM926/946

ARM7

ARM1176/1136ARM926/946

ARM7

SECSS

AESDES….

AESDES….

SYSSS

CLKCRSTC

STBYC

CLKCRSTC

STBYC

BUS-SS

64bit/32bit Multi-Layerw/ asynchronous AHB2AHB, 64bit to 32bit downsizer

64bit/32bit Multi-Layerw/ asynchronous AHB2AHB, 64bit to 32bit downsizer

64bit AXIw/ asynchronous register slice

64bit AXIw/ asynchronous register slice

AXI2AHBAXI2AHB

AHB2AXIAHB2AXI

AD

/DA

WD

T

32bit APB332bit APB3

AHB

RAM-SS

eDRAMeDRAM

BRIDGEBRIDGE

eDRAMIFeDRAMIF

AHBAHB

MEM-SS

SE

RIA

LM

EM

C

MEM-SS

UDL(SRAMIF)

UDL(SRAMIF)

ME

MC

SD

RS

DR

RO

MR

OM

SD

R M

EM

C

AHB

USBSS

USB2.0FUNC

USB2.0FUNC

AHB

USBSS

USB2.0HOST+FUNC

USB2.0HOST+FUNC

ARM Coretex A9+VFP Multi-processor

MediaSS

SDMMCSD

MMC

AHB

+

DDR2/3 Switchable(CB40L)

= Requirement aligns with Existing

Platform Product Plan

+

+

Company Confidential60

CSOC SolutionsARM Platform Solution – Smart Grid

Company Confidential61

Renesas Solutions for Smart Meter

Metrology

NANNeighborhood Area Network

SoC Zigbee Radio

NAN Radio

Communication Module

Analog Front End MCU

Smart Meter

PLC

Display LCD

Current, Voltage measurements

HANHome Area

Network

Renesas Electronics provides customersa choice of standard or custom solutions

Company Confidential62

Custom System-on-Chip (SoC) Solution

For Smart Meter and AMI Communications Cost-effective solution for high-volume applications

ARM core CPUs (ARM 7/9/11) 3rd party DSP IP such as Tensilica, for modulation scheme support Embedded memory for protocol stack/data upgrade support Security engine supporting AES-128 and 3DES Multi power domain scheme for efficient power management Wireless AFE for RF communications PLC modem for powerline communications

Wireless AFE

ARM ASIC-Platform

Security IP

MemoryCustomer

User Defined Logic

PLC AFE and Coupling

RF RadioPower Management

DSP

ARM SOC

PLC Modem

Shorten Development,

Reduce Risk, Faster Time-to-Market

Shorten Development,

Reduce Risk, Faster Time-to-Market

User Defined logic

Renesas Macro

Company Confidential63

ARM Platform – Smart Grid Implementation

CPU-SS

INTC

ARM9E

BUS-SS32bit AHB Bus

AHB

APB-SS

32bit APB3

AHB2APB

UA

RT

WD

T

AHB

MEM-SS

Serial F

lashM

EM

C

AHB AHB

AHB wrapper

CS

IAHB

SRAM-SS

SRAMIF

BRIDGE

APB

REG

UAR

T

AHB

SRAM-SS

SRAMIF

BRIDGE

ROM SRAM

AHB

ARM9E ASIC Platform (Pre-Verified by Renesas)

CSI

AHB

APB AnalogAD/DARTC

DSP(Modulation)

Security IP(AES/DES)

EMI

SRAM

Radio

AHB

AHB

UDL

DMA-SS

DMAC

AHB-M AHB-SAHB-M AHB-S

EMI

Serial Flash

EMI

Boot-ROM

Support of Security and Radio modulation requirements

SoC

Company Confidential64

Verification Platform for SoC Development

Hardware platform for SoC emulation and software development FPGA supports custom logic Supports ARM JTAG-based debugger environment and available

third-party compilers Communication Peripheral Support

802.15.4/Zigbee PowerLine communication Expansion slots for proprietary

wireless communications

ARM1176 resource ARM926 resource ARM946 resource ARM7 resource

ARM1176JZ-S×2(400MHz)

ARM926EJ-S(200MHz)

ARM946E-S(200MHz)

ARM7TDMI(100MHz)

Company Confidential65

PowerLine IP Integration on SoCImplementing Low-cost PLM-1 PLC on SoC

ARM core CPUs (ARM 7/9/11)

PLM-1 IP RTL Licensed from Ariane Controls Easily Integrateable

ASIC designs with customer ASIC team ASCP turnkey customer designs Custom MCUs

Proven IP on production silicon PLM-1 Evaluation Board interfaces to SoC Verification Platform

Wireless AFE

ARM ASIC-Platform

Security IP

MemoryCustomer

User Defined Logic

PLM-1 AFE and Coupling

RF RadioPower Management

DSP

ARM SOC

PLM-1 Modem IP

Power Line

Company Confidential66

PLM-1 Powerline Modem Standard Device

A Power Line Communications (PLC) Endpoint Solution

• Low-Cost, standard off-the-shelf components

• Renesas MCU: 8/16/32bit interface via SPI

• PLC modem: PLM-1 is Renesas Electronics manufactured, design and license in cooperation with Ariane Controls

Available Now – For low/medium bandwidth control applications

MCU

• Low-cost narrowband FSK modulation technique• Programmable transmission rate from 100 to 20,000 baud• Programmable communication frequency from 50 to 500 kHz

PLM-1 Evaluation Board Compact module with coupling unit, AFE, PLM-1 and 78K0 8-bit MCU

Part # Eval-PLM-78K0-PLCNET– Comes with 2 eval boards to form a PLC network

Available for Customer evaluation

MCU Bypass-mode for direct SPI connection to PLM-1

Renesas

Renesas

Renesas

- Renesas SoC Verification Platform

Company Confidential67

Smart Grid Applications – PLC HAN Extension

External Pool PumpExternal

HVAC unit

PLC Net

Solar Panal Management

Architectural & Area LED Lighting

PowerLine Communication in HAN PLC technology co-exist with Zigbee Extend HAN reach to niche applications

where Zigbee may have issues PLC Applications in use today

PowerLine Communication in HAN PLC technology co-exist with Zigbee Extend HAN reach to niche applications

where Zigbee may have issues PLC Applications in use today

Zigbee to PLC

Bridge

Company Confidential68

CSOC SolutionsARM Platform Solution – USB3.0/SSD

Company Confidential69

USB3.0 Device market

1st Wave Products (in 2009/10) Storage (Ex-HDD, Flash Drives, SSD ) Display

2nd Wave Products : Flash based DSC, DVC Cell phone Display

DSCCell Phone

Storage

DVC

0

100

200

300

2009 2010 2011 20120%

20%

40%

60%

80%

100% DSC/CAM

Media Player

Phone

Display

Flash

HDD

USB3.0 PCsaturation level

Source: CSOC estimate base on InSTAT2008 data

M unit

1st Wave Products

Company Confidential70

USB3.0 ASIC Solution

Renesas is a world leader for USB3.0 solutions World’s first and only certified USB3.0 Host Controller since Sept’ 09

USB3.0 IP PHY + LINK + EPC Unparalleled interoperability with Renesas USB3.0 Host

Fully-equipped USB3.0 interoperability lab Design support

Design Service to Customize the IP Core

Simulation/Verification Support

Strong IP line up for target application segment SATA Gen 2 (now), Gen 3 (55nm & 40nm) Flash I/O DDR 2/3 PHY PCIe Gen 1/2 Video macros (DAC, HDMI, DVI)

All IPs are available in CB90M Technology

Company Confidential71

Renesas ASIC Solution for Flash Controller

NAND-Flash Memory

Sub-System

DDR IO(DDR2/3)

Host System

ECC

USB 3.0 SATA Gen1/2/3

PCIe Gen1/2

Wear-levelingand

Re-mapping engine

SRAM

Flash I/F

User Defined Logic

Renesas IP

ARMPlatform

ARM Core

SRAM

DMA IntC

Peri.

Host I/F

Flash IOONFI IO

etc

eDRAMBuffering

Cache

Crypto engine

RSA SHA-1

AES DES

NVRAM(key store)

Flash controller ASIC

FlashFlash

FlashFlash

DDRDDR

DDRDDR

Data buffer

ARM Platform

CSOC SolutionsASCP - Intelligent Buffer IC (IBIC)

Company Confidential73

Concept of Intelligent Buffer IC

Large e-DRAM capacity for Higher resolution & Quality

Lower system power with new backlight control

Meet Mobile display interface standard

Intelligent Display functions & 3D display extension

Realize Higher display quality & Low power for any Mobile Platform (DBB/Application chip)

Hos

t I/F

Frame Buffere-DRAM

Image Processing

PictureAnalysis

LCD

Driv

er IF

Brightness Calculation

Gammaadjustment

LEDDrive

Intelligent Buffer IC

Company Confidential74

Tremolo-M Block Diagram

MIPIDSIRx

MIPIDSIRx

D0PD0N

D1PD1N

CLPCLN

MDDIClientMDDIClient

DD0PDD0N

DD1PDD1N

STPSTN

EngineIF

EngineIF

FrameBuffer

14.8MbeDRAM

FrameBuffer

14.8MbeDRAM

FrameBuffer

14.8MbeDRAM

FrameBuffer

14.8MbeDRAM

Memory ControlMemory Control

EngineControlEngineControl

TimingControlTimingControl

AGCPSAGCPS

MIPI-DPI(24bit RGB)

PWM(BL LED CTL)

DBITypeC

IF

DBITypeC

IF

GBRegGBReg

CLKIN PLLPLL system clkpixel clk

/RESET

TE

DBI TypeC

1.8V

VoltageRegulatorVoltage

Regulator

1.8V

1.2V

SEL_IF

AGCPS: Auto Gamma Control and Power Saving, which includes both CABC (Content Adaptive Backlight Control) and Ambient-light based Backlight Control

VSYNC. HSYNC

SLEEP

DEPCLK

Tremolo-S differences• 16Mbit edram• MIPI-DSI only In• AGCPS not included

Company Confidential75

Collateral/Customer/Promotion

Collateral Plan Evaluation board Information

– www2.renesas.com/ibic

Target customer meetings/demos Motorola, RIM, Microsoft, Apple, Intel, Dell,

Qualcomm

General Promotion Quarterly MIPI Mtgs UNH-IOL MIPI-DSI “plugfest” Tremolo-S and Tremolo-M press release Tremolo-S and Tremolo-M specs available

CSOC SolutionsASCP - Power Management IC (PMIC)

Company Confidential77

PMIC for Intel Moorestown and Oak Trail Platforms

Renesas, Freescale & Maxim are only licensed PMIC suppliers for Intel’s Moorestown and Oak Trail platforms Highly integrated: 2-chips, 23 LDOs, 10 DCDC, 24-bit audio and more Platforms require PMIC and PMIC solutions are not pin-compatible

PMIC = Power Management IC

Intel Atom Roadmap

Company Confidential78

PMIC Solution for Intel’s Moorestown PlatformIntel® Atom™ Processor Z6xx Series & Intel® Platform Controller Hub MP20

Intel Moorestown Platform(Launched May 4, 2010)

RenesasPMIC

OS Support:

Z6xx Series ------Z6xx Series ------

MP20 ------MP20 ------

Battery Charger &5V OTG Boost

DAC

VoltageRegulators

SPIRegister Map

AudioClass A, B, D

RTC

GPIO

CommSPI

Driver

USB/Adapter

RGB

Display

Comms

DDR2

PowerButton

Crystal

MIC Speaker Headphone

BatteryPack

TouchScreen

Sensor

Lincroft

Langwell

Briertown PMIC*

*Generic block diagram – does not show Renesas 2-chip partitioning

Company Confidential79

17 LDOs6 DC-DC Bucks1 DC-DC Buck/Boost

6 LDOs2 DC-DC Bucks1 DC-DC Boost

Ball-pitch = 0.5mm

TouchScreen

White LEDDriver

(BOOST)

BuckConverter

Buck Converter

RGBLED

Driver6 LDOs

AUDIO/ VOICE

Head Phone

SpeakerEarPiece

Micro -Phone

R

Micro -Phone

L

Bri ghtnes sC

ontrol

2 VID Controlled

BuckConverters

4 Buck Converters

17 LDOs

CH

AR

GE

R(D

C/D

C)

Ba

ttery

RTC

SPI

LincroftLangwell

SPI

Coulomb Counter

(Fuel Gauge)

RF Module(2G/3G, WiMAX,

WiFi, GPS, Bluetooth)

ADC

SPI

Interrupt

3 2.768 KHz

32.768KHz

Vibrator

VID (7bits)

Sideband I/FCHIP1 CHIP2

ImageSemsor

PCM/I2S

Thermometer

Light SensorMisc Analog Inputs

LCD Backlight

Camera Scene Illum

PD9975 PD9976

TouchScreen

White LEDDriver

(BOOST)

BuckConverter

Buck Converter

RGBLED

Driver6 LDOs

AUDIO/ VOICE

Head Phone

SpeakerEarPiece

Micro -Phone

R

Micro -Phone

L

Bri ghtnes sC

ontrol

2 VID Controlled

BuckConverters

4 Buck Converters

17 LDOs

CH

AR

GE

R(D

C/D

C)

Ba

ttery

RTC

SPI

LincroftLangwell

SPI

Coulomb Counter

(Fuel Gauge)

RF Module(2G/3G, WiMAX,

WiFi, GPS, Bluetooth)

ADC

SPI

Interrupt

3 2.768 KHz

32.768KHz

Vibrator

VID (7bits)

Sideband I/FCHIP1 CHIP2

ImageSemsor

PCM/I2S

Thermometer

Light SensorMisc Analog Inputs

LCD Backlight

Camera Scene Illum

PD9975 PD9976

195-pin, 8.5mm2 BGAμPD9975

163-pin, 8.0mm2 BGAμPD9976

UX4 CMOS (in production since’04)Process

NEC Part # Package

195-pin, 8.5mm2 BGAμPD9975

163-pin, 8.0mm2 BGAμPD9976

UX4 CMOS (in production since’04)Process

NEC Part # Package

Renesas PMICMoorestown: uPD9975 & uPD9976Oak Trail: uPD9975

Most widely tested, robust PMIC solutionUnique PMIC GUI & technical supportBetter tablet features than competitionOptimized Oak Trail PMIC planned

Company Confidential80

Target Applications

Moorestown Oak Trail

OS support:OS support:

CSOC Contacts and Collateral

Company Confidential82

Custom SOC Solutions - Marketing

No b uko Sh iraishiExec. Adm in. Specialis t

C21101 1004, S C

G reg Kasp rza kSr. P rogram M anage r

IB IC , CB ICF DC

Ch ris Tenn an tProgram M anage rCBIC, G ate A rray

CRO

M ark F o xDirecto r

Industrial, IB ICF DC

W arren W o ngSr. P rogram M anage rCom m unications, PL C

SC

Seo w TanSr. P rogram M anage r

Sm art G ridSC

Dan M cL au g h linProgram M anage r

CO TSC

Su d h ir M allyaDirecto r

Sm art G rid, COTSC

Daisu ke Saka iM arketing M anage r

S torag eSC

Patrick YuSr. M arketing M anage r

PM ICSC

Au d rey G oreProgram M anage r

USB3.0SC

Steven Kaw am o toDirecto r

PM IC, S torageSC

Tim Ng u yenG eneral M anage rC21011 004, S C

General CBICEast: Mark FoxWest: Sudhir Mallya

Company Confidential83

Collateral

Technology/application information

www2.renesas.com/asic /tech /ibic

america2.renesas.com/applications/smart_energy/index.html

www.renesas.com/app

ContractsREA Intranet>NECEL Intranet>Services>Core

>Business Services>Forms and Policies

Company Confidential84

Summary

Renesas Electronics offers and ideal platform for power conscious products with our industry leading low power CBIC, eDRAM and PMIC technologies

CSOC offers a variety of ASIC/ASCP solutions with proven including ARM CPU’s, eDRAM, peripherals and high speed interfaces as well as quick time-to-market Gate Arrays

As an IDM, CSOC provides One Stop Shopping – providing Solutions, Design, IP, Fabrication, Packaging, Test, Quality, Reliability, …

CSOC would like to collaborate with Sales to develop account strategies to build customer relationships and create opportunities based on our values and solutions

Failure Analysis

Shipment

Failed ChipsFeedback for Quality Improvement

Testing

ProductionDesignProcess

ChipPackage

Design for TestDesign for Analysis

High Reliability

Quality Control Stressed TestHigh Fault Coverage

Company Confidential85

Renesas Electronics America Inc.Company Confidential