Requirements for BIST-able designsRequirements for BIST-able designs

ScanabilityScanability• connectivity and tracingconnectivity and tracing• data propagationdata propagation• clockingclocking

No bus conflicts No bus conflicts No X state propagation to observable outputsNo X state propagation to observable outputs Random pattern testabilityRandom pattern testability

Sources of X statesSources of X states

Violation on a TIE-X gateViolation on a TIE-X gate Violation on a transparent latchViolation on a transparent latch ROMs or RAMsROMs or RAMs Violation on a busViolation on a bus Non-scan cellNon-scan cell

11

00 11

11

conflictconflict

00

ZZ

00

floatingfloating

Effect of X propagation to MISREffect of X propagation to MISR

Every unknown value can double the number of “correct” signaturesEvery unknown value can double the number of “correct” signatures

00110100101111001010011010010111100101

00110100101110011010010111XX0010100101

Test responseTest response SignatureSignature

For 32 unknown values there are no signatures For 32 unknown values there are no signatures left for fault detection if 32-bit MISR is usedleft for fault detection if 32-bit MISR is used!

00110011XX1001011110010111XX0010100101

Control of three-state driversControl of three-state drivers Avoid using three state drivers Exactly one driver should be active at any time

in normal and test mode

Avoid using three state drivers Exactly one driver should be active at any time

in normal and test mode

decoderdecoder

TT

TT

T

No test pointsNo test points!

Preferred mux-based implementationPreferred mux-based implementation

Feedback loopsFeedback loops

00

00

11

00 00

00

00

Unknown oscillatory state X bounding by blocking the output of the loop Loop cutting by control points

Unknown oscillatory state X bounding by blocking the output of the loop Loop cutting by control points

00

11

11

11

11

Memory test schemesMemory test schemes

BypassBypass

Test modeTest mode

Black boxingBlack boxing• space compactors can be used on inputsspace compactors can be used on inputs• multiplexing or gating on the outputmultiplexing or gating on the output• driven by flip-flops and MTPIdriven by flip-flops and MTPI

TransparTransparency

MemoryMemoryblockblock

Uncontrollable clocksUncontrollable clocks

ClockClock

Test modeTest mode

Make them controllable in test mode!Make them controllable in test mode!

DD QQ DD QQ

Pseudo-random testingPseudo-random testing

Though generated deterministically, test vectors Though generated deterministically, test vectors have the characteristics of random patternshave the characteristics of random patterns

Applicable to both combinational and sequential Applicable to both combinational and sequential circuitscircuits

Fault simulation is requiredFault simulation is required No test data to storeNo test data to store Tests generated by very simple hardwareTests generated by very simple hardware Applicable to BISTApplicable to BIST Must be supplemented by other techniques if Must be supplemented by other techniques if

random-pattern-resistant faults occurrandom-pattern-resistant faults occur

Random pattern resistanceRandom pattern resistance

20% - 40% of faults are typically random 20% - 40% of faults are typically random pattern resistantpattern resistant

Fault coverage

0

20

40

60

80

100

0 20 40 60 80 100

The number of test patterns

%

?

Example of RPRExample of RPR

Only one out of 2Only one out of 23232 (4 billion) patterns detects the fault (4 billion) patterns detects the fault

s-a-0s-a-0

Test points - control pointsTest points - control points

Types of control pointsTypes of control points• AND - enhance controllability of “0”AND - enhance controllability of “0”• OR - enhance controllability of “1”OR - enhance controllability of “1”• XOR - balance control of “0” and “1” without XOR - balance control of “0” and “1” without

reducing observabilityreducing observability Source of stimuliSource of stimuli

• generator of test patterns - pseudorandom and generator of test patterns - pseudorandom and switching independentlyswitching independently

• additional scan cells - pseudorandom and switching additional scan cells - pseudorandom and switching independentlyindependently

• phase decoder - quasistatic and strongly correlatedphase decoder - quasistatic and strongly correlated

AND and OR control pointsAND and OR control points

Test modeTest mode

Test modeTest mode

Control points driven by scanControl points driven by scan

PPRRPPGG

MMIISSRR

Test modeTest mode

Test modeTest mode

11

11

11

11

11

11

11

00

11

11

11

11

11

11

11

00

Multiphase test point insertion (MTPI)Multiphase test point insertion (MTPI)

C4C4

C3C3

C2C2

C1C1

PatternPatterncountercounter

AA

CC

BB

DD00

00

00

00

11

11

11

11

11

11

11

00

11

11

00

11

11

11

11

11 Phase Phase C1C1 C2C2 C3C3 C4C4 TestTest00 00 00 00 00 --11 00 11 11 11 AA22 11 00 11 11 BB33 11 11 00 11 CC44 11 11 11 00 DD

00 44

MTPI architectureMTPI architecture

00 11 22 33

100%100%

FaultFaultcoveragecoverage

Phase decoderPhase decoder

Logic off-limits to control pointsLogic off-limits to control points

Critical paths Bus “one-hot” encoding logic for buses Outputs of large drivers Bounding logic

STUMPS architectureSTUMPS architecture

scan chainsscan chains

TTEESSTT

GGEENNEERRAATTOORR

CCOOMMPPAACCTTOORR

ControlControl

Logic BIST architecture - MTPILogic BIST architecture - MTPI

MTPIMTPIMTPIMTPI

PPRRPPGG

PPHHAASSEE

SSHHIIFFTTEERR

PPHHAASSEE

SSHHIIFFTTEERR

RunRunResetReset

DoneDoneHold /ResetHold /Reset

Hold /ResetHold /Reset

SenSen

......

BIST controllerBIST controllerBIST controllerBIST controller

ScanScanScanScan

......

ScanScanScanScan

ScanScanScanScan++

++

......

MMIISSRR

ClockClock

Logic BIST architecture - TPILogic BIST architecture - TPI

PPRRPPGG

PPHHAASSEE

SSHHIIFFTTEERR

PPHHAASSEE

SSHHIIFFTTEERR

RunRunResetReset

DoneDoneHold /ResetHold /Reset

Hold /ResetHold /Reset

SenSen

......

BIST controllerBIST controllerBIST controllerBIST controller

ScanScanScanScan

......

ScanScanScanScan++

++

......

MMIISSRR

ClockClock

ScanScanScanScan

BIST sessionBIST session

ResetReset

SenSen

PPRRPPGG

ClockClock

......

MMIISSRR

ScanScanScanScan

ScanScanScanScan

HoldHoldResetResetHoldHold

ClockClock

SenSen

SCSC

PCPC

128128

00

00128128

11

CC

loadingloading unloadingunloading

Simple BIST controllerSimple BIST controller

BIST ResetBIST Reset

holdhold

SenSen

BISTBISTDoneDone

BIST RunBIST Run.....

.

ClockClock

......

Shift counterShift counterShift counterShift counter

Pattern counterPattern counterPattern counterPattern counter

SenSen

ScanScanScanScan

ScanScanScanScan

SinSin SoutSout

MMIISSRR

PPRRPPGG

BIST controller and TAPBIST controller and TAPSenSen

holdhold.....

. ......

Shift counterShift counterShift counterShift counter

Pattern counterPattern counterPattern counterPattern counter

SenSen

ScanScanScanScan

ScanScanScanScan

SinSin SoutSout

MMIISSRR

PPRRPPGG

1148.1 TAP1148.1 TAPClk Reset RunClk Reset Run

Boundary scan and BISTBoundary scan and BIST

Load BIST registers

RUNBISTUnload MISR

Application logicApplication logicApplication logicApplication logic

Boundary scanBoundary scanBoundary scanBoundary scan

Instruction registerInstruction registerInstruction registerInstruction register

Instruction decoderInstruction decoder

TAPTAP

OutputOutputbufferbuffer

OutputOutputbufferbuffer

TDITDI

TRST*TRST*TCKTCKTMSTMS

TDOTDO

BRBRBRBR

Device ID registerDevice ID registerDevice ID registerDevice ID register

Pattern counterPattern counterPattern counterPattern counter

PRPG / M ISRPRPG / M ISRPRPG / M ISRPRPG / M ISR

Shift counterShift counterShift counterShift counter

Signature comparisonSignature comparison

MMIISSRR

00

11

00

11

00

11

hardwired comparatorhardwired comparator

Handling of primary inputsHandling of primary inputs

Handling of primary outputsHandling of primary outputs

BISTBIST

Logic BIST flowLogic BIST flow

SCANSCAN X-BoundX-Bound Test PointsTest PointsGate level netlistGate level netlistGate level netlistGate level netlist final core netlistfinal core netlistfinal core netlistfinal core netlist

BIST ControllerBIST ControllerSynthesisSynthesis

Parallel PatternParallel PatternSimulatorSimulator

RTL for controllerRTL for controllerRTL for controllerRTL for controller

Fault coverageFault coveragereportsreports

Fault coverageFault coveragereportsreports

PRPG and MISRPRPG and MISRvalues per patternvalues per patternPRPG and MISRPRPG and MISR

values per patternvalues per pattern

Scan chain load/Scan chain load/unload dataunload data

Scan chain load/Scan chain load/unload dataunload data

RTL toRTL toGatesGates

Testbench & TestTestbench & TestVector GenerationVector Generation

Verilog / VHDLVerilog / VHDLtestbenchtestbench

Verilog / VHDLVerilog / VHDLtestbenchtestbench

Time-basedTime-basedSimulationsSimulations

WGL vectorsWGL vectorsWGL vectorsWGL vectors ATEATE resultsresultsresultsresults

Diagnostics - overviewDiagnostics - overview

Use bypass mode and conventional ATPGUse bypass mode and conventional ATPG• Different pattern set for ATPG versus diagnosticsDifferent pattern set for ATPG versus diagnostics

Use only MISR values to diagnose faultUse only MISR values to diagnose fault• Minimal data volumeMinimal data volume• complex algorithms to isolate failing gatescomplex algorithms to isolate failing gates• Must deal with MISR corruptionMust deal with MISR corruption

Hybrid techniquesHybrid techniques• MISR value is used to identify failing pattern MISR value is used to identify failing pattern • BYPASS mode unloads subset of failing patternsBYPASS mode unloads subset of failing patterns

Diagnostics- hybrid approachDiagnostics- hybrid approach

128k patterns128k patterns128k patterns128k patterns

8k patterns8k patterns8k patterns8k patterns

8k patterns with MISR re-load after each pattern8k patterns with MISR re-load after each pattern8k patterns with MISR re-load after each pattern8k patterns with MISR re-load after each pattern

Check

MISR

Check

MISR

Check

MISR 8k patterns8k patterns8k patterns8k patterns Check

MISR

Check

MISR 8k patterns8k patterns8k patterns8k patterns Check

MISR

Check

MISR

Run pass/fail test

Identify failing pattern regions

Identify individual failing patterns

Seed PRPG,Seed PRPG,

apply patternapply pattern

unload scan dataunload scan data

Seed PRPG,Seed PRPG,

apply patternapply pattern

unload scan dataunload scan data

Unload a subset of failing patternsSeed PRPG,Seed PRPG,

apply patternapply pattern

unload scan dataunload scan data

Seed PRPG,Seed PRPG,

apply patternapply pattern

unload scan dataunload scan data

Seed PRPG,Seed PRPG,

apply patternapply pattern

unload scan dataunload scan data

Seed PRPG,Seed PRPG,

apply patternapply pattern

unload scan dataunload scan data............

............

TI ResultsTI Results

ASIC-1ASIC-1

125MHz

65K

96.0%

3.4%

0.1s

0.6h

0.9h

At-speed test ? At-speed test ?

BIST pattern count BIST pattern count

BIST stuck-at grade BIST stuck-at grade

BIST gate overhead BIST gate overhead

BIST silicon run time BIST silicon run time

Delta RTL to gates Delta RTL to gates

Fault simulation time Fault simulation time

ASIC-1ASIC-1 ASIC-1ASIC-1 ASIC-1ASIC-1

75MHz

262K

95.7%

2.6%

0.6s

3.0h

3.4h

75MHz

262K

95.3%

2.1%

0.9s

6.0h

5.2h

75MHz

262K

95.6%

1.6%

1.2s

13.4h

4.0h

Other resultsOther results

SizeSize

1250KCisco Telecom

Design

SpeedSpeed CoverageCoverage

62.5MHz 96.15%

# patterns# patterns

16K

SizeSize

~90K ARM Core

SpeedSpeed CoverageCoverage

? Over 95%

# patterns# patterns

32K

967 ctrl points, 1000 observe points

200 ctrl points, 200 observe points

(ITC 2001)(ITC 2001)(ITC 2001)(ITC 2001)

SummarySummary

BIST-able design should have• scan• no internal bus conflicts or floating buses• no X states propagating to observable outputs• be random-pattern testable

X states are bounded by test logic Random pattern testability is improved by control

and observe points ATPG patterns may be used to achieve the

highest possible coverage