Research ArticleImproved Quantization Error Compensation Method forFixed-Width Booth Multipliers
Xiaolong Ma Jiangtao Xu and Guican Chen
School of Electronics and Information Engineering Xirsquoan Jiaotong University Xirsquoan 710049 China
Correspondence should be addressed to Jiangtao Xu jtxumailxjtueducn
Received 13 September 2013 Accepted 22 December 2013 Published 6 February 2014
Academic Editor M Renovell
Copyright copy 2014 Xiaolong Ma et al This is an open access article distributed under the Creative Commons Attribution Licensewhich permits unrestricted use distribution and reproduction in any medium provided the original work is properly cited
A novel quantization error (QE) compensation method is proposed in design of high accuracy fixed-width radix-4 Boothmultipliers which will effectively reduce the QE and save the area of multipliers when they are employed in cognitive radio (CR)detector and digital signal processor (DSP)The truncated partial-products of the proposedmultipliers are finely divided into threesections reserved section adaptive compensation section and constant compensation sectionTheQE compensation carries of themultipliers are generated by applying probability estimation based on a shrunkenminor truncated sectionwhich is a combination ofthe constant compensation and adaptive compensationThe proposed compensation method not only reduces the QE of the fixed-width Booth multipliers but also avoids the exhaustive computing resources (time and memory) during getting the compensationcarries by statistical simulationThe proposedmethod can achieve higher accuracy than the existing works under the same area andpower budgets Simulation and experiment results show that the improved compensation method has the minimum power-delayproducts compared with the existing methods under the same area and can save up to 30 area for realization of full-width radix-4Booth multipliers
1 Introduction
The fixed-width multipliers have been widely used in thedesign of digital signal processor (DSP) due to their smallerarea and lower power dissipation [1ndash3] In order to reducethe chip area of channel detector for cognitive radio manyfixed-width Booth multipliers have been used Howeverthey reduce the detection accuracy because of truncatedpartial-products Therefore a quantization error compensa-tion (QEC) technique is required in the design of fixed-widthBooth multipliers
The traditional methods of QEC for fixed-widthmultipli-ers can be divided into three categories The first category isconstant compensation [4] In this method the value of QECis a constant and it has the advantage of simplicity but leadsto large quantization error (QE)The second category is adap-tive QEC [5] This method can reduce the truncated errorby using variable compensation value The third category ishybrid error compensation which uses both constant andadaptive QEC techniques together to reduce the truncatederror Compared with the first two categories this category
is more accurate [6] In [7 8] two new QEC methods havebeen presented respectively However these two methodsare usually used in the design of Baugh-Wooley multiplierand are not applicable for the design of Booth multipliersAnother QEC method using binary threshold algorithm hasbeen presented in [9] but its accuracy is lower comparedwiththemethod presented in [1] In [2] the statistical analysis andlinear regression analysis are adopted to generate QEC valueand the adaptiveQECmethod is introduced into the design offixed-width radix-4 Booth multipliers for the first time TheadaptiveQECmethod has higher accuracy comparedwith [1]but is very complex In order to overcome the disadvantagesof [2] [10] has presented a method of dividing the truncatedpartial-products into the major truncated section and theminor truncated section The major truncated section isadjacent to the reserved section while the QEC of the minortruncated section is realized by adaptive method In [11] anew QEC method based on [10] is proposed Its truncationerror is more symmetric but its quantization accuracy is notimproved distinctly Refrence [12] has proposed an adaptiveQEC method with conditional-probability estimator instead
Hindawi Publishing CorporationVLSI DesignVolume 2014 Article ID 451310 9 pageshttpdxdoiorg1011552014451310
2 VLSI Design
of the time-consuming exhaustive simulation of the previousworks especially for large bit-width Booth multipliers Oneclosed form formula was derived in [13] with the traditionalmethod of probabilistic estimation to estimate the QECHowever the closed form formula is only an approximationof the mean of the minor truncated section which decreasedthe compensation accuracy
The compensation carries of the minor truncated sectionin [10ndash13] are generated by exploiting adaptive QECmethodsbased on all the truncated partial-products In [10 11] thecompensation carries are generated by all the truncatedpartial-products and hence the simulation statistics willconsume large amount of computer resources (time andmemory requirements) The demanded resources are almostan exponential function of the bit-width Therefore for themultipliers with wider bits an ordinary computer cannotcompete for the simulations Although the resources aredecreased in [12 13] their QEC accuracy cannot be effectivelyimproved
Based on the trade-off between the accuracy and com-puter resources the minor truncated section is divided intotwo parts in this paper the lower partial-products and theupper partial-products In fact the compensation carriesare less affected by the lower partial-products of the minortruncated sectionTherefore we propose that a compensationconstant of the lower partial-products can be generatedby statistical analysis and then the compensation constantis incorporated into the upper partial-products to form ashrunken minor truncated section Finally the quantitativecompensation carries are created by applying probabilityestimation based on the shrunken minor truncated sectionhereafter this multiplier is called shrunken partial-productscompensation (SPPC) Booth multiplier The proposed QECmethod not only reduces the QE of the multipliers butalso avoids the exhaustive simulation resource requirementsSimulations and experiments show that comparing withthe previous works [9ndash13] the proposed QEC method caneffectively improve the QE and performances of the fixed-width Booth multipliers In order to verify the proposedQEC method we have also designed different width SPPCmultiplier circuits and have compared them with other samewidth multipliers based on TSMC 018 120583m process Theexperiments show that the proposed SPPC Booth multipliershave smaller die area as the width of multipliers increases
The rest of the paper is organized as follows Section 2introduces the principle of the modified radix-4 Booth mul-tiplier Proposed QECmethod is discussed in Section 3 alongwith circuit realization Simulation results comparisonsand an application experiment are presented in Section 4Section 5 concludes the paper
2 Modified Radix-4 Booth Multiplier
The modified radix-4 Booth recoding method was proposedin [14] which is a common method used in Booth multiplierdesigns
The N-bit multiplicand 119883 and M-bit multiplicator 119884 ofthe 2-complementsrsquo multiplier are expressed as follows
119883 = minus119909119873minus1
+
119873minus1
sum
119894=1
119909119873minus1minus119894
2minus119894 (1)
119884 = minus119910119872minus1
+
119872minus1
sum
119894=1
119910119872minus1minus119894
2minus119894 (2)
According to modified radix-4 Booth recoding from themost significant bit (MSB) every three bits form a group andadjacent groups overlap by one bit When M is odd 119910
119872=
119910119872minus1
is assumed for proper recoding for sign extension Inany case 119910
minus1= 0 119884 in (2) can be rewritten as
119884 =
1198722minus1
sum
119894=0
1199101015840
1198722minus1minus1198942minus(2119894+1)
(3)
where
1199101015840
1198722minus1minus119894= minus2119910
2119894+1+ 1199102119894+ 1199102119894minus1
(4)
The recoding radix upon (1) is listed in Table 1119883119894sel1119883119894sel2 119878
119894sel and 11991010158401015840
119894denote the binary expression
signs and nonzero states of recoding values respectivelyThe scheme of the modified radix-4 Booth recoding is shownin Figure 1
In a radix-4 Booth multiplier each partial-product (119901119894119895)
associates with two adjacent bits in 119883 The partial-productsof four possible combinations of 119909
119895and 119909
119895minus1are shown in
Table 2A 16 times 16 radix-4 Booth multiplier will be used as a
demo in the following discussion Its partial-product array isshown in Figure 2 The 119904
119894can be concluded by Table 3 the
sign extension bit ei (119894 = 0 7) can be described as thefollowing expression [15]
31 Generation of QEC Carries The partial-products ofmodified Booth multipliers can be divided into two sectionsreserved section 119875
119872and truncated section 119875
119871 as shown in
Figure 2 To improve the accuracy of fixed-width multipliersan additional column 119875
119871119872following PM is reserved and the
compensation carries are derived by the simulated statisticresults [10] In this paper we further divide the rest of 119875
119871into
119875119871119860
and 119875119871119862
and then the product of the multiplier is
119875 = Sum (119875119872) + Sum (119875
119871)
= Sum (119875119872) + Sum (119875
119871119872) + Sum (119875
119871119860) + Sum (119875
119871119862)
(6)
Table 3 Partial-products of different 1199101015840119894
1199101015840
11989411990111989416
11990111989415
11990111989414
sdot sdot sdot 1199011198942
1199011198941
1199011198940
119904119894
0 0 0 0 sdot sdot sdot 0 0 0 01 119909
1511990915
11990914
sdot sdot sdot 1199092
1199091
1199090
0minus1 119909
1511990915
11990914
sdot sdot sdot 1199092
1199091
1199090
12 119909
1511990914
11990913
sdot sdot sdot 1199091
1199090
0 0minus2 119909
1511990914
11990913
sdot sdot sdot 1199091
1199090
1 1
Assuming that a decimal point is between PM and PLwhich does not affect the results of discussion then
Sum (119875119871119872
) = 2minus1
(119901015
+ 119901113
+ 119901211
+ 11990139
+ 11990147
+ 11990155
+ 11990163
+ 11990171
)
(7)
Sum (119875119871119860
) = 2minus2
(119901014
+ 119901112
+ 119901210
+ 11990138
+ 11990146
+ 11990154
+ 11990162
+ 11990170
+ 1199047)
+ 2minus3
(119901013
+ 119901111
+ 11990129
+ 11990137
+ 11990145
+ 11990153
+ 11990161
)
+ 2minus4
(119901012
+ 119901110
+ 11990128
+ 11990136
+ 11990144
+ 11990152
+ 11990160
+ 1199046)
(8)
4 VLSI Design
Sum (119875119871119862
) = 2minus5
(119901011
+ 11990119
+ 11990127
+ 11990135
+ 11990143
+ 11990151
)
+ 2minus6
(119901010
+ 11990118
+ 11990126
+ 11990134
+ 11990142
+ 11990150
+ 1199045)
+ 2minus16
(11990100
+ 1199040)
(9)
In the proposedmethod theQEof119875119871119860
is compensated byadaptive QEC and the QE of119875
119871119862is compensated by constant
QEC As a rule of thumb 3sim5 columns of partial-products areneeded to compose119875
119871119860when thewidth ofmultipliers is 8sim32
bitsIn Table 1 we have defined
11991010158401015840
119894= 119883119894sel1 oplus 119883
119894sel2 (10)
If Booth recoding is nonzero (minus2 minus1 1 2) that is 11991010158401015840119894
= 1then the probability of 119901
119894119895= 0 equals that of 119901
119894119895= 1
Supposing that both the probabilities of119901119894119895
= 1 and 119904119894= 1
are 12 then
119864 [119901119894119895] = 119864 [119904
119894] =
1
2 (11)
where 119864[sdot] is the expected value Substituting (11) in (9) wecan obtain
119864 [Sum (119875119871119862
)] = 2minus5
(1
2+ sdot sdot sdot ) + 2
minus6(1
2+ sdot sdot sdot )
+ sdot sdot sdot + 2minus16
(1
2+
1
2) =
3
16
(12)
Thus the constant 316 acts as the QEC value of 119875119871119862
Similarly the expected value of 119904
7is 12 We replace 119904
7with
12 in (8) obtaining its equivalent decimal value of 18Based on the above proposed SPPC multiplier the 119875
119871119860
with carries in Figure 2 can be redisplayed in Figure 3 whichis denoted by 119875
1015840
119871119860
The maximum carries will be generated if all pij in PLAare 1 In Figure 3 the maximum carries need 7 bits thereforewe register the carry output states of PLA in the variable119903119894(119894 = 0 6) temporarily In the following we propose one
method that associates the nonzero recoding label 11991010158401015840119894with
the compensation carriesAccording to the number of 1 in 119910
10158401015840
119894 we divide the
shrunken partial-product section 1198751015840
119871119860in Figure 3 into
9 categories If there is only one 1 in 11991010158401015840
119894 such as
11991010158401015840
711991010158401015840
611991010158401015840
511991010158401015840
411991010158401015840
311991010158401015840
211991010158401015840
111991010158401015840
0= 00000001 then only one row in
1198751015840
119871119860is nonzero which is the first category (cate-1) We count
the total numbers of 119903119894
= 1 in all the simulation cases Ifthere are two 1rsquos in 119910
10158401015840
119894 such as 119910
10158401015840
711991010158401015840
611991010158401015840
511991010158401015840
411991010158401015840
311991010158401015840
211991010158401015840
111991010158401015840
0=
00000011 then there are two rows in 1198751015840
119871119860that are nonzero
As discussed above once again we count the total numbersof 119903119894= 1 in all the cases by simulation which is named the
second category (cate-2) The remaining seven categories are
1 0
00
+)
131618
P998400LA
p70
p38 p37 p36
p46 p45 p44
p54 p53 p52
p62 p61 p60
p210 p29 p28
p112 p111 p110
p014 p013 p012
p70
p38 p37 p36
p46 p45 p44
p54 p53 p52
p62 p61 p60
p210 p29 p28
p112 p111 p110
p014 p013 p012
s6s6
Figure 3 Rebuilt shrunken adaptive section
deduced as above Compared with [10 11] the method cangreatly reduce the simulation cost The statistical results ofdifferent categories are listed in Table 4 (note that the middlebit between 119901
70and 1199046in 1198751015840
119871119860is still regarded as a partial-
product in simulation)We then encode each category with 4-bits to associate 119910
10158401015840
119894
with compensation carries For example cate-0 is encoded1199113119911211991111199110= 0000 cate-1 is encoded 119911
3119911211991111199110= 0001 and so
onThe compensation carries 119888119894are derived by Table 4 which
comply with the following rule if the numbers of 119903119894= 1 are
larger than a half of the numbers of simulations (NoS) then119888119894= 1 otherwise 119888
119894= 0 The corresponding relations between
the code (1199113119911211991111199110) and ci are listed in Table 5
According to Table 5 the carries 1198880sim1198883are
32 Architecture Design of SPPC Booth Multipliers Thecircuit implementation of category encoding is shown inFigure 4 where the 2Bs-Adder and 3Bs-Adder denote thetwo-bit adder and three-bit adder respectively
In light of (13) one implementation of carry generationcircuits is shown in Figure 5
According to the above discussions a modified radix-4 Booth fixed-width multiplier with the proposed QECcircuits is shown in Figure 6 The traditional Booth recodingencoder circuits of the proposed category encoding andcarry generation compose the QEC circuits to generate theQEC carries
VLSI Design 5
Table 4 The statistic of carry output states for different categories
41 Quantization Accuracy Simulations The comparison ofvarious errors between the proposed SPPC Booth multipliersand the ideal truncated Booth multiplier and other previousworks is listed in Table 6 These errors include the averageerror 120576mean maximum error 120576max and variance 120576var Inaccuracy simulation all the pair data samples are inputted toestimate the QE of the SPPC multiplier The 120576mean 120576max and120576var are defined as follows
120576mean = 119864 [119875 minus 119875119902]
120576max = max 10038161003816100381610038161003816119875 minus 119875119902
10038161003816100381610038161003816
120576var = 119864 [(119875 minus 119875119902)2
] minus (119864 [119875 minus 119875119902])2
(14)
where 119875 and 119875119902are the ideal product and the quantized
product of Booth multipliers respectively | sdot | and maxsdot arethe absolute and maximum operators respectively
The adaptive estimation methods in [9ndash11] have beenadopted to improve the truncation error Instead of exhaus-tive computing resource simulation methods in previousworks [9ndash11] the QE of SPPC multipliers is analyzed andderived from a simpler statistical method It is seen fromTable 6 that the proposed SPPC multipliers have almostthe best error performance compared with previous worksexcept [11] that has the highest performance of 120576mean Thereason is that it uses more information from Booth encoder
to alleviate the truncation errors [11] Nevertheless the areacost in [11] is increased from the extra information ofcompensation circuits Even though 120576max and 120576var of themultipliers in [13] are smaller than other multipliers their120576mean is larger compared with the proposed SPPC multiplierand multipliers in [10ndash12]
The distributions of QE have been calculated in differentmultipliersThe sample ratios of QE value (ie 120576) are listed inthe last three columns of Table 6 It is seen from the statisticalresults that the sample rations of |120576| lt 1 in the SPPC Boothmultipliers are higher than that in [9ndash11] by about 13 Onthe other hand this shows that the quantization accuracy ofthe proposed SPPCmultiplier is higher compared with thosefour methods
42 Performance Simulation A comparison of performancesbetween the proposed SPPC and previous works is imple-mented by using their own compensation circuitsMultiplierswith different widths are synthesized by Synopsys DesignCompiler using a standard cell library of TSMC 018120583mCMOS process Their area delay and power dissipation arelisted in Table 7
In general there exists a trade-off between the hardwareoverhead and the accuracy in these compensation circuitsThe multiplier proposed in [11] has the highest accuracy in120576mean but it has a larger area delay and power Howeverthe SPPC multiplier has the same area as the multipliers in[12 13] and lower area compared with the multipliers in [9ndash11] As a result the proposed SPPCmultipliers achieve higheraccuracy at the cost of the lower area
In order to comprehensively compare the performancesof different multipliers we consider their power-delay prod-ucts as the standard of comparisons which are listed in thelast column of the Table 7 It is shown that the power-delayproducts ofmultipliers proposed in [9ndash11] are larger than thatof other multipliers distinctly Compared with the other twomultipliers in [12 13] the proposed SPPC multipliers havebetter comprehensive performances
43 Verification in FIR Filter The QEC performance of theproposed SPPC is verified by means of a 20 taps low-passdirect form FIR filter The filter is designed to have 8MHzpass-band (with a 40MHz sampling frequency) and 70 dB
attenuation in the stop-band for a CR detector All the widthsof input output and coefficient of the FIR filter are 16 bitsand the internal adders of the FIR filter are 22 bits The inputfor test is a 5MHz sinusoidal signal with a sampling rate of40MHz
Four different multipliers (16 times 16 bits) including theSPPC multiplier and three other multipliers in [11ndash13] areinstantiated in the filter The error mean and error varianceof the output samples in different instantiated multipliers arelisted in Table 8 It is seen from Table 8 that the error meanof [11] is the smallest and the error mean of SPPC is better
than that of [12 13] whereas the error variance of SPPC is thesmallest These results are consistent with the QE accuracysimulation results in the previous section
In CR detectors it is very important to detect the signalrsquosspectral peak-values for determining whether the channelis idle [16] The relative errors of the average spectral peak-values (with 100 times of simulations)with respect to the idealspectral peak-values of the FIR filter outputs are listed in thelast column of Table 8 Table 8 shows that the spectral peak-values of the proposed SPPCmultiplier are closer to the idealpeak-value
By further dividing the minor truncated section of Boothmultiplier into the adaptive compensation and constantcompensation sections we rebuilt the adaptiveQEC for fixed-width multipliers According to the numbers of 1 in the
sequence of nonzero Booth recoding label we propose anew QEC method to generate the compensation carries Thesimulation results have shown that the QE of the SPPC issmaller compared with the existing methods The proposedQEC method and SPPC are useful for the DSP system with alarge width multipliers and higher precision requirements
8 VLSI Design
Table 7 Comparisons of performances with other methods
Width (bits) Multiplier Area (120583m2) Power (mW) Delay (ns) Power-delay product (mWsdotns)
The authors declare that there is no conflict of interestsregarding the publication of this paper
Acknowledgments
The authors gratefully acknowledge the support of ldquoSpecial-ized Research Fund for the Doctoral Program of Higher Edu-cationrdquo (Grant no 20120201120026) and ldquothe FundamentalResearch Funds for the Central Universitiesrdquo
References
[1] J M Jou S R Kuang and R D Chen ldquoDesign of low-errorfixed-width multipliers for DSP applicationsrdquo IEEE Transac-tions on Circuits and Systems II vol 46 no 6 pp 836ndash842 1999
[2] S-J Jou and H-H Wang ldquoFixed-width multiplier for DSPapplicationrdquo in Proceedings of the International Conference onComputer Design VLSI in Computers amp Processors (ICCD rsquo00)pp 318ndash322 Austin Texas USA September 2000
[3] Y-H Chen T-Y Chang and R-Y Jou ldquoA statistical error-compensated Booth multipliers and its DCT applicationsrdquo inProceedings of the IEEE Region 10 Conference (TENCON rsquo10) pp1146ndash1149 Fukuoka Japan November 2010
[4] M J Schulte and E E Swartzlander ldquoTruncated multiplicationwith correction constantrdquo in Proceedings of the IEEE Workshopon VLSI Signal Processing VI pp 388ndash396 Veldhoven TheNetherlands October 1993
[5] E J King and E E Swartzlander ldquoData-dependent truncatedscheme for parallel multiplicationrdquo in Proceedings of the 31stAsilo-mar Conference on Signals Systems amp Computers pp1178ndash1182 Pacific Grove Calif USA November 1997
[6] J E Stine and O M Duverne ldquoVariations on truncatedmultiplicationrdquo in Proceedings of the Euromicro Symposiumon Digital System Design pp 112ndash119 Belek-Antalya TurkeySeptember 2003
VLSI Design 9
[7] L-D Van and C-C Yang ldquoGeneralized low-error area-efficientfixed-width multipliersrdquo IEEE Transactions on Circuits andSystems I vol 52 no 8 pp 1608ndash1619 2005
[8] N Petra D De Caro V Garofalo E Napoli and A G MStrollo ldquoTruncated binary multipliers with variable correctionand minimum mean square errorrdquo IEEE Transactions on Cir-cuits and Systems I vol 57 no 6 pp 1312ndash1325 2010
[9] M-A Song L-DVan and S-Y Kuo ldquoAdaptive low-error fixed-width Booth multipliersrdquo IEICE Transactions on Fundamentalsof Electronics Communications and Computer Sciences vol 90no 6 pp 1180ndash1187 2007
[10] K-J Cho K-C Lee J-G Chung and K K Parhi ldquoDesignof low-error fixed-width modified booth multiplierrdquo IEEETransactions on Very Large Scale Integration (VLSI) Systems vol12 no 5 pp 522ndash531 2004
[11] J-PWang S-R Kuang and S-C Liang ldquoHigh-accuracy fixed-width modified booth multipliers for lossy applicationsrdquo IEEETransactions on Very Large Scale Integration (VLSI) Systems vol19 no 1 pp 52ndash60 2011
[12] Y-H Chen and T-Y Chang ldquoA high-accuracy adaptiveconditional-probability estimator for fixed-width Booth multi-pliersrdquo IEEE Transactions on Circuits and Systems vol 59 no 3pp 594ndash603 2012
[13] Y-H Chen C-Y Li and T-Y Chang ldquoArea-effective andpower-efficient fixed-width boothmultipliers using generalizedprobabilistic estimation biasrdquo IEEE Journal on Emerging andSelected Topics in Circuits and Systems vol 1 no 3 pp 277ndash2882011
[14] O L MacSorley ldquoHigh-speed arithmetic in binary computersrdquoProceedings of IRE vol 49 no 1 pp 67ndash91 1961
[15] G W Bewick Fast Multiplication Algorithms and Implementa-tion Stanford University Palo Alto Calif USA 1994
[16] R Tandra and A Sahai ldquoSNR walls for signal detectionrdquo IEEEJournal on Selected Topics in Signal Processing vol 2 no 1 pp4ndash17 2008
of the time-consuming exhaustive simulation of the previousworks especially for large bit-width Booth multipliers Oneclosed form formula was derived in [13] with the traditionalmethod of probabilistic estimation to estimate the QECHowever the closed form formula is only an approximationof the mean of the minor truncated section which decreasedthe compensation accuracy
The compensation carries of the minor truncated sectionin [10ndash13] are generated by exploiting adaptive QECmethodsbased on all the truncated partial-products In [10 11] thecompensation carries are generated by all the truncatedpartial-products and hence the simulation statistics willconsume large amount of computer resources (time andmemory requirements) The demanded resources are almostan exponential function of the bit-width Therefore for themultipliers with wider bits an ordinary computer cannotcompete for the simulations Although the resources aredecreased in [12 13] their QEC accuracy cannot be effectivelyimproved
Based on the trade-off between the accuracy and com-puter resources the minor truncated section is divided intotwo parts in this paper the lower partial-products and theupper partial-products In fact the compensation carriesare less affected by the lower partial-products of the minortruncated sectionTherefore we propose that a compensationconstant of the lower partial-products can be generatedby statistical analysis and then the compensation constantis incorporated into the upper partial-products to form ashrunken minor truncated section Finally the quantitativecompensation carries are created by applying probabilityestimation based on the shrunken minor truncated sectionhereafter this multiplier is called shrunken partial-productscompensation (SPPC) Booth multiplier The proposed QECmethod not only reduces the QE of the multipliers butalso avoids the exhaustive simulation resource requirementsSimulations and experiments show that comparing withthe previous works [9ndash13] the proposed QEC method caneffectively improve the QE and performances of the fixed-width Booth multipliers In order to verify the proposedQEC method we have also designed different width SPPCmultiplier circuits and have compared them with other samewidth multipliers based on TSMC 018 120583m process Theexperiments show that the proposed SPPC Booth multipliershave smaller die area as the width of multipliers increases
The rest of the paper is organized as follows Section 2introduces the principle of the modified radix-4 Booth mul-tiplier Proposed QECmethod is discussed in Section 3 alongwith circuit realization Simulation results comparisonsand an application experiment are presented in Section 4Section 5 concludes the paper
2 Modified Radix-4 Booth Multiplier
The modified radix-4 Booth recoding method was proposedin [14] which is a common method used in Booth multiplierdesigns
The N-bit multiplicand 119883 and M-bit multiplicator 119884 ofthe 2-complementsrsquo multiplier are expressed as follows
119883 = minus119909119873minus1
+
119873minus1
sum
119894=1
119909119873minus1minus119894
2minus119894 (1)
119884 = minus119910119872minus1
+
119872minus1
sum
119894=1
119910119872minus1minus119894
2minus119894 (2)
According to modified radix-4 Booth recoding from themost significant bit (MSB) every three bits form a group andadjacent groups overlap by one bit When M is odd 119910
119872=
119910119872minus1
is assumed for proper recoding for sign extension Inany case 119910
minus1= 0 119884 in (2) can be rewritten as
119884 =
1198722minus1
sum
119894=0
1199101015840
1198722minus1minus1198942minus(2119894+1)
(3)
where
1199101015840
1198722minus1minus119894= minus2119910
2119894+1+ 1199102119894+ 1199102119894minus1
(4)
The recoding radix upon (1) is listed in Table 1119883119894sel1119883119894sel2 119878
119894sel and 11991010158401015840
119894denote the binary expression
signs and nonzero states of recoding values respectivelyThe scheme of the modified radix-4 Booth recoding is shownin Figure 1
In a radix-4 Booth multiplier each partial-product (119901119894119895)
associates with two adjacent bits in 119883 The partial-productsof four possible combinations of 119909
119895and 119909
119895minus1are shown in
Table 2A 16 times 16 radix-4 Booth multiplier will be used as a
demo in the following discussion Its partial-product array isshown in Figure 2 The 119904
119894can be concluded by Table 3 the
sign extension bit ei (119894 = 0 7) can be described as thefollowing expression [15]
31 Generation of QEC Carries The partial-products ofmodified Booth multipliers can be divided into two sectionsreserved section 119875
119872and truncated section 119875
119871 as shown in
Figure 2 To improve the accuracy of fixed-width multipliersan additional column 119875
119871119872following PM is reserved and the
compensation carries are derived by the simulated statisticresults [10] In this paper we further divide the rest of 119875
119871into
119875119871119860
and 119875119871119862
and then the product of the multiplier is
119875 = Sum (119875119872) + Sum (119875
119871)
= Sum (119875119872) + Sum (119875
119871119872) + Sum (119875
119871119860) + Sum (119875
119871119862)
(6)
Table 3 Partial-products of different 1199101015840119894
1199101015840
11989411990111989416
11990111989415
11990111989414
sdot sdot sdot 1199011198942
1199011198941
1199011198940
119904119894
0 0 0 0 sdot sdot sdot 0 0 0 01 119909
1511990915
11990914
sdot sdot sdot 1199092
1199091
1199090
0minus1 119909
1511990915
11990914
sdot sdot sdot 1199092
1199091
1199090
12 119909
1511990914
11990913
sdot sdot sdot 1199091
1199090
0 0minus2 119909
1511990914
11990913
sdot sdot sdot 1199091
1199090
1 1
Assuming that a decimal point is between PM and PLwhich does not affect the results of discussion then
Sum (119875119871119872
) = 2minus1
(119901015
+ 119901113
+ 119901211
+ 11990139
+ 11990147
+ 11990155
+ 11990163
+ 11990171
)
(7)
Sum (119875119871119860
) = 2minus2
(119901014
+ 119901112
+ 119901210
+ 11990138
+ 11990146
+ 11990154
+ 11990162
+ 11990170
+ 1199047)
+ 2minus3
(119901013
+ 119901111
+ 11990129
+ 11990137
+ 11990145
+ 11990153
+ 11990161
)
+ 2minus4
(119901012
+ 119901110
+ 11990128
+ 11990136
+ 11990144
+ 11990152
+ 11990160
+ 1199046)
(8)
4 VLSI Design
Sum (119875119871119862
) = 2minus5
(119901011
+ 11990119
+ 11990127
+ 11990135
+ 11990143
+ 11990151
)
+ 2minus6
(119901010
+ 11990118
+ 11990126
+ 11990134
+ 11990142
+ 11990150
+ 1199045)
+ 2minus16
(11990100
+ 1199040)
(9)
In the proposedmethod theQEof119875119871119860
is compensated byadaptive QEC and the QE of119875
119871119862is compensated by constant
QEC As a rule of thumb 3sim5 columns of partial-products areneeded to compose119875
119871119860when thewidth ofmultipliers is 8sim32
bitsIn Table 1 we have defined
11991010158401015840
119894= 119883119894sel1 oplus 119883
119894sel2 (10)
If Booth recoding is nonzero (minus2 minus1 1 2) that is 11991010158401015840119894
= 1then the probability of 119901
119894119895= 0 equals that of 119901
119894119895= 1
Supposing that both the probabilities of119901119894119895
= 1 and 119904119894= 1
are 12 then
119864 [119901119894119895] = 119864 [119904
119894] =
1
2 (11)
where 119864[sdot] is the expected value Substituting (11) in (9) wecan obtain
119864 [Sum (119875119871119862
)] = 2minus5
(1
2+ sdot sdot sdot ) + 2
minus6(1
2+ sdot sdot sdot )
+ sdot sdot sdot + 2minus16
(1
2+
1
2) =
3
16
(12)
Thus the constant 316 acts as the QEC value of 119875119871119862
Similarly the expected value of 119904
7is 12 We replace 119904
7with
12 in (8) obtaining its equivalent decimal value of 18Based on the above proposed SPPC multiplier the 119875
119871119860
with carries in Figure 2 can be redisplayed in Figure 3 whichis denoted by 119875
1015840
119871119860
The maximum carries will be generated if all pij in PLAare 1 In Figure 3 the maximum carries need 7 bits thereforewe register the carry output states of PLA in the variable119903119894(119894 = 0 6) temporarily In the following we propose one
method that associates the nonzero recoding label 11991010158401015840119894with
the compensation carriesAccording to the number of 1 in 119910
10158401015840
119894 we divide the
shrunken partial-product section 1198751015840
119871119860in Figure 3 into
9 categories If there is only one 1 in 11991010158401015840
119894 such as
11991010158401015840
711991010158401015840
611991010158401015840
511991010158401015840
411991010158401015840
311991010158401015840
211991010158401015840
111991010158401015840
0= 00000001 then only one row in
1198751015840
119871119860is nonzero which is the first category (cate-1) We count
the total numbers of 119903119894
= 1 in all the simulation cases Ifthere are two 1rsquos in 119910
10158401015840
119894 such as 119910
10158401015840
711991010158401015840
611991010158401015840
511991010158401015840
411991010158401015840
311991010158401015840
211991010158401015840
111991010158401015840
0=
00000011 then there are two rows in 1198751015840
119871119860that are nonzero
As discussed above once again we count the total numbersof 119903119894= 1 in all the cases by simulation which is named the
second category (cate-2) The remaining seven categories are
1 0
00
+)
131618
P998400LA
p70
p38 p37 p36
p46 p45 p44
p54 p53 p52
p62 p61 p60
p210 p29 p28
p112 p111 p110
p014 p013 p012
p70
p38 p37 p36
p46 p45 p44
p54 p53 p52
p62 p61 p60
p210 p29 p28
p112 p111 p110
p014 p013 p012
s6s6
Figure 3 Rebuilt shrunken adaptive section
deduced as above Compared with [10 11] the method cangreatly reduce the simulation cost The statistical results ofdifferent categories are listed in Table 4 (note that the middlebit between 119901
70and 1199046in 1198751015840
119871119860is still regarded as a partial-
product in simulation)We then encode each category with 4-bits to associate 119910
10158401015840
119894
with compensation carries For example cate-0 is encoded1199113119911211991111199110= 0000 cate-1 is encoded 119911
3119911211991111199110= 0001 and so
onThe compensation carries 119888119894are derived by Table 4 which
comply with the following rule if the numbers of 119903119894= 1 are
larger than a half of the numbers of simulations (NoS) then119888119894= 1 otherwise 119888
119894= 0 The corresponding relations between
the code (1199113119911211991111199110) and ci are listed in Table 5
According to Table 5 the carries 1198880sim1198883are
32 Architecture Design of SPPC Booth Multipliers Thecircuit implementation of category encoding is shown inFigure 4 where the 2Bs-Adder and 3Bs-Adder denote thetwo-bit adder and three-bit adder respectively
In light of (13) one implementation of carry generationcircuits is shown in Figure 5
According to the above discussions a modified radix-4 Booth fixed-width multiplier with the proposed QECcircuits is shown in Figure 6 The traditional Booth recodingencoder circuits of the proposed category encoding andcarry generation compose the QEC circuits to generate theQEC carries
VLSI Design 5
Table 4 The statistic of carry output states for different categories
41 Quantization Accuracy Simulations The comparison ofvarious errors between the proposed SPPC Booth multipliersand the ideal truncated Booth multiplier and other previousworks is listed in Table 6 These errors include the averageerror 120576mean maximum error 120576max and variance 120576var Inaccuracy simulation all the pair data samples are inputted toestimate the QE of the SPPC multiplier The 120576mean 120576max and120576var are defined as follows
120576mean = 119864 [119875 minus 119875119902]
120576max = max 10038161003816100381610038161003816119875 minus 119875119902
10038161003816100381610038161003816
120576var = 119864 [(119875 minus 119875119902)2
] minus (119864 [119875 minus 119875119902])2
(14)
where 119875 and 119875119902are the ideal product and the quantized
product of Booth multipliers respectively | sdot | and maxsdot arethe absolute and maximum operators respectively
The adaptive estimation methods in [9ndash11] have beenadopted to improve the truncation error Instead of exhaus-tive computing resource simulation methods in previousworks [9ndash11] the QE of SPPC multipliers is analyzed andderived from a simpler statistical method It is seen fromTable 6 that the proposed SPPC multipliers have almostthe best error performance compared with previous worksexcept [11] that has the highest performance of 120576mean Thereason is that it uses more information from Booth encoder
to alleviate the truncation errors [11] Nevertheless the areacost in [11] is increased from the extra information ofcompensation circuits Even though 120576max and 120576var of themultipliers in [13] are smaller than other multipliers their120576mean is larger compared with the proposed SPPC multiplierand multipliers in [10ndash12]
The distributions of QE have been calculated in differentmultipliersThe sample ratios of QE value (ie 120576) are listed inthe last three columns of Table 6 It is seen from the statisticalresults that the sample rations of |120576| lt 1 in the SPPC Boothmultipliers are higher than that in [9ndash11] by about 13 Onthe other hand this shows that the quantization accuracy ofthe proposed SPPCmultiplier is higher compared with thosefour methods
42 Performance Simulation A comparison of performancesbetween the proposed SPPC and previous works is imple-mented by using their own compensation circuitsMultiplierswith different widths are synthesized by Synopsys DesignCompiler using a standard cell library of TSMC 018120583mCMOS process Their area delay and power dissipation arelisted in Table 7
In general there exists a trade-off between the hardwareoverhead and the accuracy in these compensation circuitsThe multiplier proposed in [11] has the highest accuracy in120576mean but it has a larger area delay and power Howeverthe SPPC multiplier has the same area as the multipliers in[12 13] and lower area compared with the multipliers in [9ndash11] As a result the proposed SPPCmultipliers achieve higheraccuracy at the cost of the lower area
In order to comprehensively compare the performancesof different multipliers we consider their power-delay prod-ucts as the standard of comparisons which are listed in thelast column of the Table 7 It is shown that the power-delayproducts ofmultipliers proposed in [9ndash11] are larger than thatof other multipliers distinctly Compared with the other twomultipliers in [12 13] the proposed SPPC multipliers havebetter comprehensive performances
43 Verification in FIR Filter The QEC performance of theproposed SPPC is verified by means of a 20 taps low-passdirect form FIR filter The filter is designed to have 8MHzpass-band (with a 40MHz sampling frequency) and 70 dB
attenuation in the stop-band for a CR detector All the widthsof input output and coefficient of the FIR filter are 16 bitsand the internal adders of the FIR filter are 22 bits The inputfor test is a 5MHz sinusoidal signal with a sampling rate of40MHz
Four different multipliers (16 times 16 bits) including theSPPC multiplier and three other multipliers in [11ndash13] areinstantiated in the filter The error mean and error varianceof the output samples in different instantiated multipliers arelisted in Table 8 It is seen from Table 8 that the error meanof [11] is the smallest and the error mean of SPPC is better
than that of [12 13] whereas the error variance of SPPC is thesmallest These results are consistent with the QE accuracysimulation results in the previous section
In CR detectors it is very important to detect the signalrsquosspectral peak-values for determining whether the channelis idle [16] The relative errors of the average spectral peak-values (with 100 times of simulations)with respect to the idealspectral peak-values of the FIR filter outputs are listed in thelast column of Table 8 Table 8 shows that the spectral peak-values of the proposed SPPCmultiplier are closer to the idealpeak-value
By further dividing the minor truncated section of Boothmultiplier into the adaptive compensation and constantcompensation sections we rebuilt the adaptiveQEC for fixed-width multipliers According to the numbers of 1 in the
sequence of nonzero Booth recoding label we propose anew QEC method to generate the compensation carries Thesimulation results have shown that the QE of the SPPC issmaller compared with the existing methods The proposedQEC method and SPPC are useful for the DSP system with alarge width multipliers and higher precision requirements
8 VLSI Design
Table 7 Comparisons of performances with other methods
Width (bits) Multiplier Area (120583m2) Power (mW) Delay (ns) Power-delay product (mWsdotns)
The authors declare that there is no conflict of interestsregarding the publication of this paper
Acknowledgments
The authors gratefully acknowledge the support of ldquoSpecial-ized Research Fund for the Doctoral Program of Higher Edu-cationrdquo (Grant no 20120201120026) and ldquothe FundamentalResearch Funds for the Central Universitiesrdquo
References
[1] J M Jou S R Kuang and R D Chen ldquoDesign of low-errorfixed-width multipliers for DSP applicationsrdquo IEEE Transac-tions on Circuits and Systems II vol 46 no 6 pp 836ndash842 1999
[2] S-J Jou and H-H Wang ldquoFixed-width multiplier for DSPapplicationrdquo in Proceedings of the International Conference onComputer Design VLSI in Computers amp Processors (ICCD rsquo00)pp 318ndash322 Austin Texas USA September 2000
[3] Y-H Chen T-Y Chang and R-Y Jou ldquoA statistical error-compensated Booth multipliers and its DCT applicationsrdquo inProceedings of the IEEE Region 10 Conference (TENCON rsquo10) pp1146ndash1149 Fukuoka Japan November 2010
[4] M J Schulte and E E Swartzlander ldquoTruncated multiplicationwith correction constantrdquo in Proceedings of the IEEE Workshopon VLSI Signal Processing VI pp 388ndash396 Veldhoven TheNetherlands October 1993
[5] E J King and E E Swartzlander ldquoData-dependent truncatedscheme for parallel multiplicationrdquo in Proceedings of the 31stAsilo-mar Conference on Signals Systems amp Computers pp1178ndash1182 Pacific Grove Calif USA November 1997
[6] J E Stine and O M Duverne ldquoVariations on truncatedmultiplicationrdquo in Proceedings of the Euromicro Symposiumon Digital System Design pp 112ndash119 Belek-Antalya TurkeySeptember 2003
VLSI Design 9
[7] L-D Van and C-C Yang ldquoGeneralized low-error area-efficientfixed-width multipliersrdquo IEEE Transactions on Circuits andSystems I vol 52 no 8 pp 1608ndash1619 2005
[8] N Petra D De Caro V Garofalo E Napoli and A G MStrollo ldquoTruncated binary multipliers with variable correctionand minimum mean square errorrdquo IEEE Transactions on Cir-cuits and Systems I vol 57 no 6 pp 1312ndash1325 2010
[9] M-A Song L-DVan and S-Y Kuo ldquoAdaptive low-error fixed-width Booth multipliersrdquo IEICE Transactions on Fundamentalsof Electronics Communications and Computer Sciences vol 90no 6 pp 1180ndash1187 2007
[10] K-J Cho K-C Lee J-G Chung and K K Parhi ldquoDesignof low-error fixed-width modified booth multiplierrdquo IEEETransactions on Very Large Scale Integration (VLSI) Systems vol12 no 5 pp 522ndash531 2004
[11] J-PWang S-R Kuang and S-C Liang ldquoHigh-accuracy fixed-width modified booth multipliers for lossy applicationsrdquo IEEETransactions on Very Large Scale Integration (VLSI) Systems vol19 no 1 pp 52ndash60 2011
[12] Y-H Chen and T-Y Chang ldquoA high-accuracy adaptiveconditional-probability estimator for fixed-width Booth multi-pliersrdquo IEEE Transactions on Circuits and Systems vol 59 no 3pp 594ndash603 2012
[13] Y-H Chen C-Y Li and T-Y Chang ldquoArea-effective andpower-efficient fixed-width boothmultipliers using generalizedprobabilistic estimation biasrdquo IEEE Journal on Emerging andSelected Topics in Circuits and Systems vol 1 no 3 pp 277ndash2882011
[14] O L MacSorley ldquoHigh-speed arithmetic in binary computersrdquoProceedings of IRE vol 49 no 1 pp 67ndash91 1961
[15] G W Bewick Fast Multiplication Algorithms and Implementa-tion Stanford University Palo Alto Calif USA 1994
[16] R Tandra and A Sahai ldquoSNR walls for signal detectionrdquo IEEEJournal on Selected Topics in Signal Processing vol 2 no 1 pp4ndash17 2008
31 Generation of QEC Carries The partial-products ofmodified Booth multipliers can be divided into two sectionsreserved section 119875
119872and truncated section 119875
119871 as shown in
Figure 2 To improve the accuracy of fixed-width multipliersan additional column 119875
119871119872following PM is reserved and the
compensation carries are derived by the simulated statisticresults [10] In this paper we further divide the rest of 119875
119871into
119875119871119860
and 119875119871119862
and then the product of the multiplier is
119875 = Sum (119875119872) + Sum (119875
119871)
= Sum (119875119872) + Sum (119875
119871119872) + Sum (119875
119871119860) + Sum (119875
119871119862)
(6)
Table 3 Partial-products of different 1199101015840119894
1199101015840
11989411990111989416
11990111989415
11990111989414
sdot sdot sdot 1199011198942
1199011198941
1199011198940
119904119894
0 0 0 0 sdot sdot sdot 0 0 0 01 119909
1511990915
11990914
sdot sdot sdot 1199092
1199091
1199090
0minus1 119909
1511990915
11990914
sdot sdot sdot 1199092
1199091
1199090
12 119909
1511990914
11990913
sdot sdot sdot 1199091
1199090
0 0minus2 119909
1511990914
11990913
sdot sdot sdot 1199091
1199090
1 1
Assuming that a decimal point is between PM and PLwhich does not affect the results of discussion then
Sum (119875119871119872
) = 2minus1
(119901015
+ 119901113
+ 119901211
+ 11990139
+ 11990147
+ 11990155
+ 11990163
+ 11990171
)
(7)
Sum (119875119871119860
) = 2minus2
(119901014
+ 119901112
+ 119901210
+ 11990138
+ 11990146
+ 11990154
+ 11990162
+ 11990170
+ 1199047)
+ 2minus3
(119901013
+ 119901111
+ 11990129
+ 11990137
+ 11990145
+ 11990153
+ 11990161
)
+ 2minus4
(119901012
+ 119901110
+ 11990128
+ 11990136
+ 11990144
+ 11990152
+ 11990160
+ 1199046)
(8)
4 VLSI Design
Sum (119875119871119862
) = 2minus5
(119901011
+ 11990119
+ 11990127
+ 11990135
+ 11990143
+ 11990151
)
+ 2minus6
(119901010
+ 11990118
+ 11990126
+ 11990134
+ 11990142
+ 11990150
+ 1199045)
+ 2minus16
(11990100
+ 1199040)
(9)
In the proposedmethod theQEof119875119871119860
is compensated byadaptive QEC and the QE of119875
119871119862is compensated by constant
QEC As a rule of thumb 3sim5 columns of partial-products areneeded to compose119875
119871119860when thewidth ofmultipliers is 8sim32
bitsIn Table 1 we have defined
11991010158401015840
119894= 119883119894sel1 oplus 119883
119894sel2 (10)
If Booth recoding is nonzero (minus2 minus1 1 2) that is 11991010158401015840119894
= 1then the probability of 119901
119894119895= 0 equals that of 119901
119894119895= 1
Supposing that both the probabilities of119901119894119895
= 1 and 119904119894= 1
are 12 then
119864 [119901119894119895] = 119864 [119904
119894] =
1
2 (11)
where 119864[sdot] is the expected value Substituting (11) in (9) wecan obtain
119864 [Sum (119875119871119862
)] = 2minus5
(1
2+ sdot sdot sdot ) + 2
minus6(1
2+ sdot sdot sdot )
+ sdot sdot sdot + 2minus16
(1
2+
1
2) =
3
16
(12)
Thus the constant 316 acts as the QEC value of 119875119871119862
Similarly the expected value of 119904
7is 12 We replace 119904
7with
12 in (8) obtaining its equivalent decimal value of 18Based on the above proposed SPPC multiplier the 119875
119871119860
with carries in Figure 2 can be redisplayed in Figure 3 whichis denoted by 119875
1015840
119871119860
The maximum carries will be generated if all pij in PLAare 1 In Figure 3 the maximum carries need 7 bits thereforewe register the carry output states of PLA in the variable119903119894(119894 = 0 6) temporarily In the following we propose one
method that associates the nonzero recoding label 11991010158401015840119894with
the compensation carriesAccording to the number of 1 in 119910
10158401015840
119894 we divide the
shrunken partial-product section 1198751015840
119871119860in Figure 3 into
9 categories If there is only one 1 in 11991010158401015840
119894 such as
11991010158401015840
711991010158401015840
611991010158401015840
511991010158401015840
411991010158401015840
311991010158401015840
211991010158401015840
111991010158401015840
0= 00000001 then only one row in
1198751015840
119871119860is nonzero which is the first category (cate-1) We count
the total numbers of 119903119894
= 1 in all the simulation cases Ifthere are two 1rsquos in 119910
10158401015840
119894 such as 119910
10158401015840
711991010158401015840
611991010158401015840
511991010158401015840
411991010158401015840
311991010158401015840
211991010158401015840
111991010158401015840
0=
00000011 then there are two rows in 1198751015840
119871119860that are nonzero
As discussed above once again we count the total numbersof 119903119894= 1 in all the cases by simulation which is named the
second category (cate-2) The remaining seven categories are
1 0
00
+)
131618
P998400LA
p70
p38 p37 p36
p46 p45 p44
p54 p53 p52
p62 p61 p60
p210 p29 p28
p112 p111 p110
p014 p013 p012
p70
p38 p37 p36
p46 p45 p44
p54 p53 p52
p62 p61 p60
p210 p29 p28
p112 p111 p110
p014 p013 p012
s6s6
Figure 3 Rebuilt shrunken adaptive section
deduced as above Compared with [10 11] the method cangreatly reduce the simulation cost The statistical results ofdifferent categories are listed in Table 4 (note that the middlebit between 119901
70and 1199046in 1198751015840
119871119860is still regarded as a partial-
product in simulation)We then encode each category with 4-bits to associate 119910
10158401015840
119894
with compensation carries For example cate-0 is encoded1199113119911211991111199110= 0000 cate-1 is encoded 119911
3119911211991111199110= 0001 and so
onThe compensation carries 119888119894are derived by Table 4 which
comply with the following rule if the numbers of 119903119894= 1 are
larger than a half of the numbers of simulations (NoS) then119888119894= 1 otherwise 119888
119894= 0 The corresponding relations between
the code (1199113119911211991111199110) and ci are listed in Table 5
According to Table 5 the carries 1198880sim1198883are
32 Architecture Design of SPPC Booth Multipliers Thecircuit implementation of category encoding is shown inFigure 4 where the 2Bs-Adder and 3Bs-Adder denote thetwo-bit adder and three-bit adder respectively
In light of (13) one implementation of carry generationcircuits is shown in Figure 5
According to the above discussions a modified radix-4 Booth fixed-width multiplier with the proposed QECcircuits is shown in Figure 6 The traditional Booth recodingencoder circuits of the proposed category encoding andcarry generation compose the QEC circuits to generate theQEC carries
VLSI Design 5
Table 4 The statistic of carry output states for different categories
41 Quantization Accuracy Simulations The comparison ofvarious errors between the proposed SPPC Booth multipliersand the ideal truncated Booth multiplier and other previousworks is listed in Table 6 These errors include the averageerror 120576mean maximum error 120576max and variance 120576var Inaccuracy simulation all the pair data samples are inputted toestimate the QE of the SPPC multiplier The 120576mean 120576max and120576var are defined as follows
120576mean = 119864 [119875 minus 119875119902]
120576max = max 10038161003816100381610038161003816119875 minus 119875119902
10038161003816100381610038161003816
120576var = 119864 [(119875 minus 119875119902)2
] minus (119864 [119875 minus 119875119902])2
(14)
where 119875 and 119875119902are the ideal product and the quantized
product of Booth multipliers respectively | sdot | and maxsdot arethe absolute and maximum operators respectively
The adaptive estimation methods in [9ndash11] have beenadopted to improve the truncation error Instead of exhaus-tive computing resource simulation methods in previousworks [9ndash11] the QE of SPPC multipliers is analyzed andderived from a simpler statistical method It is seen fromTable 6 that the proposed SPPC multipliers have almostthe best error performance compared with previous worksexcept [11] that has the highest performance of 120576mean Thereason is that it uses more information from Booth encoder
to alleviate the truncation errors [11] Nevertheless the areacost in [11] is increased from the extra information ofcompensation circuits Even though 120576max and 120576var of themultipliers in [13] are smaller than other multipliers their120576mean is larger compared with the proposed SPPC multiplierand multipliers in [10ndash12]
The distributions of QE have been calculated in differentmultipliersThe sample ratios of QE value (ie 120576) are listed inthe last three columns of Table 6 It is seen from the statisticalresults that the sample rations of |120576| lt 1 in the SPPC Boothmultipliers are higher than that in [9ndash11] by about 13 Onthe other hand this shows that the quantization accuracy ofthe proposed SPPCmultiplier is higher compared with thosefour methods
42 Performance Simulation A comparison of performancesbetween the proposed SPPC and previous works is imple-mented by using their own compensation circuitsMultiplierswith different widths are synthesized by Synopsys DesignCompiler using a standard cell library of TSMC 018120583mCMOS process Their area delay and power dissipation arelisted in Table 7
In general there exists a trade-off between the hardwareoverhead and the accuracy in these compensation circuitsThe multiplier proposed in [11] has the highest accuracy in120576mean but it has a larger area delay and power Howeverthe SPPC multiplier has the same area as the multipliers in[12 13] and lower area compared with the multipliers in [9ndash11] As a result the proposed SPPCmultipliers achieve higheraccuracy at the cost of the lower area
In order to comprehensively compare the performancesof different multipliers we consider their power-delay prod-ucts as the standard of comparisons which are listed in thelast column of the Table 7 It is shown that the power-delayproducts ofmultipliers proposed in [9ndash11] are larger than thatof other multipliers distinctly Compared with the other twomultipliers in [12 13] the proposed SPPC multipliers havebetter comprehensive performances
43 Verification in FIR Filter The QEC performance of theproposed SPPC is verified by means of a 20 taps low-passdirect form FIR filter The filter is designed to have 8MHzpass-band (with a 40MHz sampling frequency) and 70 dB
attenuation in the stop-band for a CR detector All the widthsof input output and coefficient of the FIR filter are 16 bitsand the internal adders of the FIR filter are 22 bits The inputfor test is a 5MHz sinusoidal signal with a sampling rate of40MHz
Four different multipliers (16 times 16 bits) including theSPPC multiplier and three other multipliers in [11ndash13] areinstantiated in the filter The error mean and error varianceof the output samples in different instantiated multipliers arelisted in Table 8 It is seen from Table 8 that the error meanof [11] is the smallest and the error mean of SPPC is better
than that of [12 13] whereas the error variance of SPPC is thesmallest These results are consistent with the QE accuracysimulation results in the previous section
In CR detectors it is very important to detect the signalrsquosspectral peak-values for determining whether the channelis idle [16] The relative errors of the average spectral peak-values (with 100 times of simulations)with respect to the idealspectral peak-values of the FIR filter outputs are listed in thelast column of Table 8 Table 8 shows that the spectral peak-values of the proposed SPPCmultiplier are closer to the idealpeak-value
By further dividing the minor truncated section of Boothmultiplier into the adaptive compensation and constantcompensation sections we rebuilt the adaptiveQEC for fixed-width multipliers According to the numbers of 1 in the
sequence of nonzero Booth recoding label we propose anew QEC method to generate the compensation carries Thesimulation results have shown that the QE of the SPPC issmaller compared with the existing methods The proposedQEC method and SPPC are useful for the DSP system with alarge width multipliers and higher precision requirements
8 VLSI Design
Table 7 Comparisons of performances with other methods
Width (bits) Multiplier Area (120583m2) Power (mW) Delay (ns) Power-delay product (mWsdotns)
The authors declare that there is no conflict of interestsregarding the publication of this paper
Acknowledgments
The authors gratefully acknowledge the support of ldquoSpecial-ized Research Fund for the Doctoral Program of Higher Edu-cationrdquo (Grant no 20120201120026) and ldquothe FundamentalResearch Funds for the Central Universitiesrdquo
References
[1] J M Jou S R Kuang and R D Chen ldquoDesign of low-errorfixed-width multipliers for DSP applicationsrdquo IEEE Transac-tions on Circuits and Systems II vol 46 no 6 pp 836ndash842 1999
[2] S-J Jou and H-H Wang ldquoFixed-width multiplier for DSPapplicationrdquo in Proceedings of the International Conference onComputer Design VLSI in Computers amp Processors (ICCD rsquo00)pp 318ndash322 Austin Texas USA September 2000
[3] Y-H Chen T-Y Chang and R-Y Jou ldquoA statistical error-compensated Booth multipliers and its DCT applicationsrdquo inProceedings of the IEEE Region 10 Conference (TENCON rsquo10) pp1146ndash1149 Fukuoka Japan November 2010
[4] M J Schulte and E E Swartzlander ldquoTruncated multiplicationwith correction constantrdquo in Proceedings of the IEEE Workshopon VLSI Signal Processing VI pp 388ndash396 Veldhoven TheNetherlands October 1993
[5] E J King and E E Swartzlander ldquoData-dependent truncatedscheme for parallel multiplicationrdquo in Proceedings of the 31stAsilo-mar Conference on Signals Systems amp Computers pp1178ndash1182 Pacific Grove Calif USA November 1997
[6] J E Stine and O M Duverne ldquoVariations on truncatedmultiplicationrdquo in Proceedings of the Euromicro Symposiumon Digital System Design pp 112ndash119 Belek-Antalya TurkeySeptember 2003
VLSI Design 9
[7] L-D Van and C-C Yang ldquoGeneralized low-error area-efficientfixed-width multipliersrdquo IEEE Transactions on Circuits andSystems I vol 52 no 8 pp 1608ndash1619 2005
[8] N Petra D De Caro V Garofalo E Napoli and A G MStrollo ldquoTruncated binary multipliers with variable correctionand minimum mean square errorrdquo IEEE Transactions on Cir-cuits and Systems I vol 57 no 6 pp 1312ndash1325 2010
[9] M-A Song L-DVan and S-Y Kuo ldquoAdaptive low-error fixed-width Booth multipliersrdquo IEICE Transactions on Fundamentalsof Electronics Communications and Computer Sciences vol 90no 6 pp 1180ndash1187 2007
[10] K-J Cho K-C Lee J-G Chung and K K Parhi ldquoDesignof low-error fixed-width modified booth multiplierrdquo IEEETransactions on Very Large Scale Integration (VLSI) Systems vol12 no 5 pp 522ndash531 2004
[11] J-PWang S-R Kuang and S-C Liang ldquoHigh-accuracy fixed-width modified booth multipliers for lossy applicationsrdquo IEEETransactions on Very Large Scale Integration (VLSI) Systems vol19 no 1 pp 52ndash60 2011
[12] Y-H Chen and T-Y Chang ldquoA high-accuracy adaptiveconditional-probability estimator for fixed-width Booth multi-pliersrdquo IEEE Transactions on Circuits and Systems vol 59 no 3pp 594ndash603 2012
[13] Y-H Chen C-Y Li and T-Y Chang ldquoArea-effective andpower-efficient fixed-width boothmultipliers using generalizedprobabilistic estimation biasrdquo IEEE Journal on Emerging andSelected Topics in Circuits and Systems vol 1 no 3 pp 277ndash2882011
[14] O L MacSorley ldquoHigh-speed arithmetic in binary computersrdquoProceedings of IRE vol 49 no 1 pp 67ndash91 1961
[15] G W Bewick Fast Multiplication Algorithms and Implementa-tion Stanford University Palo Alto Calif USA 1994
[16] R Tandra and A Sahai ldquoSNR walls for signal detectionrdquo IEEEJournal on Selected Topics in Signal Processing vol 2 no 1 pp4ndash17 2008
QEC As a rule of thumb 3sim5 columns of partial-products areneeded to compose119875
119871119860when thewidth ofmultipliers is 8sim32
bitsIn Table 1 we have defined
11991010158401015840
119894= 119883119894sel1 oplus 119883
119894sel2 (10)
If Booth recoding is nonzero (minus2 minus1 1 2) that is 11991010158401015840119894
= 1then the probability of 119901
119894119895= 0 equals that of 119901
119894119895= 1
Supposing that both the probabilities of119901119894119895
= 1 and 119904119894= 1
are 12 then
119864 [119901119894119895] = 119864 [119904
119894] =
1
2 (11)
where 119864[sdot] is the expected value Substituting (11) in (9) wecan obtain
119864 [Sum (119875119871119862
)] = 2minus5
(1
2+ sdot sdot sdot ) + 2
minus6(1
2+ sdot sdot sdot )
+ sdot sdot sdot + 2minus16
(1
2+
1
2) =
3
16
(12)
Thus the constant 316 acts as the QEC value of 119875119871119862
Similarly the expected value of 119904
7is 12 We replace 119904
7with
12 in (8) obtaining its equivalent decimal value of 18Based on the above proposed SPPC multiplier the 119875
119871119860
with carries in Figure 2 can be redisplayed in Figure 3 whichis denoted by 119875
1015840
119871119860
The maximum carries will be generated if all pij in PLAare 1 In Figure 3 the maximum carries need 7 bits thereforewe register the carry output states of PLA in the variable119903119894(119894 = 0 6) temporarily In the following we propose one
method that associates the nonzero recoding label 11991010158401015840119894with
the compensation carriesAccording to the number of 1 in 119910
10158401015840
119894 we divide the
shrunken partial-product section 1198751015840
119871119860in Figure 3 into
9 categories If there is only one 1 in 11991010158401015840
119894 such as
11991010158401015840
711991010158401015840
611991010158401015840
511991010158401015840
411991010158401015840
311991010158401015840
211991010158401015840
111991010158401015840
0= 00000001 then only one row in
1198751015840
119871119860is nonzero which is the first category (cate-1) We count
the total numbers of 119903119894
= 1 in all the simulation cases Ifthere are two 1rsquos in 119910
10158401015840
119894 such as 119910
10158401015840
711991010158401015840
611991010158401015840
511991010158401015840
411991010158401015840
311991010158401015840
211991010158401015840
111991010158401015840
0=
00000011 then there are two rows in 1198751015840
119871119860that are nonzero
As discussed above once again we count the total numbersof 119903119894= 1 in all the cases by simulation which is named the
second category (cate-2) The remaining seven categories are
1 0
00
+)
131618
P998400LA
p70
p38 p37 p36
p46 p45 p44
p54 p53 p52
p62 p61 p60
p210 p29 p28
p112 p111 p110
p014 p013 p012
p70
p38 p37 p36
p46 p45 p44
p54 p53 p52
p62 p61 p60
p210 p29 p28
p112 p111 p110
p014 p013 p012
s6s6
Figure 3 Rebuilt shrunken adaptive section
deduced as above Compared with [10 11] the method cangreatly reduce the simulation cost The statistical results ofdifferent categories are listed in Table 4 (note that the middlebit between 119901
70and 1199046in 1198751015840
119871119860is still regarded as a partial-
product in simulation)We then encode each category with 4-bits to associate 119910
10158401015840
119894
with compensation carries For example cate-0 is encoded1199113119911211991111199110= 0000 cate-1 is encoded 119911
3119911211991111199110= 0001 and so
onThe compensation carries 119888119894are derived by Table 4 which
comply with the following rule if the numbers of 119903119894= 1 are
larger than a half of the numbers of simulations (NoS) then119888119894= 1 otherwise 119888
119894= 0 The corresponding relations between
the code (1199113119911211991111199110) and ci are listed in Table 5
According to Table 5 the carries 1198880sim1198883are
32 Architecture Design of SPPC Booth Multipliers Thecircuit implementation of category encoding is shown inFigure 4 where the 2Bs-Adder and 3Bs-Adder denote thetwo-bit adder and three-bit adder respectively
In light of (13) one implementation of carry generationcircuits is shown in Figure 5
According to the above discussions a modified radix-4 Booth fixed-width multiplier with the proposed QECcircuits is shown in Figure 6 The traditional Booth recodingencoder circuits of the proposed category encoding andcarry generation compose the QEC circuits to generate theQEC carries
VLSI Design 5
Table 4 The statistic of carry output states for different categories
41 Quantization Accuracy Simulations The comparison ofvarious errors between the proposed SPPC Booth multipliersand the ideal truncated Booth multiplier and other previousworks is listed in Table 6 These errors include the averageerror 120576mean maximum error 120576max and variance 120576var Inaccuracy simulation all the pair data samples are inputted toestimate the QE of the SPPC multiplier The 120576mean 120576max and120576var are defined as follows
120576mean = 119864 [119875 minus 119875119902]
120576max = max 10038161003816100381610038161003816119875 minus 119875119902
10038161003816100381610038161003816
120576var = 119864 [(119875 minus 119875119902)2
] minus (119864 [119875 minus 119875119902])2
(14)
where 119875 and 119875119902are the ideal product and the quantized
product of Booth multipliers respectively | sdot | and maxsdot arethe absolute and maximum operators respectively
The adaptive estimation methods in [9ndash11] have beenadopted to improve the truncation error Instead of exhaus-tive computing resource simulation methods in previousworks [9ndash11] the QE of SPPC multipliers is analyzed andderived from a simpler statistical method It is seen fromTable 6 that the proposed SPPC multipliers have almostthe best error performance compared with previous worksexcept [11] that has the highest performance of 120576mean Thereason is that it uses more information from Booth encoder
to alleviate the truncation errors [11] Nevertheless the areacost in [11] is increased from the extra information ofcompensation circuits Even though 120576max and 120576var of themultipliers in [13] are smaller than other multipliers their120576mean is larger compared with the proposed SPPC multiplierand multipliers in [10ndash12]
The distributions of QE have been calculated in differentmultipliersThe sample ratios of QE value (ie 120576) are listed inthe last three columns of Table 6 It is seen from the statisticalresults that the sample rations of |120576| lt 1 in the SPPC Boothmultipliers are higher than that in [9ndash11] by about 13 Onthe other hand this shows that the quantization accuracy ofthe proposed SPPCmultiplier is higher compared with thosefour methods
42 Performance Simulation A comparison of performancesbetween the proposed SPPC and previous works is imple-mented by using their own compensation circuitsMultiplierswith different widths are synthesized by Synopsys DesignCompiler using a standard cell library of TSMC 018120583mCMOS process Their area delay and power dissipation arelisted in Table 7
In general there exists a trade-off between the hardwareoverhead and the accuracy in these compensation circuitsThe multiplier proposed in [11] has the highest accuracy in120576mean but it has a larger area delay and power Howeverthe SPPC multiplier has the same area as the multipliers in[12 13] and lower area compared with the multipliers in [9ndash11] As a result the proposed SPPCmultipliers achieve higheraccuracy at the cost of the lower area
In order to comprehensively compare the performancesof different multipliers we consider their power-delay prod-ucts as the standard of comparisons which are listed in thelast column of the Table 7 It is shown that the power-delayproducts ofmultipliers proposed in [9ndash11] are larger than thatof other multipliers distinctly Compared with the other twomultipliers in [12 13] the proposed SPPC multipliers havebetter comprehensive performances
43 Verification in FIR Filter The QEC performance of theproposed SPPC is verified by means of a 20 taps low-passdirect form FIR filter The filter is designed to have 8MHzpass-band (with a 40MHz sampling frequency) and 70 dB
attenuation in the stop-band for a CR detector All the widthsof input output and coefficient of the FIR filter are 16 bitsand the internal adders of the FIR filter are 22 bits The inputfor test is a 5MHz sinusoidal signal with a sampling rate of40MHz
Four different multipliers (16 times 16 bits) including theSPPC multiplier and three other multipliers in [11ndash13] areinstantiated in the filter The error mean and error varianceof the output samples in different instantiated multipliers arelisted in Table 8 It is seen from Table 8 that the error meanof [11] is the smallest and the error mean of SPPC is better
than that of [12 13] whereas the error variance of SPPC is thesmallest These results are consistent with the QE accuracysimulation results in the previous section
In CR detectors it is very important to detect the signalrsquosspectral peak-values for determining whether the channelis idle [16] The relative errors of the average spectral peak-values (with 100 times of simulations)with respect to the idealspectral peak-values of the FIR filter outputs are listed in thelast column of Table 8 Table 8 shows that the spectral peak-values of the proposed SPPCmultiplier are closer to the idealpeak-value
By further dividing the minor truncated section of Boothmultiplier into the adaptive compensation and constantcompensation sections we rebuilt the adaptiveQEC for fixed-width multipliers According to the numbers of 1 in the
sequence of nonzero Booth recoding label we propose anew QEC method to generate the compensation carries Thesimulation results have shown that the QE of the SPPC issmaller compared with the existing methods The proposedQEC method and SPPC are useful for the DSP system with alarge width multipliers and higher precision requirements
8 VLSI Design
Table 7 Comparisons of performances with other methods
Width (bits) Multiplier Area (120583m2) Power (mW) Delay (ns) Power-delay product (mWsdotns)
The authors declare that there is no conflict of interestsregarding the publication of this paper
Acknowledgments
The authors gratefully acknowledge the support of ldquoSpecial-ized Research Fund for the Doctoral Program of Higher Edu-cationrdquo (Grant no 20120201120026) and ldquothe FundamentalResearch Funds for the Central Universitiesrdquo
References
[1] J M Jou S R Kuang and R D Chen ldquoDesign of low-errorfixed-width multipliers for DSP applicationsrdquo IEEE Transac-tions on Circuits and Systems II vol 46 no 6 pp 836ndash842 1999
[2] S-J Jou and H-H Wang ldquoFixed-width multiplier for DSPapplicationrdquo in Proceedings of the International Conference onComputer Design VLSI in Computers amp Processors (ICCD rsquo00)pp 318ndash322 Austin Texas USA September 2000
[3] Y-H Chen T-Y Chang and R-Y Jou ldquoA statistical error-compensated Booth multipliers and its DCT applicationsrdquo inProceedings of the IEEE Region 10 Conference (TENCON rsquo10) pp1146ndash1149 Fukuoka Japan November 2010
[4] M J Schulte and E E Swartzlander ldquoTruncated multiplicationwith correction constantrdquo in Proceedings of the IEEE Workshopon VLSI Signal Processing VI pp 388ndash396 Veldhoven TheNetherlands October 1993
[5] E J King and E E Swartzlander ldquoData-dependent truncatedscheme for parallel multiplicationrdquo in Proceedings of the 31stAsilo-mar Conference on Signals Systems amp Computers pp1178ndash1182 Pacific Grove Calif USA November 1997
[6] J E Stine and O M Duverne ldquoVariations on truncatedmultiplicationrdquo in Proceedings of the Euromicro Symposiumon Digital System Design pp 112ndash119 Belek-Antalya TurkeySeptember 2003
VLSI Design 9
[7] L-D Van and C-C Yang ldquoGeneralized low-error area-efficientfixed-width multipliersrdquo IEEE Transactions on Circuits andSystems I vol 52 no 8 pp 1608ndash1619 2005
[8] N Petra D De Caro V Garofalo E Napoli and A G MStrollo ldquoTruncated binary multipliers with variable correctionand minimum mean square errorrdquo IEEE Transactions on Cir-cuits and Systems I vol 57 no 6 pp 1312ndash1325 2010
[9] M-A Song L-DVan and S-Y Kuo ldquoAdaptive low-error fixed-width Booth multipliersrdquo IEICE Transactions on Fundamentalsof Electronics Communications and Computer Sciences vol 90no 6 pp 1180ndash1187 2007
[10] K-J Cho K-C Lee J-G Chung and K K Parhi ldquoDesignof low-error fixed-width modified booth multiplierrdquo IEEETransactions on Very Large Scale Integration (VLSI) Systems vol12 no 5 pp 522ndash531 2004
[11] J-PWang S-R Kuang and S-C Liang ldquoHigh-accuracy fixed-width modified booth multipliers for lossy applicationsrdquo IEEETransactions on Very Large Scale Integration (VLSI) Systems vol19 no 1 pp 52ndash60 2011
[12] Y-H Chen and T-Y Chang ldquoA high-accuracy adaptiveconditional-probability estimator for fixed-width Booth multi-pliersrdquo IEEE Transactions on Circuits and Systems vol 59 no 3pp 594ndash603 2012
[13] Y-H Chen C-Y Li and T-Y Chang ldquoArea-effective andpower-efficient fixed-width boothmultipliers using generalizedprobabilistic estimation biasrdquo IEEE Journal on Emerging andSelected Topics in Circuits and Systems vol 1 no 3 pp 277ndash2882011
[14] O L MacSorley ldquoHigh-speed arithmetic in binary computersrdquoProceedings of IRE vol 49 no 1 pp 67ndash91 1961
[15] G W Bewick Fast Multiplication Algorithms and Implementa-tion Stanford University Palo Alto Calif USA 1994
[16] R Tandra and A Sahai ldquoSNR walls for signal detectionrdquo IEEEJournal on Selected Topics in Signal Processing vol 2 no 1 pp4ndash17 2008
41 Quantization Accuracy Simulations The comparison ofvarious errors between the proposed SPPC Booth multipliersand the ideal truncated Booth multiplier and other previousworks is listed in Table 6 These errors include the averageerror 120576mean maximum error 120576max and variance 120576var Inaccuracy simulation all the pair data samples are inputted toestimate the QE of the SPPC multiplier The 120576mean 120576max and120576var are defined as follows
120576mean = 119864 [119875 minus 119875119902]
120576max = max 10038161003816100381610038161003816119875 minus 119875119902
10038161003816100381610038161003816
120576var = 119864 [(119875 minus 119875119902)2
] minus (119864 [119875 minus 119875119902])2
(14)
where 119875 and 119875119902are the ideal product and the quantized
product of Booth multipliers respectively | sdot | and maxsdot arethe absolute and maximum operators respectively
The adaptive estimation methods in [9ndash11] have beenadopted to improve the truncation error Instead of exhaus-tive computing resource simulation methods in previousworks [9ndash11] the QE of SPPC multipliers is analyzed andderived from a simpler statistical method It is seen fromTable 6 that the proposed SPPC multipliers have almostthe best error performance compared with previous worksexcept [11] that has the highest performance of 120576mean Thereason is that it uses more information from Booth encoder
to alleviate the truncation errors [11] Nevertheless the areacost in [11] is increased from the extra information ofcompensation circuits Even though 120576max and 120576var of themultipliers in [13] are smaller than other multipliers their120576mean is larger compared with the proposed SPPC multiplierand multipliers in [10ndash12]
The distributions of QE have been calculated in differentmultipliersThe sample ratios of QE value (ie 120576) are listed inthe last three columns of Table 6 It is seen from the statisticalresults that the sample rations of |120576| lt 1 in the SPPC Boothmultipliers are higher than that in [9ndash11] by about 13 Onthe other hand this shows that the quantization accuracy ofthe proposed SPPCmultiplier is higher compared with thosefour methods
42 Performance Simulation A comparison of performancesbetween the proposed SPPC and previous works is imple-mented by using their own compensation circuitsMultiplierswith different widths are synthesized by Synopsys DesignCompiler using a standard cell library of TSMC 018120583mCMOS process Their area delay and power dissipation arelisted in Table 7
In general there exists a trade-off between the hardwareoverhead and the accuracy in these compensation circuitsThe multiplier proposed in [11] has the highest accuracy in120576mean but it has a larger area delay and power Howeverthe SPPC multiplier has the same area as the multipliers in[12 13] and lower area compared with the multipliers in [9ndash11] As a result the proposed SPPCmultipliers achieve higheraccuracy at the cost of the lower area
In order to comprehensively compare the performancesof different multipliers we consider their power-delay prod-ucts as the standard of comparisons which are listed in thelast column of the Table 7 It is shown that the power-delayproducts ofmultipliers proposed in [9ndash11] are larger than thatof other multipliers distinctly Compared with the other twomultipliers in [12 13] the proposed SPPC multipliers havebetter comprehensive performances
43 Verification in FIR Filter The QEC performance of theproposed SPPC is verified by means of a 20 taps low-passdirect form FIR filter The filter is designed to have 8MHzpass-band (with a 40MHz sampling frequency) and 70 dB
attenuation in the stop-band for a CR detector All the widthsof input output and coefficient of the FIR filter are 16 bitsand the internal adders of the FIR filter are 22 bits The inputfor test is a 5MHz sinusoidal signal with a sampling rate of40MHz
Four different multipliers (16 times 16 bits) including theSPPC multiplier and three other multipliers in [11ndash13] areinstantiated in the filter The error mean and error varianceof the output samples in different instantiated multipliers arelisted in Table 8 It is seen from Table 8 that the error meanof [11] is the smallest and the error mean of SPPC is better
than that of [12 13] whereas the error variance of SPPC is thesmallest These results are consistent with the QE accuracysimulation results in the previous section
In CR detectors it is very important to detect the signalrsquosspectral peak-values for determining whether the channelis idle [16] The relative errors of the average spectral peak-values (with 100 times of simulations)with respect to the idealspectral peak-values of the FIR filter outputs are listed in thelast column of Table 8 Table 8 shows that the spectral peak-values of the proposed SPPCmultiplier are closer to the idealpeak-value
By further dividing the minor truncated section of Boothmultiplier into the adaptive compensation and constantcompensation sections we rebuilt the adaptiveQEC for fixed-width multipliers According to the numbers of 1 in the
sequence of nonzero Booth recoding label we propose anew QEC method to generate the compensation carries Thesimulation results have shown that the QE of the SPPC issmaller compared with the existing methods The proposedQEC method and SPPC are useful for the DSP system with alarge width multipliers and higher precision requirements
8 VLSI Design
Table 7 Comparisons of performances with other methods
Width (bits) Multiplier Area (120583m2) Power (mW) Delay (ns) Power-delay product (mWsdotns)
The authors declare that there is no conflict of interestsregarding the publication of this paper
Acknowledgments
The authors gratefully acknowledge the support of ldquoSpecial-ized Research Fund for the Doctoral Program of Higher Edu-cationrdquo (Grant no 20120201120026) and ldquothe FundamentalResearch Funds for the Central Universitiesrdquo
References
[1] J M Jou S R Kuang and R D Chen ldquoDesign of low-errorfixed-width multipliers for DSP applicationsrdquo IEEE Transac-tions on Circuits and Systems II vol 46 no 6 pp 836ndash842 1999
[2] S-J Jou and H-H Wang ldquoFixed-width multiplier for DSPapplicationrdquo in Proceedings of the International Conference onComputer Design VLSI in Computers amp Processors (ICCD rsquo00)pp 318ndash322 Austin Texas USA September 2000
[3] Y-H Chen T-Y Chang and R-Y Jou ldquoA statistical error-compensated Booth multipliers and its DCT applicationsrdquo inProceedings of the IEEE Region 10 Conference (TENCON rsquo10) pp1146ndash1149 Fukuoka Japan November 2010
[4] M J Schulte and E E Swartzlander ldquoTruncated multiplicationwith correction constantrdquo in Proceedings of the IEEE Workshopon VLSI Signal Processing VI pp 388ndash396 Veldhoven TheNetherlands October 1993
[5] E J King and E E Swartzlander ldquoData-dependent truncatedscheme for parallel multiplicationrdquo in Proceedings of the 31stAsilo-mar Conference on Signals Systems amp Computers pp1178ndash1182 Pacific Grove Calif USA November 1997
[6] J E Stine and O M Duverne ldquoVariations on truncatedmultiplicationrdquo in Proceedings of the Euromicro Symposiumon Digital System Design pp 112ndash119 Belek-Antalya TurkeySeptember 2003
VLSI Design 9
[7] L-D Van and C-C Yang ldquoGeneralized low-error area-efficientfixed-width multipliersrdquo IEEE Transactions on Circuits andSystems I vol 52 no 8 pp 1608ndash1619 2005
[8] N Petra D De Caro V Garofalo E Napoli and A G MStrollo ldquoTruncated binary multipliers with variable correctionand minimum mean square errorrdquo IEEE Transactions on Cir-cuits and Systems I vol 57 no 6 pp 1312ndash1325 2010
[9] M-A Song L-DVan and S-Y Kuo ldquoAdaptive low-error fixed-width Booth multipliersrdquo IEICE Transactions on Fundamentalsof Electronics Communications and Computer Sciences vol 90no 6 pp 1180ndash1187 2007
[10] K-J Cho K-C Lee J-G Chung and K K Parhi ldquoDesignof low-error fixed-width modified booth multiplierrdquo IEEETransactions on Very Large Scale Integration (VLSI) Systems vol12 no 5 pp 522ndash531 2004
[11] J-PWang S-R Kuang and S-C Liang ldquoHigh-accuracy fixed-width modified booth multipliers for lossy applicationsrdquo IEEETransactions on Very Large Scale Integration (VLSI) Systems vol19 no 1 pp 52ndash60 2011
[12] Y-H Chen and T-Y Chang ldquoA high-accuracy adaptiveconditional-probability estimator for fixed-width Booth multi-pliersrdquo IEEE Transactions on Circuits and Systems vol 59 no 3pp 594ndash603 2012
[13] Y-H Chen C-Y Li and T-Y Chang ldquoArea-effective andpower-efficient fixed-width boothmultipliers using generalizedprobabilistic estimation biasrdquo IEEE Journal on Emerging andSelected Topics in Circuits and Systems vol 1 no 3 pp 277ndash2882011
[14] O L MacSorley ldquoHigh-speed arithmetic in binary computersrdquoProceedings of IRE vol 49 no 1 pp 67ndash91 1961
[15] G W Bewick Fast Multiplication Algorithms and Implementa-tion Stanford University Palo Alto Calif USA 1994
[16] R Tandra and A Sahai ldquoSNR walls for signal detectionrdquo IEEEJournal on Selected Topics in Signal Processing vol 2 no 1 pp4ndash17 2008
attenuation in the stop-band for a CR detector All the widthsof input output and coefficient of the FIR filter are 16 bitsand the internal adders of the FIR filter are 22 bits The inputfor test is a 5MHz sinusoidal signal with a sampling rate of40MHz
Four different multipliers (16 times 16 bits) including theSPPC multiplier and three other multipliers in [11ndash13] areinstantiated in the filter The error mean and error varianceof the output samples in different instantiated multipliers arelisted in Table 8 It is seen from Table 8 that the error meanof [11] is the smallest and the error mean of SPPC is better
than that of [12 13] whereas the error variance of SPPC is thesmallest These results are consistent with the QE accuracysimulation results in the previous section
In CR detectors it is very important to detect the signalrsquosspectral peak-values for determining whether the channelis idle [16] The relative errors of the average spectral peak-values (with 100 times of simulations)with respect to the idealspectral peak-values of the FIR filter outputs are listed in thelast column of Table 8 Table 8 shows that the spectral peak-values of the proposed SPPCmultiplier are closer to the idealpeak-value
By further dividing the minor truncated section of Boothmultiplier into the adaptive compensation and constantcompensation sections we rebuilt the adaptiveQEC for fixed-width multipliers According to the numbers of 1 in the
sequence of nonzero Booth recoding label we propose anew QEC method to generate the compensation carries Thesimulation results have shown that the QE of the SPPC issmaller compared with the existing methods The proposedQEC method and SPPC are useful for the DSP system with alarge width multipliers and higher precision requirements
8 VLSI Design
Table 7 Comparisons of performances with other methods
Width (bits) Multiplier Area (120583m2) Power (mW) Delay (ns) Power-delay product (mWsdotns)
The authors declare that there is no conflict of interestsregarding the publication of this paper
Acknowledgments
The authors gratefully acknowledge the support of ldquoSpecial-ized Research Fund for the Doctoral Program of Higher Edu-cationrdquo (Grant no 20120201120026) and ldquothe FundamentalResearch Funds for the Central Universitiesrdquo
References
[1] J M Jou S R Kuang and R D Chen ldquoDesign of low-errorfixed-width multipliers for DSP applicationsrdquo IEEE Transac-tions on Circuits and Systems II vol 46 no 6 pp 836ndash842 1999
[2] S-J Jou and H-H Wang ldquoFixed-width multiplier for DSPapplicationrdquo in Proceedings of the International Conference onComputer Design VLSI in Computers amp Processors (ICCD rsquo00)pp 318ndash322 Austin Texas USA September 2000
[3] Y-H Chen T-Y Chang and R-Y Jou ldquoA statistical error-compensated Booth multipliers and its DCT applicationsrdquo inProceedings of the IEEE Region 10 Conference (TENCON rsquo10) pp1146ndash1149 Fukuoka Japan November 2010
[4] M J Schulte and E E Swartzlander ldquoTruncated multiplicationwith correction constantrdquo in Proceedings of the IEEE Workshopon VLSI Signal Processing VI pp 388ndash396 Veldhoven TheNetherlands October 1993
[5] E J King and E E Swartzlander ldquoData-dependent truncatedscheme for parallel multiplicationrdquo in Proceedings of the 31stAsilo-mar Conference on Signals Systems amp Computers pp1178ndash1182 Pacific Grove Calif USA November 1997
[6] J E Stine and O M Duverne ldquoVariations on truncatedmultiplicationrdquo in Proceedings of the Euromicro Symposiumon Digital System Design pp 112ndash119 Belek-Antalya TurkeySeptember 2003
VLSI Design 9
[7] L-D Van and C-C Yang ldquoGeneralized low-error area-efficientfixed-width multipliersrdquo IEEE Transactions on Circuits andSystems I vol 52 no 8 pp 1608ndash1619 2005
[8] N Petra D De Caro V Garofalo E Napoli and A G MStrollo ldquoTruncated binary multipliers with variable correctionand minimum mean square errorrdquo IEEE Transactions on Cir-cuits and Systems I vol 57 no 6 pp 1312ndash1325 2010
[9] M-A Song L-DVan and S-Y Kuo ldquoAdaptive low-error fixed-width Booth multipliersrdquo IEICE Transactions on Fundamentalsof Electronics Communications and Computer Sciences vol 90no 6 pp 1180ndash1187 2007
[10] K-J Cho K-C Lee J-G Chung and K K Parhi ldquoDesignof low-error fixed-width modified booth multiplierrdquo IEEETransactions on Very Large Scale Integration (VLSI) Systems vol12 no 5 pp 522ndash531 2004
[11] J-PWang S-R Kuang and S-C Liang ldquoHigh-accuracy fixed-width modified booth multipliers for lossy applicationsrdquo IEEETransactions on Very Large Scale Integration (VLSI) Systems vol19 no 1 pp 52ndash60 2011
[12] Y-H Chen and T-Y Chang ldquoA high-accuracy adaptiveconditional-probability estimator for fixed-width Booth multi-pliersrdquo IEEE Transactions on Circuits and Systems vol 59 no 3pp 594ndash603 2012
[13] Y-H Chen C-Y Li and T-Y Chang ldquoArea-effective andpower-efficient fixed-width boothmultipliers using generalizedprobabilistic estimation biasrdquo IEEE Journal on Emerging andSelected Topics in Circuits and Systems vol 1 no 3 pp 277ndash2882011
[14] O L MacSorley ldquoHigh-speed arithmetic in binary computersrdquoProceedings of IRE vol 49 no 1 pp 67ndash91 1961
[15] G W Bewick Fast Multiplication Algorithms and Implementa-tion Stanford University Palo Alto Calif USA 1994
[16] R Tandra and A Sahai ldquoSNR walls for signal detectionrdquo IEEEJournal on Selected Topics in Signal Processing vol 2 no 1 pp4ndash17 2008
By further dividing the minor truncated section of Boothmultiplier into the adaptive compensation and constantcompensation sections we rebuilt the adaptiveQEC for fixed-width multipliers According to the numbers of 1 in the
sequence of nonzero Booth recoding label we propose anew QEC method to generate the compensation carries Thesimulation results have shown that the QE of the SPPC issmaller compared with the existing methods The proposedQEC method and SPPC are useful for the DSP system with alarge width multipliers and higher precision requirements
8 VLSI Design
Table 7 Comparisons of performances with other methods
Width (bits) Multiplier Area (120583m2) Power (mW) Delay (ns) Power-delay product (mWsdotns)
The authors declare that there is no conflict of interestsregarding the publication of this paper
Acknowledgments
The authors gratefully acknowledge the support of ldquoSpecial-ized Research Fund for the Doctoral Program of Higher Edu-cationrdquo (Grant no 20120201120026) and ldquothe FundamentalResearch Funds for the Central Universitiesrdquo
References
[1] J M Jou S R Kuang and R D Chen ldquoDesign of low-errorfixed-width multipliers for DSP applicationsrdquo IEEE Transac-tions on Circuits and Systems II vol 46 no 6 pp 836ndash842 1999
[2] S-J Jou and H-H Wang ldquoFixed-width multiplier for DSPapplicationrdquo in Proceedings of the International Conference onComputer Design VLSI in Computers amp Processors (ICCD rsquo00)pp 318ndash322 Austin Texas USA September 2000
[3] Y-H Chen T-Y Chang and R-Y Jou ldquoA statistical error-compensated Booth multipliers and its DCT applicationsrdquo inProceedings of the IEEE Region 10 Conference (TENCON rsquo10) pp1146ndash1149 Fukuoka Japan November 2010
[4] M J Schulte and E E Swartzlander ldquoTruncated multiplicationwith correction constantrdquo in Proceedings of the IEEE Workshopon VLSI Signal Processing VI pp 388ndash396 Veldhoven TheNetherlands October 1993
[5] E J King and E E Swartzlander ldquoData-dependent truncatedscheme for parallel multiplicationrdquo in Proceedings of the 31stAsilo-mar Conference on Signals Systems amp Computers pp1178ndash1182 Pacific Grove Calif USA November 1997
[6] J E Stine and O M Duverne ldquoVariations on truncatedmultiplicationrdquo in Proceedings of the Euromicro Symposiumon Digital System Design pp 112ndash119 Belek-Antalya TurkeySeptember 2003
VLSI Design 9
[7] L-D Van and C-C Yang ldquoGeneralized low-error area-efficientfixed-width multipliersrdquo IEEE Transactions on Circuits andSystems I vol 52 no 8 pp 1608ndash1619 2005
[8] N Petra D De Caro V Garofalo E Napoli and A G MStrollo ldquoTruncated binary multipliers with variable correctionand minimum mean square errorrdquo IEEE Transactions on Cir-cuits and Systems I vol 57 no 6 pp 1312ndash1325 2010
[9] M-A Song L-DVan and S-Y Kuo ldquoAdaptive low-error fixed-width Booth multipliersrdquo IEICE Transactions on Fundamentalsof Electronics Communications and Computer Sciences vol 90no 6 pp 1180ndash1187 2007
[10] K-J Cho K-C Lee J-G Chung and K K Parhi ldquoDesignof low-error fixed-width modified booth multiplierrdquo IEEETransactions on Very Large Scale Integration (VLSI) Systems vol12 no 5 pp 522ndash531 2004
[11] J-PWang S-R Kuang and S-C Liang ldquoHigh-accuracy fixed-width modified booth multipliers for lossy applicationsrdquo IEEETransactions on Very Large Scale Integration (VLSI) Systems vol19 no 1 pp 52ndash60 2011
[12] Y-H Chen and T-Y Chang ldquoA high-accuracy adaptiveconditional-probability estimator for fixed-width Booth multi-pliersrdquo IEEE Transactions on Circuits and Systems vol 59 no 3pp 594ndash603 2012
[13] Y-H Chen C-Y Li and T-Y Chang ldquoArea-effective andpower-efficient fixed-width boothmultipliers using generalizedprobabilistic estimation biasrdquo IEEE Journal on Emerging andSelected Topics in Circuits and Systems vol 1 no 3 pp 277ndash2882011
[14] O L MacSorley ldquoHigh-speed arithmetic in binary computersrdquoProceedings of IRE vol 49 no 1 pp 67ndash91 1961
[15] G W Bewick Fast Multiplication Algorithms and Implementa-tion Stanford University Palo Alto Calif USA 1994
[16] R Tandra and A Sahai ldquoSNR walls for signal detectionrdquo IEEEJournal on Selected Topics in Signal Processing vol 2 no 1 pp4ndash17 2008
The authors declare that there is no conflict of interestsregarding the publication of this paper
Acknowledgments
The authors gratefully acknowledge the support of ldquoSpecial-ized Research Fund for the Doctoral Program of Higher Edu-cationrdquo (Grant no 20120201120026) and ldquothe FundamentalResearch Funds for the Central Universitiesrdquo
References
[1] J M Jou S R Kuang and R D Chen ldquoDesign of low-errorfixed-width multipliers for DSP applicationsrdquo IEEE Transac-tions on Circuits and Systems II vol 46 no 6 pp 836ndash842 1999
[2] S-J Jou and H-H Wang ldquoFixed-width multiplier for DSPapplicationrdquo in Proceedings of the International Conference onComputer Design VLSI in Computers amp Processors (ICCD rsquo00)pp 318ndash322 Austin Texas USA September 2000
[3] Y-H Chen T-Y Chang and R-Y Jou ldquoA statistical error-compensated Booth multipliers and its DCT applicationsrdquo inProceedings of the IEEE Region 10 Conference (TENCON rsquo10) pp1146ndash1149 Fukuoka Japan November 2010
[4] M J Schulte and E E Swartzlander ldquoTruncated multiplicationwith correction constantrdquo in Proceedings of the IEEE Workshopon VLSI Signal Processing VI pp 388ndash396 Veldhoven TheNetherlands October 1993
[5] E J King and E E Swartzlander ldquoData-dependent truncatedscheme for parallel multiplicationrdquo in Proceedings of the 31stAsilo-mar Conference on Signals Systems amp Computers pp1178ndash1182 Pacific Grove Calif USA November 1997
[6] J E Stine and O M Duverne ldquoVariations on truncatedmultiplicationrdquo in Proceedings of the Euromicro Symposiumon Digital System Design pp 112ndash119 Belek-Antalya TurkeySeptember 2003
VLSI Design 9
[7] L-D Van and C-C Yang ldquoGeneralized low-error area-efficientfixed-width multipliersrdquo IEEE Transactions on Circuits andSystems I vol 52 no 8 pp 1608ndash1619 2005
[8] N Petra D De Caro V Garofalo E Napoli and A G MStrollo ldquoTruncated binary multipliers with variable correctionand minimum mean square errorrdquo IEEE Transactions on Cir-cuits and Systems I vol 57 no 6 pp 1312ndash1325 2010
[9] M-A Song L-DVan and S-Y Kuo ldquoAdaptive low-error fixed-width Booth multipliersrdquo IEICE Transactions on Fundamentalsof Electronics Communications and Computer Sciences vol 90no 6 pp 1180ndash1187 2007
[10] K-J Cho K-C Lee J-G Chung and K K Parhi ldquoDesignof low-error fixed-width modified booth multiplierrdquo IEEETransactions on Very Large Scale Integration (VLSI) Systems vol12 no 5 pp 522ndash531 2004
[11] J-PWang S-R Kuang and S-C Liang ldquoHigh-accuracy fixed-width modified booth multipliers for lossy applicationsrdquo IEEETransactions on Very Large Scale Integration (VLSI) Systems vol19 no 1 pp 52ndash60 2011
[12] Y-H Chen and T-Y Chang ldquoA high-accuracy adaptiveconditional-probability estimator for fixed-width Booth multi-pliersrdquo IEEE Transactions on Circuits and Systems vol 59 no 3pp 594ndash603 2012
[13] Y-H Chen C-Y Li and T-Y Chang ldquoArea-effective andpower-efficient fixed-width boothmultipliers using generalizedprobabilistic estimation biasrdquo IEEE Journal on Emerging andSelected Topics in Circuits and Systems vol 1 no 3 pp 277ndash2882011
[14] O L MacSorley ldquoHigh-speed arithmetic in binary computersrdquoProceedings of IRE vol 49 no 1 pp 67ndash91 1961
[15] G W Bewick Fast Multiplication Algorithms and Implementa-tion Stanford University Palo Alto Calif USA 1994
[16] R Tandra and A Sahai ldquoSNR walls for signal detectionrdquo IEEEJournal on Selected Topics in Signal Processing vol 2 no 1 pp4ndash17 2008
[7] L-D Van and C-C Yang ldquoGeneralized low-error area-efficientfixed-width multipliersrdquo IEEE Transactions on Circuits andSystems I vol 52 no 8 pp 1608ndash1619 2005
[8] N Petra D De Caro V Garofalo E Napoli and A G MStrollo ldquoTruncated binary multipliers with variable correctionand minimum mean square errorrdquo IEEE Transactions on Cir-cuits and Systems I vol 57 no 6 pp 1312ndash1325 2010
[9] M-A Song L-DVan and S-Y Kuo ldquoAdaptive low-error fixed-width Booth multipliersrdquo IEICE Transactions on Fundamentalsof Electronics Communications and Computer Sciences vol 90no 6 pp 1180ndash1187 2007
[10] K-J Cho K-C Lee J-G Chung and K K Parhi ldquoDesignof low-error fixed-width modified booth multiplierrdquo IEEETransactions on Very Large Scale Integration (VLSI) Systems vol12 no 5 pp 522ndash531 2004
[11] J-PWang S-R Kuang and S-C Liang ldquoHigh-accuracy fixed-width modified booth multipliers for lossy applicationsrdquo IEEETransactions on Very Large Scale Integration (VLSI) Systems vol19 no 1 pp 52ndash60 2011
[12] Y-H Chen and T-Y Chang ldquoA high-accuracy adaptiveconditional-probability estimator for fixed-width Booth multi-pliersrdquo IEEE Transactions on Circuits and Systems vol 59 no 3pp 594ndash603 2012
[13] Y-H Chen C-Y Li and T-Y Chang ldquoArea-effective andpower-efficient fixed-width boothmultipliers using generalizedprobabilistic estimation biasrdquo IEEE Journal on Emerging andSelected Topics in Circuits and Systems vol 1 no 3 pp 277ndash2882011
[14] O L MacSorley ldquoHigh-speed arithmetic in binary computersrdquoProceedings of IRE vol 49 no 1 pp 67ndash91 1961
[15] G W Bewick Fast Multiplication Algorithms and Implementa-tion Stanford University Palo Alto Calif USA 1994
[16] R Tandra and A Sahai ldquoSNR walls for signal detectionrdquo IEEEJournal on Selected Topics in Signal Processing vol 2 no 1 pp4ndash17 2008
