Design and Verification of Model of Neural Networks

using SystemVerilog School of Engineering , SFSU

Research Advisor -: Dr. Hamid Mahmoodi

Graduate Student :- Prashis Raghuwanshi

Neuron Model

Plasticity and Weight In our Neuron Model, different Neurons are getting connected to form Neural Networks. The weights of different Neurons gets added . The plasticity of Neurons is increased if new connection is made. The plasticity of Neurons is decreased if connection is lost. The addition of plasticity is the “Memory” for our Brain Model System

Ganglion Cell

● A type of Neuron located near the Inner Surface of the Retina of an eye

● Ganglion Cell transmits Images from Retina in form of action potential to several regions of the midbrain.

● In Verilog Model , Ganglion cell is used for setting orientation for edge detection.

Hubel and Weisel’s Complex Cell Model

Verification Flow

INTERFACE

TOP LEVEL

FPGA Board Cyclone 3

FPGA Cyclone 3 Altera

● 256 megabits (Mb) of DDR SDRAM

● 1 megabyte (MB) of synchronous SRAM

● 16 MB of Intel P30/P33 flash memory

Why we need functional verification?

To build confidence and stay in business. A primary purpose for functional verification is to detect failures so that bugs can be identified and

corrected before it gets shipped to costumer. If RTL designer makes a mistake in designing or coding, this results as a bug in the Chip. If this bug is executed, in certain situations the system will produce

wrong results, causing a failure. Not all mistakes will necessarily result in failures. The bug in the dead code will never result in failure. A single mistake may result in a wide range of failure symptoms. Not all bugs are caused by coding errors. There are possibilities that error may in the specification itself.

Sometimes miscommunications between teams may lead to wrong design.

System Verilog Model

Findings in Research

Convolutional Neural Networks

Neuron Model Specifications

● Multiple synapses are Inputs to the Neuron and one axon signal for the neuron output

● All Inputs to the Neuron are digital pulses and take values 0 or 1 ● in the Design , Different Neurons have different number of Integers ● The threshold is set to 12 bit value

Neuron Model

● Synapses Inputs are added together in Sum Threshold block

● When the sum of all integration values from all the inputs reach a preset threshold, the neuron sends a pulse to the output

● A Threshold value is preset . If Synapse Input is greater than the set Threshold value ,Neuron is Fired

Building Basic Testbenches in Verilog

DUT SpecificationsNEURON - : IT has Ten Input Ports

Neuron Line Type -: It has four Input ports

Neuron_Eighteen -: It has Eighteen Input Ports .

Ganglion_Cell -: Complex cell used for Edge Detection

Top Level File -: itp_Controller.v

Inputs -: clock , Reset_n

Neuron

NeuronLine Type

Neuron Eighteen

Systemverilog Verification Approach ● Building Directed Testbench for Ganglion Cell in SystemVerilog ● Building Directed Testbench for Simple Cell in Systemverilog● Building Directed Testbench for Neuron ● Building Directed Testbench for Neuron Line Type● Building Directed Testbench for Neuron Eighteen ● Random Stimulus Generation● Building Random Testbench for Neuron ● Building Random Testbench for Neuron Line Type● Building Random Testbench for Neuron EIghteen

Self Checking Model ● Building new model of Self checking for DUT’s involving Ganglion Cell ● Repeating self check for 1000 times to check every aspect of the DUT

Functional Coverage Approach● Defining number of bins for auto bins for uniform distribution ● Defining manual bins to cross verify the Functional Coverage