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Integrated Systems Laboratory

Eidgen ssische Technische Hochschule Z rich

Microelectronics Design Center

Swiss Federal Institute of Technology Zurich

Research Review 2002

W. Fichtner Q. Huang H. Kaeslin N. Felber D. Aemmer

2

Cover Image:

Microchip Design by Students

The cover image shows the photomicro-

graph of an Integrated Circuit (IC) that has

been developed by a student at the Integrat-

ed Systems Laboratory of ETH Zurich. With

the background of the 6

th

-term lecture

VLSI I: Architectures of Highly Integrated

Circuits on

specification, formulation in a

hardware description language (VHDL), and

verification of the behavior of a chip, he start-

ed the project (see page 118). The task, in

this case formulated by assistants of the lab-

oratory, was to design an Application-Specif-

ic Integrated Circuit (ASIC) which will serve

as demonstration object in the 5

th

-term prac-

tical that aims at motivating students for

studies in VLSI (page 116). A video image fil-

ter chip has been chosen since beyond the

design aspects, it is also well suited to dem-

onstrate functionality. Programmable filter

characteristics enable undergraduates to ex-

periment with working ICs.

During his 7

th

semester the student designer

realized the chip in his first term project. The

lecture

VLSI II: Design of Highly Integrated

Circuits

provided the know-how for the whole

design flow. Thanks to the perfect tool sup-

port by the Microelectronics Design Center

and the professional help by the assisting

PhD students of the laboratory a full design flow becomes possible during the 14 weeks of the winter term with

50% regular working time (but often with some additional nights!). All student chips have been fabricated in

austriamicrosystems 0.6

μ

m CMOS technology on the

same wafer (see figure above).

In the summer term 2002 the prototype silicon has been

successfully tested by the design student in the exercis-

es of the course

VLSI III: Fabrication and Verification of

Highly Integrated Circuits

. This step has completed his

experience of the whole ASIC development process.

A printed circuit board has then been realized which en-

ables the chip to process the digital video signals of the

CCD camera (see figure to the left). The small connec-

tor on this board is a serial computer interface through

which the filter characteristics can be loaded onto the

ASIC.

The integrated circuit designed by an EE student will

now be used by many undergraduates to learn how

VLSI chips work. A more detailed description of the chip

can be found on page 95 of this report.

Address of the Laboratory:

Integrated Systems Laboratory Phone: +41 1 632 42 68ETH Zentrum, ETZ Fax: +41 1 632 11 94Gloriastrasse 35 e-mail: [email protected] Z rich www: http://www.iis.ee.ethz.chSwitzerland

Plot of all student chips of the winter semester 2001/02. They are arranged

as for fabrication on the wafer, on the so-called reticle. It measures 17 mm by

19 mm. The placement allows to saw the differently sized chips on this mul-

tichip module by horizontal and vertical cuts. The cover shows the photo-

graph of the image filtering ASIC positioned on top-left on this reticle.

Commercial CCD camera board with daughter PCB on top

which contains the image filtering chip developed by a student.

3

Contents

Preface 7

Organization 10

Representative Figures 11

Staff 14

Former PhD Students 16

Academic Guests 22

Partners and Funding Agencies 24

Awards and Patents 34

History of the Integrated Systems Laboratory (IIS) 35

Research Projects:IC and System Design and Test 39

A MIMO-Extended UMTS Receiver 40

Real-Time MIMO OFDM Testbed 40

Runtime-Reconfigurable System on Chip (SoC) for Multimedia Data Processing 41

All-Digital Standardcell-Based Audio Sample Clock Synthesis 41

Multi-Point Interconnects for Globally-Asynchronous Locally-Synchronous Systems 42

Testability of GALS Modules 42

Self-Calibrating Oscillators for GALS 43

OSCAR: Integration of 24 Oscillators for GALS 43

Testbed for GALS Multi-Point Interconnects 44

Variable-Delay Adder 44

IRRQ Testing, a Replacement for IDDQ Testing of Deep-Submicron CMOS Technologies 45

Tightly Coupled Coprocessor for General-Purpose Processors in Network Applications 45

Research Projects:Analog and Mixed-Signal Design 47

UMTS Transmit I/Q Modulator in 0.12

μ

m CMOS 48

Baseband Circuits for Direct Conversion UMTS Mobile Receiver 48

LNA and I/Q Demodulator for UMTS Receiver 49

Carrier Leakage Suppression in Direct-Conversion WCDMA Transmitters 49

Integrated Transmitter Architectures 50

Broadband D/A Converters for Telecommunications Applications 50

A High-Speed 14-bit D/A Converter with Background Calibration 51

Multi-Standard Baseband Sigma-Delta A/D Converter 51

Broadband, Low-Oversampled

ΣΔ

A/D Converter for Telecommunications Applications 52

A High-Speed Folding and Interpolation Analog-to-Digital Converter 52

A 4GHz 0.18

μ

m CMOS Integer-N Frequency Synthesizer 53

10 GHz Voltage-Controlled Oscillator and Prescaler 53

Research Projects:Technology CAD 55

Mobility in DGSOI MOSFETs 56

Revised SRH Lifetimes for Quantum Transport Modeling 56

Monte Carlo Simulation and Measurement of Nanoscale nMOSFETs 57

Quasi-Exciton Densities in Bulk Silicon at Room Temperature 57

4

Simulation of Quantum Ballistic Transport in Nano-Devices 58

Physical Model Interface Based Noise Simulation in BJTs 58

A Posteriori Error Indicators for Device Simulation 59

Construction of Isosurfaces 59

Anisotropic Meshing in 3D 60

Coupled Electro-Optical 3D Simulation of a Tunable Multisection DBR Laser 60

Importing Tabulated Gain Data Into a Laser Device Simulator 61

Improved Quantum-Mechanical Calculations for Laser Simulations 61

Thermodynamic Laser Simulation Including Heat-Sink and Packaging 62

Confirmation of Thermal Roll-Off Models in Laser Simulations 62

Spectral Portrait of VCSEL Eigenmodes 63

A Comprehensive VCSEL Device Simulator 63

TCAD Based Design of VCSELs 64

Simulation of Energy Band Profiles for PIN Photodetector Structure 64

Simulation of Infrared Quantum-Well Photodetectors 65

Photodetector Simulation with Ray-Trace Generated Optical Absorption 65

Simulation of Tunable Air-Gap Filters 66

Development of a Drift-Diffusion Solver with the Kinetic Monte Carlo Method 66

Arsenic Activation and Deactivation in Heavily Doped Silicon 67

Vacancy Mediated Arsenic Diffusion in Silicon 67

Ab Initio Molecular Dynamics Simulation of the Self-Interstitial in Silicon 68

Parallel Incomplete LU-Factorization on Shared Memory Multiprocessors 68

Research Projects:Physical Characterization 69

Compact Modeling of Integrated Power Semiconductor Modules 70

Electrothermal Simulation of IGBT Devices for Automotive Applications 70

Theoretical and Experimental Accuracy in Delineating the Electrical Junction by SCM 71

Imaging of Deep-Submicrometer Bipolar Devices by Scanning Capacitance Microscopy 71

Quantitative Dopant Profiling in Silicon Carbide by Scanning Capacitance Microscopy 72

Simulation and Design of Silicon Test Structures for Very High Temperatures 72

Investigation of VCSEL Temperature Profiles Using Scanning Thermal Microscopy 73

Optimization of Substrate Contact Placement in Smart Power ICs 73

Device Simulation of Immunity Test Transients in Automotive Applications 74

Device Simulation and Backside Laser Interferometry in ESD Protection Development 74

Research Projects:Bio—Electromagnetics and Electromagnetic Compatibility 75

Development and Improvement of Recipes for Head and Body Tissue Simulating Liquids 76

Risk Assessment: Dosimetry of Exposure Systems for Toxicity/Carcinogenicity Studies in Rats 76

Risk Assessment: Detailed Dosimetry of TEM Cell Exposure Setup for

In Vitro

Studies 77

Risk Assessment: Dosimetry of the RF Circular-Waveguide Setup for

In Vivo

Studies 77

Improved Methodology for Base Station Site Evaluation 78

Full Wave Time Domain Simulation of a VCSEL in Three Dimensions 78

Comparative Analysis of Anatomical Head Phantoms for the Compliance Testing of MTE 79

Analysis of the Numerical Properties of the FDTD Algorithm at Dielectric Material Interfaces 79

Modeling of Advanced Antenna Applications Using FDTD Simulations 80

RF Characterization of MTE Using a Combined NF Measurement-Simulation Toolset 80

Improved Modeling of Thin PEC Sheets in the FDTD Method 81

Simulation of Temperature Increase in Brain Tissues During Usage of Mobile Phones 81

Development of a Novel FD Quasi-Static Solver for Low Frequency Applications 82

Risk Assessment: TA Project Pervasive Computing 82

Risk Assessment: Exposure Setup for Studies of Acute Effects on Mice at 900MHz 83

Standards: Scaling of Exposures from Animal to Human 83

Pilot Study Time-Domain Field Sensors 84

Risk Assessment: GSM Exposure System for Tox./Car. Study at RCC, ARCS, Zhejiang Univ. 84

Risk Assessment: RF Induced Thermal Threshold Measurements in Rodents 85

Risk Assessment: Development of an

In Vitro

Exposure Setup for 835MHz and 935MHz 85

Risk Assessment: Development of an

In Vitro

Exposure Setup for UMTS 86

5

Temperature Distributions Inside Cell Cultures Exposed to EMF

In Vitro 86

Characterization of a Novel High-Resolution Temperature Probe 87

Effects of RF EMF Exposure on Sleep EEG and Regional Cerebral Blood Flow 87

Education Program:Student Projects 89

Rijndael Crypto Chip Realization 91

Serpent Crypto Chip Realization 91

Adaptive Arithmetic Coder ASIC 92

Source Coding for Bio-Medical Signals 92

Smart Sensors on the LIN Local Interconnect Network 93

FFT-Based Digital Audio Equalizer 93

PIC 16C5X 8-bit Microcontroller 94

Java Virtual Machine Coprocessor ASIC 94

Real-Time Video Image Filter 95

OIF — SPI-5 Receiver 95

Runtime-Reconfigurable Arithmetical Logical Unit 96

CDMA MIMO Frontend 96

Pseudo-Random Number Generator 97

Low-Power, Low-Frequency Digital Transceiver 97

Low-Power GPS Radio-Frequency Front-End in 0.18

μ

m CMOS 98

Design of a 200MHz Frequency Synthesizer 98

Sigma-Delta Audio D/A-Converter 99

Sigma-Delta Audio D/A-Converter 99

Fast Comparator for the Application in an Analog-to-Digital Converter 100

3D-DCT Video Compression System 100

FFT-Based Digital Audio Crossover Network for Loudspeakers 101

LED Floodlight with Electronically Controlled Color Characteristics 101

PCI-FPGA Board for D/A Converter Modulator Prototype 102

Encrypted Audio Compact Disk 102

Audio Data Transmission over Firewire 103

Acoustic Communication 103

Quantum-Well Laser Gain Calculations using High-Order k¥p Methods 104

2D Optical Simulation of Vertical-Cavity Lasers with Step-Index Apertures 104

Lifetime Prediction Models and Thermal Transient Analysis of Power Semiconductor Devices 105

Thermo-Electric Modeling and Simulation of IGBT Modules for Automotive Applications 105

PhD Theses — Abstracts 106

Diploma Theses — Overview 110

Student Theses — Overview 111

Microelectronics Design Center (DZ) 112

Joint Research Cooperation with IT IS 114

Workshops and Courses 115

Education at IIS — Overview 116

Lectures 118

IC Design Projects — Overview 122

Research Projects — Overview 124

Presentations 131

6

Publications 137

Technical Reports 143

Design, Electronic Test, and Physical Characterization Equipment 144

Computer Equipment 148

7

Preface

Introduction

This is a report on the academic and research

activities of the Integrated Systems Laboratory (IIS)

and the Microelectronics Design Center (DZ) at the

Department of Information Technology and Electri-

cal Engineering (D-ITET) of the Swiss Federal Insti-

tute of Technology in Zurich (ETH Zurich) for the

year 2002.

The IIS staff includes two professors, five research

associates, nine post docs, forty six (46) PhD stu-

dents, three computer system administrators, three

secretaries, and five technicians.

Research topics in digital, mixed, and analog inte-

grated circuit (IC) design range from sensitive sen-

sor interfaces to GHz RF circuits on the analog

side, over analog-to-digital converters to the digital

field covering projects from low-power design meth-

odologies to complex systems-on-a-chip (SoC).

Technology CAD (TCAD), technology and device

development, characterization, and bio-electro-

magnetics complement the research fields of IIS

towards professional tools for modeling and opti-

mizing micro-electronic and opto-electronic devices

in the deep-submicron and nanometer range as

well as micro-systems and bio-electromagnetic

systems.


The Microelectronics Design Center, headed by

Dr. H. Kaeslin, with four staff members, is a service

organization of the Department of Information

Technology and Electrical Engineering. It is closely

co-operating with IIS and other D-ITET and ETH

Zurich laboratories in their design research and

teaching activities for VLSI, analog, and system

electronics (see page 112).

Research Projects and Funding

Following the trends of earlier years, our co-opera-

tion with national and international partners is at the

center of our activities. In 2002 one new European

(funded by BBW, Swiss Federal Office for Educa-

tion and Science), two new KTI (Swiss Commission

for Technology and Innovation), one new industrial,

and two new research projects funded by ETH Zur-

ich have started in the fields of semiconductor pro-

cess and device development and simulation,

complex digital systems on chip, and sensitive ana-

log circuits. Overall, IIS was involved in a total of 39

research projects. Nine of them were EU projects

funded by BBW, eleven by KTI, three by ETH Zur-

ich, two by SNF, four by TOP NANO 21, and eleven

by industry in Switzerland, Europe, USA, and

Japan.

A total of 47 job positions at IIS was financed by

third-party projects, which, in relation to the 21 ETH

positions, and in comparison with other laboratories

of ETH Zurich, is a sign of the quality of research

performed by our staff.

PhD Students

In 2002, six PhD students finished their doctoral

thesis successfully. IIS offers an excellent and

highly stimulating research environment that per-

mits PhD students to work on very attractive topics

and, nevertheless, to finish their thesis in a compar-

atively short time. However, it is still an ambitious

challenge to find very qualified PhD students from

all over the world. We try the best to overcome this

situation by an appropriate salary policy and by

focusing the student activities on scientific work in

order to reduce the administrative and educational

overhead.

Analog and Mixed Signal Group

For the Analog and Mixed Signal Group of

Prof. Huang, the year 2002 has shown a continua-

tion of work around the group s focus in the field of

RF and base-band circuit design for telecommuni-

cations applications. An international, EU-funded

project on the realization of UMTS transceivers in

most advanced CMOS technology has been suc-

cessfully completed. The transceiver uses modern,

direct-up and down-conversion architectures for

transmitter and receiver, respectively, and achieves

very low power consumption due to thorough opti-

mization throughout all levels of design and single-

chip implementation. The project has led to three

ISSCC publications, one in 2002 and two in 2003.

Low power consumption is also a key element of

the group s two other publications at ISSCC 2002,

representing the variety of subjects studied. The

first is a quadrature demodulator suitable for GSM

or UMTS receiver applications with excellent per-

formance, and the other presents a complete Delta-

Sigma based A/D converter for ADSL-type wireline

applications at the lowest power consumption

achieved for its bandwidth and resolution. The

group s experience in CMOS RF circuit design has

also been transferred to an advanced level course

open to electrical engineering students and engi-

neers from industry, giving them the opportunity to

learn about these recent developments.

IC and System Design and Test Group

The digital design group started a research collabo-

ration between the Communication Theory Group

(Prof. Helmut B lcskei) of the Communication

Technology Laboratory (IKT-ETHZ) in the field of

multiple-antenna (MIMO) mobile communications

8

systems. Despite the rather critical financial situa-

tion this strategic project gets funding by ETH.

While following a different technical approach it

supplements well the project with Lucent Wireless

Research that has been extended for another year.

The VLSI research for multimedia systems led to a

highly efficient processor with realtime-reconfig-

urable hardware units that will provide adequate

signal processing power and networking support in

several second-generation multimedia chips of the

research partner Bridgeco AG. The design method-

ology for Globally-Asynchronous Locally-Synchro-

nous (GALS) systems on chips could be

supplemented by new bus interconnect topologies,

flexible local oscillators, and an enhanced tool suite

for inclusion of testable asynchronous modules.

Technology CAD Group

TCAD has been a main research area in our labo-

ratory. During the last year, a broad range of activi-

ties led to interesting results in the fields of ultra-

small electronic devices, optoelectronic devices,

first-principle mechanical modeling, mesh genera-

tion, and linear solvers. Activities in the Nano

Device Modeling Group focused on the study of

quantum and ballistic effects in ultra-small elec-

tronic devices. In an attempt to apply the quantum-

drift-diffusion (QDD) model to direct tunneling

through potential barriers it could be shown that

observed negative differential resistance is a spuri-

ous effect in any case. The effect of 1D quantiza-

tion on generation-recombination rates was studied

and the necessary modifications in the QDD model

were derived. Double-gate SOI MOSFETs were

simulated with a quantum-mechanical mobility

model revealing the conditions for the desired

mobility enhancement. Our single-electron simula-

tor SIMNAD was further improved. Excellent agree-

ment between simulated and measured

conductance of GaAs split-gate quantum point con-

tacts was shown. The influence of strongly corre-

lated (excitonic) two-particle states on the band gap

and the transport properties of bipolar devices has

been investigated by means of a many-body

Green s function technique, which is also used in

the development of a bulk mobility model incorpo-

rating electron-electron and electron-hole scatter-

ing effects. Single-particle Monte Carlo simulations

were iteratively coupled with the nonlinear Poisson

equation resulting in stable and efficient self-con-

sistent simulations at the high doping levels typical

for contemporary MOSFETs. Good agreement with

measured drain currents of nanoscale MOSFETs

from Toshiba Inc. was achieved without any param-

eter fitting. In June 2002, the new Monte Carlo sim-

ulator SPARTA was included in the release 8.0 of

ISE Integrated Systems Engineering AG. Further-

more, Monte Carlo simulations of nanoscale

strained-silicon MOSFETs were performed. From

the found anisotropy of in-plane transport it could

be concluded that the on-current is influenced by

quasi-ballistic effects. Monte-Carlo generated

transport parameters were applied in device simu-

lation via the Physical Model Interface of DESSIS

and device noise simulation far from equilibrium is

now possible based on Monte-Carlo generated RF

noise sources.

Activities in process simulation at atomic level con-

centrated on developing diffusion models, with

charged defects and clusters, capable of explaining

deactivation phenomena. The energy levels of

point defects and various dopant-defect clusters

were determined with ab initio techniques. Ab initio

molecular dynamics was also used for calculating

defect diffusivities. In addition, a combination

between the binary collision approximation and the

kinetic Monte Carlo method is under development

for the simulation of ion implantation.

The mesh generator noffset3d was constructed

around the normal offsetting algorithm, which

allows the construction of anisotropic mesh layers

at material interfaces. A new development allows

the construction of anisotropic layers at isosurfaces

(implicitly defined surfaces). For example, pn-junc-

tions can be refined anisotropically by this method.

The goal of a general anisotropic mesh generator is

not yet reached but many examples in process and

device simulation can be handled.

A new iterative linear solver has been developed

and parallelized for shared memory processors to

solve more robustly and efficiently large scale prob-

lems in semiconductor device simulation. The auto-

matic grid generation and adaptation module for

the device simulator has been extended by imple-

menting faster error indicators and more advanced

smoothing techniques for device operating condi-

tions with large avalanche generation.

Optoelectronics Modeling Group

A fundamental challenge in the accurate simulation

of modern semiconductor optoelectronic devices is

the self-consistent solution of the optical field

including the dependence of the refractive index on

temperature and carrier density. Examples include

the modeling of vertical-cavity surface-emitting

lasers (VCSELs) in operating condition (where ther-

mal lensing changes the optical near and far field),

or the 3D simulation of tunable edge-emitting

lasers. To achieve the coupled simulation, an opti-

cal mode solver on a finite-element basis has been

integrated into the device simulator DESSIS in a

way that allows for a repeated solution of the opti-

cal field. As a result, continuous-wave VCSEL oper-

ation can be simulated including thermal roll-off.

Furthermore, since the photon life time of individual

cavity modes can be obtained by the optical mode

solver, the simulator can be used to optimize mode

discrimination, which is an important design objec-

tive in industrial VCSEL development.

9

Physical Characterization Group

In the physical characterization group further

progress has been made in the characterization of

pn junctions by Scanning Capacitance Microscopy

(SCM). The interpretation and the quantification of

complex SCM spectra has been assisted by exten-

sive physical simulation of the measurement pro-

cess in 2D and 3D. The atomic force microscope

has been upgraded to enable Scanning Spreading

Resistance Microscopy mapping. Innovative self-

heating and optically heated test structures have

been designed and integrated to characterize the

fundamental physical parameters of silicon at tem-

peratures up to 1000K. The design has been opti-

mized by physical simulation with the scope to

reduce the impact of spurious effects such as the

thermal carrier generation. Considerable progress

has been made in the field of the reliability assess-

ment and prediction of power devices for automo-

tive applications. New physical models and new

extraction procedures have been successfully

developed in conjunction with major car manufac-

turers worldwide.

Bio-Electromagnetics Group

IT IS, the Foundation for Research on Information

Technologies in Society (headed by ETH adjunct

Prof. Niels Kuster), a non-profit research institution

supported by ETH Zurich, established its scientific

and technical work in close collaboration with our

laboratory. The research activities of IT IS are in the

domain of the interaction of electromagnetic radia-

tion with biological organisms, and in advanced

measurement equipment for electromagnetic radia-

tion. A growing number of research projects and

PhD students at IIS is funded by the global wireless

communications industry, several governmental

agencies, and the Commission of the European

Union. It turned out that this collaboration with IT IS

is very fruitful and a benefit for both institutions (see

page 114).

Education

Next to research, teaching occupies a central role

in our activities. Our staff is responsible for several

core lectures in the Electrical Engineering and

other departments (see page 118). The chapter on

student projects (page 89) gives an overview on

the manifold diploma theses and term projects.

While most of these student theses are in the field

of IC design, some hardware and software activi-

ties are included as well. Some outstanding stu-

dents have been encouraged to submit papers to

the

36th Asilomar Conference On Signals, Systems

And Computers

, to the

13th European Symposium

on Reliability of Electron Devices, Failure Physics

and Analysis

, and to the

International Conference

on Numerical Simulation of Semiconductor Opto-

electronic Devices

, which were all accepted and

have been presented by the students themselves.

Events

The second International Conference on Numeri-

cal Simulation of Semiconductor Optoelectronic

Devices NUSOD-02 from 25—27 September 2002

was organized by IIS and carried out at ETH Zur-

ich. Prof. Joachim Piprek (UC Santa Barbara, USA)

and Prof. Wolfgang Fichtner acted as conference

chairmen. Despite the economic situation in world-

wide optoelectronics industry, 111 participants from

Europe, USA, and Japan attended this new confer-

ence. 13 invited talks by well known experts from

USA and Europe, 19 regular talks, 10 posters, and

5 company presentations were given and estab-

lished a platform for further scientific and technical

collaborations between academia and industry.

Prof. Fichtner is currently Head of the Department

of Information Technology and Electrical Engineer-

ing, and he was reelected to hold this position until

the end of September 2005.

Partners and Funding Agencies

The activities of our laboratory were only possible

through the support from the governing board of

our university, and several national and interna-

tional institutions and industrial parties. Special

thanks go to our school, to the computing services

of ETH Zurich, as well as to the Department of

Information Technology and Electrical Engineering

and its services and administration.

Finally, we would like to express our gratitude to the

Swiss Commission for Technology and Innovation

(KTI), the Swiss National Science Foundation

(SNF), the Swiss Federal Office for Education and

Science (BBW), the Swiss program TOP NANO 21,

and the Commission of the European Union for

their financial support. Just as much we would like

to thank our partners ABB Switzerland, austriami-

crosystems Austria, Avalon Photonics Switzerland,

Bernafon Switzerland, Bosch Germany, BridgeCo

Switzerland, EPFL Switzerland, FNM Switzerland,

Fraunhofer-Gesellschaft Germany, Fujitsu Japan,

German Government Germany, IBM Research

R schlikon Switzerland, IMEC Belgium, Infineon

Germany, INRIA France, ISE Integrated Systems

Engineering AG Switzerland, IT IS Foundation

Switzerland, Lucent Technologies USA, Motorola

USA, Bookham Switzerland, NTT Japan, Opto

Speed Switzerland, Philips Semiconductors Zurich

Switzerland, Siemens Germany, SIGMA C Ger-

many, SPEAG Switzerland, ST Microelectronics

Italy and France, Toshiba Japan, Toyota Japan,

Technical University Wien Austria, University of

Bologna Italy, University of California Santa Bar-

bara USA, University of Linz Austria, University of

Pisa Italy, WIAS Germany, and the ETH Zurich lab-

oratories IBT, IFH, IKT, IWR, and TIK for the fruitful

cooperation in research projects as well as for their

financial support.

10

Org

an

izatio

n

11

Representative Figures

Staff

Number of full job positions at the Integrated Systems Laboratory from 1993 to 2002.

PhD Theses

Number of completed PhD theses per year at the Integrated Systems Laboratory from 1993 to 2002.

Abstracts of PhD theses 2002: see page 106.

12

Journal and Book Publications

Number of journal and book publications by the Integrated Systems Laboratory from 1993 to 2002.

References: see page 137.

Conference and Workshop Presentations

Number of conference and workshop presentations by the Integrated Systems Laboratory from 1993 to

2002. References: see page 131.

13

IIS Research Projects

Number of research projects with external funding at the Integrated Systems Laboratory from 1993 to

2002. Overview of research projects: see page 124. Partners and funding agencies: see page 24.

Research Partners of IIS

CH Europe USA Japan Others World

Industry 12 19 1 4 0 36

Academia 10 27 1 0 1 39

Research partners of the Integrated Systems Laboratory in Switzerland (CH), Europe, and worldwide.

Addresses of partners: see page 24.

14

Staff

Professors

Fichtner Wolfgang, Dr., Professor for Electronics, Head since 1 Sept 1985

Huang Qiuting, Dr., Professor for Electronics since 1 Jan 1993


Kaeslin Hubert, Dr., Dipl. El.-Ing. ETH, Head since 1 Jan 1986

Br ndli Matthias, Dipl. El.-Ing. ETH since 1 May 2001

Camarero Francisco, Dipl. Ing. since 12 June 2002

Haldemann Richard, Dipl. El.-Ing. ETH 1 July 1998 — 31 Mar 2002

K ppel Rudolf, FEAM since 1 Apr 1995

Scientific Staff

Aemmer D lf, Dr., Dipl. Phys. ETH, Senior Scientist since 1 Sept 1985

Alonso Eduardo, Dr., Industrial Engineer since 1 July 2000

Balmelli Pio, Dipl. El.-Ing. ETH since 1 Apr 1998

Barlini Davide, Electronic Eng. since 1 Oct 2002

Benkler Stefan, Dipl. Rech. Wiss. ETH since 15 Oct 2002

B sch Thomas, Dipl. El.-Ing. ETH since 1 Apr 2000

Brenna Gabriel, Dipl. El.-Ing. ETH since 1 Mar 2000

Brugger Simon, Dipl. El.-Ing. ETH since 1 Mar 2000

Bufler Fabian, Dr., Dipl.-Phys. since 1 Nov 1997

Burg Andreas, Dipl. El.-Ing. ETH since 6 Nov 2000

Burger Thomas, Dr., Dipl. El.-Ing. ETH since 1 Oct 1994

Carbognani Flavio, Telecommunications Eng. since 1 Dec 2002

Chavannes Nicolas, Dr., Dipl. El.-Ing. ETH 14 Apr 1998 — 28 Feb 2002

Chen Xinhua, M. Sc. EE since 1 Sept 2001

Cherubini Emilio, Dipl. Phys. ETH 8 Jan 2001 — 30 Apr 2002

Chevtchenko Serguei, Eng.-Phys. 1 Aug 2001 — 31 Dec 2002

Christ Andreas, Dipl.-Ing. der Nachrichtentechnik 1 Oct 1999 — 30 Nov 2002

Ciappa Mauro, Dr., Dipl.-Phys. since 1 Jan 1998

Corvasce Chiara, Dipl.-Phys. since 8 Apr 2002

Deiss Armin, Dr., Dipl. El.-Ing. ETH 15 Feb 1997 — 30 June 2002

Ebert Sven, Dipl.-Phys. since 15 May 2000

Eom Sang Jin, M. Sc. EE since 3 July 2002

Felber Norbert, Dr., Dipl. Phys. ETH, Senior Scientist since 1 July 1987

Francese Pier-Andrea, Dipl. El.-Ing. since 1 Sept 2000

Futter Peter, M. Sc. EE since 26 Aug 2002

Geelhaar Frank, Dipl.-Phys. since 1 Oct 1998

Glaser Ulrich, Dipl.-Phys. since 1 Oct 2002

Glass Boris, Dipl.-Phys. 1 Mar 1998 — 30 Apr 2002

G rkaynak Frank, Dipl. El.-Ing. since 15 Sept 2000

H ne Simon, Dipl. El.-Ing. ETH since 1 June 2002

Hammerschmied Clemens, Dr., Dipl. El.-Ing. ETH since 1 June 1994

Heinz Frederik, Dipl. Phys. ETH since 25 Apr 2000

Hertle J rgen, Dipl. Ing. Elektrotechnik since 2 Mar 1998

H hr Tim, Dipl.-Phys. since 15 Mar 2001

Jacob Biju, Dr., MTech. since 1 Sept 2002

Kouchev Ilian, M. of Science since 1 Sept 2000

Krause Jens, Dipl.-Phys. since 1 Nov 1997

Laino Valerio, Electrical Eng. since 1 Oct 2002

Martelli Chiara, Dipl. El.-Ing. since 17 Jan 2001

M ller Christoph, Dipl. Phys. ETH since 1 June 2000

Nikoloski Neviana, M. Sc. Engineering Physics since 15 Nov 2002

Oesch Walter, Dipl. Natw. ETH since 15 Aug 2000

Oetiker Stephan, Dipl. Informatik-Ing. ETH since 1 May 2001

15

Oila Kari, M. Sc. (Mech. Eng.) since 13 Aug 2001

Perels, Dipl. El.-Ing. ETH since 1 Feb 2001

Pfaff Dirk, Dipl. El.-Ing. ETH since 1 Mar 1997

Pfeiffer Michael, Dipl.-Phys. since 1 Oct 1999

Pomp Andreas, Dr., Dipl. Math. 1 Jan 1999 — 30 Apr 2002

Pontarolo Gianpaolo, Dipl. El.-Ing. ETH since 1 Mar 2002

Reutemann Robert, Dipl. El.-Ing. ETH since 15 Jan 1998

Rogin J rgen, Dipl. El.-Ing. ETH since 1 Apr 1999

R llin Stefan, Dipl. Math. ETH since 1 Apr 2000

Roth Eric, Dipl. El.-Ing. ETH since 5 Apr 2000

Sahli Beat, Dipl.-Phys. since 1 June 2000

Schaldach Markus, Dipl.-Ing. since 1 Mar 2000

Schenk Andreas, PD, Dr., Dipl.-Phys. since 1 Aug 1991

Schenkel Michael, Dr., Dipl. El.-Ing. ETH 1 Mar 1999 — 31 Dec 2002

Schmith sen Bernhard, Dr., Dipl.-Mathematiker since 27 May 1996

Schneider Lutz, Dipl. Phys. ETH since 7 May 2001

Schuderer J rgen Rudolf, Dipl.-Phys. since 1 Oct 1999

Stangoni Maria, Dipl. El.-Ing. since 15 Feb 2001

Streiff Matthias, Dipl. El.-Ing. ETH since 7 Feb 2000

Tschopp David, Dipl. El.-Ing. ETH since 1 May 1999

Villiger Thomas, Dipl. El.-Ing. ETH since 1 May 1998

Witzig Andreas, Dr., Dipl. El.-Ing. ETH since 1 Aug 1997

Zehnder Oliver, Dipl. Phys. ETH since 1 Nov 2002

Computer Staff

B hm Anja, Dipl. Geologie since 1 Apr 2001

Richardet Christoph, Oberstufenlehrer since 10 May 2000

Wicki Christoph, Dipl. El.-Ing. ETH since 1 Oct 1985

Technical Staff

Balmer Christoph, Dipl. El.-Ing. HTL since 1 Aug 1989

Gisler Hansj rg, Industriespengler (80%) since 1 Sept 1989

Illien Fritz, Dipl. El.-Ing. HTL since 1 May 1998

Mathys Hanspeter, Elektromonteur since 15 Dec 1990

Rheiner Rudi, Dipl. El.-Ing. HTL since 15 Nov 1996

Administrative Staff

Boksberger Margit (60%) since 1 Jan 2000

Fischer Bruno, Dipl. El.-Ing. HTL since 14 Apr 1992

Haller Christine, Betriebs konom HWV (95%) since 8 Mar 1993

Plank Eva (50%) since 1 July 1998

Roffler Verena (50%) since 1 Sept 1999

16

Former PhD Students

Name Degree Now with

received

Bach Carlo 1993 Interstaatliche Hochschule f r Technik (NTB)

Werdenbergstrasse 4

CH-9470 Buchs, Switzerland

Basedau Philipp 1999 Philips Semiconductors AG

Binzstrasse 44

CH-8045 Z rich, Switzerland

Bonnenberg Heinz 1993 Micronas Munich GmbH

Frankenthalerstrasse 2

D-81539 M nchen, Germany

B rgler Josef 1990 Hochschule Technik+Architektur Luzern

Technikumstrasse 21

CH-6048 Horw, Switzerland

Burger Thomas 2002 Integrated Systems Laboratory

ETH Z rich


Chavannes Nicolas 2002 IT IS Foundation

Zeughausstrasse 43


Ciampolini Lorenzo 2001 9, Rue de Dr. Mazet

F-38000 Grenoble, France

Ciappa Mauro 2000 Integrated Systems Laboratory

ETH Z rich


Conti Paolo 1991 esmertec ag

CFO & Head HR

Lagerstrasse 14

CH-8600 D bendorf, Switzerland

Curiger Andreas 1993 Omnisec AG

Rietstrasse 14

CH-8108 D llikon, Switzerland

Deiss Armin 2002 Microtune, Inc.

2201 10th Street

Plano, TX 75074, USA

Dettmer Hartmut 1994 Infineon Technologies

AI IP DD LV 1

Balanstrasse 73


Doswald Daniel 2000 ATI Research GmbH

Moosstrasse 18B

D-82319 Starnberg, Germany

Eicher Simon 1996 ABB Semiconductors AG

R&D Lb2

Fabrikstrasse 3

CH-5600 Lenzburg, Switzerland

17

Esmark Kai 2001 Infineon Technologies

DAT LIB TI-ESD/Latch-up

Postfach 80 17 09


Fillo Marco 1993 Quadrics Supercomputers World Ltd.

Via Marcellina 11

I-00131 Roma, Italy

Gappisch Steffen 1996 Philips Semiconductors AG

Binzstrasse 44


Garreton Gilda 1998 UBS AG, Stamford Branch

Washington Boulevard 677

Stamford, CT 06901, USA

Gull Ronald 1996 BridgeCo AG

Ringstrasse 14


Hager Christian 2000 McKinsey & Company

Alpenstrasse 3


Hammerschmied Clemens 2000 Integrated Systems Laboratory

ETH Z rich


Heeb Hansruedi 1989 esmertec ag

CEO

Lagerstrasse 14


Heiser Gernot 1991 School of Computer Science & Engineering

University of New South Wales

P.O. Box 1

Sydney, 2052 NSW, Australia

Herkersdorf Andreas 1991 IBM Zurich Research Laboratory

S umerstrasse 4

CH-8803 R schlikon, Switzerland

Herrigel Alexander 1990 R3 Security Engineering AG

Z richstrasse 151

CH-8607 Aathal-Seegr ben, Switzerland

Heusler Lucas 1990 IBM Zurich Research Laboratory

S umerstrasse 4


Hitschfeld Nancy 1993 Departamento de Ciencias de la Computaci n

Universidad de Chile

Blanco Encalada 2120

Santiago, Chile

H fler Alexander 1997 Motorola, Inc.

6501 West William Cannon Drive

Mail Drop OE341

Austin, TX 78735, USA

Humbel Oliver 2000 ABB Semiconductors AG

Produktion Lb2

Fabrikstrasse 3

CH-5600 Lenzburg, Switzerland

18

Kells Kevin 1994 179 Capital Lane

Roseburg, OR 97470, USA

K rner Thomas 1999 ABB Business Services Ltd.

SLE-I Intellectual Property

Brown Boveri Strasse 6

CH-5400 Baden, Switzerland

Krause Jens 2001 Integrated Systems Laboratory

ETH Z rich


Krumbein Ulrich 1996 Infineon Technologies

WS SD D TrMOS

Postfach 80 09 49


Kuratli Christoph 1999 Bernafon Ltd.

IC-Design

Morgenstrasse 131

CH-3018 Bern, Switzerland

Lamb Peter 1990 55 Gilbert ST

Hackett 2602

Canberra, Australia

Lendenmann Heinz 1994 ABB Corporate Research

Dept. G

SE-721 78 V ster s, Sweden

Leonhardt G tz 2000 Sun Microsystems, Inc.

901 San Antonio Road

M/S USUN02-301

Palo Alto, CA 94303-4900, USA

Liegmann Arno 1995 R ti 18

CH-8357 Guntershausen, Switzerland

Litsios James 1996 Actant AG

Bahnhofstrasse 10

CH-6300 Zug, Switzerland

Menolfi Christian 2000 IBM Zurich Research Laboratory

S umerstrasse 4


Mergens Markus 2001 Sarnoff Corporation

201 Washington Road CN-5300

Princeton, NJ 08543-5300, USA

M ller Stephan 1994 371 Maeve Court

San Jose, CA 95136, USA

Muttersbach Jens 2001 Philips Semiconductors AG

R ffelstrasse 29

8045 Z rich, Switzerland

Neeracher Matthias 1998 Apple Computer, Inc.

MS 301-3KM

1 Infinite Loop

Cupertino, CA 95014, USA

19

Nussbaum Miguel 1988 Departamento de Ciencia de la Computaci n

Escuela de Ingenier a

Universidad Cat lica de Chile

Santiago, Chile

Oberle Michael 2002 miromico ag

Technoparkstrasse 1


Omura Ichiro 2001 Toshiba Corp. Semiconductor Comp.

Discrete Semiconductor Division

1, Komukai Toshiba-cho, Saiwai-ku

Kawasaki 212-8583, Japan

Orsatti Paolo 2000 NemeriX SA

Stabile Gerre 2000

Casella postale 425

CH-6928 Manno, Switzerland

Pf ffli Paul 1999 Fellenbergstrasse 71

CH-9000 St. Gallen, Switzerland

Piazza Francesco 2000 NemeriX SA

Stabile Gerre 2000

Casella postale 425

CH-6928 Manno, Switzerland

Pommerell Claude 1992 CH-I Information Technology

ABB (Switzerland) Ltd.

Brown Boveri Strasse 6

CH-5400 Baden, Switzerland

R wer Thomas 2000 IBM T. J. Watson Research Center

P.O. Box 218

Yorktown Heights, NY 10598, USA

Rogenmoser Robert 1996 Broadcom Corporation

Broadband Processor Business Unit

2451 Mission College Boulevard

Santa Clara, CA 95054, USA

Rothacher Fritz 1995 Infineon Technologies

WS BB D CR FE2

P.O. Box 80 09 49


R hl Roland 1992 PDF Solutions, Inc.

333 West San Carlos Street


Ryter Roland 1996 Philips Semiconductors AG

Binzstrasse 44


Schenk Olaf 2000 University Basel

Department of Computer Science

Klingelbergstrasse 50

CH-4056 Basel, Switzerland

Schenkel Michael 2002 ISE Integrated Systems Engineering AG

Balgriststrasse 102


20

Schmith sen Bernhard 2001 Integrated Systems Laboratory

ETH Z rich


Sch nb chler Edgar 1998 Wallsten Medical SA

Avenue Riond-Bosson 14

CH-1110 Morges, Switzerland

Scholze Andreas 2000 Integrated Systems Engineering, Inc.

111 North Market Street, Suite 710


Schuster Christian 2000 IBM T. J. Watson Research Center

P.O. Box 218

Yorktown Heights, NY 10598, USA

Seda Steven 1993 Zurich Financial Services

Mythenquai 2


Stadler Manfred 2000 BridgeCo AG

Ringstrasse 14


Stricker Andreas 2000 IBM Microelectronics

MS 972C, 1000 Riverstreet

Essex Junction, VT 05452, USA

Thalmann Markus 2000 BridgeCo AG

Ringstrasse 14


Villablanca Luis 2000 Synopsys, Inc.

48371 Fremont Boulevard

Fremont, CA 94538, USA

von Arx Christoph 1996 cva technical consulting ag

Geissfluhweg 30

CH-4600 Olten, Switzerland

Wassner J rgen 2001 Schmid Telecom AG

Binzstrasse 35


Westermann Marc 1995 Logismata AG

Hardturmstrasse 76


Wettstein Andreas 2000 ISE Integrated Systems Engineering AG

Balgriststrasse 102


Wikstr m Tobias 2000 ABB Corporate Research AB

Dept. D

S-721 78 V ster s, Sweden

Witzig Andreas 2002 Integrated Systems Laboratory

ETH Z rich


Witzigmann Bernd 2000 Ortel — A Division of Emcore

2015 West Chestnut Street

Alhambra, CA 91803-1542, USA

21

Yun Chan-Su 2000 Integrated Systems Engineering, Inc.



Zahir Rumi 1991 428 Glenwood Avenue

Menlo Park, CA 94025, USA

Zelenka Stefan 2001 Integrated Systems Engineering, Inc.



Zimmermann Reto 1997 Synopsys, Inc.

2025 NW Cornelius Pass Road

Hillsboro, OR 97124, USA

22

Academic Guests

H. Yabuhara Toshiba Corporation, Yokohama, Japan 1 Jan — 15 Mar 2002

G. Coquery INRETS, Paris, France 15 Jan 2002

Dr. P. Dovano FIAT, Turin, Italia 15 Jan 2002

F. Lecoq Renault, Paris, France 15 Jan 2002

Dr. N. Seliger Siemens AG, Munich, Germany 15 Jan 2002

Prof. Dr. W. Eckhard Siemens AG, Munich, Germany 15 Jan 2002

Dr. K. G rtner WIAS, Berlin, Germany 4 Feb — 5 Feb 2002

Dr. O. Schenk Department of Computer Science, Basel, Switzerland 20 Feb 2002

Dr. J. Reiner EMPA, D bendorf, Switzerland 22 Feb 2002

Dr. Y. Yamada Toyota Central R&D Labs. Inc., Aichi, Japan 20 Mar 2002

T. Hoeren XPEQT NV, Tessenderlo, Belgium 2 Apr 2002

Prof. Dr. R. Castello University of Pavia, Pavia, Italy 5 Apr 2002

Dr. A. Herkersdorf IBM Research Center, R schlikon, Switzerland 18 Apr 2002

Dr. M. T. Asom SyChip, Warren, NJ, USA 24 Apr 2002

G. J. Barber SyChip, Warren, NJ, USA 24 Apr 2002

Dr. K. Sun SyChip, Warren, NJ, USA 24 Apr 2002

K. Hamada Toyota Motor Corporation, Aichi, Japan 24 Apr 2002

B. Jacob University of Sheffield, Sheffield, Great Britain 21 May — 22 May 2002

Dr. E. Lyumkis Integrated Systems Engineering, Inc.,

San Jose, CA, USA 30 May 2002

Dr. Prott Universit t Kassel, Kassel, Germany 24 June 2002

T. Hori Kanematsu Electronics Ltd., Tokyo, Japan 26 June — 27 June 2002

Dr. K. Shirai Toshiba Corporation, Yokohama, Japan 26 June — 27 June 2002

Dr. S. Takagi Toshiba Corporation, Yokohama, Japan 26 June — 27 June 2002

T. Yoshida Kanematsu Electronics LTD, Tokyo, Japan 26 June — 27 June 2002

Dr. Y. Yamada Toyota Central R&D Labs. Inc., Aichi, Japan 4 July 2002

T. Kojima Toyota Central R&D Labs. Inc., Aichi, Japan 4 July — 10 July 2002

T. F llenbach Fraunhofer Institut, Sankt Augustin, Germany 15 July — 16 July 2002

Dr. K. St ben Fraunhofer Institut, Sankt Augustin, Germany 15 July — 16 July 2002

Dr. S. Takagi Toshiba Corporation, Yokohama, Japan 16 July 2002

Dr. A. Herkersdorf IBM Research Center, R schlikon, Switzerland 13 Aug 2002

Dr. Ch. Heer Infineon Technologies, Munich, Germany 30 Aug 2002

T. Sekiguchi Hitachi Ltd., Tokyo, Japan 1 Sept — 31 Dec 2002

Prof. H. Reddy California State University, Long Beach, CA, USA 9 Sept 2002

Dr. P.-L. Yeh Realtek Corporation, Taipei, Taiwan 10 Sept 2002

23

F. R mer Universit t Kassel, Kassel, Germany 10 Sept — 27 Sept 2002

M. Eatherton Robert Bosch GmbH, Reutlingen, Germany 18 Sept 2002

Dr. W. Wilkening Robert Bosch GmbH, Reutlingen, Germany 18 Sept 2002

D. M ller CADENCE Design Systems, Munich, Germany 20 Sept 2002

K. Sigl CADENCE Design Systems, Munich, Germany 20 Sept 2002

Dr. O. Penzin Integrated Systems Engineering, Inc.,

San Jose, CA, USA 30 Sept 2002

Dr. R. Raschke Fujitsu Ltd., Kawasaki, Japan 4 Oct 2002

Dr. Y. Watanabe Fujitsu Ltd., Kawasaki, Japan 4 Oct 2002

Prof. J. Katzenelson Technion, Israel Institute of Technology, Haifa, Israel 1 Oct — 31 Dec 2002

Dr. M. Moser Avalon Photonics, Zurich, Switzerland 9 Oct 2002

Prof. Dr. Y.-M. Wan I-Shou University, Ta Hsu Hsiang, Taiwan 21 Oct — 25 Oct 2002

B. Sadigh Lawrence Laboratory, Livermore, CA, USA 6 Nov — 8 Nov 2002

J. Lorenz Fraunhofer Institut, Erlangen, Germany 7 Nov 2002

K. Hirakawa Toshiba Corporation, Kawasaki, Japan 8 Nov 2002

H. Takada ISE Japan Ltd., Tokyo, Japan 8 Nov 2002

T. Hori ISE Japan Ltd., Tokyo, Japan 8 Nov 2002

Dr. H. Yoshimura Toshiba Corporation, Yokohama, Japan 13 Nov 2002

Dr. A. Stricker IBM Microelectronics Division,

Essex Junction, VT, USA 20 Nov — 21 Nov 2002

Dr. K. Esmark Infineon Technologies, Munich, Germany 28 Nov 2002

Dr. H. Gossner Infineon Technologies, Munich, Germany 28 Nov 2002

Dr. W. Stalder Infineon Technologies, Munich, Germany 28 Nov 2002

Dr. W. Wilkening Robert Bosch GmbH, Reutlingen, Germany 2 Dec 2002

Ch. U-Hyeong Ministry of Information and Communication, Seoul,

Republic of Korea 13 Dec 2002

Prof. Dr. S.-G. Lee Information and Communications University, Daejeon,


K. Seog-Jun Ministry of Information and Communication, Seoul,


Prof. Dr. S.-O. Park University of Information and Communications, Daejeon,


Prof. Dr. G.-W. Yoon University of Information and Communications, Daejeon,


S. Centoni Stanford University, Stanford, CA, USA 16 Dec — 19 Dec 2002

24

Partners and Funding Agencies

ABB Corp. Research

ABB Corporate Research Ltd.

Segelhof

CH-5405 D twil AG

Switzerland

ABB Semiconductors

ABB Semiconductors AG

Fabrikstrasse 3

CH-5600 Lenzburg

Switzerland

AMUW Wien

Universit tsklinik f r Innere Medizin IV

Klinische Abteilung Arbeitsmedizin

W hringer G rtel 18—20

A-1090 Wien

Austria

Ansaldo

Ansaldo Transporti SpA

Ingegneria Divisione Veicoli

Via Nuove delle Brecce 260

I-80147 Napoli

Italy

austriamicrosystems

austriamicrosystems AG

Schloss Premst tten

A-8141 Unterpremst tten

Austria

Avalon

Avalon Photonics

Badenerstrasse 569

CH-8048 Z rich

Switzerland

BBT

Bundesamt f r Berufsbildung und Technologie

(Federal Office for Professional Education and Technology,

a Swiss Government Agency)

Effingerstrasse 27

CH-3003 Bern

Switzerland

BBW

Bundesamt f r Bildung und Wissenschaft

(Federal Office for Education and Science,


Wildhainweg 9

CH-3001 Bern

Switzerland

Bernafon

Bernafon AG

Morgenstrasse 131

CH-3018 Bern

Switzerland

BfS

Bundesamt f r Strahlenschutz

Willy-Brandt-Strasse 5

D-38226 Salzgitter

Germany

Bookham

Bookham (Switzerland) AG

Binzstrasse 17

CH-8045 Z rich

Switzerland

25

Bosch

Robert Bosch GmbH

T binger Strasse 123

D-72703 Reutlingen

Germany

and

Robert Bosch GmbH

Wernerstrasse 1

D-70442 Stuttgart

Germany

BridgeCo

BridgeCo AG

Ringstrasse 14

CH-8600 D bendorf

Switzerland

CNR-IMETEM

Consiglio Nationale di Metodologie e Tecnologie per la Microelettronica

(IMETEM)

Stradale Primosole 50

I-95121 Catania

Italy

CRF

Centro Ricerche Fiat SCpA

Strada Torino 50

I-10043 Orbassano

Italy

Elektrovac

Electrovac Fabrikation Elektrotechnischer Spezialartikel GmbH

Zentrale Forschung und Entwicklung

Aufeldgasse 37—39

A-3400 Klosterneuburg

Austria

ENSCPB Talence

Ecole Nationale Sup rieure de Chimie et de Physique de Bordeaux

Avenue Pey Berland

F-33405 Talence

France

EPFL Ecole Polytechnique F d ral Lausanne

(Swiss Federal Institute of Technology Lausanne)

CH-1002 Lausanne

Switzerland

ETHZ Eidgen ssische Technische Hochschule Z rich

(Swiss Federal Institute of Technology Z rich)

ETH Zentrum

CH-8092 Z rich

Switzerland

EU-GROWTH Community Research in the Fifth Framework Programme

Competitive and sustainable growth (GROWTH) of the European Union.

EU-IST Community Research in the Fifth Framework Programme

User-friendly information society (IST) of the European Union.

EU-QUAL Community Research in the Fifth Framework Programme

Quality of life and management of living resources (QUAL) of the

European Union.

EU-RTN Community Research in the Fifth Framework Programme

Improving human research potential and the socio-economic knowledge

base: Research Training Networks (RTN) of the European Union.

26

EUPEC EUPEC GmbH

Max-Planck-Strasse 5

D-59581 Warstein

Germany

Ferraz Ferraz Date Industries S.A.

Les Revoulins — Route de St-Honore

F-38350 La Mure

France

FhG-IIS-B Fraunhofer-Institut f r Integrierte Schaltungen

Bauelementetechnologie

Schottkystrasse 10

D-91058 Erlangen

Germany

FNM Forschungskoperation Nachhaltiger Mobilfunk

c/o Institut f r Feldtheorie und H chstfrequenztechnik

(Laboratory for Electromagnetic Fields and Waves)

ETH Z rich

Gloriastrasse 35

CH-8092 Z rich

Switzerland

Fujitsu Fujitsu Laboratories Ltd.

10-1, Morinosato-Wakamiya

Atsugi 243-01

Japan

and

Fujitsu Laboratories of Europe Ltd.

Hayes Park Central

Hayes End Road

Hayes, Middlesex UB4 8FE

United Kingdom

HERCULAS Consortium CNR-IMETEM, Catania (Italy)

HMI, Berlin (Germany)

IHP, Frankfurt (Germany)

IMEC, Leuven (Belgium)

KTH, Kista (Sweden)

Philips Nederland, Eindhooven (The Netherlands)

ST Crolles, Crolles (France)

TAU, Ramat Aviv (Israel)

Uni Hamburg, Hamburg (Germany)

HIMRATE Consortium Ansaldo, Napoli (Italy)

CRF, Orbassano (Italy)

Electrovac, Klosterneuburg (Austria)

EUPEC, Warstein (Germany)

Ferraz, La Mure (France)

INTRETS, Arcueil (France)

Regienov, Guyancourt (France)

Siemens M nchen, M nchen (Germany)

TU M nchen, M nchen (Germany)

TU Wien, Wien (Austria)

HMI Hahn-Meitner-Institut Berlin GmbH

Glienicker Strasse 100

D-14019 Berlin

Germany

27

IBM Research IBM Research Laboratory

S umerstrasse 4

CH-8803 R schlikon

Switzerland

IFH-ETHZ Institut f r Feldtheorie und H chstfrequenztechnik

(Laboratory for Electromagnetic Fields and Waves)

ETH Z rich

Gloriastrasse 35

CH-8092 Z rich

Switzerland

IFBH Hannover Institut f r Biophysik

Universit t Hannover

Herrenh userstrasse 2

D-30419 Hannover

Germany

IHP Institute for Semiconductor Physics (IHP)

Walter-Korsing-Strasse 2

D-15230 Frankfurt (Oder)

Germany

IIS-ETHZ Integrated Systems Laboratory

ETH Z rich

Gloriastrasse 35

CH-8092 Z rich

Switzerland

(i.e. the publisher of this Research Review 2002 )

IKT-ETHZ Institut f r Kommunikationstechnik

(Laboratory for Communication Technology)

ETH Z rich

Sternwartstrasse 7

CH-8092 Z rich

Switzerland

IMEC Interuniversity Microelectronics Centre

Kapeldreef 75

B-3001 Leuven

Belgium

Infineon Infineon Technologies AG

Otto-Hahn-Ring 6

D-81730 M nchen

Germany

and

Infineon Technologies AG

Balanstrasse 73

D-81609 M nchen

Germany

and

Infineon Technologies AG

St. Martin-Strasse 53

D-81541 M nchen

Germany

INRETS Institut National de Recherche sur les Transport et leur S curuit

2, Avenue du G n ral Malleret-Joinville

F-94114 Arcueil

France

28

INRIA Institute National de Recherche en Informatique et Automatique

BP 105 Domaine de Voluceau

F-78153 Le Chesnay

France

IPK Gatersleben Institut f r Pflanzengenetik und Kulturpflanzenforschung Gatersleben

Correnstrasse 3

D-06466 Gatersleben

Germany

ISE AG ISE Integrated Sysems Engineering AG

Balgriststrasse 102

CH-8008 Z rich

Switzerland

and

ISE Integrated Systems Engineering Inc.

111 North Market Street

Suite 710

San Jose CA 95113

USA

IT IS IT IS Foundation for Research on Information Technologies in Society

ETHZ VAW Geb ude

Gloriastrasse 37/39

CH-8006 Z rich

Switzerland

and

IT IS Foundation for Research on Information Technologies in Society

Zeughausstrasse 43

CH-8004 Z rich

Switzerland

IT IS Partners ARCS, Seibersdorf (Austria)

ARIB, Tokyo (Japan)

CiS, Gen ve (Switzerland)

Ericsson, Stockholm (Sweden)

EMPA, D bendorf (Switzerland)

GSM-Association, Gen ve (Switzerland)

IMTEK, Freiburg (Germany)

IfW, St. Gallen (Switzerland)

IPT-UNIZH, Z rich (Switzerland)

IZT, Berlin (Germany)

MMF, Brussels (Belgium)

Motorola, Ft. Lauderdale (USA)

Nortel, Harlow (UK)

TA-SWISS, Bern (Switzerland)

Zhejiang University, Hangzhou (China)

IWR-ETHZ Institut f r Wissenschaftliches Rechnen

(Institute for Scientific Computing)

ETH Z rich

Haldeneggsteig 4

CH-8092 Z rich

Switzerland

KTH Kungl Tekniska H gskolan

Department of Electronics — Laboratory of Semiconductor Materials

Isafjordsgatan 22—26

S-16440 Kista

Sweden

29

KTI Kommission f r Technologie und Innovation

(Commission for Technology and Innovation,


Effingerstrasse 27

CH-3003 Bern

Switzerland

Lucent Lucent Technologies

Wireless Research Department

791 Holmdel-Keyport Road

Holmdel, NJ 07733-400

USA

MATH-ETHZ Forschungsinstitut f r Mathematik

(Research Institute for Mathematics)

ETH Z rich

R mistrasse 101

CH-8092 Z rich

Switzerland

MEDEA+ MEDEA+

and

German Bundesministerium f r Bildung und Forschung

Germany

MPG Stuttgart Max-Planck-Institut f r Festk rperforschung

Heisenbergstrasse 1

D-70565 Stuttgart

Germany

NTT Nippon Telegraph and Telephone Corporation

3-1, Otemachi 2-Chome, Chiyoda-Ku

Tokyo 100-8116

Japan

Opto Speed Opto Speed AG

Moosstrasse 2

CH-8803 R schlikon ZH

Switzerland

PERFORM A Consortium Partners of the research project PERFORM A — In Vivo Research on Possible

Health Effects Related to Mobile Telephones and Base Stations

FhG-ITA, Hannover (Germany)

RCC, Ittingen (Switzerland)

ARCS, Seibersdorf (Austria)

RBM, Colleretto Giacosa (Italy)

IT IS, Z rich (Switzerland)

RCL/AUTH, Thessaloniki (Greece)

PERFORM B Consortium PIOM, Bordeaux (France)

ENEA, Cassacia (Italy)

NRPB (CYTO), Oxon (United Kingdom)

NRPB (NIR), Oxon (United Kingdom)

UKU, Kuopio (Finland)

ULP, Strasbourg (France)

Philips Belgium Philips Research Leuven

Interleuvenlaan 74—76

B-3001 Leuven

Belgium

Philips Nederland Philips Electronics Nederland B.V.

Professor Holstlaan 4

NL-5656 AA Eindhoven

The Netherlands

30

Philips Zurich Philips Z rich AG, Semiconductors

Binzstrasse 44

CH-8045 Z rich

Switzerland

PSI PSI Paul Scherrer Institut

CH-5332 Villingen

Switzerland

REFLEX Consortium AMUW Wien, Wien (Austria)

ENSCPB Talence, Talence (Belgium)

IFBH Hannover, Hannover (Germany)

IPK Gatersleben, Gatersleben (Germany)

STUK Helsinki, Helsinki (Finland)

UKFB Berlin, Berlin (Germany)

UMIL Milano, Milano (Italy)

Uni Bologna, Bologna (Italy)

VERUM, M nchen (Germany)

VERYC Madrid, Madrid (Spain)

Regienov Regienov — Renault Recherche et Innovation

1, Avenue du Golf

F-78288 Guyancourt

France

Siemens M nchen Siemens AG

Otto-Hahn-Ring 6

D-81730 M nchen

Germany

SIGMA C SIGMA C GmbH

Rosenheimer Landstrasse 74

D-85521 Ottobrunn

Germany

SNF Swiss National Science Foundation

Wildhainweg 20

CH-3012 Bern

Switzerland

SPEAG Schmid & Partner Engineering AG

Zeughausstrasse 43

CH-8004 Z rich

Switzerland

ST Agrate ST Microelectronics

Via Carlo Olivetti 2

20041 Agrate Brianza (MI)

Italy

ST Crolles ST Microelectronics

850 rue Jean Monnet

F-38921 Crolles

France

ST Gentilly ST Microelectronics

937 Avenue Gallieni

F-94253 Gentilly

France

STUK Helsinki STUK — Radiation and Nuclear Safety Authority

Laippatie 4

FIN-00880 Helsinki

Finland

31

TAU Tel-Aviv University (TAU)

Department of Physical Electronics

Tel-Aviv University, Ramat Aviv

IL-69978 Israel

TDC TDC Switzerland AG

Thurgauerstrasse 60

CH-8050 Z rich

Switzerland

TIK-ETHZ Institut f r Technische Informatik

(Computer Engineering and Network Laboratory)

ETH Z rich

Gloriastrasse 35

CH-8092 Z rich

Switzerland

TOP NANO 21 Swiss Technology Oriented Program NANO 21

Universit t Basel

Institut f r Physik


CH-4056 Basel

Switzerland

and

Themas AG

Egnacherstrasse 69

CH-9320 Arbon

Switzerland

Toshiba Toshiba Corporation

1-1, Shibaura 1-chome, Minato-ku

Tokyo 105-8001

Japan

and

Toshiba Corporation

2-5-1, Kasama, Sakae-ku

Yokohama 247-8585

Japan

and

Toshiba Corporation

1, Komukai, Toshibacho, Saiwai-ku

Kawasaki 210

Japan

Toyota Toyota Central R&D Labs. Inc.

Nagakute-cho, Aichi-gun

Aichi 480-1192

Japan

32

TU M nchen Technische Universit t M nchen

Lehrstuhl f r technische Elektrophysik

Arcisstrasse 21

D-80290 M nchen

Germany

and

Technische Universit t M nchen

Walter Schottky Institut E26

Am Coulombwall

D-85748 Garching

Germany

TU Wien Technical University Vienna

Institute for Microelectronics

Gusshausstrasse 27—29

A-1040 Wien

Austria

and

Technical University Vienna

Department of Materials Science and Testing

Karlsplatz 13

A-1040 Wien

Austria

UCSB University of California

ECE Department

Santa Barbara, CA 93106-9560

USA

UKBF Berlin Universit tsklinikum Benjamin Franklin der freien Universit t Berlin

Institut f r klinische Chemie und Pathobiochemie

Hindenburgdamm 30

D-12200 Berlin

Germany

UMIL Milano Universita degli Studi di Milano

Dipartimento di Farmacologia

Via Vanvitelli 32

I-20129 Milano

Italy

Uni Basel Universit t Basel

Institut f r Informatik


CH-4056 Basel

Uni Bologna Universita degli Studi di Bologna

Dipartimento di Elettronica Informatica e Sistemistica

Via Zamboni 33

I-40126 Bologna

Italy

and

Universita degli Studi di Bologna

Dipartimento di Fisica

Viale Berti Pichart 6/2

I-40127 Bologna

Italy

33

Uni Cork University College Cork

National Microelectronics Research Centre

Lee Maltings, Prospect Row

Cork

Ireland

Uni Hamburg Universit t Hamburg

Institut f r Angewandte Physik

Jungius-Strasse 11

D-20335 Hamburg

Germany

Uni Kassel Universit t Kassel

Fachbereich Elektrotechnik/Informatik

Heinrich-Plett-Strasse 40

D-34132 Kassel

Germany

Uni Linz Johannes Kepler Universit t Linz

Institute for Communications and Information Engineering

Altenbergstrasse 69

A-4040 Linz

Austria

Uni Pisa Universita degli studi di Pisa

Dipartimento di Ingegneria della Informazione:

Elettronica, Informatica, Telecomunicazioni

Lungarno Pacinotti 43/44

I-56126 Pisa

Italy

Uni W rzburg Bayerische Julius-Maximilians Universit t W rzburg

Sanderring 2

D-97070 W rzburg

Germany

VEECO VEECO Instruments GmbH

Siemensstrasse 1

D-85716 Unterschleissheim

Germany

VERUM Stiftung f r Verhalten und Umwelt

Pettenkoferstrasse 33

D-80336 M nchen

Germany

VERYC Madrid Investigacion Bioelectromagnetismo

Hospital Ramon y Cajal

Carretara de Colmenar

E-28034 Madrid

Spain

WIAS Weierstrass-Institut f r Angewandte Analysis und Stochastik

Mohrenstrasse 39

D-10117 Berlin

Germany

34

Awards and Patents

Awards

Flavio Carbognani, Mauro Ciappa, Paolo Cova, Wolfgang Fichtner

received the

ESREF 2002 — Best Paper Award

for the paper

A novel thermomechanism-based lifetime prediction model

for cycle fatigue mechanisms in power semiconductors

at the

13th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF 2002),

Bellaria, Italy, Oct. 7—11, 2002

Patents

Title: System for Long-Term Remote Medical Monitoring

Owner: Astrium GmbH

Inventors: Wilfried Rode, Rolf Klintworth, Klaus-Peter Ludwig,

Michael Oberle

Patent No.: US 6,315,719 B1

35

History of the Integrated Systems Laboratory (IIS)

1985 Appointment of Wolfgang Fichtner, Professor for Electronics, Department of Electrical Engineer-

ing, ETH Zurich.

Formation of the research group VLSI in the Electronics Laboratory.

First research project (2D device simulation, funded by KTI).

Installation of 3 minicomputer DEC VAX-11/785 (1 CPU, 16 MBytes memory).

1986 Foundation of the Integrated Systems Laboratory by merging of the research groups of

Prof. Wolfgang Fichtner (Department of Electrical Engineering) and Prof. Martin Morf (Depart-

ment of Computer Science).

Start of the lecture Electronics Systems (undergraduate EE students).

Start of the lecture series Design of Integrated Circuits I, II, III (graduate EE, CS, and physics

students).

Summer school VLSI Design in Beatenberg/Switzerland (2 weeks, 85 participants from Europe

and Switzerland), organization as well as scientific and technical responsibility by IIS. 15 invited

talks by well known experts from USA, Europe, and Switzerland, presentations and hands-on

experience on workstations.

1987 Leaving of Prof. Martin Morf.

Appointment of Marco Annaratone, assistant professor for Parallel Computing, Department of

Computer Science, ETH Zurich.

Start of the lecture Digital Design and Processor Structures (undergraduate CS students).

Design and integration of the first student ICs (20MHz, 7000 transistors).

Installation of the HILEVEL TOPAZ 50 ASIC test system (50MHz, 96 I/O channels).

Installation of a mini-supercomputer Alliant FX/80 (6 CPUs, 112 MBytes shared memory).

Introduction of the first professional CAD tool for IC design in teaching and research (VLSI Tech-

nology Inc., later Compass Design Automation Inc.).

Installation of the parallel computer Sequent Symmetry (26 CPUs, 160 MBytes shared memory).

1988 Foundation of the Microelectronics Design Center (Department of Electrical Engineering, associ-

ated to the Integrated Systems Laboratory).

First PhD thesis of a computer science student at IIS.

Design and integration of the first VLSI chip (Viterbi decoder, 35000 transistors).

1989 First European research project (parallel computer architecture).

First PhD thesis of a physics student at IIS.

2nd prize Seymour Cray Competition Switzerland for Multi-Dimensional Semiconductor Device

Simulation to members of scientific staff of IIS.

First Intensive Course on ASIC Design and Test with ETH-internal and -external participants.

First functional 2D simulation program for semiconductor devices developed by IIS scientific staff.

1990 First PhD thesis of an electrical engineering student at IIS.

Start of the lecture Semiconductor Devices: Technology and Modeling .

CEI-Europe Elsevier course VLSI Process and Device Simulation in Davos/Switzerland. Orga-

nization as well as scientific and technical responsibility by IIS (1 week, 35 participants).

Start of the project Education and Research in Microelectronics , generous funding by the board

of ETH Zurich for IC integration and measurement equipment.

36

Evaluation of the Department of Electrical Engineering of ETH Zurich and the laboratories of the

department by a group of international experts. Qualification of the research at the Integrated

Systems Laboratory compared at the international level:

¥ process and device simulation: outstanding.

¥ VLSI design: very efficient.

¥ parallel computer architectures: very good ideas, realization has to be proven.

Prof. Wolfgang Fichtner elected IEEE Fellow for the application of numerical modeling to device

scaling and submicron transistor optimization .

1991 Leaving of Prof. Marco Annaratone.

4th International Conference on Simulation of Semiconductor Devices and Processes —

SISDEP 91 , ETH Zurich/Switzerland (3 days, 200 participants), organization by IIS, Conference

Co-Chairman Prof. Wolfgang Fichtner, 3 invited papers, 44 regular papers, 18 poster presenta-

tions.

Start of the national program Microswiss to support microelectronics in Swiss SMEs and edu-

cation. Microelectronics Design Center acts as a support center.

Presentation of the IIS activities in Modeling of Microelectronic Devices at CEBIT 91 exhibition

Hannover/Germany, as a winner of the competition Technology Location Switzerland 1991 .

Installation of the IMS XL60 Mixed Signal ASIC Verification System (60MHz, 96 I/O channels).

1992 Start of the Swiss priority program LESIT — Power Electronics, Systems, Information Technol-

ogy , 11 research projects in the module Silicon Power Device Technology (module coordinated

by Prof. Wolfgang Fichtner).

Start of the first European ESPRIT project ( DESSIS — Device Simulation for Smart Integrated

Systems ).

Start of a European JESSI project (Circuits for Communication Technology).

Design and integration of a high-speed data encryption IC (177Mbit/s, 250000 transistors).

First functional 3D grid generation program developed by IIS scientific staff.

1993 Appointment of Qiuting Huang, assistant professor for Analog Integrated Circuits, Department of

Electrical Engineering, ETH Zurich.

Foundation of the IIS spin-off ISE Integrated Systems Engineering AG Zurich by IIS members

(scope of business: software and application support in Technology CAD). Location for the first

one and a half years at IIS with support of ETH Zurich.

Start of the lecture Analog Integrated Circuits (graduate EE students).

First functional 3D simulation program for semiconductor devices developed by IIS scientific staff.

1994 6th International Symposium of Power Semiconductor Devices & ICs — ISPSD 94 ,

Davos/Switzerland (3 days, 195 participants), organization by IIS, symposium chairman

Prof. Wolfgang Fichtner, 3 invited presentations, 29 regular papers, 41 poster presentations.

Planning phase of the Swiss priority program MINAST, designated program director

Prof. Wolfgang Fichtner (1994/95), provisional program direction established at IIS.

Installation of the HP83000 ASIC Verification System (660MHz, 128 I/O channels).

Microelectronics Design Center also assumes responsibility for PCB support.

1995 Completion of the Swiss priority program LESIT with outstanding scientific results and efficient

transfer of research to industry.

First functional simulation program for semiconductor processes developed by IIS scientific staff.

Move of spin-off ISE AG from ETH Zurich location to Technopark Zurich.

First course Getting started with VHDL Synthesis with ETH-internal and -external participants.

Installation of the parallel computer IBM SP2 (6 CPUs, 4.5 GBytes distributed memory).

37

1996 Start of the Swiss priority program MINAST — Micro and Nano System Technology , program

director Prof. Wolfgang Fichtner (1996—1997), program direction established at IIS, total 56 Mio

CHF granted by Swiss authorities and more than 60 Mio CHF contributions from Swiss industrial

enterprises; IIS research projects: two in the module Integrated Microsystems Technology , four

in the module Design, Simulation and Engineering of Microsystems , and one in the module

Microsystems Applications .

1997 Postdoctoral thesis (habilitation) of PD Dr. Andreas Schenk for the subject Advanced Physical

Models for Silicon Device Simulation .

Public workshop 3D Semiconductor Simulation of the European ESPRIT Project PROMPT II —

Process Optimization in Multiple Simulations for Semiconductor Technology II (3 days, 56 partic-

ipants), Monte Verit Ascona/Switzerland, 8 presentations as well as demonstrations and hands-

on experience, organization by IIS and spin-off ISE AG.

Installation of the first parallel computer DEC Alphaserver (4 CPUs, 2 GBytes shared memory).

1998 Promotion of Qiuting Huang to Professor for Electronics, Department of Electrical Engineering,

ETH Zurich.

Accommodation of the research group Physical Characterization , including well known experts

and advanced equipment from the former Reliability Laboratory at the Department of Electrical

Engineering, ETH Zurich.

Start of three new European research projects.

Two patents on telecommunication ICs, inventors: IIS scientific staff, owner: Siemens Schweiz

AG.

Migration to Synopsys and Cadence EDA systems for IC design in teaching and research.

First functional simulation program for electromagnetic fields developed by IIS scientific staff.

1999 Accommodation of the research group Bioelectromagnetics/EMC from the Electromagnetic

Fields and Microwave Electronics Laboratory at the Department of Electrical Engineering, ETH

Zurich.

Election of Prof. Wolfgang Fichtner as head of the Department of Electrical Engineering

Oct 1999 — Sept 2001.

Start of the lecture Electrical Engineering I (undergraduate mechanical and process engineer-

ing students).

Completion of the Swiss priority program MINAST with outstanding scientific results and efficient

transfer of research to industry.

Public workshop ESD Protection Design Methodology of the ESPRIT Project ESDEM as an

open meeting of the EMC 99 Zurich Symposium , (1 day, 86 participants), ETH Zurich/Switzer-

land, 5 invited talks by well known experts from USA and Europe, demonstrations of the method-

ology, organization by IIS and spin-off ISE AG.

Design and integration of a high-quality video image processor (100MHz, 1.8Giga Ops/s,

2.7 Mio transistors).

Establishment of the Foundation for Research on Information Technologies in Society IT IS

(Zurich, director Dr. Niels Kuster). Associated to ETH Zurich and a close research partner of the

IIS research group Bio Electromagnetics/EMC.

2000 Graduation of no less than 21 PhD students at IIS due the conclusion of the 4th framework pro-

gram of the European Union as well as the Swiss priority program MINAST.

IEEE Andrew S. Grove Award of the Year 2000 to Prof. Wolfgang Fichtner for outstanding contri-

butions to semiconductor device simulations .

World s first chip of relevant complexity in GALS (Globally Asynchronous Locally Synchronous)

technique, a SAFER SK-128 cipher implementation.

Ultra low offset (200nV) chopper amplifier.

First functional simulation program for semiconductor lasers by IIS scientific staff.

38

Simulation platform SEMCAD for design and optimization of antennas in complex environments

by IIS and IT IS scientific staff.

Evaluation of the Department of Electrical Engineering ETH Zurich by a group of international

experts with high scientific reputation. Overall qualification: The international standing of Inte-

grated Systems Laboratory regarding its core activities is definitely among the best of the world.

Introduction of a new organization structure of ETH Zurich with autonomous departments and

global budget.

2001 Prof. Qiuting Huang elected IEEE Fellow for outstanding contributions to integrated circuits for

wireless communications.

Election of Prof. Wolfgang Fichtner as head of the Department of Information Theory and Electri-

cal Engineering Oct 2001 — Sept 2003.

Start of the lecture Semiconductor Devices (undergraduate EE students).

Start of the lecture Communications Electronics (undergraduate EE students).

Start of the lecture series Optoelectronic Devices (graduate EE students).

Three contributions from IIS to the new Project Oriented Work program (undergraduate EE stu-

dents).

Configurable hardware optimization and timing recovery for the first multimedia chip of the

research partner company BridgeCo AG.

13.5mW 185MSample/s Delta-Sigma Modulator for UMTS/GSM Dual-Standard IF Reception.

Completion of the European research project SUBSAFE with excellent review results.

First functional optical eigenmodes solver for Vertical-Cavity Surface-Emitting Lasers (VCSELs).

ESPRIT-Project MADBRIC One-Day Workshop on A/D Converters for Telecommunication in

Pf ffikon, Switzerland with 42 participants from 12 different countries.

Pilot User Workshop Simulation of Semiconductor Laser Devices at ETH Zurich/Switzerland (2

days, 29 participants from Europe, USA, and Japan), 3 invited talks by well known experts from

USA and Europe, 5 talks, 1 tutorial, computer lab, organization by IIS.

2002 Start of a close collaboration with the new Communication Theory Group of Prof. Helmut

B lcskei (Communication Technology Laboratory, IKT) in the field of multiple-antenna (MIMO)

research. A large, ETH-funded project on MIMO research has been approved by the board of

ETH.

Successful completion of the European project LEMON on the design and implementation of a

UMTS transceiver in deep sub-micron CMOS technology.

14bit, 1MHz Bandwidth Delta-Sigma A/D converter with lowest power consumption published so

far.

The new Monte Carlo simulator SPARTA for stable and efficient self-consistent simulations of

contemporary MOSFETs was included in the release 8.0 of ISE Integrated Systems Engineering

AG.

Self-consistent coupling of opto-electro-thermal equations in device simulation of Vertical-Cavity

Surface-Emitting Lasers (VCSEL).

Three accepted papers resulting from Master student theses to international conferences were

presented by the students.

First Linux-cluster for physical simulations in Technology CAD (22 PCs with 2.2GHz CPUs).

International Conference on Numerical Simulation of Semiconductor Optoelectronic Devices

NUSOD-02 , 25—27 September 2002, organized by IIS at ETH Zurich, 111 participants from

Europe, USA, and Japan, 13 invited talks by well known experts from USA and Europe, 19 talks,

10 posters, and 5 company presentations.

39

Research Projects

IC and System Design and Test

Coordinator:

Norbert Felber

40

A MIMO-Extended UMTS

Receiver

Personnel: Andreas Burg

Funding: Lucent, ETHZ

Partners: Lucent

The introduction of UMTS is the first step towards the de-

ployment of new multimedia-capable wireless cellular net-

works. The new standard promises higher data rates for a

growing number of users. However, recent investigations

show that the actual capacity of these systems under real-

world conditions is not sufficient to support the challeng-

ing target applications such as real-time video and high-

quality audio streaming.

The application of multiple antennas at the transmitter

and/or at the receiver allows for a variety of techniques to

improve capacity significantly. Multiple-Input-Multiple-

Output (MIMO) systems can, for example, transmit multi-

ple data streams concurrently in the same frequency

band, thereby greatly increasing the spectral efficiency

(spatial multiplexing). During the first phase of this project

MIMO has been applied to the UMTS-FDD downlink. An

FPGA/DSP based prototype of the system was developed

by Lucent Technologies in cooperation with IIS and was

demonstrated at the CTIA trade show.

In the second phase of the project low-complexity hard-

ware architectures for the ASIC integration of advanced

MIMO receiver algorithms were developed. They include

the implementation of a 40Mbps Maximum-Likelihood de-

tector for a 4x4 QPSK-based MIMO system and investiga-

tions of low-complexity linear MIMO equalization

algorithms.

Simulation results for a 4x4 MIMO UMTS FDD (Frequen-

cy-Division-Domain) Duplex compared to a RAKE re-

ceiver with an MMSE (Minimum-Mean-Square-

Estimation) and a ZF (Zero-Forcing) equalizer.

Real-Time MIMO OFDM Testbed

Personnel: Simon Haene, David Perels

Funding: ETHZ TH-6 02-2

Partners: IKT-ETHZ

New applications of mobile communications are increas-

ing the demand for high-speed and high-quality, band-

width-efficient wireless access solutions. The application

of multiple antennas, both in the transmitter and in the re-

ceiver (MIMO) has been demonstrated to drastically im-

prove the channel capacity compared to single-antenna

systems. Orthogonal Frequency Division Multiplexing

(OFDM) is one of the prime modulation technique candi-

dates for fourth-generation (4G) mobile wireless systems.

The practical feasibility of MIMO OFDM and the achiev-

able capacity gain can be assessed only through real-time

experimental investigations under real-world propagation

conditions.

The goal of this project is a real-time MIMO OFDM test-

bed. It is being developed in joint collaboration of the

Communication Technology Laboratory (IKT) and IIS and

will allow research on different topics: channel measure-

ment and modeling, algorithm development for optimal

MIMO gain, and VLSI implementations of MIMO systems.

IIS focuses on the ASIC design aspects of the project.

One key contribution is to provide feedback to the algo-

rithm designers of IKT by analyzing and optimizing the

suggested algorithms with respect to their suitability for

optimized hardware implementation, concerning the as-

pects of low power dissipation and low silicon area and

cost.

An FPGA-based implementation of the testbed with a

commercial RF frontend will allow limited real-time verifi-

cation. Critical components of the system will finally be im-

plemented as ASICs in order to reach unlimited real-time

operation.

Testbed hardware components and block diagram of a

MIMO OFDM receiver architecture.

41

Runtime-Reconfigurable

System on Chip (SoC) for

Multimedia Data Processing

Personnel: Thomas Boesch, Eric Roth;

BridgeCo: Markus Thalmann

Funding: KTI-5845.1 LANWAN2,

BridgeCo

Partners: BridgeCo

The success of multimedia consumer equipment de-

mands real-time interconnection networks. Tasks like de-

cryption, decompression, and signal processing ask for

high computation performance. On the other hand, ever

changing algorithms and fast time-to-market require flexi-

ble and programmable solutions. Today s solutions use

dedicated hardware to provide maximum performance,

but suffer from low flexibility and high design risk. Alterna-

tively, high-end DSPs are too expensive. Reconfigurable

hardware implementations are a compromise between

these two conventional design approaches.

An SoC consisting of a host processor and two runtime-

reconfigurable engines for data processing has been inte-

grated. Each engine consists of a general-purpose RISC

CPU associated with a runtime-reconfigurable processing

unit (RPU). The RPU contains a reconfigurable network

(RN) which interconnects programmable functional blocks

of different granularity. Fast, compact, coarse-grained

blocks (CB) are able to perform multiple arithmetic opera-

tions in parallel. Fine-grained structures (FB) provide con-

trol of the parallel data flow and high flexibility for bit-

oriented operations. The RPU operates either as runtime-

modifiable instruction set extension or executes macro

operations concurrently to the CPU. Customized instruc-

tions initiate and synchronize independent hardware-con-

trolled processing. An associated software tool chain has

been developed.

Block diagram of one runtime-reconfigurable engine.

All-Digital Standardcell-Based

Audio Sample Clock Synthesis

Personnel: Eric Roth, Thomas Boesch

Funding: KTI-5845.1 LANWAN2,

BridgeCo

Partners: BridgeCo, TIK-ETHZ

The growing popularity of digital multimedia consumer

equipment increases the demand for an interconnectivity

network between these devices. Distribution of real-time

multimedia data over such a network requires alignment

of data rates at the sending and receiving nodes to pre-

vent data losses due to buffer overflows or underflows.

Phase-Locked Loops (PLL) are commonly used to syn-

chronize phase and frequency of sampling events to a ref-

erence clock. Conventional PLLs employ an analog VCO

which cannot be fully integrated in digital standardcell de-

signs. The digital implementation of phase detector, loop

filter, and clock dividers is straightforward, whereas a dig-

ital substitute for the analog VCO is a challenging prob-

lem. In this project, a digitally controlled oscillator (DCO)

consisting of digital standardcells only has been devel-

oped. Based on a crystal clock, the position of every DCO

clock edge is pre-calculated. A delay line shifts this edge

to the predetermined position. In order to provide high res-

olution on limited space, it consists of coarse- and fine-de-

lay elements. To track process, temperature, and voltage

variations, two identical reference delay lines are used for

calibration.

DCO principle and photograph of the prototype chip.

42

Multi-Point Interconnects for

Globally-Asynchronous

Locally-Synchronous Systems

Personnel: Thomas Villiger

Funding: KTI-4897.1 IRRQ,

Infineon

Partners: Infineon, Philips Zurich

The Globally-Asynchronous Locally-Synchronous design

style (GALS) is an approach to VLSI system design that

combines the advantages of both synchronous and asyn-

chronous operation. It employs a self-timed communica-

tion scheme between coarse-grained synchronous

functional blocks.

The first GALS circuits only supported point-to-point con-

nections. However, a shared system bus or another form

of multi-point data exchange is a key necessity for a mod-

ern System-on-Chip (SoC) design in order to provide the

necessary modularity. To compete with standard synchro-

nous solutions, three interconnection topologies have

been added to the current GALS technique:

The first one is a shared bus. It is realized by extending the

point-to-point concept with port controllers that are able to

manage the self-timed data transfers between different

GALS modules by properly arbitrating the shared bus re-

sources. A central arbiter handles the access to the bus.

A second alternative is a switch network that routes the in-

coming requests from the senders to the appropriate re-

ceivers. This switch can be built from a matrix of smaller

self-timed switching elements. Arbitration between the in-

coming requests are handled within the switching ele-

ments.

The third variant is a self-timed ring topology that con-

nects GALS modules in a circular fashion. Dedicated ring

transceivers have been developed which are able to de-

couple the synchronous islands from the ring s timing.

Self-timed ring for GALS systems overlaid on the layout

plot of the test chip.

Testability of GALS Modules

Personnel: Frank G rkaynak


Philips Zurich

Partners: Philips Zurich, Infineon

Globally-Asynchronous Locally-Synchronous (GALS) ar-

chitectures have the potential to overcome clock distribu-

tion and synchronization problems associated with the

design of large Systems on Chip (SoC). This project ad-

dresses the testability problem of GALS-based systems

which has not been solved so far.

A new functional test methodology has been developed to

provide testability for the GALS system. In this methodol-

ogy, each GALS module is augmented by a test extension

element that gives a centralized test controller access to

the GALS module. The test controller can activate individ-

ual data transfer channels between GALS modules. Test-

ing is achieved by observing correct data transfers

between GALS modules.

The functional test methodology is primarily used to verify

the self-timed interface between GALS modules. Each

test extension element can be interfaced to a standard

JTAG port and thus provides a test solution for the en-

closed synchronous functional block as well.

This methodology calls for customized test extension ele-

ments for all GALS modules within a system. This is

achieved by a design and test automation script that auto-

matically generates all test-related hardware and assem-

bles the entire GALS system.

Simplified block level schematic showing the JTAG inter-

face of the Test Extension Element and data I/O. The

JTAG interface provides test access to the Locally-Syn-

chronous Island (LSI).

43

Self-Calibrating Oscillators for

GALS

Personnel: Stephan Oetiker, Frank G rkaynak


Philips Zurich

Partners: Philips Zurich

In Globally-Asynchronous Locally-Synchronous (GALS)

integrated circuits the local clock oscillators of the individ-

ual locally-synchronous islands do not require accurate

frequencies. Care has to be taken though that the average

frequency is slightly faster than the equivalent in a syn-

chronous implementation of the same chip. In order to

reach the same speed as a synchronous implementation,

the actually required frequency for a locally-synchronous

island depends on the communication network. Each in-

teraction with another GALS module will temporarily stop

the clock by stretching its period. Although this stretching

can occur at irregular time intervals, the average frequen-

cy constraint still has to be met.

At power-up of the chip, the exact frequency of the local

oscillators is not known. An estimation is available from

simulations. Altering operating conditions will change the

frequency. Therefore, each oscillators either has to be ad-

justed at startup, or the locally-synchronous islands need

to be designed with a speed overhead to account for the

worst case.This can be far above the actually required op-

erating frequency. Both methods are not practically appli-

cable.

In this project, a clock generator circuit has been devel-

oped which uses a slow (e.g. 32kHz) reference clock to

adjust its delay line to the desired frequency. Calibration

can be performed at startup, or at runtime by using two

delay lines. Runtime calibration has the advantage of

compensating for varying operating conditions.

The oscillator makes use of three different delay elements

with typically 6ps, 18ps, and 320ps delays in a 0.25μm

CMOS technology. Oscillators with seven different calibra-

tion modes have been integrated on the test chip for the

multi-point interconnects (see page 44).

Routed clock generator with manually placed delay lines

for better matching (highlighted in yellow and light-blue).

OSCAR: Integration of

24 Oscillators for GALS

Personnel: Stephan Oetiker, Frank G rkaynak


Philips Zurich


One advantage of Globally-Asynchronous Locally-Syn-

chronous (GALS) circuits is power reduction by avoiding a

large global clock tree. In order to actually benefit from this

advantage, a pausable clock generator with a fine resolu-

tion at high frequencies is required. Optimum perfor-

mance can only be achieved if the frequency aimed at is

sufficiently accurate after tuning the oscillator.

In this project, a test chip in a 0.6μm CMOS technology

has been developed which contains 24 different oscillator

architectures. The oscillators consist of standardcells rou-

tinely available in any standardcell library. Twenty-four

variants have been designed in order to explore sub-gate-

delay resolution. Measurements have shown that every

oscillator works as expected. A delay slice using a stan-

dardcell from the library generates an increment of 900ps.

The oscillator which uses three cascades of phaseblender

circuits divides this 900ps into 8 delay steps and therefore

achieves a resolution of about 100ps. The custom de-

signed standard cell which uses capacitive loads has

shown to yield the most accurate delay steps (designed

for 100ps).

Micrograph of the 24-oscillator chip.

44

Testbed for GALS Multi-Point

Interconnects

Personnel: Frank G rkaynak, Stephan Oetiker,

Thomas Villiger


Philips Zurich

Partners: Philips Zurich, Infineon

One of the research topics of the Globally-Asynchronous

Locally-Synchronous (GALS) research team is to provide

solutions for multi-point interconnects between GALS

modules. Several alternative interconnect architectures

have been developed for this purpose (see page 42).

In this project, a testbed has been developed in order to

evaluate the relative performances of five different inter-

connect architectures. The functional component for the

locally-synchronous islands of this testbed is a versatile

microcontroller, called portprocessor. This microcontroller

with SIMD architecture is capable of activating up to eight

input/output ports simultaneously. For each of the eight

ports a dedicated pattern memory stores stimuli and re-

sponses which can be accessed externally. A special syn-

chronization GALS port is used for synchronization with

external tester hardware.

The testbed consists of 25 GALS modules, each of which

contains a portprocessor. Its GALS ports are capable of

supporting different interconnect architectures. Custom-

ized design scripts have been used to generate fully char-

acterized and verified hardware macros for each GALS

module.

The design has been implemented in a standard 0.25μm

CMOS technology, occupies an area of 25mm2, and con-

tains roughly 3 million transistors.

Block-level schematic of the portprocessor developed for

the multi-point interconnect testbed.

Variable-Delay Adder

Personnel: Andreas Burg, Frank G rkaynak

Funding: ETHZ

Efficient adder implementation is one of the oldest but still

one of the major problems in VLSI design. Various archi-

tectures have been suggested to alleviate the problems

associated with the so called curse of the carry . The es-

sence of the problem is the fact that the carry propagation

determines the longest path and thereby the worst-case

delay in any kind of adder architecture. The length of this

path grows with the word width. It becomes especially sig-

nificant for very long operands, as they appear for exam-

ple in cryptography applications (>128bits). Traditional

approaches aim at speeding up this path by using com-

plex carry-look-ahead or carry-select logic.

In this work a different approach has been investigated. It

is based on the observation that for random input data the

longest path is almost never excited since carry propaga-

tion is often stopped after only few stages. These interrup-

tions in the carry chain can be discovered by a series of

rather simple detection circuits. Their combined results

determine the number of cycles required to complete the

addition. It has been shown that for very wide operands, a

low-complexity ripple-carry adder with early-termination

detection achieves on average almost the performance of

a significantly more complex Carry-Look-Ahead adder. As

early-termination detection can be applied to different ba-

sic adder architectures, it offers a variety of new pareto-

optimal area/delay trade-offs with excellent AT-products.

AT diagram comparing Area and Timing of a 128bit and

a 256bit variable-delay adder to other architectures.

45

IRRQ Testing, a Replacement

for IDDQ Testing of Deep-Sub-

micron CMOS Technologies

Personnel: Gianpaolo Pontarolo


Philips Zurich


The integrated circuit s (ICs) complexity keeps growing

while transistor size shrinks. This translates into a need

for new testing techniques that certify IC quality and reli-

ability for the upcoming processes.

In fact, in deep sub-micron technologies, test methods

based on Stuck-At and IDDQ models are becoming less

effective.

The IRRQ (Inherently Redundant logic Repeated Qualifi-

cation) test technique is a possible candidate for replacing

both Scan- and IDDQ test techniques. In contrast to well

known and established testing techniques, IRRQ bases

its fault model on transistor level and not on gate level.

This leads to a better physical fault coverage since it pro-

vides an effective solution for leakage oriented faults. Last

but not least, it is technology-independent.

This project investigates and analyzes new methods for

testing of CMOS technologies which might be realized lo-

cally on chip and therefore provides potential for built-in

self test. In particular it focusses on aspects regarding the

detection of Transistor-Stuck-Open and Stuck-On faults in

standardcells adapted for IRRQ.

Short detection in a p-channel transistor of an AOI gate.

Tightly Coupled Coprocessor

for General-Purpose Proces-

sors in Network Applications

Personnel: Silvio Dragone

Funding: IBM Research

Partners: IBM Research

In today s Network Processors (NPU) the packet process-

ing unit mostly consists of a RISC-type processor. This

processor has to handle the packet forwarding or protocol

termination data path functions commonly associated

with Layer 3 to Layer 7 processing (referred to the OSI ref-

erence model). In order to reach the required wire-speed

performance for OC-48 or higher, several processors are

clustered in various forms of parallel processor configura-

tions. An additional possibility to improve the performance

of the processor cluster in packet processing is to assist

them with coprocessors which perform certain applica-

tion-specific functions much faster.

Subject of this project are the tightly coupled coproces-

sors running synchronously to the General-Purpose Pro-

cessor (GPP). This type of coprocessor usually

accelerates application-specific operations which other-

wise would consume a considerable number of elementa-

ry GPP instructions. Thus, tightly coupled coprocessors

are a natural way to extend the Instruction Set Architec-

ture (ISA) of the GPP with application-specific operations.

Network protocols like TCP, SCTP, and RTP make exten-

sive use of timers; e.g. already at OC-48 several 10 000

timers may be allocated. Therefore, as an initial extension,

an instruction set and a HW architecture for a Timer Man-

ager have been identified. A hierarchical heap has been

defined as data structure. This structure requires no link-

ing pointers and it makes parallel processing possible.

Thus, it is memory efficient and it minimizes the latency of

the instructions. Due to the opportunity to split this struc-

ture into on- and off-chip memory (as shown in the figure

below) it is suitable as a HW implementation.

Timer Manager as a tightly coupled coprocessor.

47

Research Projects

Analog and Mixed-Signal Design

Coordinator:

Qiuting Huang

48

UMTS Transmit I/Q Modulator in

0.12μμμμm CMOS

Personnel: Gabriel Brenna

Funding: BBW, EU-IST-11081 LEMON

Partners: Infineon, Uni Linz

Recently, a first integration for this project has been able

to show that direct up-conversion transmitters based on

CMOS technology fulfil the high linearity and low power

requirements of 3rd generation WCDMA cellular radio

networks.

A remaining limitation of the direct up-conversion archi-

tecture is carrier leakage. Due to power accuracy and er-

ror vector magnitude (EVM) reasons, carrier leakage

must be kept low for all gain settings. This makes it difficult

to implement a wide range of accurate gain control in the

baseband section of a mobile terminal. Circuit techniques

to suppress carrier leakage therefore hold the key to a

high integration level through the direct up-conversion ar-

chitecture.

In this contribution, circuit and calibration techniques are

investigated that significantly improve carrier leakage. For

this purpose, a fully integrated WCDMA Tx IC has been

implemented in a 0.12μm CMOS process. It includes a

baseband filter, an I/Q divider, an I/Q modulator, a variable

gain RF pre-amplifier and a carrier leakage calibration

loop. The chip has been fully characterized and shows ex-

cellent performance at very low power consumption.

Chip micrograph of the complete transmitter IC.

Baseband Circuits for Direct

Conversion UMTS Mobile

Receiver

Personnel: J rgen Rogin



To offer higher data rates to mobile communications us-

ers, third generation Universal Mobile Telecommunica-

tions System (UMTS) services will become available in

the imminent future. For better customer acceptance and

full area coverage, multimode terminals including GSM

(Global System for Mobile Communications) capabilities

in small form factors and with decent standby times are a

must.

In this project, a direct-conversion transceiver has been

developed, eliminating the need for external, passive fil-

ters for image rejection and for channel selection.

In the zero-IF receiver, the baseband part is of particular

importance, combining accurate gain control and channel

select filtering with low noise and high linearity require-

ments. Additionally, since amplification takes place

around DC, offset compensation must be provided.

The baseband filter, like the whole transceiver, has been

integrated in a 0.12μm CMOS process. It includes a sixth

order leapfrog low pass filter, a first order all pass, an off-

set compensation loop and an automatic tuning circuit

that fixes the filter cut-off frequency under process and

temperature variations. Compared to the 0.25μm CMOS

prototype described in the last research review, the power

consumption has been significantly reduced from

37.5mW to 8.25mW, owing partly to the reduction in sup-

ply voltage (from 2.5V to 1.5V), but also to the significant-

ly reduced current consumption (from 15mA to 5.5mA).

Such a low power design allows longer standby times

from a smaller battery, significantly enhancing the mobile

terminal.

Chip photograph of the 0.12μm CMOS baseband filter

and programmable gain amplifier.

49

LNA and I/Q Demodulator for

UMTS Receiver

Personnel: Ilian Kouchev



The direct conversion architecture is a very attractive can-

didate for highly integrated UMTS receivers. It avoids the

image suppression problem and allows higher integration

by reduction of the bulky external components at the price

of tougher building block specifications.

The I/Q demodulator design for a homodyne receiver is a

challenging task, which requires thorough circuit under-

standing and very careful design. For the second version

of the I/Q demodulator, in order to overcome the limita-

tions of the reduced voltage headroom, a new improved

architecture has been chosen. The I/Q demodulator has

been fabricated in a 0.12μm CMOS advanced technology

and has been evaluated successfully. A voltage gain of

12dB, an equivalent input referred noise voltage of

4.8nV/√Hz, an iIP3 of 0dBVrms and an iCP which equals

—18.7dBVrms have been measured. The I/Q demodulator

consumes 6mA of current.

As a part of the receiver a single-ended low-noise ampli-

fier (LNA) with matched input and output to 50Ohm has

been designed, implemented in a 0.12μm CMOS technol-

ogy and successfully tested. Power gain of 12dB, noise

figure (NF) of 2.3dB, iIP3 of 5.4dBm and iCP of —12dBm

have been measured. The LNA draws a current of 6.5mA.

Chip micrograph of the LNA and the I/Q demodulator.

Carrier Leakage Suppression in

Direct-Conversion WCDMA

Transmitters

Personnel: David Tschopp



Modern communications standards like 3GPP UMTS

(WCDMA) pose very stringent requirements on mobile

transmitters. Large output power control range combined

with high linearity and low power consumption make the

design of a direct up-conversion (DUC) transmitter a very

demanding task.

This research work solves the problem of the carrier leak-

ing to the signal band. In the direct up-conversion archi-

tecture this component is in the middle of the channel and

degrades the quality of the modulated signal. Three differ-

ent techniques can be applied, each by itself or together

in order to suppress the carrier leakage. Firstly, some or

all of the gain control can be done in the RF part of the

transmitter. Secondly, at lower gain settings the bias cur-

rent in the modulator can be reduced. Finally, calibration

can be used if the previously mentioned techniques are

not able to fulfil a given specification. Calibration relies on

the fact that mismatches in the baseband circuit and the

modulator bias current sources lead to a DC offset that

appears as carrier leakage. The baseband circuits and

the modulator have been extended so that it is possible to

control the amount of carrier leakage. The carrier leakage

is detected with a simple RF power detector. Its output is

used by a digital calibration algorithm that sets the trans-

mitter s carrier control inputs in order to minimize the

amount of carrier power at the output.

Measurements have shown that the applied carrier sup-

pression techniques work very well and enable the DUC

architecture to be used even for very demanding commu-

nications standards.

Block diagram of WCDMA transmitter with calibration

loop.

50

Integrated Transmitter

Architectures

Personnel: David Tschopp

Funding: KTI-5731.1 OTRACOM


For decades the intermediate frequency (IF) architecture

was the workhorse for virtually all transmitter applications.

With the trend of integrating more and more components

onto a single chip the question arises whether the IF ar-

chitecture is still a good way to design highly integrated

transmitters. The direct up-conversion (DUC) architecture

could be a better choice nowadays because of its inher-

ently low number of components. The omission of an IF fil-

ter, IF gain stage, RF mixer and IF frequency generation

makes the DUC architecture also attractive in terms of

power consumption.

Some severe limitations have prohibited the wide-spread

application of the DUC architecture so far. In discrete de-

signs the mismatch in I and Q was a limiting factor. Inte-

grating the I and Q path on the same die greatly reduces

this problem, leaving the carrier leakage as the major lim-

itation. For very undemanding or proprietary systems the

DUC architecture is a simple and cheap solution whereas

for modern communications standards like GSM/EDGE

and 3GPP s UMTS (WCDMA), it is still questionable

whether the DUC has a clear-cut advantage over the IF

architecture.

The winning strategy: Direct up-conversion (DUC) vs.

intermediate frequency (IF) architecture.

Broadband D/A Converters

for Telecommunications

Applications

Personnel: Pier Andrea Francese

Funding: KTI-5731.1 OTRACOM


This project is focused on the study and realization of in-

novative D/A converter architectures for applications in

the transmit path of a mobile terminal, implementing stan-

dards such as GSM, GPRS, or UMTS.

The choice of the architecture plays an important role in

the converter specification. The research is pointing to-

wards placing the digital-to-analog conversion as close as

possible to the power amplifier. This has the great advan-

tage that most of the signal path is kept in the digital do-

main, with the main goal of generating the modulated

signal by software. However, very broadband and high-

resolution D/A converters are required in order to realize

this kind of solution. Therefore, one of the problems for the

realization of transmitter software reconfigurability is that

the CMOS integration of this high-spec converters is diffi-

cult and the price in terms of power consumption and sili-

con area is high.

In this study three candidate architectures are being eval-

uated. The first design is a delta-sigma multibit D/A con-

verter with a multistage architecture, both in the voltage

domain using switched capacitor, and in the current do-

main. The second one is a pipelined D/A converter based

on passive charge bisection and mismatch shaping. Final-

ly, a current steering D/A converter using background or

power-on calibration is evaluated.

The analog part of the first architecture has been imple-

mented in a 0.18μm CMOS process that has an operating

voltage of 1.8V. The digital part is implemented on a Xilinx

XCV300E FPGA. The target resolution is >12bit for a sig-

nal bandwidth of 4MHz and a clock frequency of 100MHz.

The implementation uses SC techniques and also in-

cludes an SC FIR-IIR reconstruction filter.

Layout of the analog part of the ΔΣ D/A converter.

51

A High-Speed 14-bit D/A

Converter with Background

Calibration

Personnel: Pier Andrea Francese, Chiara Martelli,

Jannik Nielsen (DTU), Clemens

Hammerschmied

Funding: ETHZ

Wireline communications services such as ADSL, VDSL,

or powerline communications systems provide high data

rates by using already existing cable connections to the

customer premises. Usually the physical available band-

width for transmitting data is limited, therefore the need of

sophisticated modulation schemes. Their implementation

requires high linearity and high spurious free dynamic

range of the A/D and D/A converters. This is the reason

why the new wireline communications services are one of

the driving forces behind the current research efforts of

new data converters.

For D/A converters, resolutions in the order of 14 bits at

conversion rates of up to 200Msample/s are required in

the head-ends of wire-based communications systems.

This accuracy cannot be usually obtained by pure match-

ing of passive or active devices, therefore on-chip calibra-

tion has to be used.

The D/A converter implemented in this project utilizes a

completely floating current source that allows the mea-

surement and the calibration of the unit current, while the

device is in full operation mode. This provides a true back-

ground calibration. The actual calibration of the thirty-two

current sources, which determine the five most significant

bits, is performed by an analog feedback loop. The D/A

converter is implemented in an advanced digital 0.18μm

single-poly CMOS process with six metal layers. The

achieved resolution with on-chip calibration is 14 bits with

a maximum update rate of 200Msample/s. The linearity of

the device amply satisfies the requirements.

Chip micrograph of the 14 bit D/A converter.

Multi-Standard Baseband

Sigma-Delta A/D Converter

Personnel: Thomas Burger, Robert Reutemann

Funding: ETHZ

For new generations of mobile communications devices,

multiple standards will have to be incorporated. For exam-

ple, UMTS will allow wide-area medium-speed data con-

nections, while GSM will provide speech and lower-rate

data coverage in remote areas. For in-house, and in-

creasingly also open-air use, the addition of WLAN com-

patibility will add high-speed data connections to the mix.

For space and cost reasons, hardware has to be shared

as much as possible. Since users will expect performance

(battery life, size and weight, ease of use) to be at least as

good as for current single-standard devices, the perfor-

mance and power consumption of key elements must be

comparable to state of the art implementations for each

standard.

The A/D converter in the receive path is one of the key el-

ements in such a device. A ΣΔ converter is an attractive

choice for a multi-standard solution, since speed (over-

sampling ratio) can be traded for resolution. Nevertheless,

covering multiple cellular and WLAN standards is a chal-

lenge, since the spread of bandwidth and resolution is

very high. With these widely varying requirements, the

digital decimation filter also has to provide a wide range of

possible settings, while still achieving high performance

and low power consumption. In the decimation filter, a

maximum of flexibility is highly desirable, at least in the

last stages, to allow for different post-processing ap-

proaches or to adapt to evolving standards.

In this project, a ΣΔ converter covering GSM, UMTS and

WLAN standards is being developed. Optimization op-

tions for maximum resource sharing and low power con-

sumption are being examined. The converter is being

implemented in an advanced CMOS process to be com-

patible with fully integrated transceiver developments in

mainstream technologies.

Example modulator noise transfer functions (dashed)

and decimation filter responses (solid) for two different

standards.

52

Broadband, Low-Oversampled

ΣΣΣΣΔΔΔΔ A/D Converter for Telecom-

munications Applications

Personnel: Pio Balmelli

Funding: ETHZ

Oversampled Sigma-Delta (ΣΔ) ADCs are highly suited

for integrated circuit implementations since they do not

need a precision S/H stage, have relaxed requirements

for the anti-aliasing filter, and achieve very good linearity

despite the use of relatively imprecise building blocks.

However, the need for oversampling reduces the achiev-

able conversion bandwidth. This limitation has kept the in-

put bandwidth of published converters below 4MHz. In

this work an architecture suitable for achieving input

bandwidths of 8 MHz or more has been investigated.

ΣΔ modulators can be implemented in two main architec-

tures namely cascaded and single-loop. Single-loop ar-

chitectures usually achieve lower resolution than

cascaded architectures because part of the noise shaping

capability is lost to keep the loop-filter stable. But cascad-

ed architectures allow lower sampling frequencies to be

achieved because more precision is required in the ana-

log building blocks. In this work the single-loop architec-

ture has been selected and its stability has been improved

with a multibit internal quantizer/DAC.

Since the DAC output is directly compared with the input

signal, the DAC unit capacitors have to match with a pre-

cision comparable to the overall converter resolution.

Standard technologies can only achieve a precision of

8bit. To increase the DAC linearity the mismatch error is

reduced over multiple clock cycles using a data weighted

averaging algorithm (DWA).

Modern technologies are fast but the low supply voltages

reduce the swing of the analog signals. To reduce the off-

set requirement for the comparators of the internal ADC a

pre-amplifier is used. Due to speed considerations an

open-loop amplifier has been preferred to a simple SC

gain stage. The gain of the open-loop amplifier is kept

constant over temperature and fabrication variations.

Block diagram of the ΣΔ modulator.

A High-Speed Folding and

Interpolation Analog-to-Digital

Converter

Personnel: J rgen Hertle

Funding: ETHZ

The goal of this project is to design a high-speed analog-

to-digital converter in a modern submicron CMOS tech-

nology. The folding and interpolation architecture has

been chosen, because in several communications sys-

tems latency is of major importance and hence the well

established pipelined architecture cannot be used. The

flash converter has to be precluded as well, because it

suffers from high power consumption at resolutions of

more than 6—7bits.

The main challenges are first to overcome the high offset

voltages of fast differential pairs in CMOS technology,

which limit the accuracy of folding analog-to-digital con-

verters to 6—8bits. This problem can be overcome by the

implementation of an offset calibration scheme which

does not interfere with the normal operation of the analog-

to-digital converter. This substantially increases the com-

plexity of the design. The second challenge is related to

the high speed demands of the converter. Since high

speed inevitably requires high bandwidth also the noise

bandwidth will be very high. As a consequence the sam-

pling noise of the sample-and-hold and the inherent noise

of the ADC limit the achievable signal-to-noise ratio, de-

spite offset calibration. All these demanding requirements

shall be met under the constraint of minimal power con-

sumption.

In the first part of the project an architecture for the ADC

has been worked out and is shown in the picture below.

The amount of folding and the amount of interpolation are

distributed over several stages to keep the load at the in-

ternal nodes low. This is the key premise to achieve low

power consumption at high operation speed..

Architecture of a high speed folding and interpolation

analog-to-digital converter.

53

A 4GHz 0.18μμμμm CMOS

Integer-N Frequency

Synthesizer

Personnel: Dirk Pfaff

Funding: ETHZ

Frequency synthesizers provide the local oscillator signal

required by wireless transceivers to perform frequency

translation from and to the RF band. Extraordinary stiff re-

quirements to the purity and accuracy of the synthesized

signal are demanded by GSM and other standards. Be-

sides these constraints, low power consumption and com-

patibility with standard CMOS are the main synthesizer

requirements for cellular handsets.

An integer-N 4GHz frequency synthesizer with 400kHz

frequency resolution has been designed in a 0.18μm

CMOS technology. The integrated circuit provides a dual

modulus prescaler designed for minimum power con-

sumption, a frequency divider which is programmable

through a serial interface, a phase frequency detector and

a charge pump. A few passive components for the loop fil-

ter and a voltage controlled oscillator (VCO) module com-

plete the frequency synthesizer.

A novel charge pump circuit, designed for rail-to-rail out-

put operation and for minimum spurious tones generation

has been developed. Spurious tones are reduced by a

self-calibration technique diminishing the mismatch of the

charge pump current sources.

A test board and a PC based control program have been

set up to characterize the synthesizer performance. First

measurements show the synthesizer to be fully operation-

al.

Synthesizer chip micrograph and synthesizer evaluation

board.

10 GHz Voltage-Controlled

Oscillator and Prescaler

Personnel: Xinhua Chen

Funding: ETHZ

Recently, low-IF and zero-IF (direct-conversion) receivers

appear to be promising for highly integrated implementa-

tions for wireless receivers. However, these receivers re-

quest a quadrature demodulator where the frequency-

doubled voltage-controlled oscillator (VCO) and the fol-

lowing quadrature divider tend to consume much power.

Thus the low power design for these two blocks is a great

challenge.

The power consumption of a VCO depends much on the

quality of the resonator. Usually, in the GHz frequency

range, on-chip coils and varactors suffer from substrate

coupling and exhibit a low quality factor. And because of

the self-resonance, their use is limited up to a frequency

of several GHz. Thus a fully integrated VCO at 10GHz is

either impossible, or has a very high power consumption.

On the other hand, microstrip line resonators are widely

used in microwave oscillators. These oscillators usually

have better noise performance and low power, but very lit-

tle tuning range. Therefore, for the trade-off between the

low power and the large tuning range, an off-chip

microstrip line and commercial varactor based hybrid res-

onator is proposed. Moreover, the flip chip bonding tech-

nique has to be used in order to eliminate the

unacceptable parasitic inductance introduced by the bond

wire at such a high frequency. For the system application

as well as easy measurement, the 10GHz VCO is fol-

lowed by a quadrature divider and a dual modulus pres-

caler. The basic high-speed divide-by-2 cell is also

optimized for minimum power consumption. The design

has been implemented in standard 0.18μm CMOS tech-

nology. The overall power consumption could be as low as

40mW.

The design will be useful for the applications of wireless

LAN transceivers in the 5GHz range.

Circuit diagram of the proposed VCO.

55

Research Projects

Technology CAD

Coordinators:

Wolfgang Fichtner

Andreas Schenk

D lf Aemmer

56

Mobility in DGSOI MOSFETs

Personnel: Andreas Schenk;

ISE AG: Andreas Wettstein

Funding: ETHZ, ISE AG

Partners: ISE AG

Ultra-thin DGSOI (double gate silicon-on-insulator) tran-

sistors are among the most promising devices for future

VLSI. Besides improvements of the sub-threshold behav-

ior, an increase of the effective channel mobility has been

anticipated from results of numerical simulations.

In this project, a quantum-mechanical mobility model

based on solutions of the integrated Schr dinger-Poisson

solver in DESSIS was applied to double-gate SOI MOS-

FETs varying basic parameters like silicon slab thickness

and buried-oxide thickness. Convergence was improved

by a hybrid technique, where the whole device is simulat-

ed with the density-gradient model and only the channel

mobility is computed based on the Schr dinger solver. It

was found that the volume-inversion related enhancement

of mobility and on-current is bound to comparable thick-

nesses of gate oxide tox and buried oxide tbox. Thick bur-

ied oxides, as common in today s SIMOX technology,

inhibit the inversion of the buried channel and limit the ef-

fective mobility to its bulk value.

Upper: Effective electron mobility for front oxide thick-

ness tox = 2nm and various Eeff and tbox. Lower: Conduc-

tion band profile (left) and electron density (right) across

the silicon film for various tbox.

Revised SRH Lifetimes for

Quantum Transport Modeling

Personnel: Timm H hr

Funding: KTI-4082.2 HYBRID, ISE AG

Partners: ISE AG

The inclusion of quantum effects is crucial for the TCAD of

modern deep-submicron devices. Advanced device simu-

lators solve the 1D Schr dinger equation or use the den-

sity gradient model. In applying those methods, the

consistent modeling of transport coefficients is an impor-

tant issue.

Here, the Shockley-Read-Hall (SRH) recombination is

studied for a one-dimensional triangular well (a semicon-

ductor in a constant electric field next to a wall). This cor-

responds, for example, to a perpendicular cut through a

MOSFET channel. The recombination occurs via deep

traps that are assumed to be strongly localized in space.

Transitions between the bands and the trap level are en-

abled by multiphonon processes. Only one single-fre-

quency phonon mode is assumed. Quantum mechanics

enters the densities and the lifetimes via a local density of

states, which is composed by the eigenstates of the well.

Lifetime profiles as a function of position have been ob-

tained numerically using MATLAB. Because of the rising

energetic separation between trap levels and the involved

subbands, the lifetime increases towards the wall within a

distance of a few nm. Apart from a field-independent fit

factor this region is well described by an analytical approx-

imation accounting only for contributions from the lowest

subband.

SRH lifetime τ(x) divided by the constant lifetime τclass

(without quantum confinement and field F=0) as a func-

tion of the distance x to the wall. A small phonon energy

of 2meV was chosen.

Filled symbols: numerical results for various field

strengths taking all relevant subbands into account;

Open symbols: only lowest subband for F=1MV/cm; Sol-

id lines: approximation for the case of lowest subband

only; Dashed lines: without quantum confinement.

57

Monte Carlo Simulation and

Measurement of Nanoscale

nMOSFETs

Personnel: Fabian Bufler

Funding: KTI-4082.2 HYBRID, ISE AG

Partners: ISE AG, Toshiba

Full-band Monte Carlo (FBMC) simulation allows to con-

sider quasi-ballistic transport effects which occur in the

sub-0.1μm regime. However, every device simulator must

be verified for exemplary typical transistor structures, be-

cause otherwise there would be no confidence in the sim-

ulation results when exploring novel devices.

First, it was checked in the transfer characteristics that the

quantum mechanical threshold shift can be considered

via a modification of the work function by 60mV. Then the

MC simulation reproduced the measurement, while the

surface mobility in the drift-diffusion model had to be ad-

justed for the nanoscale MOSFETs. The FBMC model

matched also the output characteristics without any fitting,

but the analytic-band MC model overestimates the on-cur-

rent due to band structure deviations above 100meV.

Top: Measured and simulated transfer characteristics.

Bottom: Measured and simulated output characteristics.

Quasi-Exciton Densities in Bulk

Silicon at Room Temperature

Personnel: Frank Geelhaar

Funding: SNF 21-58811.99 Correlated Transport

The electrons and holes in a semiconductor are capable

of forming bound states known as excitons. In the familiar

drift-diffusion scheme, however, this third species is usu-

ally not accounted for. It has been claimed in parts of the

literature that excitons should be incorporated into the de-

vice simulation to obtain accurate results, even at room

temperature.

In order to investigate the potential impact of composite

particles on the transport properties of bipolar devices, a

many-body calculation of the excitonic mass action con-

stant has been performed. Various degrees of mutual

compensation between electron-hole bound- and scatter-

ing state contributions lead to different, but physically

equivalent quasi-particle pictures. In either case, it is

found that for T = 300K, excitonic states play only a mar-

ginal role and can safely be neglected from a simulation

point of view.

Excitonic densities for two different quasi-particle pic-

tures. The term n0 denotes the concentration of quasi-

free carriers in the symmetrical electron-hole plasma.

58

Simulation of Quantum Ballistic

Transport in Nano-Devices

Personnel: Frederik Ole Heinz

Funding: BBW, EU-IST-10828 NANOTCAD

Partners: Uni Pisa, Uni Cork, MPG Stuttgart,

TU Wien, Uni W rzburg

In nano-devices with quantum confinement there are two

main mechanisms of charge transfer: tunnelling and

quantum ballistic transport. Tunnelling is the dominant

mechanism in the presence of thin potential barriers that

are much higher than the thermal voltage kBT/e. Here,

thermionic excitation over the barrier is strongly sup-

pressed. Still, the system may exhibit non-zero conduc-

tance, since the quantum-mechanical wave-functions of

the electrons extend into the classically forbidden region.

As the barrier height is decreased, excitation events over

the barrier become increasingly more likely, and the sys-

tem gradually switches to the ballistic regime. In this re-

gime, lateral quantization effects may be observed in

narrow ( quasi-1D ) channels: the quantum wire acts as

a wave-guide for electron waves. Only a discrete set of

transverse modes ( sub-bands ) may exist inside the wire;

and as in a classical wave-guide, each mode is associat-

ed with a cut-off energy. If the spacing of the sub-band en-

ergies is larger than kBT, it is possible to switch on the in-

dividual modes one by one. This results in a staircase-like

conductance-characteristic with step height G0=2e2/h.

This effect was studied by 3D simulations of a split gate

GaAs/AlGaAs structure manufactured at the University of

W rzburg. Surface gates were used to define and control

two (nominally identical) quantum wires (labelled as up-

per gates and lower gates in the figure).

Agreement between simulation results and experimental

data is striking: the deviation of the simulation results from

the experimental conductance values is no larger than the

difference between the measurements of the two identi-

cal wires. The staircase structure is clearly visible.

Simulation results and experimental data of a III/V split

gate structure: stairs indicate quantum ballistic transport.

Physical Model Interface Based

Noise Simulation in BJTs

Personnel: Simon Brugger, Andreas Schenk,

Fabian Bufler


Partners: Toshiba, ISE AG

In a previous project, tables of bulk transport parameters

and bulk noise sources were computed using Full Band

Monte Carlo (FBMC) simulations. The quantities were pa-

rametrized with the electrical field intensity (E), the doping

concentration (N), and the carrier densities (n).

To consistently use those quantities, one has to simulate

and compute the noise Greens functions using the FBMC

transport parameters, and to compute the total current

noise of the device using the FBMC bulk noise sources.

A library was created that allows making the FBMC bulk

data look to the user like differentiable functions of E,N,

and n. With the help of this library it was then simple to

write a Physical Model Interface (PMI) for our simulator.

Those tools now allow to compute the terminal current

noise of any device as long as interfaces effects are neg-

ligible (e.g. BJTs).

Simulation of a Toshiba BJT showed that the new method

predicts more noise than thought before.

NF50 and NFmin as a function of the collector current for

two frequencies of interest. The violet curves show the

results of the new method.

59

A Posteriori Error Indicators

for Device Simulation

Personnel: Bernhard Schmith sen


Partners: WIAS, ISE AG

Numerical simulation of semiconductor devices is exten-

sively used for scientific and industrial investigations of

device operation. Nevertheless, in most cases, the appli-

cation engineer is left alone to judge the reliability of sim-

ulation results. A posteriori error indicators or estimators

might support the engineer to estimate the accuracy of the

simulation results. For automatic grid adaptation proce-

dures a posteriori error indicators are indispensable as

they are used as local adaptation criteria and as global in-

dicators when the grid has to be adapted.

In this project, different anisotropic a posteriori error indi-

cators for the drift-diffusion model have been developed to

be used in the grid adaptation procedure aiming at accu-

rate device terminal currents. They estimate errors of ei-

ther the system dissipation rate or the device terminal

currents, utilize solutions of local Dirichlet problems (Di-

richlet error indicators), or measure jumps of relevant den-

sity-like quantities (residual error indicators), and have

been proven useful for wide ranges of operating condi-

tions for different devices. The residual error indicator for

the dissipation rate turns out to be comparable to the Di-

richlet indicator in wide regions of the device and, hence,

provides a reasonable choice for practical adaptation cas-

es due to its low computational costs.

Comparison of the local residual, Dirichlet, and relaxed

Dirichlet error indicators J(DAGM), E(DAGM), and

D(DAGM), respectively, for the dissipation rate DAGM of a

reverse biased 1D pn-diode on an adaptively achieved

grid where E(DAGM) is almost equidistributed.

Construction of Isosurfaces

Personnel: Jens Krause

Funding: BBW, EU-IST-11433 MAGIC_FEAT

Partners: ISE AG, FhG-IIS-B, INRIA, ST Gentilly,

TU Wien

For meshing in process and device simulation it is in some

cases necessary to construct isosurfaces for certain data

functions, like pn-junctions or diffusion fronts. Given a

proper scaling of the problem, the level set zero of a func-

tion defined on the domain must be approximated as a tri-

angulated surface.

The task is similar to surface reconstruction in terrain

modelling, but in our problem the sampling is coupled to

the reconstruction process and for stability topological

correctness is important. The key idea of our approach is

that a volume triangulation is constructed first, which is

then iteratively refined until the isosurface is sufficiently

captured. Refinement points are found on edges that

cross the level set zero (because the function values at

end points have different signs). The exact location of the

refinement point is found such that the point lies on the

isosurface.

Triangles that are formed by three refinement points are

candidates for the isosurface. Ambiguous situations occur

when all four points of a tetrahedron are isosurface points.

To resolve these situations, further refinement points are

necessary. Due to this ambiguity resolution the separation

of nearby patches is possible.

Top: extracted pn-junction for a bipolar transistor, bottom:

view of the auxiliary volume triangulation at the end of the

procedure: due to the ambiguity resolution the two patch-

es can be separated.

60

Anisotropic Meshing in 3D

Personnel: Jens Krause

Funding: BBW, EU-IST-11433 MAGIC_FEAT

Partners: ISE AG, FhG-IIS-B, INRIA, ST Gentilly,

TU Wien

Fully general anisotropic meshing is still an open problem

in three dimensions. For process and device simulation

the task is even harder because the simulators in this field

require Delaunay meshes, which favour isotropic ele-

ments. However, research for anisotropic meshes (with

stretched elements) is conducted because they allow sim-

ulations with smaller meshes without losing accuracy (if

properly used).

The normal offsetting procedure is the construction of

anisotropic layers of elements at domain boundaries. This

is a limited solution towards anisotropy, but helpful in prac-

tice for problems with boundary layers. An example for ex-

treme boundary layers is the inversion channel in

MOSFET devices.

For problems with interior layers, the anisotropy of the

mesh can often be linked to isosurfaces, like the pn-junc-

tion or diffusion fronts. Then it is straightforward to couple

the algorithm that constructs isosurfaces with the normal

offsetting mesh generator, The construction of the isosur-

faces is the first step and the layering handles the isosur-

face like a material boundary.

Inside view of a MOSFET transistor with anisotropic

mesh at material interfaces (silicon-silicon oxide) and at

an isosurface (pn-junction).

Coupled Electro-Optical 3D

Simulation of a Tunable

Multisection DBR Laser

Personnel: Lutz Schneider, Andreas Witzig,

Michael Pfeiffer, Matthias Streiff;

ISE AG: Peter Regli, Gyorgy Kiralyfalvi

Funding: TOP NANO 21 5785.1 MQW, ISE AG

Partners: Bookham, ISE AG

Tunable lasers are expected to play an important role in

optical communications systems within the next few

years. They offer many compelling advantages over fixed

wavelength solutions in that they reduce device count, al-

low dynamic wavelength provisioning, and simplify net-

work control software. Distributed Bragg reflector (DBR)

lasers are promising candidates to satisfy the needs of the

market. From a modeling point of view these devices are

much more complex than Fabry-Perot lasers since they

are no longer homogenous in the longitudinal direction.

In this project, an approach to 3D simulation of multisec-

tion DBR lasers was developed. The optical field is formed

by interpolating between the normalized optical mode pat-

terns of several transverse cross-sections and modulating

with the mean optical field as obtained from the solution of

a 1D cavity problem using the transfer matrix method. The

laser is driven to its operating point by injecting current

into the gain section. Then current is injected into the

Bragg and phase sections in order to tune the wavelength.

Optical output power and lasing wavelength vs. terminal

current characteristics (top). Optical intensity and current

density distribution in the central region of a three-sec-

tion, three-electrode DBR laser (bottom).

61

Importing Tabulated Gain Data

Into a Laser Device Simulator

Personnel: Michael Pfeiffer;

Mathieu Luisier (Student)



Many efforts have been made to improve the accuracy in

simulations of III-V optoelectronic semiconductor devices.

Important aspects are the calculation of electronic band-

structures and the inclusion of many-body effects. Be-

cause of the complexity of such calculations, it would be

desirable to import pre-calculated information into avail-

able semiconductor device simulator.

In this project, the laser module of the device simulator

DESSIS has been extended to import tabulated gain data

(e.g. from microscopic simulations) into optoelectronic de-

vice simulations. Internally, a multidimensional spline in-

terpolation of the data is used to ensure highest speed

and excellent numerical convergence.

Top: Tabulated laser gain values for given carrier densi-

ties as function of device temperature and transition en-

ergy. Bottom: Tabulated laser gain values for given

temperature and transition energies as function of the

carrier densities.

Improved Quantum-Mechanical

Calculations for Laser Simula-

tions

Personnel: Michael Pfeiffer;

Stefan Odermatt (Student);

ISE AG: Andreas Wettstein



In DESSIS laser simulations, the quantum-mechanical

states of the charge carriers within quantum wells are cal-

culated by analytically solving a single band effective

mass Schr dinger equation assuming flat bands. This ap-

proach neglects any coupling between the quantum wells

(e.g. tunneling).

In this project, a general Schr dinger solver interface has

been implemented for the laser module of DESSIS. It al-

lows to extract valence and conduction band data of the

laser device for each applied bias voltage and to pass the

data to any plugged-in Schr dinger solver, thus enabling

the re-calculation of quantum well subbands, carrier

wavefunctions, and the laser gain in the case of built-in

and applied electric fields.

Quantum-mechanical electron wavefunctions in a sys-

tem of seven quantum wells for two different bias voltag-

es. Even for a low bias voltage (top) the wavefunctions

are not confined to just one well. For higher voltages (bot-

tom) the wavefunctions spread across the entire system.

62

Thermodynamic Laser Simula-

tion Including Heat-Sink and

Packaging

Personnel: Andreas Witzig, Michael Pfeiffer;

Bookham: Remo Badii, Berthold Schmidt

Funding: TOP NANO21 5785.1 MQW, ISE AG


Semiconductor lasers show significant dependence on

temperature. High power applications very often require

active temperature stabilization. However, the overall sys-

tem costs can be reduced with the development of un-

cooled devices.

In this project, numerical simulation is applied to optimize

the thermal management. The simulation structures have

been extended by additional non-semiconductor regions

such as the nitride layer, metallization or ridge protect

structures have to be accounted for.

In order to avoid that the simulation results depend on the

choice of artificial thermal boundary condition, non-uni-

form temperature distributions in the die and the heat sink

are treated in detail. The thermal equations are solved on

a large simulation domain, while electron and hole conti-

nuity equations as well as the laser equations are restrict-

ed to a smaller domain. In the metallization layers, the

current equations are solved and additional Joule heating

is accounted for.

Simulation results include external characteristics such as

current-power and current-voltage plots. In addition, the

field distributions of all optical and electronic variables can

be displayed in the cross section of the device, as shown

in the figure.

a) Optical intensity in a ridge waveguide laser.

b) Current density.

Confirmation of Thermal

Roll-Off Models in Laser

Simulations

Personnel: Valerio Laino, Andreas Witzig,

Michael Pfeiffer;

UCSB: Joachim Piprek

Funding: ETHZ, TOP NANO 21 5782.2

Photodetector, ISE AG

Partners: UCSB, Bookham, ISE AG

Numerical simulation of laser diodes allows to reduce en-

gineering cost of new devices and makes an easy optimi-

zation possible. The model must be consistent with the

measured data in electrical, thermal and optical aspects.

Experimental data is available for a multi-quantum-well la-

ser from Bookham. Prof. Piprek (UCSB) has performed an

analysis of the device using LASTIP.

The objective of this project is to use DESSIS to analyze

experimental results and in particular to validate Piprek s

explanation of roll-off in the laser output characteristic.

This phenomenon can be explained as the combination of

the decrease in the carrier mobility and the increase in Au-

ger recombination, both driven by temperature. Most of

the heat is generated in the ridge waveguide, but the heat

flows mainly into the substrate as the top is covered with

semi-insulating material. Mobility is a complex function of

lattice temperature, doping level and electric field, but be-

cause of the big number of unknowns, only the first two

dependencies are taken into account. Both two factors are

causes of the roll-off, but mobility plays a dominant role

because as temperature increases, mobility decreases

causing an increase in Joule-effect generated heat, giving

rise to a positive feedback that amplifies itself; the limit be-

comes the device thermal breakdown. With fixed thermal

condition, the Auger-driven roll-off is located at higher

temperature, with respect to the mobility-driven one.

Thermal roll-off for different simulated conditions.

63

Spectral Portrait of VCSEL

Eigenmodes

Personnel: Andreas Witzig, Matthias Streiff

Funding: TOP NANO 21 5103.1 VCSEL, ISE AG

Partners: ISE AG, Avalon, Uni Kassel

In recent years, vertical-cavity surface-emitting lasers

(VCSELs) have attracted a great deal of attention in opti-

cal fibre networks applications. In this project, the reso-

nance wavelength as well as the decay time of the

fundamental (A) and several higher order modes

(B, C,..., I) are calculated. The method is suitable for the

opto-electro-thermal simulation of VCSELs. However, for

the validation of the simulator, vertical-cavity air-gap filters

are investigated, since no carrier transport and no self-

heating have to be considered.

Top: Optical eigenmodes of a vertical-cavity air-gap filter.

Bottom: Spectral portrait of the same structure, consist-

ing of the resonance wavelength and the mode loss.

A Comprehensive VCSEL

Device Simulator

Personnel: Matthias Streiff, Andreas Witzig,

Michael Pfeiffer


Partners: ISE AG

This work deals with the design and implementation of a

self-consistent electro-thermo-optical device simulator for

vertical-cavity surface-emitting lasers (VCSEL).

The model is based on the photon rate equation ap-

proach. For the bulk electro-thermal transport a thermo-

dynamic model is employed in a rotationally symmetric

body. Heterojunctions are modeled using a thermionic

emission model and quantum wells are treated as scatter-

ing centres for carriers. The optical field is expanded into

modes that are eigensolutions of the vectorial electro-

magnetic wave equation with an arbitrary, complex dielec-

tric function. The open nature of the VCSEL cavity is treat-

ed by employing perfectly matched layers (PML). The

optical gain and absorption model in the quantum well ac-

tive region is based on Fermi s Golden Rule. The sub-

bands in the quantum well are determined by solving the

stationary Schr dinger equation and using a parabolic

band approximation for the electrons, light and heavy

holes.

The simulator was implemented as an extension to the

DESSIS technology CAD device simulator.

VCSEL device structure for simulation, and DC optical

power and terminal voltage versus terminal current char-

acteristics of AlGaAs(GaAs) 850nm oxide-confined

VCSEL device.

64

TCAD Based Design of VCSELs

Personnel: Matthias Streiff;

ISE AG: Pavel Tikhomirov


Partners: ISE AG

Today s efforts in VCSEL device design address low-cost

applications in wavelength division multiplexed (WDM)

optical fibre networks for data- and telecommunications.

As process technology matures, more options become

available to the device designer to choose from. Compre-

hensive technology CAD simulators are therefore becom-

ing essential tools to explore the design parameter space

for an optimum solution. At the same time, the indepen-

dence of the manufacturing process gained by using a

simulator lowers cost and the time required for a design

cycle.

The DESSIS device simulator with a VCSEL extension is

employed in this project to carry out optimization tasks. A

versatile Finite-Element (FE) formulation is employed. In

order to explore and develop novel and diverse VCSEL

device concepts, a flexible approach, such as the FE

method, turns out to be a requirement.

As an example, the procedure for optimizing the higher or-

der mode suppression in a VCSEL is presented.

AlGaAs(GaAs) 850nm oxide-confined VCSEL device

structure with dielectric aperture. Normalized intensity of

fundamental optical mode on logarithmic grey scale, and

contrast between resonant Q of fundamental and first or-

der mode.

Simulation of Energy Band

Profiles for PIN Photodetector

Structure

Personnel: Biju Jacob, Andreas Witzig;

Opto Speed: Nejla Bektas,

Markus Blaser

Funding: TOP NANO 21 5782.2 Photodetector,

ISE AG

Partners: Opto Speed, ISE AG

The demand in the speed and capacity of information pro-

cessing has been increasing higher and higher. Optical fi-

ber communications systems will be required to have a

high capacity of information transmission. Therefore, it is

necessary to design and fabricate pin photodetectors of

large bandwidth. The InGaAs/InP pin photodetector is

preferred because of its high speed, high quantum effi-

ciency, low voltage operation and ease of fabrication.

In this project, an InGaAs/InP pin photodiode structure

has been simulated by using the device simulator DES-

SIS. The energy band profile has been obtained. Further-

more, the capacitance-voltage characteristics of Opto

Speed pin photodetectors have been measured. The

comparison between measurement and simulation is

used to determine the material parameters of the photo-

detector model.

Energy band profiles of the pin structure at two different

values of reverse bias (red ⇒ —1V and blue ⇒ —2V) and

capacitance-voltage characteristics of the pin structure.

65

Simulation of Infrared

Quantum-Well Photodetectors

Personnel: Serguei Chevtchenko, Andreas Witzig,

Michael Pfeiffer

Funding: Fujitsu, ETHZ, TOP NANO 21 5782.2

Photodetector, ISE AG

Partners: Fujitsu

Photon absorption in multi quantum-well structures can

be used to build highly sensitive infrared photodetectors.

In this work, the incident optical field into one pixel of an

infrared sensor chip is simulated by the use of the finite-

difference time-domain (FDTD) method.

The detailed quantum-well analysis shows that normal in-

cident light is not absorbed as efficiently as light rays that

cross the quantum well in an acute angle. In conse-

quence, the light sensitivity can be increased with a de-

sign where the incident optical beam is reflected at a

metal backplane. Furthermore, the light beam is trapped

in a stratified semiconductor material so that the quantum

well region is passed several times.

Top: Schematic structure details for one pixel.

Bottom: Simulated optical intensity.

Photodetector Simulation with

Ray-Trace Generated Optical

Absorption

Personnel: Biju Jacob, Serguei Chevtchenko,

Andreas Witzig; Opto Speed: Nejla Bektas,

Michaela Klemenc

Funding: TOP NANO 21 5782.2 Photodetector,

ISE AG

Partners: Opto Speed, ISE AG

Photodetectors are essential components in the emerging

10Gb/s Ethernet and 40Gb/s telecom applications. By

proper design these devices can be optimized, either for

ultimate speed or for a good trade-off between responsiv-

ity and speed as dictated by the system requirements. In

comparison with an exclusive experimental procedure for

this optimization the TCAD methodology exhibits advan-

tages of reduced development costs and development

time.

The simulation of photodetectors essentially involves the

following two steps: (1) the computation of light intensity

(and hence the photo-carrier generation rate) within the

absorption region of the photodetector and (2) the deter-

mination of the terminal current using an appropriate car-

rier-transport model. For the case of a vertically

illuminated photodetector (VPD), in which interference ef-

fects are not important, the light intensity can be comput-

ed efficiently by a ray-tracing model. In this method the

incident plane electromagnetic wave is represented as a

bunch of rays. Ray-tracing then approximates the behav-

ior of the plane wave propagation in the device by follow-

ing these rays.

In this project a ray-tracing model has been developed to

simulate optical absorption in a In0.53Ga0.47As/InP p-i-n

VPD. The ray-trace generated photocarrier density was

fed into the electrical simulator, DESSIS, to obtain the

photodetector characteristics.

Optical ray-tracing allows to compute light intensity within

a complicated semiconductor geometry.

66

Simulation of Tunable Air-Gap

Filters

Personnel: Andreas Witzig, Matthias Streiff;

Uni Kassel: Friedhard R mer


Partners: ISE AG, Uni Kassel

For many applications it is desirable to have lasers with

electrically tunable emission wavelength. A promising tun-

ing concept is the vertical-cavity air-gap design. Prior to

the fabrication of vertical-cavity lasers, prototypes of ver-

tical-cavity air-gap filters are fabricated and characterized.

The filter structure consists of an air cavity, sandwiched by

two Bragg stacks. The resonance wavelength can be con-

trolled by electrically charging the top and the bottom mir-

rors, as shown schematically in the figure.

The fabrication of air-gap filters and lasers is technologi-

cally challenging. Tilted or bent mirrors strongly degrade

the optical mode in the device and the radiation field. In

this work, the consequences of convex and concave

bending of the top mirror stack has been investigated.

The numerical calculation of the optical field shows that

for convex mirrors, the optical field is focussed, and the

resonance wavelength changes only within a few nano-

meters. For concave mirrors, in contrast, the optical field

is de-focussed and consequently, the mode shows only

weak coupling into optical fibers. Furthermore, the mode

loss and the resonance frequency shift more in case of

concave mirrors.

Top: Tuning, tilt and bending of air-gap filters.

Bottom: Optical field in structures with concave and con-

vex bending of 20nm.

Development of a Drift-Diffu-

sion Solver with the Kinetic

Monte Carlo Method

Personnel: Eduardo Alonso

Funding: TOP NANO 21 5779.2 MOLDYN, ISE AG

Partners: ISE AG

The kinetic Monte Carlo method (KMC) is a powerful tool

for solving large systems of coupled diffusion equations in

3D. However, existing codes do not allow for the imple-

mentation of different diffusion models, they are inade-

quate for studying heterostructures and can calculate only

in parallelepipedic geometries. Moreover, although the

diffusion methodology appears to be well established,

there is no widely accepted scheme for treating the drift

term.

This project contributes to circumventing these shortcom-

ings, especially the lack of charged defects and field ef-

fects. In order to meet the flexibility requirements, it was

necessary to develop the code from the scratch. At the

moment, the code is an object oriented diffusion solver

with a module which determines the Fermi level locally

within the quasi neutral approximation. It uses ISE AG s li-

braries for reading complicated geometries and meshes

in DF-ISE format. Different species and diffusion models

may be defined for each material.

Electronic density of a boron spike as a function of depth

at 1000K calculated with our Fermi level module. As ex-

pected, there is a depleted zone at the spike and the con-

tribution from other native defects may be neglected.

67

Arsenic Activation and

Deactivation in Heavily

Doped Silicon

Personnel: Christoph M ller

Funding: ISE AG

Partners: ISE AG

Arsenic is the most widely used dopant for high concen-

tration n-type regions in silicon-based devices. The deac-

tivation of As during thermal annealing is, however, a

serious problem and subject of ongoing research. First

principles calculations offer insight into the underlying

atomic scale processes. Today, there is strong evidence,

both experimental and theoretical, that dopant-vacancy

(As-V) clustering is responsible for the As deactivation.

The main focus of this project is to examine the electronic

structure of various As-V complexes in crystalline silicon.

By evaluating defect states we can determine the degree

of deactivation of the dopant in such complexes.

Band structures and electronic states of arsenic-vacancy

clusters in silicon. Top, Left: The As1V complex exhibits

two acceptor levels and one donor level in the band gap.

Occupied bands are blue, empty bands are gray, and

partly filled bands (at 0K) are represented by dashed

lines. Right: The first acceptor state constitutes a bond

between the three Si atoms (blue spheres) adjacent to

the vacancy (in the center). The red sphere represents

the As. Bottom: The As3V complex acts as a single elec-

tron acceptor, the localization of the corresponding state

is depicted at the right.

Vacancy Mediated Arsenic

Diffusion in Silicon

Personnel: Christoph M ller

Funding: ISE AG

Partners: ISE AG

In order to increase the conductivity in the ever shallower

junctions of silicon devices, dopant concentrations are

pushed towards the solubility limit in the host crystal. In

heavily doped silicon, very complicated diffusion behavior

of the As has been observed, and diffusivities exhibit a

strong concentration dependence. A thorough under-

standing of the diffusion mechanisms at the atomic scale

is a prerequisite for the predictive simulation of dopant

profiles and dopant activation/deactivation in silicon pro-

cessing.

In this project, the complicated diffusion behavior of the

n-type dopant As in highly doped crystalline silicon is sub-

ject to investigation. By means of density functional theory

(DFT), different diffusion mechanisms are examined,

which provide temperature and doping concentration de-

pendencies of the diffusion process.

Percolation effect in highly As-doped Si: Potential energy

diagram for As-V as a function of the vacancy coordinate

with (blue dots) and without (red dots) another As atom

at the sixth neighbor site of As (represented by red

spheres in the upper picture). The corresponding vacan-

cy sites are indicated by white spheres.

68

Ab Initio Molecular Dynamics

Simulation of the Self-Intersti-

tial in Silicon

Personnel: Beat Sahli

Funding: TOP NANO 21 5779.2 MOLDYN, ISE AG

Partners: ISE AG

The properties of the self-interstitial in silicon have been

investigated by ab initio simulation methods many times.

Up to now there have been mainly static simulations. Only

recently long molecular dynamics simulations have be-

come possible due to the growing computing power and

the improvements of the simulation methods. With dy-

namic simulations it is possible to calculate properties

which could not be determined with only static simula-

tions. One example is the prefactor of the diffusion coeffi-

cient. It is the goal of this project to calculate the complete

diffusion coefficient of the self-interstitial diffusion in sili-

con as a function of temperature and to extract the migra-

tion energy and the prefactor.

The particle trajectories are created with the VASP code

developed at Vienna University. Since the particles which

form the self-interstitial defect may be exchanged during

the migration of the defect, it is necessary to use an algo-

rithm which determines the location of the defect from the

positions of all particles in the simulation box. Several

such algorithms have been implemented and compared.

In one of these methods all particles are assigned to the

closest site on a perfect reference lattice. The self-intersti-

tial is then assumed to be located at the perfect lattice site

which has two particles assigned to it.

The reference lattice is shown in grey. The Voronoi cell of

the red reference atom is shown in transparent red.

There are two silicon atoms assigned to this reference

site (also shown in red). Thus the self-interstitial is locat-

ed at the position of this reference site.

Parallel Incomplete LU-Factor-

ization on Shared Memory

Multiprocessors

Personnel: Stefan R llin

Funding: KTI-4922.1 Numerik II, ISE AG

Partners: ISE AG

The parallelization of iterative methods for large sparse

linear systems can reduce the runtime of a semiconductor

device simulation significantly. Iterative methods consist

of vector-vector operations, matrix-vector multiplications,

and the application of a preconditioner. The first two are

easy to parallelize on shared memory multiprocessors.

Unfortunately, it is not straightforward to parallelize incom-

plete LU-factorizations, which are used as precondition-

ers in semiconductor device simulations.

In this project, a technique from sparse direct methods

has been analyzed, which is solely based on the matrix in-

formation. Elimination trees are used to determine the de-

pendencies between the variables. With this information,

it is possible to compute a large part of the incomplete LU-

factorization in parallel.

The proposed strategy has been implemented and tested

on several shared memory multiprocessor architectures.

The measured results for the computation of the incom-

plete LU-factorization and for the application of it in an it-

erative method show good speedups for a modest

number of processors on all tested architectures.

Wallclock time for the computation of the incomplete LU-

factorization for three typical matrices extracted from 3D

DESSIS simulations. The results were conducted on a

Compaq AlphaServer with four 667MHz processors.

69

Research Projects

Physical Characterization

Coordinators:

Wolfgang Fichtner

Mauro Ciappa

70

Compact Modeling of

Integrated Power

Semiconductor Modules

Personnel: Kari Oila, Mauro Ciappa

Funding: BBW, EU-GROWTH-00275 HIMRATE

Partners: HIMRATE Consortium

Recent studies have shown that the implementation of a

crankshaft starter-generator, which performs start-stop

operations and regenerative braking, can lead to a 10%

reduction in the fuel consumption in particular in the urban

environment, where the improvement of the air quality is

of special interest. The starter-generator is driven by pow-

er semiconductor modules in high ambient temperatures,

making the thermal management of the system extremely

important.

A method for calculating the temperature evolution in pre-

selected points in the system has been realized using

compact modeling. Also a fast, semi-automated method

for calibrating the boundary conditions of the simulation

model to measurements has been generated.

A comparison between experimental and calibrated simu-

lation results shows that a CAD approach delivers reliable

results which can be used in thermal and reliability studies

to evaluate and compare different ideas already very early

in the design process.

The NMVEG ( New Motor Vehicle Emission Group stan-

dard) emission profile (top left), a temperature evolution

of one possible system using the same profile (top right)

and one of the systems under study (bottom).

Electrothermal Simulation of

IGBT Devices for Automotive

Applications

Personnel: Mauro Ciappa, Marco Chiavarini,

Flavio Carbognani;

Toyota: Yasushi Yamada

Funding: Toyota

Partners: Toyota

The thermal management (TM) is one among the most

relevant engineering activities when developing efficient

and reliable IGBT converters for hybrid vehicles. Current

solutions are still characterized by the use of single pack-

aged chips cooled by dedicated water cooling circuits. A

possible solution for improving the efficiency and for de-

creasing both the weight and cost of power converters is

system integration. At present, there are attempts to use

highly-integrated modules and to share the cooling circuit

with the internal combustion engine. Since the usual tem-

perature of the cooling water in internal combustion en-

gines is 90°C, this implies the use of high-temperature

semiconductors (190°C). This requires the optimization of

the TM with the aim to dissipate the thermal losses of the

devices and to avoid inefficient thermal interfaces. In par-

ticular, compact thermal models are needed to simulate

very accurately the temperature at the different package

locations as a function of realistic applications profiles.

Front: IGBT test vehicle used to develop the extraction

procedure. Backside: related thermal compact model.

71

Theoretical and Experimental

Accuracy in Delineating the

Electrical Junction by SCM

Personnel: Maria Stangoni, Mauro Ciappa;

Toshiba: Hidehiko Yabuhara

Funding: BBW, EU-RTN-00031 HERCULAS

Partners: HERCULAS Consortium

Scanning Capacitance Microscopy (SCM) is a scanning

probe technique to provide two-dimensional dopant pro-

files of semiconductors. It has been shown that the carri-

ers concentration in the vicinity of a depletion layer differs

from the one in the bulk.

In this project, the physics of the SCM signal generation

has been investigated in very low-doped epitaxial PN-

junctions by using a two-dimensional device simulator

(DESSIS) and the results have been compared with ex-

perimental data. Special attention has been paid to the ef-

fect that takes place as soon as the scanning SCM probe

approaches and enters the depletion region of a bipolar

sample. Different regions of interest have been defined af-

ter the simulation by analyzing the obtained Capacitance

versus Voltage curves. These regions are related either to

a partial or to a full interaction of the depletion region un-

derneath the tip with the other side of the junction. The lo-

cation of a symmetrical behavior inside the space charge

enables the definition of the maximum theoretical lateral

resolution in delineating the electrical junction.

Top: Scanning Capacitance Microscopy measurement

on a PN-junction, the P (pink) doping is 1E15cm—3 and

the N doping (yellow) 5E15cm—3. The depletion region is

the transition between them. Bottom: Regions of interest

across a junction defined by simulation, each one is re-

lated to a different type of the C(V) output characteristics.

Imaging of Deep-Submicro-

meter Bipolar Devices by Scan-

ning Capacitance Microscopy

Personnel: Maria Stangoni, Mauro Ciappa

Funding: SNF, R EQUIP 20-64539.01

Partners: HERCULAS Consortium, Veeco

In order to evaluate the lateral resolution of a new gener-

ation Scanning Capacitance Microscope equipment, a

0.35μm NPN vertical bipolar transistor has been mea-

sured. The SCM measurement describes the variation of

the local free carrier concentration, the more intense the

signal (light regions), the lower the doping concentration.

Darker regions may represent both higher doping concen-

trations and space charge zones.

For the measurement the sample has been cross-sec-

tioned, polished, and oxidized with a wet technique. The

probe used is a metal coated cantilever with a tip radius of

about 20nm. Abrupt edges must be avoided in this case

because of the wear out of this kind of probe. Once the de-

vice is located on the chip, the first image is taken, de-

scribing the expected structure. A successive zoom into

the base area shows a base length of about 0.35μm. This

is in excellent agreement with the manufacturer data, con-

sidering the fact that the space charge zone between

base and collector, represented in dark, is mostly extend-

ed in the less doped base region. The measurement re-

veals the thin dark line separating emitter and base, which

locates the junction space charge position.

Top: Zoom into the area of interest. Bottom, Left: Overall

SCM image of the transistor, Right: Description of the

transistor structure.

72

Quantitative Dopant Profiling in

Silicon Carbide by Scanning

Capacitance Microscopy

Personnel: Lorenzo Ciampolini, Mauro Ciappa;

Uni Catania: Filippo Giannazzo

Funding: BBW, EU-RTN-00031 HERCULAS

Partners: HERCULAS Consortium

One of the crucial steps for the assessment of planar tech-

nologies in Silicon Carbide (SiC) is selective doping. The

total dopant activation is generally determined by sheet

resistance and by Hall measurements. In this project, the

dopant profiles in n-type 6H-SiC implanted with N+ ions

have been measured for the first time by Scanning Capac-

itance Microscopy (SCM). The obtained carrier profiles

have been accurately quantified by calculating a complete

set of C-V curves by simulation of the measurement setup

with SCaMsim, followed by the extraction of the system

response characteristic as a function of the local carrier

concentration. The discrepancy observed to occur be-

tween the SCM data and the corresponding Secondary

Ions Mass Spectroscopy (SIMS) profiles is explained by

the fact that SCM is sensitive on the local free carriers

concentration, i.e. on the local concentration of electrically

activated dopant ions, while SIMS detects the concentra-

tions of the chemical species only.

Concentration profiles obtained by SCM and SIMS. The

active fraction in (a) is 10.2%, while in (b) it is 9.6%.

Simulation and Design of

Silicon Test Structures for Very

High Temperatures

Personnel: Chiara Corvasce, Davide Barlini,

Mauro Ciappa

Funding: BBW, EU-IST-2000-30033 DEMAND

Partners: TU Wien, Infineon, Uni Bologna,

ISE AG

The European project DEMAND aims at developing an in-

tegrated methodology for the design of ESD protections

with enhanced robustness. This is pursued by using the

Backside Laser Interferometry to monitor locally the tem-

perature evolution during the electrostatic discharge as

well as by improving device simulations suitable for the

high temperatures occurring during the stress event.

The development of physical models in the 500—1000K

temperature range requires the design of self-heating and

optically heated test structures. Basing on dedicated sim-

ulations, three test chips have been drawn including resis-

tive heaters, optical heaters, and polysilicon temperature

sensors. The first generation of test structures using alu-

minum interconnects has been already integrated. Due to

the limitations introduced by the aluminum interconnects

and by the thermal generation within the junction insula-

tion in the active and passive devices, the use of tungsten

based and SOI technologies is under evaluation.

Test chips layout and silicon sample SEM photograph.

73

Investigation of VCSEL

Temperature Profiles Using

Scanning Thermal Microscopy

Personnel: Matthias Streiff, Mauro Ciappa;

Avalon: Sven Eitel;

Veeco: Peter De Wolf


Partners: ISE AG, Avalon, Veeco

The aim of this project is to verify the thermal properties

of the VCSEL device structure, and the thermal boundary

conditions of the computational domain. This information

is needed to validate the calibration of the DESSIS elec-

tro-thermo-optical device simulator. Since the tempera-

ture distribution within the VCSEL cavity has a substantial

effect on the shape of the optical mode (thermal lensing),

this is a crucial aspect of the simulator calibration proce-

dure.

Scanning thermal microscopy (SThM) is employed to ob-

tain a 2D spatially resolved temperature profile of the VC-

SEL surface using scanning probe microscope (SPM)

techniques. SThM uses an SPM probe with a miniature,

integrated, temperature sensitive thin film resistor. The

change in the probe resistance is measured by a resistive

bridge type circuit and is used to establish the thermal im-

age. Absolute temperature values are obtained by cali-

brating the system with a reference heat source.

Temperature resolution is around 0.5K and spatial resolu-

tion approximately 200nm.

Temperature distribution obtained from a scan in the ap-

erture of a 850nm oxide-confined VCSEL at different la-

ser currents. The lasing threshold of the VCSEL is at

1mA.

Optimization of Substrate

Contact Placement in Smart

Power ICs

Personnel: Michael Schenkel

Funding: ETHZ

Partners: Bosch, ISE AG

Substrate currents due to inductive load recirculation in

motor control H-bridges are difficult to control because of

their distributed and three-dimensional character, the

crosswise injection, and the injection of majority and mi-

nority carriers. Three-dimensional device simulation is

best suited for the investigation of substrate current ef-

fects and has been used to optimize the placement of sub-

strate contacts. The simulation tool was calibrated and

validated with measurements prior to the optimization.

A full-chip 3D simulation structure with four power transis-

tors (L1, L2, H1, H2), substrate contacts (LSC1, LSC2,

SC, back) at different positions, and a substrate current

collecting n-tub has been set up and realistic substrate

current injection has been simulated. The bottom figure

shows that the capacitive coupling during switching and

the quasi-static n-tub current depend in a counteracting

manner on the distance of the grounded substrate contact

to the n-tub. Design recommendations therefore strongly

depend on the specific configurations and conditions.

Top: Realistic simulation structure of a motor control H-

bridge during recirculation with substrate contacts at dif-

ferent positions. Bottom: Parasitic n-tub currents for three

different substrate grounding configurations.

74

Device Simulation of Immunity

Test Transients in Automotive

Applications

Personnel: Markus Schaldach

Funding: Bosch, MEDEA+ ASDESE

Partners: Bosch

Integrated circuits in automotive applications are subject

to significant electrical disturbances. Transients originat-

ing from various sources such as the ignition system are

coupled into electronic devices. Immunity against such

transients is mandatory for ICs in the automotive environ-

ment to assure safe operation of the vehicle. Immunity

against transients on supply lines is tested according to

the ISO 7637 test standard.

Transient 2D device simulations of a Smart Power test

chip subject to ISO test pulses of type 3a and 3b were

conducted. The circuit under investigation was a simpli-

fied ESD protection circuit. It comprised three intercon-

nected devices sharing a common substrate: a diode, a

DMOS transistor and a pull-down resistor. The electrical

isolation of the three devices was attained using junction

isolation. The cross section of the entire test chip was

modeled leading to more than 70000 mesh points.

ISO 7637 test pulses of type 3a and 3b are characterized

by voltage changes of up to 150V within 5ns. The electri-

cal behavior of the test circuit during these harsh tran-

sients is heavily influenced by avalanche generation,

carrier injection into the substrate, and displacement cur-

rents across p-n junctions. An increase of device robust-

ness against transients was observed in both

measurements and simulations when using grounded

substrate contacts.

Cross section of the test chip showing the carrier gener-

ation (depicted in blue) and recombination (depicted in

red) in the DMOS transistor and its vicinity. The thickness

of the cross section is 100μm. Carriers generated in the

drain and bulk regions of the DMOS transistor (top) dur-

ing an ISO 7637 test pulse are injected deeply into the

substrate where they recombine.

Device Simulation and Back-

side Laser Interferometry in

ESD Protection Development

Personnel: Ulrich Glaser;

Infineon: Kai Esmark

Funding: Infineon, ETHZ

Partners: Infineon, TU Wien

A precise understanding of the behavior of the active de-

vices and possible protection elements under ESD stress

is inevitable for the development of ESD protection con-

cepts. Methods are required which reveal information

about physical relevant parameters. Today, ESD device

simulation has been proven to be a powerful tool for the

ESD engineer. A large variety of physical parameters un-

der ESD stress can be deduced and the high current char-

acteristic of active elements and protection elements can

be nicely reproduced by means of 2D and 3D device sim-

ulation. Therefore, based on well-calibrated doping pro-

files, ESD protection concepts can be deduced from

device simulation in a phase where no silicon is available.

Backside laser interferometry (BLI) can give experimental

access to important parameters like carrier concentration

and temperature during an ESD pulse. A 2D thermal map-

ping of a device or even of large complex protection cir-

cuits can be done easily with BLI. ESD device simulation

and BLI can be used very successfully as complementary

methodologies during the different phases of the ESD

protection concept development.

Triggering behavior of a 100μm wide ggNFET along the

width x of the device for different stress currents Id. Part

a) shows the simulated current flux under the gate of the

NFET and part b) demonstrates the measured phase

shift distribution. The parasitic bipolar transistor is trig-

gered only in certain parts along the width of the ggNFET

for stress levels below 5mA/μm.

75

Research Projects

Bio—Electromagnetics

and

Electromagnetic Compatibility

Coordinator:

Niels Kuster

(Adjunct Professor, Department of

Information Technology and Electrical Engineering)

76

Development and Improvement

of Recipes for Head and Body

Tissue Simulating Liquids

Personnel: Neviana Nikoloski;

IT IS: Darko Saik, Niels Kuster

Funding: ARIB

Partners: IT IS

Assessment of the real-world exposure from wireless

communications equipment with electromagnetic safety

guidelines is a task of greatest importance. One of the

open issues concerning the existing procedures for com-

pliance testing of mobile telecommunications equipment

is the development of new recipes for homogeneous head

and body tissue simulating liquids (or emulsions) at fre-

quencies above 1900MHz consisting of only nontoxic and

nonaggressive substances. The study of a wide variety of

commercially available products and chemical substanc-

es provided deep insight into the main relaxational pro-

cesses responsible for the dielectric properties of a

material in general, as well as the proper chemical struc-

ture of the ingredients forming an experimental mixture for

enabling its targeted behavior. The new types of liquid

compositions which were developed (oily emulsions i.e.

oil-in-water solutions), have many advantages in compar-

ison with the recipes for tissue simulating liquids defined

in the current standards, since they are nontoxic, nonag-

gressive to the phantom and probe materials at room tem-

perature, easily disposable, and have stable parameters

for a much wider frequency range, within which the devi-

ation from the target dielectric parameters is less than

0.2dB or 5%.

Permittivity and conductivity (S/m) for oily emulsion, wa-

ter, and fructose compared to the target dielectric proper-

ties for head tissue equivalent liquids.

Risk Assessment: Dosimetry of

Exposure Systems for Toxicity/

Carcinogenicity Studies in Rats

Personnel: Neviana Nikoloski, Sven Ebert,

Walter Oesch;

IT IS: J rg Fr hlich, Niels Kuster

Funding: BBW, IT IS Partners

Partners: PERFORM A Consortium

Two types of exposure systems for rats operating at

902MHz and 1747MHz were developed as part of the

project PERFORM A which, under the Fifth Framework

Program of the European Union, addresses the major

long-term animal studies of the WHO agenda on possible

carcinogenic and co-carcinogenic effects of RF radiation

in animal models. The dosimetric requirements were (1)

as uniform as possible distribution of the specific absorp-

tion rate (SAR) within the animal, with the whole body

SAR varying less than 2dB over its lifetime, (2) well spec-

ified SAR distribution of each organ, (3) as minimal as

possible deviation of the whole-body SAR between ani-

mals in the same wheel. Both exposure systems were

carefully evaluated by numerical and experimental

means. The numerical dosimetry, performed using the Fi-

nite-Difference Time-Domain (FDTD) simulation platform

SEMCAD including its thermal solver extension, enabled

the implementation of a power control function for adjust-

ing the incident exposure as a function of the animal

weight in order to guarantee fairly uniform exposure dur-

ing the entire lifespan of the animals. The experimental

verification of the results was conducted using the near-

field scanner DASY4 equipped with the latest probe tech-

nology, including RF transparent temperature probes. The

highest exposure level was determined in a pre-study by

temperature measurements fixing the exposure levels for

the main study at 4W/kg for the high dose, one third or

1.33W/kg for the mid dose, and 0.44W/kg (1/9) for the low

dose.

PERFORM A exposure system for rats at RCC in Basel,

Switzerland.

77

Risk Assessment: Detailed

Dosimetry of TEM Cell Expo-

sure Setup for In Vitro Studies

Personnel: Neviana Nikoloski, Joachim Goecke,

J rgen Schuderer;


Funding: IT IS Partners

Partners: PERFORM B Consortium

PERFORM B is a two-year project that specifically ad-

dresses in vitro and in vivo replication studies recom-

mended by the WHO agenda. One of the proposed

studies includes the verification of the findings reported by

the Litovitz research group (Penafiel et al., 1997, Bioelec-

tromagnetics, 18, 132—141). The objective of this study

was to design, optimize, manufacture, and characterize a

TEM (Transversal Electromagnetic) cell based in vitro ex-

posure setup which can provide the same exposure con-

ditions as the original setup, but with greatly improved

parameter control. The carrier frequency is 835MHz, and

the modulation corresponds to that of DAMPS (IS135).

The setup consists of two modified TEM cells (computer-

controlled assignment for exposure and sham), and is

housed in a 37°C water-jacketed incubator. Each cell

holds four 25cm2 flasks filled with 5ml of cell culture, as in

the original experiments. The exposure will be software

controlled, and all relevant environmental parameters will

be monitored continuously during the experiment. The

evaluation and optimization of the setup was performed

using the Finite-Difference Time-Domain (FDTD) simula-

tion platform SEMCAD including its thermal solver exten-

sion for the numerical assessment of the temperature

load. The results were carefully verified using the near-

field scanner DASY4 equipped with the latest probe tech-

nology (H-field, E-field, dosimetric and temperature

probes). An RF-transparent probe was also used for the

experimental determination of the temperature load.

TEM cell exposure setup for in vitro replication studies at

UKU in Kuopio, Finland.

Risk Assessment: Dosimetry of

the RF Circular-Waveguide

Setup for In Vivo Studies


IT IS: J rg Fr hlich, Niels Kuster;

SPEAG: Cristiano Pianezzi



The study had the objective of evaluating a waveguide

system designed for the chronic exposure of rats at

2450MHz ISM frequency and is part of the project PER-

FORM B: a two-year project that specifically addresses in

vitro and in vivo replication studies recommended by the

WHO agenda. The system consists of a wire-screen cylin-

drical waveguide previously developed to operate at

918MHz and modified on both sides by additional

2450MHz waveguides with built-in circular polarizer for

exciting the circularly polarized wave. Each exposed ani-

mal is placed in a plastic chamber in the middle of the

guide. The experimental dosimetry, performed using the

near-field scanner DASY4 equipped with the latest probe

technology, verified the results reported by A. W. Guy et

al. [Radio Science 14 (1979)] and H. Lai [Bioelectromag-

netics 16:207—210 (1995)] that the system provides rela-

tively constant and easily quantifiable coupling of

microwave energy to each animal, regardless of their po-

sition and posture. The exposure system will be used in a

replication study of the original experiment of H. Lai, who

reported a deficit in spatial reference memory in rats

caused by acute exposure to pulsed 2450MHz micro-

waves (pulse with 2 s, 500 pulses/s, average power den-

sity 2mW/cm2).

Specific absorption rate (SAR) distribution in a numerical

rat phantom used for dosimetrical evaluation of the expo-

sure setup.

78

Improved Methodology for

Base Station Site Evaluation


IT IS: Axel Kramer, Niels Kuster

Funding: FNM, TDC

Partners: IT IS

With the increasing use of wireless technologies great so-

cial concern has risen about possible health effects that

might be caused by the interaction of electromagnetic

waves with the human body. The objective of this study is

to provide the missing scientific data and methodologies

for measurement techniques which allow the evaluation of

non-ionizing exposure in apartments and offices. Engi-

neering tools enabling the accurate measurement of inho-

mogeneous field distributions have to be developed,

resulting in measurement recommendations with mini-

mum measurement uncertainty. A semi-automated mea-

surement tower for a 3D high-resolution mapping of

inhomogeneous indoor field distributions was designed. It

consists of two horizontal platforms, separated by one

meter in height and carrying four miniaturized field probes

each. Using this setup, the reliability of calibration meth-

ods for antennas used for measuring inhomogeneous

fields as well as determining the influence of the measur-

ing operator on the antenna response will be investigated.

Validation of the recommended protocols for indoor emis-

sion measurements by comparison of numerical simula-

tions, high resolution 3D field mapping, and conventional

antenna measurements shall result in development of im-

proved measurement guidelines and recommendations to

local and federal authorities and international standard-

ization committees.

Simulation of inhomogeneous field distribution for testing

the averaging volume of conventional measurement an-

tennas.

Full Wave Time Domain

Simulation of a VCSEL in

Three Dimensions

Personnel: Andreas Christ, Andreas Witzig,

Matthias Streiff;

IT IS: J rg Fr hlich

Funding: KTI-4789.1 SEMCAD++, IT IS, SPEAG

Partners: IT IS, SPEAG, ISE AG

Traditionally, the update coefficients of the Finite-Differ-

ence Time-Domain (FDTD) algorithm at material interfac-

es are calculated by the arithmetic mean of the material

properties of both sides. This approach leads together

with the dispersion error of the algorithm to numerical in-

accuracies of the reflection coefficient depending on grid

resolution and frequency.

Within the bounds of this project, a novel method has

been proposed to calculate the update coefficients such

that the FDTD algorithm exactly fulfills the boundary con-

ditions at a frequency of optimization. Further, it compen-

sates the grid dispersion error for a preferential

propagation direction. The method has been applied to

the 3D-simulation of a vertical cavity surface emitting la-

ser (VCSEL). These lasers use highly reflective Bragg

mirrors to keep their cavity active. The numerical model-

ing of these mirrors is very sensitive to the errors in phase

an reflection. Using the proposed methods, the mirrors

can be modelled with a significantly coarser grid resolu-

tion, saving a factor of three of the required memory and

a factor of eight of the simulation time compared with the

conventional FDTD formulation. The resonance frequen-

cy of the fundamental mode and the quality factor of the

cavity were calculated and are in excellent agreement

with reference results from a body-of-revolution finite-ele-

ment code in cylindrical coordinates.

Field distribution in the VCSEL at the resonance frequen-

cy of the fundamental mode with the conventional FDTD

algorithm (left) and with correction (right).

79

Comparative Analysis of Ana-

tomical Head Phantoms for the

Compliance Testing of MTE

Personnel: Andreas Christ, Nicolas Chavannes,

Neviana Nikoloski;

IT IS: Anja Klingenb ck, J rg Fr hlich


Partners: SPEAG, IT IS

A new human head phantom has been introduced by var-

ious standardization commissions for compliance testing

of handheld mobile telecommunications equipment

(MTE). This Specific Anthropomorphic Mannequin (SAM)

phantom has been compared to several high-resolution

anatomical head models of different ages, sizes, and sex-

es. The anatomical head models (see figure) were de-

rived from MRI scans (three year old child, European

female) and from the Visual Human Project (adult male).

The specific absorption rate (SAR) was evaluated for the

standard test positions according to the procedure de-

fined by IEEE and CENELEC. The test devices used were

1) a generic mobile phone equipped with different anten-

na types, and 2) a CAD model of a commercial mobile

phone. The results for SAM and the Generic Head Phan-

tom have been verified by experimental means. The find-

ings confirm that the SAM phantom filled with the

proposed tissue simulating liquid constitutes a conserva-

tive approach.

Head phantoms: a) three year old child, b) European

female, c) adult male, d) SAM.

Analysis of the Numerical Prop-

erties of the FDTD Algorithm at

Dielectric Material Interfaces

Personnel: Andreas Christ;

IT IS: J rg Fr hlich



Boundary methods for electromagnetic field simulation

such as the Generalized Multipole Technique or the Meth-

od of Moments are based on enforcing the continuity of

the electromagnetic fields and fluxes on the material inter-

faces. In contrast, domain methods, such as finite ele-

ments or the Finite-Difference Time-Domain (FDTD)

method, discretize the whole computational volume with

differently located vector field components. For these

methods, the computational algorithms have to assert

whether the boundary conditions for the continuity of the

fields at the material interfaces are fulfilled.

Within the bounds of this project, the numerical reflection

coefficient of the FDTD algorithm has been derived ana-

lytically. This enables the detailed characterization of the

field behavior in the grid at material interfaces. It is shown

that the numerical error of the reflection coefficient de-

pends on a large number of parameters, such as the grid

resolution, time step and angle, frequency, and polariza-

tion of the incident wave. In conclusion, the FDTD algo-

rithm does not inherently fulfill the boundary conditions for

the continuity of the fields. In this context, the numerical

total reflection and the Brewster angle were rigorously

studied as well as the discretization influences on the spe-

cific absorption rate (SAR). The developed techniques for

the analysis of the numerical errors serve as a basis for

the formulation of optimized FDTD coefficients.

Numerical and analytical reflection coefficient at a dielec-

tric half-space for TM-polarization at different grid resolu-

tions.

80

Modeling of Advanced Antenna

Applications Using FDTD

Simulations

Personnel: Peter Futter, Nicolas Chavannes,

J rg Fr hlich, Niels Kuster



One of the particular aims of the KTI-sponsored SEM-

CAD++ project was the provision of an efficient numerical

tool for the analysis, design, and evaluation of real-world

antenna structures by application of the Finite-Difference

Time-Domain (FDTD) method.

After having greatly enhanced and widened the SEMCAD

simulation platform s features, within this study the specif-

ic topic is addressed using different antennas which are

well characterized either by different numerical methods

or commercially available transmitters. All calculated re-

sults were consequently compared to high precision mea-

surements using the latest tools available as well as to

data obtained from other software vendors. Guidelines

were then derived with respect to geometrical representa-

tion, feed point modeling as well as necessary grid reso-

lution. Excellent agreement between all examined data

has been obtained for the antenna structures evaluated

thus far. This further substantiates the applicability of

user-friendly simulation environments, supported by en-

hanced modeling capabilities for general and reliable an-

tenna design.

Antenna applications considered in this study.

RF Characterization of MTE

Using a Combined NF Measure-

ment-Simulation Toolset

Personnel: Peter Futter, Nicolas Chavannes,




Today s radio frequency (RF) engineers are heavily chal-

lenged to produce more and more efficient devices, re-

vealing a definite demand for new tools, effectively

supporting R&D procedures. A recent study (IIS Research

Review 2001, p. 80) demonstrated the straightforward

ability to include TCAD tools based on the Finite-Differ-

ence Time-Domain (FDTD) method into the design pro-

cess of mobile telecommunications equipment (MTE).

This issue shall be further addressed with respect to all

relevant performance parameters needed in order to in-

vestigate the electromagnetic (EM) behavior of such de-

vices prior to the prototype phase. CAD data sets of

commercial mobile phones are used as a basis for the nu-

merical modeling process within the simulation platform

SEMCAD, which incorporates the ability to import CAD

data together with high-resolution anatomical models.

The devices can be analyzed for different modes of oper-

ation, e.g., in free-space as well as in the vicinity of vari-

ous biological scatterers. Furthermore, all results are

compared to measurements using the DASY4 near-field

scanner. This study delivers additional insights with re-

spect to the level of needed modeling detail intensity and

the degree of accuracy in order to easily apply TCAD tools

within industrial R&D processes.

Mobile phone under investigation.

81

Improved Modeling of Thin PEC

Sheets in the FDTD Method

Personnel: Stefan Benkler;

IT IS: Nicolas Chavannes, Niels Kuster



Although the Finite-Difference Time-Domain (FDTD)

method has proven its wide suitability regarding electro-

magnetic (EM) simulation capabilities, for extremely high

ratios with respect to wavelength and the smallest possi-

ble spatial extension of the geometrical structure, the ap-

plication of special FDTD subcell models is necessary. In

particular for thin structures like wires, sheets, and slots,

a straightforward modeling by the common FDTD scheme

would quickly lead to limitations of computational resourc-

es. By straightforward application of coarsely resolved

grids to geometries with spatial subcell extension, the di-

mension of the structure will be determined by the grid

resolution, which hardly ever matches its actual dimen-

sion.

The aim of this project is to investigate and implement dif-

ferent models of thin PEC (Perfect Electric Conductor)

sheets in the widely used FDTD algorithm. The model

takes advantage of analytical quasistatic solutions near

PEC edges. It incorporates these solutions by integrating

Maxwell s equations in order to achieve a special update

scheme. The novel schemes and implementations are

thoroughly tested on the basis of various applications in-

corporating thin PEC structures such as the PCBs of mo-

bile phones, patch antennas, etc., and are finally

benchmarked to data obtained from other numerical

schemes as well as experimental results from the DASY4

near-field scanner.

PCB of a commercial mobile phone with its antenna.

Simulation of Temperature

Increase in Brain Tissues

During Usage of Mobile Phones

Personnel: Nicolas Chavannes, Theodoros Samaras,




It is known that in setting the standards for limiting human

exposure to non-ionizing radiation, thermal effects play a

significant role. Therefore, it is always useful to assess the

temperature increase inside tissues under various expo-

sure conditions.

The aim of this project is to numerically calculate the tem-

perature increase in the heads of mobile phone users and

deliver a reliable thermal model for the respective expo-

sure situation. The Finite-Difference Time-Domain

(FDTD) based SEMCAD simulation platform is used for all

computations, which offers the possibility to perform elec-

tro-thermal simulations with its thermal solver extension,

implementing the Bio-Heat Transfer Equation with con-

vective boundary conditions. The electromagnetic power

absorbed inside the tissues acts as the main heat source

for the calculations. Calculations are performed using nu-

merical head phantoms of the finest resolution based on

MRI scans as well as different transmitter structures. The

physiological parameters of thermoregulation (e.g. blood

flow rate) are varied in the models, in order to find chang-

es in temperature rise. This is a critical part of the study in

order to produce valid thermal models, since literature on

the respective physiological parameters is scarce.

Temperature distribution in the head of an adult mobile

phone user (generic phone at 1800MHz).

82

Development of a Novel FD

Quasi-Static Solver for Low

Frequency Applications

Personnel: Nicolas Chavannes, Harald Songoro,

Niels Kuster



Within this project, in the context of the health risk assess-

ment of electromagnetic field exposure, a novel Finite-Dif-

ference Time-Domain (FDTD) method has been

developed to overcome the shortcomings of the Yee-

FDTD and ADI-FDTD methods at low frequencies. Typical

applications of interest are the calculation of induced cur-

rents in the leads of electronic implants, the calculation of

the field distribution of defibrillator pulses in anatomically

realistic human phantoms as well as the evaluation and

performance optimization of filters for electronic implants.

The developed FDTD method is unconditionally stable

and combines high order accuracy, implicitness and stag-

gering, which leads to a cost-effective finite difference

scheme. The use of a state-of-the-art pre-conditioned

BicgStab(l) to solve the highly sparse linear system offers

competitive performance with respect to other FDTD

methods. Moreover, the new solver will be fully integrated

within the SEMCAD simulation framework as well as opti-

mized for simulation of complex inhomogeneous anatom-

ical models.

SEMCAD simulation: numerical modeling of peacemak-

er and anatomical details in the human chest region.

Risk Assessment: TA Project

Pervasive Computing

Personnel: Nicolas Chavannes, J rg Fr hlich,

Niels Kuster

Funding: TA-SWISS

Partners: IT IS, EMPA, IZT, IfW, CiS

The Center for Technology Assessment TA-SWISS at the

Swiss Science and Technology Council issued a project

entitled The Principle of Precaution in an Information So-

ciety: Pervasive Computing and its Effects on Health and

on the Environment . The objective of this study is to

present possible scenarios for the evolution of the new in-

formation and communications technologies, with a spe-

cial focus on pervasive computing. Based on the

outcome, measures will be recommended in order to cope

with the possible risks of these novel techniques.

In addition, TA-SWISS issued a mandate to IT IS to pro-

vide an estimation of the public s future exposure gener-

ated by current and future communications technologies.

The assessment of future exposure is carried out by re-

viewing current safety guidelines and their physical and

biological basis, including limitations based on the latest

research results. Subsequently, the new technologies are

evaluated with respect to their electromagnetic character-

istics, and the expected exposures are analyzed in terms

of exposed tissues, induced RF field strengths, amplitude

modulation, and ELF fields. The study will further identify

scientific gaps with respect to a conclusive exposure as-

sessment of pervasive computing.

Pervasive Computing: possible effects on health and on

the environment?

83

Risk Assessment: Exposure

Setup for Studies of Acute

Effects on Mice at 900MHz

Personnel: Sang Jin Eom, Neviana Nikoloski;

IT IS: J rg Fr hlich, Jean-Claude Gr bli,

Niels Kuster


Partners: Perform B Consortium

The objective of this study was the development of an ex-

posure setup for whole-body exposure of mice. The eval-

uation and optimization of the setup was performed using

the advanced Finite-Difference Time-Domain (FDTD)

simulation platform SEMCAD and the near-field scanner

DASY4. The specific absorption rate (SAR) assessment

with a temperature method was performed with a highly

resistive thermistor probe. The design concept of the Fer-

ris Wheel was adopted. The radius of the wheel was opti-

mized to house at least four mice and maximize

suppression of higher modes. The location of the animals

was optimized to achieve similar exposure conditions as

in the PERFORM A mouse studies. Good performance

was achieved for a wheel radius of 166.5mm, housing

eight mice. The exposure is controlled using calibrated E-

field sensors located near the antenna in the bottom plate.

Radial isotropy was assessed using temperature mea-

surements to be within 0.2dB. Simulation and measure-

ment results were compared with respect to field

distribution and whole-body SAR. Furthermore, four high-

resolution anatomical mouse models together with four

dummies were simulated, representing the final arrange-

ment used for the experiments. The whole-body exposure

was assessed, as well as organ and tissue specific SAR

values.

Experimental and numerical evaluation of the exposure

system for acute effects on mice.

Standards: Scaling of

Exposures from Animal to

Human

Personnel: Sang Jin Eom;


Funding: BfS, TDC


One issue of great concern within risk assessment of mo-

bile telecommunications devices regarding compliance

testing and design of bio-experiments is the ratio between

the spatial peak SAR and the whole body SAR within ex-

posed animals and humans. Since measurements within

living bodies are not easily realizable, appropriate numer-

ical and physical models have to be developed. Accurate

and reliable numerical assessment of SAR distributions

within animals and the human body require high resolu-

tion anatomical models. The development of these ana-

tomical models requires special techniques. Previous

studies have demonstrated that resolutions of larger than

1mm are insufficient to achieve reliable estimates of the

SAR in animals. The resolution of such models should be

at least 0.5mm, preferably better than 0.1mm.

The objective of this study is the development of appropri-

ate numerical high-resolution anatomical models (mouse,

rat, human) and the evaluation of the related SAR distri-

bution at the technical relevant frequencies. Different po-

larizations (frontal, dorsal, and lateral) with respect to an

incoming plane wave are examined and the SAR distribu-

tions as well as the averaged SAR of animal and human

models are compared using the SEMCAD simulation en-

vironment.

SAR distribution in a slice through the body at 450MHz,

900MHz, and 1800MHz (from left to right).

84

Pilot Study Time-Domain Field

Sensors

Personnel: Oliver Zehnder, J rgen Schuderer;

IT IS: Axel Kramer, Niels Kuster

Funding: IT IS, TDC

Partners: IT IS, SPEAG

There is a great demand for near-field sensors in various

areas of research and industrial applications. Due to the

increased clock speed and miniaturization in wireless ap-

plication devices, EMI/EMC problems will significantly in-

crease. With an analysis tool like the Time-Domain-

Sensor problem zones can be localized and analyzed in

early design phases.

The realization of a Time-Domain-(TD)-sensor is tracing a

new approach based on optical remote sensing, aiming

an ultra-broad frequency range from DC up to 10GHz. In

contrast to related methodologies, where the sensor is

used as a passive device involving large dimensions, the

target here is to exploit active signal transduction. This al-

lows a significant size reduction down to sub-millimeter di-

mensions.

The focus is directed towards electro-optic methods with

special attention to all optical fiber link sensors. There are

three popular techniques for high-speed modulation of

light, the Pockels effect, the electroabsorption effect, and

direct laser modulation. The latter among these is the

most promising method, since powerful laser diodes have

emerged. VCSE-lasers with their large bandwidth, small

size, and low power consumption are very promising can-

didates to meet the requirements for high-speed electro-

optic signal transduction in a miniaturized E-field sensor.

Schematic view of our time-domain sensor approach.

Risk Assessment: GSM Expo-

sure System for Tox./Car. Study

at RCC, ARCS, Zhejiang Univ.

Personnel: Sven Ebert, Walter Oesch;

IT IS: Jean-Claude Gr bli, Niels Kuster

Funding: BBW, PERFORM A Consortium,

IT IS Partners

Partners: PERFORM A Consortium

The project PERFORM A is one of the largest toxicologi-

cal studies being performed in the context of the health

risk assessment of mobile communications with the ob-

jective of addressing the issue of potential carcinogenic

effects in humans from low-level exposure to the RF of

mobile phones.

Part of the project involves in vivo studies with rats. These

studies are performed at three partner Institutes: RCC (Li-

estal, Switzerland), ARCS (Seibersdorf, Austria), and

Zhejiang Medical University (Hang Zhou, China). At RCC

the study consists of two classical combined chronic tox-

icity and carcinogenicity two-year bioassays conducted at

both GSM frequency bands (GSM900 and DCS1800). At

ARCS and Zhejiang Medical University the evaluation of

900MHz GSM signals on DMBA-induced mammary tu-

mors are being conducted. The biological studies are con-

ducted in compliance with GLP and satisfy international

guidelines.

A total of 56 setups have been installed (32 at RCC, 16 for

each frequency and 12 at ARCS and 12 at Zhejiang Uni-

versity). Pre-studies were successfully completed in sum-

mer 2002, and the main studies have begun at all three

locations.

PERFORM A exposure systems at ARCS (top) and RCC

(bottom).

85

Risk Assessment: RF Induced

Thermal Threshold Measure-

ments in Rodents

Personnel: Sven Ebert; IT IS: Niels Kuster;

RCC: Paul Smith;

Fraunhofer ITEM: Clemens Dasenbrock


Partners: PERFORM A Consortium, IT IS Partners

The objective of the two bioassay studies is to detect non-

thermal electromagnetic field (EMF) effects on cancer

endpoints and to determine whether any effect occurs in

order to establish a dose-effect relationship. Three dose

levels are applied. The highest was set just below the

thermal threshold and had been established for mice and

rats in the experimental conditions of the following pre-

studies.

The RF induced thermal threshold measurements were

conducted at the Fraunhofer ITEM (Hannover, Germany)

and RCC (Liestal, Switzerland) using the exposure sys-

tems of the PERFORM A study and optical fibre tempera-

ture probes. The performed measurements satisfy the

ethical standards, requirements, and international guide-

lines.

B6C3F1 mice and Wistar rats were exposed to 900MHz

GSM and 1800MHz DCS signals. The body temperature

prior, during and after the exposure was measured at dif-

ferent specific absorption rate (SAR) levels and for differ-

ent body weights. The measurements showed an RF

induced thermal threshold starting above 5mW/g for both

species. The highest exposure dose in the Perform A

study was therefore set to 4mW/g.

Perform A exposure setup and results of RF induced

temperature threshold measurements in Wistar rats.

Risk Assessment: Development

of an In Vitro Exposure Setup

for 835MHz and 935MHz

Personnel: J rgen Schuderer, Walter Oesch;

IT IS: Denis Sp t, Niels Kuster



The objective of this study was to design, optimize, and

build a flexible exposure setup which provides maximum

homogeneity in multiple Petri dishes, a dynamic range

from less than 1mW/kg to over 20W/kg, and amplitude

and frequency modulation schemes as emitted by mobile

phones operating within a GSM and NADC communica-

tions network at 935MHz and 835MHz.

The exposure setup is based on two R9 waveguide reso-

nators and permits the controlled exposition of monolayer

or suspended cells in eight 35mm Petri dishes. The

waveguides are excited by tunable broadband coax-to-

waveguide couplers and are terminated with easily re-

movable short cuts. Each waveguide is equipped with a

fan for rapid environmental atmospheric exchange,

whereby the air flow temperature is monitored with accu-

rate Pt100 probes. In order to ensure stable exposure in-

dependent of the loading, H-field sensors based on loop

antennas were developed to regulate the incident fields.

The signal unit is controlled by a user-friendly operating

and monitoring software and allows the double blind ex-

position of several GSM and NADC signal schemes. The

evaluation, optimization, and fine-tuning of the setup was

performed using the Finite-Difference Time-Domain

(FDTD) simulation platform SEMCAD including its ther-

mal solver extension. The results were carefully verified

by field and temperature measurements using the near-

field scanner DASY3.

E-field distribution inside the R9 resonator cavity. The

Petri dishes are placed at the minimum of the E-field,

which results in the best uniformity of the SAR distribu-

tion for cell monolayers.

86

Risk Assessment: Development

of an In Vitro Exposure Setup

for UMTS

Personnel: J rgen Schuderer, Walter Oesch;

IT IS: Niels Kuster

Funding: BBW, EU-QUAL-01574 REFLEX,

IT IS Partners

Partners: REFLEX Consortium

Currently almost all risk assessment studies in the area of

radio frequency field exposure are performed to test to-

day s second generation communications technologies,

such as GSM systems. Since the novel 3G UMTS sys-

tems will soon dominate the mobile communications mar-

ket, an exposure setup for the evaluation of possible

hazardous effects resulting from such kinds of WCDMA

modulated exposures is of high importance. Therefore,

the objective of this study was to develop a setup which

allows the exposure of several Petri dishes to controlled,

uniform field conditions with modulation schemes as re-

sulting from a handset operating inside a UMTS network.

The exposure setup is based on two R18 waveguide res-

onators that are excited by broadband coax-to-waveguide

adapters and are terminated with easily removable short

cuts. The setup fits inside a commercial incubator, and

each waveguide is equipped with a fan for rapid environ-

mental atmospheric exchange. E-field sensors were de-

veloped to regulate the incident fields, and Pt100 probes

monitor the air flow temperature. The WCDMA signals are

simulated by amplitude and frequency modulation of the

1950MHz carrier signal that also take the fast power con-

trol of the UMTS handset into consideration. Field optimi-

zation and evaluation of the setup was performed using

the Finite-Difference Time-Domain (FDTD) simulation

platform SEMCAD including its thermal solver extension.

The results were carefully verified by free space and do-

simetric field and temperature measurements using the

near-field scanner DASY3.

Exposure setup based on R18 waveguides equipped

with removable short cuts (upper one removed).

Temperature Distributions

Inside Cell Cultures Exposed

to EMF In Vitro

Personnel: J rgen Schuderer;

IT IS: Niels Kuster;

RCL (Thessaloniki): Theodoros Samaras


IT IS Partners

Partners: REFLEX Consortium

Several reports of biological effects from RF electromag-

netic fields (EMF) have been described as non-thermal

in the literature. But only few of those studies provide a

sufficient temperature analysis containing both the maxi-

mum local as well as the average temperature rise in the

exposed cell cultures. Since current technology does not

provide easy solutions for fast temperature measure-

ments of small volumes, computer simulations of the heat

transfer processes pose the best candidate for examining

the temperature distributions inside cell cultures exposed

in vitro.

The aim of this project was to evaluate the temporal

change and spatial distribution of temperature inside cell

cultures contained in Petri dishes and exposed to EMF

with a resonator exposure setup at 1800MHz. Tempera-

ture measurements and simulations have been carried

out and compared to each other in order to verify the nu-

merical boundary conditions. All calculations were per-

formed using the Finite-Difference Time-Domain (FDTD)

simulation platform SEMCAD and its integrated thermal

solver extension. It was found that for natural and forced

convection (i.e. with the cooling fans of the exposure set-

up in off and on states), the calculated variation of tem-

perature with time matched the measurement findings by

applying a thin plate model for the heat transfer parame-

ters. Since local variations of temperature are of signifi-

cance in the context of bioexperiments, nonuniform

starting and cooling conditions have been tested. It has

been shown that the possibility of hot spot generation

can be excluded.

Temperature distribution inside the air-cooled Petri dish

after 30min of RF exposure at 1800MHz and a specific

absorption rate (SAR) level of 40W/kg (starting tempera-

ture: 37.0°C).

87

Characterization of a Novel

High-Resolution Temperature

Probe



IMTEK: Gerald Urban


IT IS Partners

Partners: IT IS, SPEAG, IT IS Partners

Miniaturized temperature probes have a wide range of ap-

plications in radio frequency dosimetry and in the determi-

nation of temperature hot spots. The smallest available

E-field probes have a spatial resolution of not better than

1mm3 whereby the boundary effects prohibit measure-

ments closer than 1mm to any boundary. A temperature

probe with a resolution of considerably less than 1mm3

providing a fast time response would enable closing the

gap in micro dosimetry.

A four wire thermistor based on amorphous germanium

was realized in thin-film technology with an active area of

only 0.1mm × 0.05mm. The resistance of the sensor was

adjusted to be 4MΩ, which guarantees RF immunity. The

sensor current of approximately 100nA causes no mea-

surable self-heating. The sensor signal could be well lin-

earized in the range from 0°C to 60°C with an exponential

function for the temperature sensitive resistance. A TCR

of 2%/K at 25°C was found. Hysteretic errors of 60mK

were determined for three times cycling of the tempera-

ture from 0°C to 40°C. The noise level at 10s integration

time is 4mK, which would result in a noise level of 2W/kg

for specific absorption rate (SAR) measurements in aque-

ous media. If the probe is suddenly inserted into liquid me-

dia, the thermal time constant is less than 14ms, which

guarantees fast SAR measurements without any distur-

bance from heat flow processes. As an application, the

SAR distribution inside a Petri dish has been measured

and showed good agreement to Finite-Difference Time-

Domain (FDTD) simulations. SAR evaluation times of

much less than 10s are required to avoid errors due to

heat flow processes.

Sensor tip of the temperature probe compared to a

match stick.

Effects of RF EMF Exposure

on Sleep EEG and Regional

Cerebral Blood Flow



IPT-UNIZH: Peter Achermann

Funding: FNM, TDC

Partners: IT IS, IT IS Partners

The subject of this project was to compare and discuss

the results from four recent studies that provide consistent

evidence that radio frequency electromagnetic fields (RF

EMF) similar to mobile phones affect brain physiology.

Effects on sleep EEG were observed in three studies un-

der similar, but nevertheless significantly different condi-

tions (exposure before sleep vs. exposure during sleep,

unilateral exposure vs. exposure of the entire head, differ-

ent modulation schemes). Spectral EEG power was in-

creased in the spindle frequency range of stage 2 sleep.

The effects outlasted exposure by 20—50min (exposure

during sleep) or even hours, when the RF EMF was ap-

plied during waking prior to sleep. These changes in EEG

power were similar for both hemispheres and no asymme-

try was detected, even after unilateral exposure. RF EMF

without pulse modulation (CW) did not enhance power in

the sleep EEG; this was the first demonstration that pulse

modulation is necessary to induce the changes in the

sleep EEG. Furthermore, this experiment has shown that

the effects found cannot be related to thermal action of the

RF EMF, because the CW exposure results in the same

thermal load as the pulse modulated exposure. Finally, it

was found with positron emission tomography that com-

pared to the control, regional cerebral blood flow was in-

creased in the dorsolateral prefrontal cortex of the

exposed hemisphere after RF EMF exposure. It should be

emphasized that the observed effects were subtle and it

would be premature to draw conclusions about health

consequences.

Positron emission tomography after RF exposure.

89

Education Program

Student Projects

Coordinator:

Norbert Felber

90

Teaching microelectronics is one of the core activities of the Integrated Systems Laboratory. Shortly after the

laboratory was founded in 1986, it started to offer graduate students term projects in IC design. Probably as

the first European university ETH financed the fabrication of student chips. This gave students the opportunity

to carry out a VLSI design project from the specification to the test of their own silicon chips. Still today, the

majority of student term projects at IIS are in practical chip design and many diploma projects include the re-

alization of integrated circuits or the development of components as contribution to research ASICs.

The tools used by the stu-

dents are the same as used in

research and by our main in-

dustry partners: Mentor for

the logical verification, Synop-

sys for synthesis, Cadence for

the physical design, Mentor

for the physical verification,

and Synopsys again for test

generation. The diversity of

this design environment, de-

scribed in the order of (partial-

ly iterative) application during

a project, demonstrates the

considerable effort our stu-

dents have to provide just to

master the tools. Besides this

handcraft they want to learn

IC design, and to realize an

often challenging and com-

plex project. Despite the hard

work with many traps and

complications, almost all

chips finally work as intended.

During the 14 weeks of a se-

mester thesis, groups of one

to three students put 50% of

their work load into the real-

ization of a chip (sometimes

considerably more). First-

time-right digital ICs of al-

most industrial complexity lev-

el often result. This is only

possible due to the sound VLSI education and an excellent support for design and test offered by the PhD stu-

dents of our Laboratory and the Microelectronics Design Center of the department (see page 112).

The group of Qiuting Huang complements the field of IC design with projects for mixed-signal and analog

chips. The yellow bars in the figure above illustrate the total number of student IC design theses (digital and

analog) that have been realized as term projects and diploma theses during the last ten years.

We would like to emphasize that, without the funding by the Board of the ETH Z rich in the project Lehre und

Forschung in Mikroelektronik (Education and Research in Microelectronics), it never would have become pos-

sible to give more than 400 young engineers the experience of designing real silicon. Most of our former stu-

dents are now working in the microelectronics research and development centers of Swiss industry, while oth-

ers found the way to well-known international companies all over the world.

Besides the VLSI projects our laboratory also offers student projects in all its other fields of research. Espe-

cially the simulation of optoelectronics devices and effects attracts an increasing number of students. But also

hardware and combined software-hardware projects are popular. The total number of student projects at IIS is

displayed by the blue bars of the graph.

The high level of our student projects is confirmed by the papers which are accepted as scientific contribu-

tions in international conferences (see: G. Acunto, M. Sans et.al. on page 131, F. Carbognani et.al. on

page 131, M. Luisier et.al. on page 134).

The following pages give short descriptions of most student term and diploma theses executed during the

winter term 2001/2002 and the summer term 2002.

91

Rijndael Crypto Chip

Realization

Personnel: Andres Erni, Adrian Lutz,

Stephan Reichmuth; Frank G rkaynak,

Hubert Kaeslin (assistants)

Funding: ETHZ

In 1997, the U.S. National Institute of Standards and

Technology (NIST) initiated a process to replace the aging

Digital Encryption Standard (DES). Initially 15 algorithms

were contributed by cryptographic researchers from in-

dustry and academia. After a public selection process five

algorithms were selected as finalists, and eventually NIST

decided to propose Rijndael as the Advanced Encryption

Algorithm (AES).

In this work, a throughput-optimized Rijndael crypto core

has been implemented in a standard 0.6μm digital CMOS

technology. For a 128-bit key, the Rijndael algorithm re-

quires ten identical computational operations called

rounds. Most implementations re-use one physically im-

plemented round ten times. To increase throughput, two

parallel rounds have been realized in hardware on this in-

tegrated circuit.

The chip occupies a total area of 49mm2 and contains ap-

proximately 300,000 transistors. The prototype ASICs run

at 88.5MHz. The measured throughput is 2.26Gb/s for

both encryption and decryption in Electronic Code Book

(ECB) mode. By the time it was finished, this implementa-

tion was the fastest reported ASIC realization of the AES

algorithm.

Photomicrograph of the Rijndael crypto chip.

Serpent Crypto Chip

Realization

Personnel: G rard Basler, Pieter Rommens,

J rg Treichler; Stephan Oetiker,

Frank G rkaynak (assistants)

Funding: ETHZ

In 1997, the U.S. National Institute of Standards and

Technology (NIST) initiated a process to replace the aging

Digital Encryption Standard (DES). Initially 15 algorithms

were contributed by cryptographic researchers from in-

dustry and academia. After a public selection process five

algorithms were selected as Advanced Encryption Algo-

rithm (AES) finalists. Although the Rijndael algorithm was

eventually declared the winner, the Serpent algorithm

came a close second in the final selection process.

One of the criteria for the AES selection was hardware

suitability, but all previous comparisons of ASIC realiza-

tions of AES finalists were based on synthesis results. In

this work, a throughput-optimized Serpent crypto algo-

rithm was implemented and the result was compared to

that of the Rijndael implementation (see facing column).

Although fundamentally completely different, both algo-

rithms have resulted in hardware with remarkably close

performances. The Serpent implementation occupies ex-

actly the same area of 49mm2 as the Rijndael realization.

At a clock rate of 122.9MHz it has a measured throughput

of 1.96Gb/s for both encryption and decryption in Elec-

tronic Code Book (ECB) mode, marginally slower than the

Rijndael implementation. This work has provided a fair

comparison regarding the relative performances of ASIC

implementations of the two leading AES finalists..

Photomicrograph of the Serpent crypto chip.

92

Adaptive Arithmetic Coder

ASIC

Personnel: Giuseppe Acunto, Miquel Sans;

Andreas Burg (assistant)

Funding: ETH

Arithmetic coding is a highly efficient algorithm for loss-

less data compression. Its ability to encode symbols with

fractions of a bit makes it superior to prefix codes such as

the popular Huffman coding. Another advantage of arith-

metic coding is the fact that it does not require a precom-

puted codebook. This makes the technique most suitable

for applications where the data source is not stationary or

where its probability distribution is not known a priori.

In a previous semester thesis a non-adaptive arithmetic

coder core was implemented in VHDL. The goal of this

project was the extension of this module with an adaptive

probability modeler. The chosen architecture combines a

full RAM-based probability model with a reduced cache-

based model and a virtual table to achieve single-cycle

operation for encoding and decoding. Various algorithmic

and architectural optimizations were made and analyzed

to obtain nearly optimum compression ratio at low area

consumption and high speed.

The final design contains two encoders and two decoders,

supplemented by a PAL video interface for lossless real-

time compression of color video signals, and a direct high-

speed data interface. It has 2.4 million transistors and was

integrated in a 0.25μm 5-metal process from UMC. Initial

tests show that all samples are fully functional. En- and

decoding can be performed at a rate of 70MHz and

40MHz, respectively.

Chip photograph Adaptive Arithmetic Coder ASIC.

Source Coding for Bio-Medical

Signals

Personnel: Felix B rgin, Franziska Pfisterer;

Robert Reutemann,

Clemens Hammerschmied (assistants)

Funding: ETHZ

Even though sampling rates are usually low, long-time

monitoring of biomedical signals leads to large data vol-

umes. In order to realize small, low-power storage and

transmission systems, the data have to be compressed

efficiently. The coding scheme should achieve high com-

pression ratios with low distortion and it has to be amena-

ble to VLSI and/or DSP implementations with restricted

processing power and memory requirements.

In this semester thesis, a compression system for electro-

cardiogram (ECG) signals based on the discrete wavelet

transform (DWT) and embedded zero-tree wavelet (EZW)

coding has been implemented. The discrete wavelet

transform is realized as a dyadic filter bank, using trans-

posed-polyphase-form filters and signed-digit coefficient

representation. The EZW algorithm has been slightly

adapted for efficient VLSI implementation and uses an

FSM-based (Finite State Machine) approach. A static

Huffmann coder further reduces the bit-rate of the gener-

ated symbols from the EZW coding step.

The 21mm2 ASIC realized in a 0.6μm CMOS technology

uses a master clock of 512kHz for an input sample rate of

250Hz. Depending on the actual signals used, achievable

compression ratios are in the range of 8:1 to 10:1 for ac-

ceptably low distortion (distortion less than 5%).

Chip micrograph of the 4.6mm by 4.6mm wavelet-trans-

form and EZW-coding ASIC with block overlay.

93

Smart Sensors on the

LIN Local Interconnect Network

Personnel: Andreas Dick, Simon M ller, Marcel Pl ss;

Boris Glass (assistant);

Sensirion: Urs Rothacher

Funding: ETH

Partners: Sensirion

The LIN bus is a Local Interconnect Network standardized

by a consortium of the automotive industry. It aims at sim-

plifying the connection of the huge number of non critical

devices (switches, lamps, motors, sensors, etc.). The

physical bus consists of a single, wired-AND signal line,

ground, and power.

One key product of the startup company Sensirion is a

low-cost calibrated humidity and temperature sensor with

serial digital interface. The goal of this student design

project was the development of a prototype LIN interface

which will allows Sensirion to enter the automotive market

with their products.

The realized circuit provides all signals to control and in-

terface the existing mixed-signal sensor part. The LIN bus

controller is implemented for slave functionality. Beyond

inquiring humidity and temperature values, all further

functions of the mixed-signal part can be accessed. The

LIN hardware interface is compatible to industry-standard

physical interface chips, which are necessary due to the

high voltages of up to 40V on the signal line required for

for good EMC immunity.

The LIN ASIC is implemented on a CMOS 0.6μm three

metal layer process from austriamicrosystems. The core

occupies an area of 1.1mm2. The prototype chip is pack-

aged in a 44pin JLCC case. 398 test vectors are provided

for a fault coverage of 95%.

Photomicrograph of the LIN bus ASIC with overlaid Rel-

ative Humidity and Temperature Sensmitter SHT11 .

FFT-Based

Digital Audio Equalizer

Personnel: Marc Robert;

Norbert Felber (assistant)

Funding: ETH

This ASIC has been developed in a term project by one

student. The core functionality implements a digital filter of

order up to 2048. At 48kHz sampling rate the frequency

resolution of the 4096bin Fast Fourier Transform (FFT) is

12Hz. The overlap of adjacent FFT blocks is 2048 sam-

ples. The filter processes two stereo blocks in parallel as

real and imaginary part of the complex FFT arguments.

The arithmetic unit consists of a floating-point multiplier

and adder with 24bit mantissa and 8bit exponent. Inter-

mediate data is stored in an external SRAM.

The equalizer is realized as 9 logarithmic-spaced frequen-

cy bands with quasi-continuous amplitude resolution. The

gains can be adjusted over mechanical or optical 2-phase

encoders. An acceleration algorithm is implemented for

quick reaction combined with high resolution. On-line cal-

culated soft transitions between the frequency bands

avoid excessive filter orders which would lead to audible

FFT-block boundaries. A special mode allows access to

the SRAM in order to store arbitrary frequency responses.

The 24bit audio ports are implemented as serial I2S mas-

ter interfaces that can drive most audio codecs directly.

The chip has been integrated on a CMOS 0.6μm three

metal layer process from austriamicrosystems. The die

occupies an area of 30mm2. The prototype chip with

80000 transistors is packaged in a 120 pin PGA case.

Chip photomicrograph of the FFT-based audio equalizer.

94

PIC 16C5X 8-bit Microcontroller

Personnel: Urs Frey, Roman Leuzinger;

Frank G rkaynak, David Perels

(assistants)

Funding: ETHZ

The goal of this thesis was to implement a RISC (Re-

duced Instruction Set Controller) compatible to the Micro-

chip“ PIC165x series.

The core of the design was kept as flexible as possible to

enable the generation of any of the PIC165x series con-

trollers. The resulting core is compatible with the Micro-

chip“ PIC to a high degree, therefore the PIC design

tools can be used to develop assembler code. Since one

instruction cycle takes only one clock cycle instead of four,

the implemented PIC runs four times faster than an origi-

nal PIC at a given clock frequency.

For the design actually synthesized and assembled on sil-

icon, an architecture closest to a PIC1656 or PIC1657

was chosen. The controller has a RAM program memory

of 1024 instructions, 60 general-purpose registers, 8 bidi-

rectional, 24 output, and 20 input ports. Some other fea-

tures have been added, among these are an 8-bit

multiplier and a ROM program implementing a boot loader

routine. The program loader can fetch instructions from a

serial RS232 interface and write them to the program

memory RAM and to an external EEPROM.

The design was implemented on a CMOS 0.6μm three

metal layer process from austriamicrosystems. The max-

imum operating frequency at 5V is 55MHz when execut-

ing a program from the RAM. The ROM program runs at

a maximal speed of 105MHz.

Chip photograph of the implemented processor.

Java Virtual Machine

Coprocessor ASIC

Personnel: Silvan Wegmann;

J rgen Wassner,

Norbert Felber (assistants)

Funding: ETH

The Java Accelerator Chip (JAC) has been designed by a

Computer Science student. As co-processor it is able to

support any general-purpose processor system. It can

handle a subset of the Java byte code. Because JAC

does not interpret, but execute the instructions as ma-

chine code, it runs faster than any software-implemented

Java virtual machine. For the instructions that cannot effi-

ciently be implemented in hardware JAC provides a sim-

ple interface to access all internal registers, the stack, and

the local variables.

The current implementation is rather a case study due to

the low working frequency and the limited implemented in-

structions which cause a lot of setup overhead. Since

these student projects aim at the experience of a full VLSI

design cycle from specification to test of the silicon, this

goal has fully been reached even if the functionality is re-

stricted. In a follow-up project with the 0.25 μm technology

of the next student designs, and with more implemented

instructions, a respectable speedup can be expected spe-

cifically in embedded systems.

The chip has been integrated on a CMOS 0.6μm three

metal layer process from austriamicrosystems. The die

size is 3.9 x3.9mm2. The prototype ASIC with two 1024-

by-16bit RAMs is packaged in a 84pin JLCC case. 9 of

the 10 tested chips work correctly at clock rates up to

45MHz with 5V power supply.

Chip photograph of the Java co-processor ASIC.

95

Real-Time Video Image Filter

Personnel: Adrian Tr llinger;

Matthias Br ndli,

Stephan Oetiker (assistants)

Funding: ETHZ

The integrated circuit developed in this student project is

intended for demonstration purposes in an undergraduate

practical training on VLSI design.

The chip performs a real-time three-by-three pixel filter on

the video image data stream delivered by the camera

head, which employs a monochrome digital image sensor

from PixelCam“ (PCS2112). This sensor features a max-

imum resolution of 1288×1032, up to 16MHz pixel rate

and 10bits data per pixel. Furthermore it permits a trade-

off between resolution and frame rate via reduction of the

output window size and/or sub-sampling.

The filter integrated circuit dynamically supports all possi-

ble video modes of the PCS2112, which means that the

chip permanently adapts its operation to the current mode

while running without the need of any manual configura-

tion. The 8bit wide filter coefficients are programmable

over an RS232 serial port and can be set and read out

while the chip is performing its task.

Since this integrated circuit is designed to merely add la-

tency and otherwise act completely transparently with re-

gard to the control signals accompanying the data, the

same PCI frame grabber card and software (from EPIX¤ )

intended for use with the original unmodified camera head

can be used.

The chip is fabricated in a 0.6μm three metal layer CMOS

process and has a die area of 22mm2.

Photomicrograph of the real-time video image filter chip.

OIF — SPI-5 Receiver

Personnel: Silvio Dragone;

IBM R schlikon: Peter Buchmann;


Funding: ETH

Partners: IBM R schlikon

This diploma thesis of the ITET-ETH candidate has been

carried out at the IBM Research Laboratory in R schlikon,

Switzerland, under the supervision of IIS. The task was to

implement the receiver part of the physical layer (PHY)

device of a System Packet Interface Level5 (SPI—5).

SPI—5 has been designed for aggregate bandwidths of

OC-768ATM and Packet over SONET/SDH, as well as

other applications at the 40Gb/s data rate. The interface

basically consists of a 16bit data bus, a control line, a sta-

tus line, and the source clock. Control signals share the

same bus as the payload data and can be differentiated

only by the control line.

Since the OIF standard has not been approved during the

work, the initial implementation has been based on a pre-

liminary document. The final design however corresponds

completely to the standard.

The PHY receiver has been implemented in VHDL hard-

ware description language. Architectural optimizations

were required in order to meet the area expectations and

the required speed. The circuit has been mapped to IBM s

CU11 technology.

A test environment has been implemented to verify the

correctness of the functionality. It consists of a C program

which generates a special data sequence, and of a test

bench which stimulates the model under test and analyz-

es the output data. Timing analysis has been carried out

statically with IBM-internal tools.

Diploma thesis schedule of the pretentious VLSI project.

96

Runtime-Reconfigurable

Arithmetical Logical Unit

Personnel: Marc Schoenes, Roman Leuzinger;

Thomas B sch (assistant);

TIK: Alexandre Maxiaguine

Funding: ETHZ

In this semester thesis a reconfigurable arithmetical logi-

cal unit (ALU) and an associated software tool chain for

configuration-data generation has been developed.

A RISC processor is able to execute user defined instruc-

tions by using this ALU as an additional execution unit.

Therefore, the static general-purpose instruction set of the

processor is enhanced by a runtime-modifiable instruction

set extension. Especially bit manipulation operations that

typically require multiple clock cycles on a general-pur-

pose processor are well supported.

The ALU consists of blocks containing 32 fine-grained

LUT-based operation circuits. Several of these blocks are

arranged in a pipeline that is interleaved by registers and

multiplexer structures. Configuration data must be gener-

ated to define new operations. A custom description lan-

guage has been defined to allow high-level configuration

definition. A software tool chain translates the high-level

description into a bit file that is used by the processor to

configure the behavior of the reconfigurable ALU.

Runtime-reconfigurable ALU.

CDMA MIMO Frontend

Personnel: Thomas Dellsperger, Michael Geissmann;

Andreas Burg, David Perels (assistants)

Funding: ETHZ

Multiple-Input Multiple-Output (MIMO) wireless communi-

cations systems employ multiple antennas at the transmit-

ter and at the receiver. On one hand, these systems allow

to take advantage of high scattering environments for im-

proving the signal-to-noise ratio. On the other hand, they

allow to boost the capacity of wireless communications

systems if there is a good knowledge of the different trans-

mission channel transfer functions. Therefore, the chan-

nel estimation is an important part of a MIMO receiver and

contains a significant amount of complexity.

Based on an already-in-place software model of a 4x4

MIMO UMTS receiver frontend, a new, hardware-efficient

design was implemented. The new channel estimation ar-

chitecture reduces the register count by 70% compared to

the already-in-place solution. This substantial reduction

results from a split of the estimation of the finger position

and the finger coefficients in a transmission channel pro-

file. The finger estimates are used at a later stage in the

MIMO receiver, while the finger positions are used in the

RAKE receiver.

The implementation employs a register-transfer-level C

coding style complying with Frontier Design s A|RT Build-

er“ that finally builds the synthesizable VHDL code.

Variable channel profile (sum over 16 MIMO channels)

over 150 ms and the block diagram of the receiver front-

end.

97

Pseudo-Random Number

Generator

Personnel: Iwan Schenker; Frank G rkaynak,

Stephan Oetiker (assistants)

Funding: ETHZ

Random numbers are an integral part of a range of algo-

rithms which are used in cryptography, VLSI testing, and

system simulation. Unfortunately practical real random

number generators are exceedingly difficult to realize.

Pseudo-Random Number Generators (PRNG) are spe-

cialized algorithms that produce a sequence of numbers

which exhibit the same properties as random numbers.

In this work, the aim was to develop a simple user inter-

face for a PRNG. The generator is able to deliver the

VHDL source code, testbench, a gate level netlist as well

as test patterns for the generated module, depending on

user parameters. The user is able to specify the period of

the desired sequence, the bit-width of the resulting num-

bers, and the type of PRNG algorithm to be used. The

quality of the generated PRNG is evaluated using stan-

dard benchmarks and all results regarding the quality of

the PRNG, the active area, and the operation speed are

reported back to the user.

Flow diagram of the Pseudo-Random Number Generator

algorithm. Output files are shown in light red.

Low-Power, Low-Frequency

Digital Transceiver

Personnel: Jonas Bandi, Marc Wegm ller;

Robert Reutemann, Michael Oberle

(assistants)

Funding: ETHZ

In 1998, a team of ETHZ was awarded the first price in an

international competition for new ideas in the aerospace

sector. The innovation was to use the human body itself

as a communications channel for biomedical signals.

In this diploma thesis, a digital communications system for

such a channel has been implemented. The system uses

QPSK modulation with a 64kHz carrier frequency and up

to 64kHz symbol rate. The ASIC includes a digital trans-

mitter block (up-sampling and QPSK modulation) and a

corresponding receiver. The receiver block includes a de-

modulator, a matched filter, a timing recovery unit, and a

decoder. The ASIC can be configured to be used as mas-

ter or as one of several slaves in a simple TDMA-based

system.

This chip, together with external analog circuitry, A/D and

D/A converters, and a controller can be used to build a

test system for the evaluation of achievable transmission

speeds, noise immunity, and other parameters of a future

communications system that uses the human body as

channel.

The circuit has been implemented in a 0.6μm CMOS pro-

cess. Total die area is 29mm2 for 22.5kGates. The chip

has been packaged in a 68pin CLCC package for testing.

Typical simulated digital output spectrum (top) and chip

micrograph with block overlay (bottom) of the QPSK

transceiver ASIC.

98

Low-Power GPS Radio-Fre-

quency Front-End in 0.18μμμμm

CMOS

Personnel: Tamas Weber, Elmar Schmid;

Thomas Burger (assistant)

Funding: ETHZ

Portable receivers for the Global Positioning System

(GPS) require solutions that are compact, cheap, and low

power. To enable widespread proliferation of GPS capa-

bilities into consumer products, an integrated receiver

should minimize the number of off-chip filters, particularly

the number of expensive passive filters. These consider-

ations motivate the research. The transistor devices of

modern CMOS technologies offer enough speed to inte-

grate the radio frequency (RF) blocks, as well as the re-

quired circuit density that allows to implement all GPS

base-band signal processing operations. Deep-submi-

cron CMOS processes therefore enable a GPS receiver

to be designed in a single technology, and even to be in-

tegrated on a single chip.

This student project aimed at such a realization of a GPS

RF front-end with highest degree of integration. The con-

ceptual block diagram shows therefore antenna- and

channel-filters in the receive chain before the signal is fed

on-chip to the amplification by a low noise amplifier (LNA),

the frequency down-conversion by a quadrature mixer,

and to further amplification and filtering at intermediate

frequency. The design also includes a completely inte-

grated frequency generator with a phase-locked-loop cir-

cuit where the GPS RF frequency is obtained as an

integer multiple of the external reference clock.

Block diagram of the integrated GPS RF front-end.

Design of a 200MHz Frequency

Synthesizer

Personnel: Stephan Odermatt, Thomas Christen;

Dirk Pfaff, Chiara Martelli (assistants)

Funding: ETHZ

The design of a 200MHz frequency synthesizer is a de-

manding task due to the different nature of its building

blocks. The high-frequency oscillator and prescaler re-

quire knowledge of radio-frequency circuit design, while

analog and digital design techniques must be applied to

the charge pump and the programmable divider.

This project covered all design aspects of an integer-N

frequency synthesizer, from system down to transistor

level. First, based on a linear approximation of the phase

locked loop, the loop parameters (charge pump current,

loop filter poles and zeros) have been dimensioned to

meet the synthesizer specs. Second, a behavioral model

using Simulink“ was developed to characterize the non-

linear frequency settling.

All synthesizer building blocks have finally been analyzed,

designed, and verified by transistor-level simulations.

VHDL was used to implement the digital part. High fre-

quency building blocks could benefit from fast bipolar

transistors provided by the 0.8μm BiCMOS process.

Mixed-signal integrated circuits are often too complex to

be simulated completely, and this design is no exception.

To verify that blocks not only work as independent units,

but also as part of the full synthesizer, analog behavioral

modelling was used extensively.

Frequency synthesizer block diagram with detailed

phase-frequency detector schematic.

99

Sigma-Delta Audio D/A-

Converter

Personnel: Eyjolfur Snjolfsson;

Chiara Martelli, Pio Balmelli (assistants)

Funding: ETHZ

Sigma-Delta A/D and D/A converters operate with over-

sampling and noise shaping and permit the implementa-

tion of high-resolution converters with relatively simple

analog circuits. For low-frequency audio signals, Sigma-

Delta converters are standard today.

The goal of this semester thesis was the implementation

of such a D/A converter, that will later be used in a fully in-

tegrated USB headphone module. A MATLAB parametri-

zable implementation of the complete system has been

built. Much effort has been taken to design the oversam-

pling and interpolation blocks which are now ready to be

translated into VHDL code. The oversampling ratio of 128

has been realized in 4 steps of oversampling and interpo-

lation. Keeping into account the final hardware implemen-

tation, the assumption of a half band filter as first step, and

a sinc3 filter as last stage, was almost due. To improve the

filter s frequency response, their coefficients have been

chosen by a random search with respect to their com-

bined response. Using a 5th order Sigma-Delta loop, the

overall SNR in the signal band is about 127dB. A simple

analog filter has been dimensioned as interface between

FPGA and loud speakers.

The project is being completed by the VHDL coding and

the consequent FPGA programming to verify the correct-

ness of the system.

Sigma-Delta output, analog filter frequency response,

and filtered output.

Sigma-Delta Audio D/A-

Converter

Personnel: Peter Fercher;

Pier Andrea Francese, Chiara Martelli

(assistants)

Funding: ETHZ

For low-frequency audio signals, single-bit Sigma-Delta

(ΣΔ) DACs are very suitable for single-chip integration.

The full implementation of such devices includes an up-

sampling-interpolating filter, a noise-shaping ΣΔ digital

modulator, and a D/A converter followed by an analog

low-pass reconstruction filter. In a previous project, an up-

sampling-interpolation filter and a ΣΔ modulator with a sin-

gle-bit output were investigated in MATLAB. This was the

starting point for the present project.

The digital part of the DAC has been implemented in

VHDL and the code has been optimized and programmed

into a Xilinx XCV300E FPGA. The up-sampling factor of

128 was reached with four stages, each of them followed

by an area-optimized interpolating filter. In the first stage

a 64-coefficient halfband FIR filter is used. The second

and third stages are transversal FIR filters that use 21 and

11 coefficients, respectively. The last stage is an IIR sinc3

filter. The ΣΔ modulator used is of 5th-order. Almost 80dB

of spurious-free dynamic range was reached in simula-

tion. The final full integration additionally requires the an-

alog filter implementation.

ΣΔ audio DAC implementation and signal spectra.

100

Fast Comparator for the Appli-

cation in an Analog-to-Digital

Converter

Personnel: Peter Oertig; J rgen Hertle,

Clemens Hammerschmied (assistants)

Funding: ETHZ

Although there exist many different architectures for ana-

log-to-digital converters, all have one thing in common:

their core components are comparators which make the

final decision whether a signal bit has to be treated as dig-

ital low or as high. Especially in parallel-type analog-to-

digital converters low power consumption, low offset volt-

age, and low kick-back are mandatory.

The topic of this diploma thesis was to design an opti-

mized comparator for the application in a high-speed fold-

ing and interpolating analog-to-digital converter.

Therefore, several architectures have been investigated

and compared. Main concerns were low kick-back and

low power consumption, whereas low offset voltage was

only of minor importance, since it is planned to implement

a calibration scheme in the final analog-to-digital convert-

er. Also, only static comparators have been taken into ac-

count since the benefits of dynamic comparators vanish at

higher operation frequencies.

The resulting design is shown below. The input pair is cas-

coded in order to further reduce the kickback. The PMOS

latch is inserted to accelerate the regeneration process of

the comparator after the latch command has been given.

By carefully sizing the transistors in a standard 0.25μm

CMOS technology, a comparator with a power consump-

tion of only 200μA at a sample rate of 200MS/s could be

designed..

Principal effect of kick-back and schematic of the opti-

mized comparator.

3D-DCT Video Compression

System

Personnel: Simon Haene, Simone Buzzi,

Guiseppe Schiavello;

Andreas Burg (assistant)

Funding: ETH

Real-time video compression is one of the most challeng-

ing applications for VLSI circuits. In a previous project an

ASIC implementation of a new low-complexity compres-

sion scheme was developed. It uses a three-dimensional

discrete cosine transform to remove correlation between

subsequent frames. This avoids the computationally ex-

tremely complex motion estimation algorithms which are

used in most of the established standards.

In this project the necessary support hardware for the

ASIC was developed. It consists of a general-purpose PCI

board with a XILINX Virtex FPGA and of a sandwich board

that carries the 3D-DCT ASIC, the framebuffer memory,

and the PAL/NTSC video interface chips. In the compres-

sion mode the system records video sequences in real

time from a number of different sources to the harddisk of

a PC. In decompression mode, the compressed se-

quence is read from the harddrive through the PCI inter-

face and is decompressed and displayed. The LINUX-

based software and the necessary set of drivers allow to

control the various parameters of the ASIC and of the vid-

eo interface.

Top: 3D-DCT ASIC carrier board.

Bottom: Compression and Decompression data flow

graph with the PCI board in the background.

101

FFT-Based Digital Audio

Crossover Network for

Loudspeakers

Personnel: Davide Cescato;


Funding: ETH

The goal of this diploma project was the development of a

digital crossover network on a Digital Signal Processor

which provides a three-way filter network of very high or-

der. It is intended as development platform that allows di-

rect specification of complex frequency responses for fast

real-time experiments with loudspeakers. FFT-based fil-

ters satisfy this requirement and enable high filter orders.

The diploma candidate has implemented such a cross-

over filter on a development platform with an ADSP-

21065L signal processor and three stereo codecs. At

48kHz sampling rate it performs one 16k-point FFT on

two input channels (stereo), and three inverse FFTs after

multiplication of the spectrum with the three complex

transfer functions. The overlap-add algorithm assigns

8192 stereo samples of each audio block for overlapping,

the other 8192 are available as filter order.

The challenges of this implementation was in the memory

management much more than in arithmetic computation

optimization. Due to the limited on-chip RAM, FFT buffers

in the external SD-RAM were required, which can effi-

ciently only be accessed in sequential addressing mode.

FFT however requires random access. A good compro-

mise has been found and realized.

FIR and emulated IIR filters can easily be implemented on

this crossover platform due to the high filter order which

allows both speaker non-idealities and sound propagation

delays to be compensated. Instantaneous switching be-

tween frequency characteristics enables precise compar-

isons of different filter characteristics.

Measured frequency response of an emulated analog IIR

filter and a digital linear-phase FIR filter of order 8192!

LED Floodlight with

Electronically Controlled

Color Characteristics

Personnel: David Satz;


Funding: ETH

The goal of this diploma thesis project was an investiga-

tion on the feasibility of a floodlight (e.g. for movie scene

illuminations) with LEDs as light sources. The advantages

of such lights over conventional systems are the bright-

ness-independent color spectrum and the controllability of

the color temperature over a wide range. An important

task was the evaluation of a set of LEDs that enables to

generate white light with high efficiency and independent

angular color distribution. While ultra-efficient LEDs

(20lm/W) exist in single color/package combinations, the

project could not make use of them due to missing LEDs

for the other color components. The optimal available set

only yields 2.15lm/W @ 3200K after a diffusor.

With this selection of LEDs a prototype floodlight has

been realized in a form that allows experiments in the field

(see figure). An array of a total of 1000 white, red, green

and blue LEDs has been developed. A microprocessor-

based controller calculates the LED currents for the se-

lected intensity-color combination. For minimal heat dissi-

pation and good EMC, switched constant-(average)-

current is generated on the LED panel. Temperature de-

pendency of the luminous flux is actively controlled using

a photodiode per LED color. The user interface of the con-

troller accepts intensity and color temperature entries, or

alternatively RGB settings. Remote control over a stan-

dard DMX link is also available.

LED lamp hardware: Lamp assembly (top left), LED pan-

el on heat sink, controller, and detail of LED assembly

showing the composition of the LEDs with 4 colors.

102

PCI-FPGA Board for D/A Con-

verter Modulator Prototype

Personnel: Patrick Torta, Devid Destefanis;

Pier Andrea Francese, Eric Roth

(assistants)

Funding: ETHZ

Due to the short lifetime of many IC products it has be-

come more frequent that the development of new prod-

ucts takes place on platforms suitable for rapid

prototyping.

In this project a multipurpose PCI-FPGA board was jointly

developed with another group of students. On this devel-

opment platform a high-speed Sigma-Delta (ΣΔ) D/A dig-

ital modulator was implemented into the FPGA in order to

demonstrate the system. The MATLAB workspace was

used as the environment in which the data were generat-

ed, sent to the FPGA through the PCI bus, and finally re-

ceived back after the digital signal processing. In this way

the debugging of generic VHDL code such as for a ΣΔ dig-

ital modulator can be rapidly done.

The board basically consists of a Xilinx XCV300E FPGA

and a PLX9080 PCI controller. The PLX9080 handles the

communication between the FPGA and the PCI bus. A

software driver was developed in Windows 2000 using the

Microsoft DDK (Drivers Development Kit). This software

was written in Visual C++ and includes a set of proce-

dures for handling the communication between the MAT-

LAB workspace and the PLX9080 PCI controller. A VHDL

wrapper block was also developed in order to access the

PLX9080 local bus for the transfer of data packets in and

out the XCV300E FPGA. The FPGA was programmed via

the JTAG interface. The VHDL code of the particular ap-

plication, in our case the ΣΔ modulator, was hierarchically

inserted into the VHDL wrapper block that can transmit

and receive data frames of up to 8K vectors.

This platform has been successfully used to verify the

functionality of a high-speed digital ΣΔ modulator at up

100MHz clock frequency, sending and receiving data

frames via the MATLAB workspace through the PCI bus

running at 33MHz.

PCI-FPGA fast prototyping platform.

Encrypted Audio Compact Disk

Personnel: Beni Ingold;

Thomas B sch, Eric Roth (assistants)

Funding: ETHZ

To protect audio CDs from illegal copying several protec-

tion methods have been developed. None of the existing

solutions is really save; protected audio-CDs can still be

copied easily using a standard PC and a CD-burner.

In this diploma thesis a board as been developed that

serves to play back encrypted audio-CDs on a standard

CD-player. Therefore, the audio content is first encrypted,

e.g. by the SAFER encryption algorithm, and then written

to an audio-CD-R on a CD-ROM. Afterwards, if the CD is

played on a standard CD-player, the audio outputs deliver

only noise. If, however, the decryption board is connected

to the CD-player s digital interface, it de-frames and de-

crypts the digital audio content correctly if a PROM card

containing the encryption key is connected to the board.

For the decryption of the audio content an ASIC called

MERLIN is used which has been developed in a former

semester thesis. After decryption, the audio content is

converted to analog for play back. The system contains

an SPDIF receiver, a Xilinx Virtex“ FPGA, the MERLIN

SAFER decryption ASIC, and a D/A converter.

Audio-CD SAFER decryption board.

103

Audio Data Transmission over

Firewire

Personnel: Carlos Velasquez, Martin Polasek;

Thomas B sch, Eric Roth (assistants)

Funding: ETHZ

In this semester thesis a system for the transmission of

audio data over IEEE-1394 (Firewire“) has been devel-

oped. Based on an existing IEEE-1394 development

board, an add-on card for A/D and D/A conversion, and for

sample clock recovery was implemented. Management

software to control the data transmission on the bus has

been developed. To match the sampling times at the

sender and the receiver nodes, accurate clocks are de-

rived from the Firewire bus clock.

After digitizing a stereo audio signal by the sender s A/D

converter, the data is framed together with a timestamp.

The timestamp defines the time of presentation at the re-

ceiver nodes. After transmission over the bus the received

timestamp is compared to the node s local time. As soon

as the local time matches the received timestamp value,

the audio data is passed to the D/A converter for play back

of the audio signal.

Firewire development board with audio add-on card.

Acoustic Communication

Personnel: Marco Schurtenberger;

Andreas Burg, David Perels (assistants)

Funding: ETHZ

The goal of this semester project was the realization of an

ultrasonic communications system that operates in the

range of 30 to 100kHz. This system is useful as a demon-

strator for various transmission techniques or to intercon-

nect low-data-rate equipment in an office environment.

An electrostatic transducer has been chosen in order to

cover the frequency range to allow experiments with dif-

ferent transmission techniques. The electrostatic trans-

ducer is basically a plate capacitor. One of the plates is

mounted on a membrane. Changing the voltage over the

capacitor results in a deflection of the membrane, there-

fore converting electrical energy into acoustic waves.

Despite its advantages regarding linearity over a wide

range of frequencies, the major drawback of the electro-

static transducer is the high excitation voltage. The device

needs to be biased at 100V and the signal amplitudes

should be in the range of 40 to 70V.

For this purpose receiver and transmitter circuits where

developed for the electrostatic transducers on both the re-

ceiver and transmitter side.

Using this setup, channel measurements where obtained

in a regular office environment. Possible interferers, such

as fans and monitors, have been identified.

Photograph of an electrostatic transducer and circuit of

the receiver (top) and the transmitter (bottom).

104

Quantum-Well Laser Gain

Calculations using High-Order

k¥p Methods

Personnel: Mathieu Luisier;

Michael Pfeiffer, Andreas Witzig

(assistants)

Funding: ETHZ

For the fabrication of optoelectronic devices a wide variety

of different materials is used, mostly binary, ternary and

quarternary alloys of group III and group V semiconduc-

tors like GaAs, InGaN or InGaAsP. The accurate and fast

calculation of their electronic properties is one of the ma-

jor challenges in the area of optoelectronic device simula-

tion and TCAD.

In this diploma thesis, a library of Matlab routines has

been implemented that can be used to carry out calcula-

tions of the electronic band structures of III-V alloys as

well as deriving the gain characteristics of semiconductor

quantum-well lasers composed of such materials. For the

calculations a 4-band, 6-band, or 8-band k¥p method can

be used. The routines of the library have been applied to

analyze the band structures and gain characteristics of a

AlGaAs-GaAs and a AlGaN-GaN quantum-well laser.

Some results are shown below.

Large figure: Band structure of an AlGaAs-GaAs quan-

tum-well laser obtained by the k¥p method in different or-

ders. Black curves: 4-band, blue curves: 6-band, red

curves: 8-band k¥p. Insets: TE and TM gain of the laser

for different carrier densities n. The figures show a large

effect of the accuracy of the band structure calculation on

the resulting gain characteristics.

2D Optical Simulation of

Vertical-Cavity Lasers with

Step-Index Apertures

Personnel: Adrian Bregy; UCSB: Joachim Piprek

(supervisor); Andreas Witzig, Matthias

Streiff (assistants)

Funding: ETHZ

Partners: UCSB

In this diploma work, optical effects of step index aper-

tures in vertical-cavity lasers (VCSEL) were simulated.

Thereby, the optical modes are calculated with the optical

mode solver LUMI2. The main part of the work analyzed

a long-wavelength VCSEL which has been developed at

the University of California, Santa Barbara. It was the goal

to find an optimum aperture design for high mode discrim-

ination. Thereby, the behavior of the fundamental and the

first-order mode was investigated for variable thickness,

radius, and position of the apertures. It was shown that

stronger optical confinement provides better mode dis-

crimination, but also gives higher threshold gain and lower

slope efficiency. The maximum single-mode power was

calculated to find the optimum aperture design. The high-

est maximum single-mode power was achieved for an air

aperture with large radius (realized by under-edging the

quantum wells).

Mode confinement in a VSCEL for variable aperture radii.

105

Lifetime Prediction Models and

Thermal Transient Analysis of

Power Semiconductor Devices

Personnel: Flavio Carbognani;

Mauro Ciappa (assistant)

Funding: ETHZ

Partners: Toyota

The end-of-life period of complex multi-chip modules is of-

ten defined by thermo-mechanics related failure mecha-

nisms. The time-to-the-failure (lifetime) for these wear-out

mechanisms is normally estimated on the basis of deter-

ministic models, which are calibrated with data extracted

from accelerated power cycling experiments. These esti-

mates are referred to a given application profile, which is

specific for the technical system under consideration (hy-

brid car, locomotive, etc.). In this work the traditional life-

time prediction models, based both on the bimetallic

approximation for the thermo-mechanical stresses, and

on principle of the linear accumulation of the damage re-

lated to cyclic fatigue have been reviewed in particular in

conjuction with the procedure to extract the distribution of

the amplitude and of the duration of thermal cycles from

standardized application profiles. Furthermore, a lifetime

prediction model based on fundamental thermomechani-

cal equations has been introduced and discussed.

Set up for the measurement of the thermal impedance of

heat sinks (top). Electro-thermal compact model of an

IGBT realized in SABER (bottom).

Thermo-Electric Modeling and

Simulation of IGBT Modules for

Automotive Applications

Personnel: Marco Chiavarini;

Mauro Ciappa (assistant)

Funding: ETHZ

Partners: Toyota

Power converters for hybrid vehicles are still character-

ized by the use of single packaged chips cooled by dedi-

cated water cooling circuits. A possible solution to

improve the efficiency and to decrease both the weight

and cost of the power converter is system integration as-

sisted by compact thermal modeling. In this work tradition-

al extraction techniques have been merged and extended

to enable a fast and accurate transient thermal simulation

of complex power converters submitted to realistic stress

conditions. The procedure is based on the extraction of

the thermal impedance Zth of the system by full 3D finite

element simulation. This is followed by the convolution of

Zth with the power dissipation function. Computation

speed and accuracy have been obtained thanks to dedi-

cated numerical algorithms.

3D simulation of a switch-on transient in an IGBT.

106

PhD Theses — Abstracts

Optimal Design of Operational Transconductance Amplifiers with Application for Low Power ΔΔΔΔΣΣΣΣ Modulators.

Thomas Burger

From the beginning of analog integrated circuit design

around 1960 up to present the operational amplifier (op-

amp) has been the most important analog building block.

The operational transconductance amplifier (OTA) as

stand-alone circuit has been introduced with the develop-

ment of switched-capacitor circuits in the early 1980s.

For the ideal OTA the differential input voltage steers the

output current and so the transfer function of an OTA

stage is defined by its transconductance and the output

load. OTAs are stabilized by their load and the OTA

power consumption can be optimized for the load,

whereas op-amps need internal compensation for stabili-

zation to approach load independent behavior. Because

the OTAs are not subject to prior performance loss due to

internal compensation they can achieve superior perfor-

mance with high impedance environments, such as

switched capacitor sampled-data circuits.

High output impedance is an important OTA requirement

for many practical applications. The regulated cascode

technique supports this requirement very well. By cre-

ation of an inner feedback loop with another amplification

stage the OTA s DC-gain and thereby the output imped-

ance can be boosted to nearly ideal level without com-

promising the frequency response. With this technique

the trade-off between DC-gain and speed in amplifier

design can be resolved. While the regulating amplifier

delivers the required additional DC-gain, the main ampli-

fier can be optimized for speed at a given power or, vice

versa, for power at a given speed. The optimization of the

main cascode amplifier can be formulated analytically for

open as well as for closed loop configuration. The solu-

tion must in general be found by numerical evaluation

because of the complexity in modeling the MOS transis-

tor devices with acceptable accuracy. This optimization

has been performed for folded and telescopic cascode

amplifier topologies and the results are discussed with

respect to phase margin, output swing, capacitive load,

topology, and technology dependence. For closed loop

configuration the amplifier speed can be even increased

beyond the level of an ideal OTA. The optimization

method is proven by a series of implemented amplifiers

spanning a bias range from 1μA to 10mA. The regulating

amplifier should add the required DC-gain in a power-effi-

cient way without deterioration of the amplifier s fre-

quency response and settling behavior. It adds a pole-

zero pair to the amplifier s transfer function which can be

well controlled by the regulating amplifier s compensation

capacitance. This leads to a method for power efficient

design with good settling performance.

The ΔΣ technique trades resolution with speed in con-

verter design. With high enough oversampling the quanti-

zation noise can be rendered arbitrarily low. A ΔΣmodulator s performance is therefore usually limited by

circuit thermal noise where the first stage contributes

most. Today, the practical design for single-loop, single-

bit modulators follows well established paths. However,

the optimization of power consumption, which is a key

requirement for battery operated devices, is still an open

subject. The latter is addressed in this thesis throughout

the whole design flow. At architecture level a careful bal-

ance between quantization and circuit thermal noise is

needed. For an SC implementation at circuit level, capac-

itances and bias currents are scaled according to the rel-

ative importance of noise contribution. Behavioral level

simulations modeling the essential integrator characteris-

tics help to find tight specifications for the building blocks.

Closed loop amplifier optimization provides the link to

component level design. A power estimation formula

allows different design decisions to be compared. The

design concepts have been proven with a baseband

modulator for GSM application and an IF input modulator

for dual UMTS/GSM application.

Prof. Dr. Q. Huang, ETH Z rich, examiner Diss ETH-Nr. 14716

Dr. A. Kaelin, Siemens Schweiz AG, Z rich, co-examiner ISBN 3-89649-823-1

A Low Power 200MHz Receiver for Wireless Hearing Aid Systems

Armin Deiss

This work describes a hearing aid system with RF con-

nection between both ear-pieces for processing both sig-

nals jointly. The planning, design, implementation, and

experimental characterization of a receiver IC for these

ear-pieces is demonstrated.

Low power consumption and volume constraints were

key requirements. Power and volume have been opti-

mized from system level down to transceiver architecture

level, receiver block level, and in the choice of the semi-

conductor process. The latter is a BiCMOS 0.8μm tech-

nology providing dedicated passive elements.

The chosen system configuration includes an additional

unit attached to the body, where space and battery power

is less critical. The RF links of each ear-piece to the body

station are established via time division duplex and 8-ary

phase shift keying on a 200kHz channel spacing, sup-

porting a data rate of up to 336kbit/s.

Due to the novelty of the transmission service, no dedi-

cated specifications could be adopted, but had to be

firstly derived from general system requirements.

Antenna parameters as well as signal levels from the

body station and for blockers and interferers had to be

estimated. A 174—223MHz super-heterodyne receiver

architecture with an IF at 10.7MHz was chosen because

it promised lowest power consumption.

The implemented receiver comprises an LNA with

107

17.5dB voltage gain and 4.4nV√Hz input referred noise-

voltage spectral density, a single balanced mixer with

integrated high ohmic load resistance and power match-

ing to the external IF-filter, a linear IF-amplifier with 42dB

voltage gain in seven 6dB steps and only 0.22dB gain

error, and a fully differential demodulator. The latter con-

sists of a digital phase-shifter for inband and quadrature

component separation in ECL, for both paths double bal-

anced downconversion mixers based on the Gilbert cell,

and fifth order Bessel filters for linear phase response

void of power hungry operational amplifiers, followed by

small baseband amplifiers for final amplification and off-

chip driving.

The receiver demonstrates an error vector magnitude of

9.2% at lowest expected input signal of 25.5dBμV, thus

guaranteeing a symbol error rate of less than the

expected 10-4, while consuming merely 667μA and

occupying a reasonably small volume. It has even been

demonstrated that the receiver could be used for different

modulation schemes including those carrying information

in the amplitude like QAM due to the linear design of all

receiver blocks.

Although the power consumption might still be quite high

for adding the new functionality to contemporary single

ear-piece hearing aid solutions, with the integration of the

most critical and power hungry part of the transceiver,

this work shows that miniaturized wireless hearing aids

are feasible. It hopefully contributes important informa-

tion to further development of commercial products.

Prof. Dr. Q. Huang, ETH Z rich, examiner Diss. ETH-Nr. 14532

Prof. Dr. H. J ckel, ETH Z rich, co-examiner ISBN 3-89649-784-7

Low Power Systems-on-Chip for Biomedical Applications

Michael Oberle

This thesis describes the design and implementation of

single-chip low-power biomedical systems for a novel

generation of medical devices. Mixed-signal systems-on-

a-chip (SoC) have been designed for operation and con-

trol in implanted ventricular assist pumps and for

implanted blood pressure sensors. Finally, a specific

market analysis has been performed prior to the develop-

ment of a novel communication principle using the

human body itself as a data bus.

The first SoC described contains a 10mW 2-channel

eddy-current sensing device for 2D magnetic bearing

control, which is part of a ventricular assist pump. Power

consumption has been reduced by more than a factor of

15 and the accuracy of the position measurement has

been improved from 8 to 10bit through a new excite and

readout concept.

A micro-transponder has been designed for an implanted

blood pressure sensor applying passive telemetry for

batteryless operation. Although it drives a low-ohmic sen-

sor, the whole system including data acquisition and RF

communication has been the first of its kind consuming

less than 500μW.

The last system describes a novel communication

approach which makes use of the dielectric characteris-

tics of human tissue. Signals can be transmitted through

the human body via galvanic coupling of AC currents in

the μA range. A simplified engineering model has been

developed for the communication channel. The principle

of operation has been successfully tested with a digital

ECG demonstrator.

Prof. Dr. Q. Huang, ETH Z rich, examiner Diss. ETH-Nr. 14509

Prof. Dr. H. Niederer, ETH Z rich, co-examiner ISBN 3-89649-839-8

Modeling the Optical Processes in Semiconductor Lasers

Andreas Witzig

In modern telecommunication systems, semiconductor

lasers are key components. This doctoral thesis presents

a physics-based approach to simulate active optoelec-

tronic devices. It covers the analysis of a broad range of

devices, including Edge-Emitting Lasers (EELs) and Ver-

tical-Cavity Surface-Emitting Lasers (VCSELs). A numer-

ical solver for the optical field has been implemented,

and an interface to an electro-thermal device simulator

has been built. Contributions have been made in the for-

mulation of the physical models, and in the coupling

scheme between electronics and optics.

For EELs, the optical field can be separated into trans-

verse waveguide modes and longitudinal cavity modes.

The transverse eigenmodes have been solved in 2D

applying a general but efficient finite-element method.

The longitudinal modes have been calculated using the

transfer-matrix method. For VCSELs, a separation into

transverse and longitudinal direction is not possible.

Instead, the fields can be expanded into a Fourier series

and the eigenmodes are solved in 2D.

In addition to the finite-element solution of the optical

eigenvalue problem, the finite-difference time-domain

method has been applied for the calculation of the elec-

tromagnetic wave propagation. In a post-processing

step, the optical eigenmodes of general VCSELs have

been obtained. Furthermore, the spontaneous emission

coupling factor is calculated rigorously by a full-3D treat-

ment of an EEL structure.

The work presented here has to be seen in the context of

the activities of the Optoelectronics Modeling Group at

the Integrated Systems Laboratory (IIS) of the Swiss

Federal Institute of Technology (ETH) in Zurich, Switzer-

land. In a joint effort, this group is building a comprehen-

sive physics-based device simulation tool for opto-

electronics.

Optoelectronic device simulation is a scientific challenge.

Numerous questions need to be answered both on the

108

theory of numerical modeling and on the applied device

physics. In addition, two aspects have been important for

the successful implementation of the laser simulator:

First, a close collaboration with device manufacturers

has allowed to share detailed device specifications as

well as measurement results. With this data, the simula-

tor could be validated and calibrated. The industrial

device designers, in return, have got access to the simu-

lator at an early stage of the software development. Sec-

ond, a professional software environment is essential for

both the development and the application of the laser

models. The simulator developed in the Optoelectronics

Modeling Group is built as an extension to the general

device and circuit simulator DESSIS. The work of many

PhD theses has provided the scientific basis of this simu-

lator. Since the spin-off of ISE Integrated Systems Engi-

neering AG from IIS in 1993, the computer program has

been commercialized. In consequence, the new laser

simulator is readily equipped with state-of-the-art tools

for geometry editing, mesh generation, and visualization.

In numerous discussions with project partners and users

of device simulation software, the gap between numerics

and industrial device design became evident. This work

bridges theory and application. It provides an effective

means for the numerical calculation of the optical fields in

laser cavities and incorporates them into a versatile

device simulator. The laser extension of DESSIS has

been attested a high utility for the design of advanced

optoelectronic devices.

Prof. Dr. W. Fichtner, ETH Z rich, examiner Diss. ETH-Nr. 14694

Prof. Dr. H. Melchior, ETH Z rich, co-examiner ISBN 3-89649-803-1

Local Mesh Refinement Algorithms for Enhanced Modeling Capabilities in the FDTD Method

Nicolas Chavannes

The trend to mobility and miniaturization in communica-

tion, computing and medicine is clearly heading toward a

fusion of these subsystems in pervasive computing

interconnected intelligent subsystems providing numer-

ous services embedded within human surrounding envi-

ronments a vision rapidly becoming reality within

everyday life. Additional increasing consumer demand for

attractive performance/price ratios as well as interna-

tional mandatory safety guidelines addressing radio-fre-

quency (RF) related possible health effects confront

engineers with the development of highly efficient

devices.The exponential growth of computational power

within recent decades has established a significant posi-

tion for numerical simulation techniques, efficiently sup-

porting product research and development (R&D)

processes. The Finite-Difference Time-Domain (FDTD)

method in particular has been chosen by many research

institutions as the leading technique due to its general

applicability.

The objectives of the presented thesis were derived from

the obvious major drawbacks of the current implementa-

tions of FDTD. These are restricted spatial resolution and

poorly realized computer aided design (CAD) environ-

ments, in addition to unknown uncertainties in the com-

putation results obtained by the method. The de-

velopment of novel robust FDTD local grid refinement

schemes combined with and integrated into user-friendly

electromagnetic (EM) simulation environments became

the main focus of this research work.

A rigorous analysis of various proposed techniques,

mainly in relation to subgridding schemes, enabled the

development of two novel 3-D based methods for FDTD

local grid refinement. Excellent performance of the algo-

rithms for numerous parameters was presented on the

basis of various benchmarks. In particular the subgrid

scheme provides a uniquely wide applicability and

robustness compared to existing approaches. Within the

framework of the Commission for Technology and Inno-

vation (KTI) sponsored SEMCAD++ project, important

contributions to the implementation of a whole EM simu-

lation environment have been performed including the

techniques described in this thesis. The commercialized

simulation platform SEMCAD, providing support for grid-

independent solid modeling, has proven to be an excel-

lent tool for demonstrating the efficiency of final imple-

mentations by simulation of highly complex problems.

At the beginning of this thesis in 1998 the most enhanced

mobile telecommunications equipment (MTE) models

consisted of square shaped helices mounted on perfectly

electric conducting (PEC) boxes. The achieved modeling

improvements finally enabled the easy and efficient appli-

cation of FDTD beyond such generic setups. One of the

latest commercial multi-mode handsets was thoroughly

electromagnetically analyzed based on the electro-

mechanical CAD file of the phone, modeling spatial reso-

lutions the μm range. The performance was analyzed in

free-space as well as in the vicinity of various biological

scatterers. All data was compared to measurements

obtained by the DASY4 near-field scanner. The simula-

tions could accurately predict all performance parame-

ters, even the smallest changes in the grounding of

elements. This most detailed analysis of a real-world

handset scenario clearly demonstrated the power of the

implementation for industrial R&D environments, espe-

cially since the modeling and simulation could be com-

pleted within a few days.


Prof. Dr. N. Kuster, ETH Z rich and IT IS Foundation, ISBN number not available at time of printing

Z rich, co-examiner

109

Substrate Current Effects in Smart Power ICs

Michael Schenkel

Semiconductor companies face the demand for First Sil-

icon Success to be competitive. Substrate current

effects are one major cause for redesigns in junction-iso-

lated Smart Power technologies. Therefore, control of

these effects is paramount.

Substrate currents are difficult to control because they

are of three-dimensional nature and are strongly layout-

dependent. Moreover, protection measures can show

counteracting effects, and minority and majority carrier

effects may occur at the same time. Until now, Smart

Power IC designers have coped with substrate current

effects on an empirical basis.

The motivation for this thesis has been to develop a

Technology Computer Aided Design (TCAD)-based

methodology for substrate current safe designs. A TCAD-

guided approach offers fast evaluation of layout and pro-

tection configurations before silicon has been processed

and allows the simulation of concurrent electron and hole

injection; all this in dependence on relevant technology

and application parameters. Furthermore, the number of

experiments and processing runs can be significantly

reduced in contrast to a pure experimental methodology.

A major goal of this work was the investigation of 3D

effects on a full-chip scale.

Accurate simulation results rely on the calibration of rele-

vant technology parameters. Thus, a calibration proce-

dure validated by a small number of measurements has

been developed. Moreover, for the three-dimensional

simulation of substrate current-relevant structures on a

full-chip scale, a technology-independent topology reduc-

tion methodology that relies on the physical understand-

ing of carrier injection and collection had to be

developed. Verification of the simulation results by exper-

iments is an important and necessary task of the TCAD

methodology. Full-chip 3D device simulations have been

validated against measurements. The achieved overall

agreement is of a factor of 2. This is an enormous

advance compared to the previous situation. At the

beginning of this thesis, even the order of magnitude was

not accessible.


Dr. W. Wilkening, Robert Bosch GmbH, ISBN 3-89649-848-7

Reutlingen (Germany), co-examiner

PhD theses can be ordered from:

Hartung-Gorre Publisher Phone: +49 7533 97227

S ntisblick 26 Fax: +49 7533 97228

D-78465 Konstanz E-mail: [email protected]

Germany Web: http://home.t-online.de/home/hartung.gorre

110

Diploma Theses — Overview

Summer Semester 2002

Adrian Bregy 2D Optical Simulation of Vertical-Cavity Lasers with Step Index Apertures

Davide Cescato FFT-Based Loudspeaker Crossover Network

Flavio Carbognani A Novel Lifetime Prediction Model and Experimental Thermal Transient Analysis

of Power Semiconductor Devices

Winter Semester 2002/2003

Thomas Christen Continuous-Time ΣΔ Modulator for GSM Speech Coding

Felix B rgin Design and Implementation of an Integrated

Adrian Lutz 24-bit A/D Converter for High-Quality DVD Audio

Simon M ller ΣΔ A/D Converters for Cellular Radio Frequency

Integrated Circuit Receiver Design

Michael Gauckler Integrated FPGA Rapid Prototyping Environment

Martin Polasek

Carlos Velasquez

Marcel Pl ss ΣΔ D/A Converter with Clock Recovery for USB Audio

Marc Robert

Patrick Torta Oversampled Pipeline ADC with Mismatch Shaping

J rg Treichler for a MIMO Receiver

Stefan Odermatt Numerical Simulation of Superlattice Structures

Mathieu Luisier Many-Body Effects in Semiconductor Lasers

Matteo Ferrari Automotive Power Semiconductor Devices

111

Student Theses — Overview

Summer Semester 2002

Mathieu Luisier Numerical Calculation of the Optical Gain in Different

Semiconductor Materials

Peter Fercher ΣΔ Audio D/A Converter

Marc Schoenes Runtime-Reconfigurable ALU

Roman Leuzinger

Marco Schurtenegger Acoustical Communications

Winter Semester 2002/2003

Florian Bochud ASIC Design: Reconfigurable Instruction Set Processor

Stefan Eberli

Rolf Gr ninger ASIC Design: Virtual Component for an 8-bit Microcontroller

Roman Plessl

Nicole Hediger ASIC Design: FireWire Link Layer Controller

Reto H pli

Simon Steinegger

Dominique Gasser ASIC Design: Area-Optimized AES Cipher

Franco Hug

Lukas H mmerle ASIC Design: Transparent IDE Encryption and Decryption

Ramon Wicki

Michael Kuhn ASIC Design: Stereopsis — Stereo Vision Based Depth Visualization

Stephan Moser

Oliver Isler

Lukas Walter ASIC Design: Calculation of πRobert Hunger

Remo Jud ASIC Design: Altitude Profile Meter

Thomas Zaugg

Reinhard Bischof ASIC Design: Programmable Code Generators for SW Radio

Jonas Biveroni

Markus Br hwiler

Daniel Engeler ASIC Design: MIDI Synthesizer

Samuel Nobs

Leonardo Leone ASIC Design: Digital Audio Mixer

Kevin Martin

Christoph Pl ss

Martin Flubacher System Design: Electronic Audio Mixer Control

Michael Wagner

Ren Pedron System Design: UMTS Transmitter Demonstrator

Rolf Anderegg Direct Stream Digital (DSD) Audio to PCM Sample Rate Converter

Ulrich Fran on Digital Signal Processor

112

Microelectronics Design Center (DZ)

Personnel

Dr. H. Kaeslin (head, VLSI CAE), C. Balmer (VLSI technology), M. Br ndli (software operation, VLSI CAE/

CAD), F. Camarero (VLSI CAE/CAD), R. K ppel (PCB CAD).

Cooperation With Business Partners

During the last few years, we have witnessed significant changes in the cooperative effort that makes ultra

large scale integration a reality. Implementing a system on a chip (SoC) has made it impossible to design

every ASIC from scratch. Vendors of virtual components, also known as intellectual property modules, have

thus entered the scene. Wafer processing and library distribution, which used to be available from a single

company, are now most often run as separate businesses by a silicon foundry and a library vendor. Side

effects of advanced semiconductor technologies (such as the predominance of interconnect delays, cross-

talk, poor timing closure, subthreshold leakage, fill patterns, phase shift masks, optical proximity correction

and alike) also begin to be felt, making it necessary to piece design flows together from a loose collection of

point tools by various vendors.

The figure below illustrates the business partners that are involved in a typical university VLSI project along

with their major contributions.

Experimental VLSI circuits designed as part of research or higher education have long been fabricated on

multi-project wafers (MPW) to share up-front costs between multiple design teams. The exploding costs of a

mask set for any advanced VLSI fabrication process in conjunction with the economic pressure on foundries

to fill their fabrication lines with revenue-generating volume products have further narrowed down the choice

of available fabrication avenues and MPW vendors.

The rapid progress towards more advanced fabrication processes and ever higher integration densities would

probably have been impossible without these evolutions. Yet, it must be understood that the higher degree of

specialization has also brought about more negotiations with more business partners, more contractual obli-

gations, more compatibility and version problems, and alike. Regrettably, we have also found that the quality

of design kits has suffered from the increased complexity which burdens design centers with extra work for

debugging and design flow integration.

113

Above all, however, the modern models of cooperation imply that university laboratories must plan their

projects more thoroughly in order to make sure that all necessary resources (EDA software, foundry kits, non-

disclosure agreements, macrocells, virtual components, a workable design flow, access to fabrication, test

equipment, trained personnel, etc.) are indeed available within the limitations imposed by budgets and time-

frames. The Microelectronics Design Center has a long experience in such matters and is ready to advise pro-

spective VLSI and system designers. Do not hesitate to contact it when planning a new project.

UMC L250 Process Made Available for Education

As a case in point, consider the elements required to design ICs for UMC L250, a 0.25μm CMOS process that

now replaces the former 0.6μm technology as our mainstay for education projects. Within the Europractice IC

manufacturing service, it is IMEC in Belgium that offers MPW runs in this technology. Wafer processing is car-

ried out by UMC in Taiwan while the cell libraries must be obtained from Virtual Silicon Technology Inc. in

California. A separate non-disclosure agreement had to be signed with each of these partners.

The design flow mandates EDA tools by Synopsys, Cadence and Mentor Graphics, a fact that incited us to

implement a special cockpit software just to set up a workable design environment and to control it. Also, we

had to gain access to the detailed cell layouts as no design rule check (DRC) at the abstract level is imple-

mented in the foundry kit. With a size of 5mm by 5mm, the MPW modules initially offered were way too large

and too expensive for most of our needs. We have thus agreed with the vendor to subdivide each module into

four submodules of equal size.

The overall flow has been tested with two research projects during the summer of 2002 before being adopted

for more than ten student designs in the winter term 2002/03. Making it work and sorting out all the related dif-

ficulties, most notably in the back-end design, has been a major effort, though. There is still room for improve-

ments before the full potential of this process can be tapped.

Supported Fabrication Processes

As any list of supported fabrication processes would be outdated by the time it gets printed, we kindly ask pro-

spective users to refer to our documentation on the Intranet available at

www.dz.ee.ethz.ch/support/IC/technologies/index.en.html.

Design Activities

A statistical overview of all IC and PCB design activities conducted in 2002 with the EDA installations oper-

ated by DZ is given in the tables below along with the laboratory involved and other technical information.

IC Design Teaching Research Total

Process Family Foundry IIS ISI IfH IfE IQE

0.6μm CMOS AMS 9 3 - - - - 12

0.8μm CMOS AMS - - - - - 2 2

0.24μm BiCMOS IBM - - - 1 - - 1

0.15μm GaAs PHEMT IAF - - - 1 - - 1

InP-HBT IfE - - - - 1 - 1

0.12μm CMOS Infineon - 1 - - - - 1

0.18μm CMOS STM - 3 - - - - 3

0.6μm GaAs MESFET Triquint - - - 1 - - 1

0.18μm CMOS TSMC - - - 1 - - 1

0.25μm CMOS UMC - 3 - - - - 3

Total 9 10 - 4 1 2 26

Board Design IIS IfE ISI IQE TIK IfA NARI Total

With individual support 6 - 1 4 1 1 - 13

Freelance projects 6 1 2 23 4 3 1 40

Total 12 1 3 27 5 4 1 53

114

Joint Research Cooperation with IT IS

Foundation for Research on Information Technologies in Society IT IS

Profile

The Foundation for Research on Information Tech-

nologies in Society (IT IS) was founded on Novem-

ber 15th, 1999 through the initiative and support of

the Swiss Federal Institute of Technology in Zurich

(ETHZ), the global wireless communications indus-

try, and several governmental agencies. The aim

was to create a flexible and dynamic research insti-

tution capable of addressing the research needs of

society in the explosively expanding field of infor-

mation technologies. Some of the areas encom-

passed are:

¥ evaluation of the safety and risks related to cur-

rent and emerging information technologies

¥ exploration of information technologies for medi-

cal, diagnostic, and life support systems

¥ improvement of the accessibility of information

technologies for all members of society including

disabled persons.

IT IS is committed to the advancement of science

for the benefit of society at large and to maintaining

strict independence from any particular interest

groups. These principles are reflected in the foun-

dation s charter as well as the balance of the com-

position of its board with distinguished personalities

from science, the public sector, and the global wire-

less communications industry. IT IS is a non-profit

tax-exempt research organization.

Infrastructure and Cooperation

The main research unit of IT IS is located in the

VAW Building at ETH Zurich. In April 2000, IT IS

opened jointly with Schmid & Partner Engineering

AG the world s most advanced near-field laboratory

in downtown Zurich.

The closest and most important cooperative ties

that IT IS has are with ETH Zurich. An excellent

relationship has been established with the Inte-

grated Systems Laboratory. In addition, the IT IS

team has great experience in multi-disciplinary

cooperation through a multitude of projects, result-

ing in an international network of over 50 academic

and industry research partners in Europe, the USA,

and Asia.

Current Research Focus and Projects

The current research focus of IT IS is in the three

areas 1) sensing and computational techniques for

electromagnetic analysis, 2) health risk assess-

ment, and 3) health support systems.

Area 1) consists of six projects dealing with new

sensors and new measurement procedures for

testing the compliance of wireless devices and

base stations with safety limits. A large project con-

centrates on extensions and improvements of

FDTD for near-field applications and optics. The

currently most important research area is Health

Risk Assessment. This mainly involves the develop-

ment, provision, and maintenance of exposure set-

ups as well as the provision of detailed dosimetry

for more than thirty experiments conducted in coop-

eration with biological and medical research groups

in Switzerland, Europe, USA, China, and Japan.

These include in vitro, in vivo, and human provoca-

tion studies at different mobile communications

bands as well as some ELF experiments. In addi-

tion, we are conducting basic and review studies for

different agencies. One major project has just

begun within the activities of the area Health Sup-

port Systems; this area should become the third

main pillar of IT IS activities. Furthermore, IT IS

participates in various standardization committees

and provides near-field and dosimetric evaluations

for governments and industries.

In addition to providing research results for govern-

mental agencies through participation in standard-

ization bodies and providing consultation to

governments, IT IS also provides courses to mem-

bers of the public, industry, and universities.

Current research projects are being supported by

public funds such as those of the Quality of Life

Programme of the European Union, EUREKA, KTI,

VERUM Foundation, health agencies, and other

governmental institutions. Funding from industry

comes from major mobile communications manu-

facturers and service providers as well as from

smaller companies (see page 75ff).

Foundation for Research on Information

Technologies in Society IT IS

Prof. Dr. Niels Kuster

Director IT IS & Associate Member of the Electrical

Engineering Department of the Swiss Federal Insti-

tute of Technology ETH Z rich

ETH VAW Building, Gloriastrasse 37/39

ETH Zentrum, CH-8092 Z rich, Switzerland

Phone: +41 1 245 9696, Fax: +41 1 245 9699

www: http://www.itis.ethz.ch

IT IS Laboratories, Zeughausstrasse 43


115

Workshops and Courses

International Conference on Numerical Simulation of Semiconductor Optoelectronic Devices NUSOD-02

Organized by: Integrated Systems Laboratory

Location: Swiss Federal Institute of Technology (ETH), Z rich

Presentations: 13 invited papers, 19 talks, 10 posters, and 5 company presentations

Dates: 3 days from September 25 to 27, 2002

Participants: 111 from optoelectronics industry and academia

Publication: Conference Proceedings

NUSOD-02, Numerical Simulation of Semiconductor Optoelectronic Devices.

ISBN 3-89649-808-8

Published by Hartung Gorre Publisher

S ntisblick 26, D-78465 Konstanz, Germany

Phone: +49 7533 97227, Fax: +49 7533 97228

E-mail: [email protected]

Web: http://home.t-online.de/home/hartung.gorre

Schematic Entry and Physical Layout for PCBs

Organized by: Microelectronics Design Center

Trainer: R. K ppel

Dates: 4 days from April 11 to May 2, 2002

Participants: 5



Trainer: R. K ppel

Dates: 4 days from April 22 to May 13, 2002

Participants: 4



Trainer: R. K ppel

Dates: 4 days from November 1 to 21, 2002

Participants: 11

116

Education at IIS — Overview

117

118

Lectures

Halbleiterbauelemente 4th Sem.Semiconductor Devices EE

W. Fichtner

This lecture gives an introduction to the basics of modern semiconductor devices for micro-, opto-, and power-

electronics. It bases on semiconductor physics and covers band structures, band models, dispersion rela-

tions, statistics, transport equations, macroscopic models, and the characteristics of silicon and other semi-

conductors. An overview on device families is presented.

The part on technologies covers the properties of materials, and introduces the steps of modern process

technologies as well as packaging. To understand the basic principles of devices, ohmic and rectifying con-

tacts, physical and electrical characteristics of pn junctions, and types of diodes are explained. The lecture

continues with the bipolar transistor s function, working regions, characteristic diagrams, and its simulation.

MOS devices are treated based on band diagrams, and the MOSFET behavior is deduced. Power devices,

their working regions and static and dynamic behavior are followed by examples of optoelectronic devices as

photo conductor, photodiode, LED, and fiber. Semiconductor measurement and characterization methods

conclude the course.

Kommunikationselektronik 5th Sem.Communications Electronics EE

Q. Huang

This course provides basic design and circuit techniques for communications electronics. As a starting point,

bipolar and MOS transistors are reviewed. The discussion of circuit design begins with basic amplifier topolo-

gies, impedance matching concepts, and a bit of two-port theory. Important non-ideal aspects such as non-lin-

earity and noise are discussed. This sets the ground for more involved topics. Important building blocks of

communications equipment, such as mixers and oscillators, are examined in detail. The discussions include

the basic topologies, mathematical descriptions, and a thorough analysis of non-ideal behavior, from which

finally guidelines for the design can be derived.

The exercises form an integral part of this course. The definitions and concepts presented in the lecture will be

reinforced by small design examples, therefore providing a link between the theoretical description and real-

world problems.

VLSI I: Architektur von hochintegrierten Schaltungen 6th Sem.VLSI I: Architectures of Highly Integrated Circuits EE/CS/Phys/CSE

N. Felber, W. Fichtner, H. Kaeslin

As becomes clear from the subsequent list of topics, the first course in this series of three is mainly concerned

with system-level issues of VLSI. Terminology, overview on design methodologies and fabrication avenues,

levels of abstraction used for circuit description and simulation, VLSI design flow, dedicated VLSI architec-

tures, how to obtain an architecture for a given processing algorithm, architectural transformations for meeting

throughput, area, and power requirements. Hardware Description Languages (HDL) and their underlying con-

cepts, VHDL for simulation and synthesis, the IEEE-1164 logic system, Register Transfer Level (RTL) synthe-

sis. Timing models, Anceau diagrams, functional verification of digital circuits and systems, building blocks of

digital VLSI circuits, case studies of actual circuits, comparison with microprocessors and DSPs.

During the exercises students learn how to model digital ICs with VHDL. They write testbenches for simulation

purposes and synthesize gate-level netlists for ASICs and FPGAs.

VLSI II: Entwurf von hochintegrierten Schaltungen 7th Sem.VLSI II: Design of Highly Integrated Circuits EE/CS/Phys/CSE

N. Felber, W. Fichtner, H. Kaeslin

The second course begins with a thorough discussion of various technical aspects at the circuit and layout

level. It then moves on to economic issues of VLSI. Topics include: limitations of functional design verification,

119

techniques for improving controllability and observability, design for test, block isolation, scan-path techniques,

partial scan and its caveats. Evaluation of various synchronous clocking disciplines, skew margins, clock dis-

tribution techniques. Asynchronous inputs, data inconsistency and metastability problems, synchronization.

Cell libraries, Process-Temperature-Voltage (PTV) variations, transistor models, characteristics of CMOS

inverters, complex gates. Power estimation and low-power design. Layout parasitics, transport delay, switch-

ing currents, ground bounce, controlling noise problems, power distribution, floorplanning, chip assembly. Lay-

out design at the mask level, symbolic layout. Timing verification, physical design verification. Cost structures

of microelectronics design and fabrication, avenues to low-volume fabrication, management of VLSI projects.

Exercises are concerned with physical design and sound engineering practices for avoiding timing, testability,

and layout parasitics problems. Industrial CAD tools are being used for place and route, clock tree generation,

chip assembly, and physical design verification. Students that elect to carry through a term project at the labo-

ratory are offered the opportunity to complete a full IC design cycle on a circuit of their own which gets actually

fabricated.

VLSI III: Fabrikation und Verifikation von hochintegrierten Schaltungen 8th Sem.VLSI III: Fabrication and Verification of Highly Integrated Circuits EE/CS/Phys/CSE

N. Felber, W. Fichtner, Kaeslin

Whereas the preceding courses deal with design aspects of VLSI circuits, this one addresses manufacturing,

testing, physical analysis, and packaging issues, such as: Effects of fabrication defects, abstraction from phys-

ical to transistor- and gate-level fault models, fault grading of large ASICs. Generation of efficient test vector

sets, enhancement of testability by built-in self-test techniques. Modern IC testers: Architectures and applica-

tion. Deep-submicron CMOS fabrication processes with multi metal levels and the physical analysis of their

devices. Packaging problems and solutions. Technology outlook.

Exercises teach students how to use CAE/CAD software and automatic test equipment for verifying ASICs

after fabrication. Students that submitted a design for manufacturing at the end of the 7th semester do so on

their own circuits. Physical analysis methods with professional equipment (AFM, DLTS) complement this train-

ing.

Analoge integrierte Schaltungen 6th Sem.Analog Integrated Circuits EE

Q. Huang

This course provides a foundation in analog integrated circuit design: After a review of bipolar and MOS

devices and their small-signal equivalent circuit models, building blocks in analog circuits such as current

sources, active load, current mirrors, supply independent biasing are presented. Other topics are differential

amplifiers, cascode amplifiers, high gain structures, and output stages, and comparators, gain bandwidth

product and stability of op-amps. Second-order effects in analog circuits such as mismatch, noise, and offset

are investigated. More complex circuits such as A/D and D/A converters, analog multipliers and oscillators are

analyzed. An introduction to switched-capacitor circuits from an IC designer s point of view is given.

The exercise sessions aim to reinforce the lecture material by well-guided step-by-step design tasks. Cadence

design tools are used to facilitate the tasks. There is also an experimental session on op-amp measurements.

Festk rperelektronik 5 th Sem.Solid State Electronics EE

W. Fichtner

This lecture presents important concepts of modern solid-state physics that form the foundation of today s

devices, circuits and systems. Its goal is to relate the theoretical concepts to important practical applications.

Detailed explanations of the electronic, vibrational, and optical properties of solids, and in particular semicon-

ductors, are given. Phenomena related to electronic, optical, magnetic, and temperature effects are explored

in terms of their physical origin. The approach is physical and intuitive rather than mathematically formal and

pedantic. Special emphasis is given to the physics of modern devices, e.g. optics and transport phenomena in

lower dimensional structures. The course also contains several lectures on optical and electronic phenomena

in organic materials.

120

Grundlagen der Optoelektronik I 7th Sem.Physics of Optoelectronic Devices I EE

W. Fichtner

This lecture gives an introduction to the physical principles of optoelectronic devices and circuits. An overview

of modern semiconductor devices and circuits, and important physical effects is presented. The physical

background on quantum mechanics, quantum electronics, and solid-state physics leads to the physics of het-

erostructures. This first course on optoelectronic devices concludes with the interaction of light and matter, the

generation and detection of photons, and the modulation of light in semiconductors.

Grundlagen der Optoelektronik II 8th Sem.Physics of Optoelectronic Devices II EE

W. Fichtner

This course presents the physical foundations of the operating principles of modern optoelectronic devices. It

also includes an in-depth survey of the material science and technology used today. All modern optoelectronic

devices are treated: photoconductors and -detectors, different photodiodes and avalanche devices, light-emit-

ting diodes, members of the growing family of laser diodes (edge-emitting, VCSELs, DFBs, and quantum-cas-

cade devices).

Halbleiter-Bauelemente: Physikalische Grundlagen und Simulation 7th Sem.Semiconductor Devices: Physical Principles and Simulation EE/Phys

A. Schenk

This course aims at understanding the principles behind the physics of modern electronic silicon semiconduc-

tor devices and the foundations of physical modeling of transport and its numerical simulation. During the

course basic knowledge on quantum mechanics, semiconductor physics, and device physics is also provided.

The main topics are: Transport models for semiconductor devices (quantum transport, Boltzmann equation,

drift-diffusion model, hydrodynamic model), physical characterization of silicon (intrinsic properties, band gap

narrowing, scattering processes), mobility of cold and hot carriers, recombination (SRH statistics, lifetimes for

tunnel-assisted transitions), interband tunneling (Zener diode), impact ionization, metal-semiconductor con-

tact, MIS structure, and heterojunctions.

The exercises focus on the theory and the basic understanding of special devices, such as pn-diodes, bipolar

transistors, MOSFETs, and thyristors. Numerical simulations of these devices with an advanced simulation

package are compared with corresponding measurements, which are also part of the exercises.

Halbleitertransporttheorie und Monte-Carlo Bauelementsimulation 8th Sem.Semiconductor Transport Theory and Monte-Carlo Device Simulation EE/CSE

F. Bufler, A. Schenk

The aim of the course is, on the one hand, to establish the link between microscopic physics and its concrete

application in device simulation and, on the other hand, to introduce the numerical techniques involved. The

scope encompasses therefore the basics of quantum mechanics, transport theory, and the Monte-Carlo

method for the solution of the Boltzmann transport equation. The topics include second quantization, crystal

symmetries, band structure calculation, phonons, Boltzmann equation, probability calculus, Monte-Carlo tech-

niques, and device simulation.

The exercises comprise problems to illustrate the contents of the lecture, simple Monte-Carlo related pro-

gramming tasks as well as the application of various professional tools for device simulation.

Elektrotechnik I 3rd Sem.Electrical Engineering I MPE

Q. Huang

This course provides the basic foundation in the specific field of electrical engineering. Starting from the basic

concepts of voltage and currents, it covers the basic analyses of DC and AC networks. This includes series

and parallel circuits, resistive circuits, circuits including capacitors and inductors, as well as the Kirchhoff s

121

laws governing such circuits, and other network theorems. Transient response of RC-circuits, analysis of res-

onant circuits, concept of filtering, and simple filter circuits are all among the subjects covered in this course.

The understanding of the basic concepts of electrical engineering, particularly of circuit theory, shall be

advanced. At the end of the course, the successful student knows the basic elements of electric circuits and

the basic laws and theorems for determining voltages and currents in circuits with such elements. He/she is

also familiar with basic circuit calculations.

Abbreviations:

CS Computer Science

CSE Computational Science and Engineering

EE Electrical Engineering

MPE Mechanical and Process Engineering

Phys Physics

122

IC Design Projects — Overview

2002: Project: Status:

Reconfigurable Instruction Set Processor student project /

Calculation of π student project /

Digital Audio Mixer student project /

Stereopsis — Stereo Vision Based Depth Visualization student project /

Area-Optimized AES Cipher student project /

Transparent IDE Encryption and Decryption student project /

Altitude Profile Meter student project /

Virtual Component for an 8-bit Microcontroller student project /

MIDI Synthesizer student project /

Programmable Code Generators for SW Radio student project /

FireWire Link Layer Controller student project /

Continuos-Time ΣΔ Modulator for GSM Speech Coding diploma project /

24-bit A/D Converter for High-Quality Audio diploma project /

ΣΔ A/D Converters for Cellular Radio Frequency diploma project /

USB Audio Sample Rate Converter and DAC with Clock Recovery diploma project /

Oversampled Pipeline ADC with Mismatch Shaping for a MIMO Receiver diploma project /

14-bit 200Msample/s D/A Converter with Background Calibration research project +

Broadband Sigma-Delta D/A Converter research project /

10GHz Voltage-Controlled Oscillator and Prescaler research project /

4GHz Integer-N Frequency Synthesizer research project ~

2GHz 0.12μm CMOS Transceiver for UMTS research project +

Electro Cardiogram ASIC research project t

Test Integration for GALS Pausable Oscillators: OSCAR research project +

GALS Bus Chip research project /

Digitally Controlled Oscillator research project ~

Digitally Controlled Oscillator — Redesign research project ~

Multimedia Network SoC research project /

2001: Project: Status:

SERPENT Encryption ASIC student project +

RIJNDAEL Encryption ASIC student project ~

FFT-Based Audio Equalizer student project +

PIC Microcontroller Virtual Component student project +

LIN Automotive Network Interface Chip for Smart Sensor student project +

Real-Time Image Filter Processor ASIC student project +

JAVA Virtual Machine Co-Processor Chip student project +

Source Coder for Bio-Medical Data Transfer student project +

MIMO UMTS Baseband Integrated Circuit student project c

Compact Microcontroller Core as Virtual Component student project c

123

GSM Speech Synthesizer student project n

Fast 10-bit Sample-and-Hold Circuit student project n

Low-Voltage, Low-Power DDA-Based Front End student project n

Efficient Arithmetic Coder for Video Compression diploma project +

Digital Communications System for BodyCom diploma project +

OIF SPI-5 Receiver diploma project c

Fast Comparator for Analog-Digital Converters diploma project c

Low-Power GPS RF Front End in 0.18μm CMOS diploma project n

14-bit 50Msample/s D/A Converter with Background Calibration research project +

2GHz 0.12μm CMOS Transmit I/Q Modulator for UMTS research project p

2GHz 0.25μm CMOS Transmit I/Q Modulator for UMTS research project +

Broadband Sigma-Delta D/A Converter research project p

8-bit Folding and Interpolating A/D Converter research project +

Baseband Circuits for a UMTS Zero-IF Mobile Receiver in 0.25μm CMOS research project ~

Baseband Circuits for a UMTS Zero-IF Mobile Receiver in 0.12μm CMOS research project p

Status Marks:

+ successfully tested design / chip in fabrication

~ functioning, but with minor bugs ¥ design project in progress

— severe design errors t chip under test

n not submitted to integration (not implemented) T design for test structures

c contribution to research or industrial chip p process errors

124

Research Projects — Overview

IC and System Design and Test

Subject: Real-Time MIMO OFDM Systems for High Speed Broadband Wireless Access

Partner: Communication Technology Laboratory, ETH Z rich, Z rich (Switzerland)

Period: July 02 — June 05

Funding: ETH Z rich, Z rich (Switzerland)

Subject: Lehre und Forschung in Mikroelektronik

(Education and Research in Microelectronics)

Period: April 99 — December 03

Funding: ETH Z rich, Z rich (Switzerland)

Subject: Testable Low-Power Architectures for Multistandard Radio Systems

Partner: Philips Z rich AG Semiconductors, Z rich (Switzerland)

Period: August 00 — June 03

Funding: KTI*

Philips Z rich AG Semiconductors, Z rich (Switzerland)

Subject: Energy-Efficient Processing of Speech Data

Partner: Bernafon AG, Bern (Switzerland)

Period: August 00 — August 03

Funding: KTI*

Bernafon AG, Bern (Switzerland)

Subject: Netzwerkprozessor f r LAN/WAN Bridging im Umfeld professioneller

Multimedia Content Produktionen

(Network Processor for LAN/WAN Bridging in the Environment of

Professional Multimedia Content Productions)

Partner: BridgeCo AG, D bendorf (Switzerland)

Computer Engineering and Networks Laboratory, ETH Z rich, Z rich (Switzerland)

Period: August 00 — April 02

Funding: KTI*

BridgeCo AG, D bendorf (Switzerland)

Subject: Netzwerkprozessor f r LAN/WAN Bridging im Umfeld professioneller

Multimedia Content Produktionen 2

(Network Processor for LAN/WAN Bridging in the Environment of

Professional Multimedia Content Productions 2)

Partner: BridgeCo AG, D bendorf (Switzerland)

Computer Engineering and Networks Laboratory, ETH Z rich, Z rich (Switzerland)

Period: May 02 — Oktober 03

Funding: KTI*

BridgeCo AG, D bendorf (Switzerland)

Subject: GALS 2 Towards Practical GALS Circuits

Partner: Infineon Technologies AG, M nchen (Germany)

Period: April 01 — September 03

Funding: Infineon Technologies AG, M nchen (Germany)

125

Subject: An Integrated Wideband-MIMO Receiver for Wireless Multimedia

Communication

Partner: Lucent Technologies, Holmdel (USA)

Period: March 01 — February 02

Funding: Lucent Technologies, Holmdel (USA)

Subject: An Integrated Wideband-MIMO Receiver for Wireless Multimedia

Communication 2

Partner: Lucent Technologies, Holmdel (USA)

Period: March 02 — February 03

Funding: Lucent Technologies, Holmdel (USA)

Analog and Mixed-Signal Design

Subject: Design Methodology and Implementation of a 3rd Generation W-CDMA

Transceiver Using Deep Submicron CMOS Technologies (LEMON)

(European IST Project)


Institute for Communications and Information Engineering,

Johannes Kepler Universit t Linz, Linz (Austria)

Period: January 00 — September 02

Funding: BBW*, European Union

Subject: OTRACOM — Optimization of Highly Linear Low-Power Transmitters for

Third-Generation Mobile Communications

Partner: Philips Z rich AG Semiconductors, Z rich (Switzerland)

Period: October 01 — September 03

Funding: KTI*

Philips Z rich AG Semiconductors, Z rich (Switzerland)

Technology CAD

Subject: MAGIC FEAT — Meshes and Global Integration for Semiconductor

Front-End Simulation


Partner: Fraunhofer-Institut f r Integrierte Schaltungen,

Bauelementetechnologie, Erlangen (Germany)

Institut National de Recherche en Informatique et Automatique (INRIA),

Le Chesnay (France)

ST Microelectronics, Gentilly (France)

Technical University of Vienna, Wien (Austria)

ISE Integrated Systems Engineering AG, Z rich (Switzerland)

Period: January 00 — December 02


126

Subject: NANOTCAD — Nanotechnology Computer Aided Design


Partner: Universita degli studi di Pisa, Pisa (Italy)

National Microelectronics Research Centre, Cork (Ireland)

Max-Planck-Institut f r Festk rperforschung, M nchen (Germany)

Technical University Vienna, Institute for Microelectronics, Wien (Austria)

Bayerische Julius-Maximilians-Universit t W rzburg, W rzburg (Germany)

Period: April 00 — March 03


Subject: UPPER+ — User Group for Process Simulation European Research

+ Device Simulation


Partner: Fraunhofer-Institut f r Integrierte Schaltungen, Erlangen (Germany)

austriamicrosystems AG, Unterpremst tten (Austria)

Infineon Technologies AG, M nchen (Germany)

Philips Research Leuven, Leuven (Belgium)

STMicroelectronics SA, Crolles (France)

STMicroelectronics Srl, Agrate Brianza (Italy)


SIGMA-C, M nchen (Germany)

Institut f r Microelektronik, Technische Universit t Wien, Wien (Austria)



Subject: Large Scale Eigenvalue Problems in Opto-Electronic Semiconductor Lasers

and Accelerator Cavities

Partner: Institute for Scientific Computing, ETH Z rich, Z rich (Switzerland)

Department of Computer Science, University Basel, Basel (Switzerland)

Paul Scherrer Institute, Villigen (Switzerland)


Funding: Strategic Excellence Projects (SEP): Computational Science and Engineering

(CSE)

ETH Z rich

Subject: Hybrid-Simulatoren f r sub-0.1 μμμμ-Halbleiter-Bauelemente

(Hybrid Simulators for sub-0.1μμμμ-Semiconductor Devices)

Partner: ISE Integrated Systems Engineering AG, Z rich (Switzerland)


Funding: KTI*


Subject: Entwicklung eines Programmes zur Simulation von Quantenwell-Lasern

(Development of a Simulation Program for Quantum Well Lasers)


Bookham (Switzerland) AG, Z rich (Switzerland)


Funding: KTI*


Bookham (Switzerland) AG, Z rich (Switzerland)

127

Subject: Iterative Methoden zur parallelen L sung grosser linearer Gleichungssysteme

aus der Halbleiter-Simulation

(Iterative Methods for Parallel Solving of Large Linear Systems from

Semiconductor Simulation)


Period: July 00 — January 03

Funding: KTI*


Subject: VCSELs — Numerical Simulation of Vertical-Cavity Surface-Emitting Laser

Diodes


Pilot User: Institute for Micro- and Nanoelectronics, EPF Lausanne, Lausanne (Switzerland)

Avalon Photonics AG, Z rich (Switzerland)

Laboratory for Electromagnetic Fields and Waves, ETH Z rich, Z rich (Switzerland)

Walter Schottky Institut, TU M nchen, Garching (Germany)

Period: Oktober 00 — September 02

Funding: TOP NANO 21


Subject: Improvement of Semiconductor Process Simulator by Atomistic Simulation

Techniques (MOLDYN)





Subject: High Speed and Quantum-Well Photodetectors

Partner: Opto Speed AG, R schlikon (Switzerland)





Subject: Modeling of General Multi-Quantum-Well Structures Including Self-Consistent

Coupling to a Laser Simulator (MQW)

Partner: Bookham (Schweiz) AG, Z rich (Switzerland)





Subject: Meshes and Global Integration for Semiconductor Front-End Simulation



Funding: ISE Integrated Systems Engineering AG, Z rich (Switzerland)

Subject: Intraband Photon Absorption in Multi-Quantum-Well (MQW) Structures

Partner: Fujitsu Laboratories Ltd., Atsugi (Japan)


Funding: ISE Integrated Systems Engineering AG, Z rich (Switzerland)

Subject: Modeling and Simulation of Correlated Carrier Transport in Semiconductor

Devices


Funding: SNF*

128

Physical Characterization and Technology Development

Subject: HERCULAS — High Resolution Electrical Characterization of ULSI and

Advanced Semiconductor Devices

(European IHP—RTN Project)

Partner: Interuniversity Microelectronics Centre (IMEC), Leuven (Belgium)

Hahn-Meitner-Institut Berlin GmbH, Berlin (Germany)

STMicroelectronics SA, Crolles (France)

Philips Electronics Nederland B.V., Eindhoven (The Netherlands)

Universit t Hamburg, Hamburg (Germany)


Consiglio Nationale di Metodolgie e Tecnologie per la Microelettronica

(CNR-IMETEM), Catania (Italy)

Kungl Tekniska H gskolan, Kista (Sweden)

Institute for Semiconductor Physics, Frankfurt (Germany)

Tel-Aviv University, Tel-Aviv (Israel)

Period: Oktober 00 — September 03


Subject: HIMRATE — High-Temperature IGBT- and MOSFET-Modules for Railway

Traction and Automotive Electronic Application

(European GROWTH Project)

Partner: Siemens AG, M nchen (Germany)

Regienov — Renault Recherche et Innovation, Guyancourt (France)

Institut National de Recherche sur les Transport et leur S curuit (INRETS),

Arcueil (France)

Centro Ricerche Fiat ScpA, Orbassano (Italy)

EUPEC GmbH & Co. KG, Warstein (Germany)

Ferraz Date Industries S.A., La Mure (France)

Electrovac Fabrikation Elektrotechnischer Spezialartikel GmbH,

Klosterneuburg (Germany)


Ansaldo Transporti SpA, Napoli (Italy)

Technical University Vienna, Wien (Austria)

Technische Universit t M nchen, M nchen (Germany)

Period: November 00 — Oktober 03


Subject: DEMAND — Integrated Design Methodology for Enhanced Device Robustness



Technical University of Vienna, Wien (Austria)

Uni Bologna, Universita degli Studi di Bologna, Dipartimento di Elettronica

Informatica e Sistemistica, Bologna (Italy)


Period: September 01 — August 04


Subject: Modellierung und Charakterisierung von IGBT-Modulen

(Modeling and Characterization of IGBT-Modules)

Partner: ABB Corporate Research Ltd., D ttwil (Switzerland)

ABB Semiconductors AG, Lenzburg (Switzerland)


Period: March 01 — July 01

Funding: KTI*

ABB Corporate Research Ltd., D ttwil (Switzerland)

ABB Semiconductors AG, Lenzburg (Switzerland)

129

Subject: ASDESE — Application Specific Design for ESD and Substrate Effects

Partner: Robert Bosch GmbH, Reutlingen (Germany)

Period: September 01 — February 03

Funding: Robert Bosch GmbH, Reutlingen (Germany)

German Government

Subject: SP3M — Scanning Probe Microscopy Assisted Modeling in Microelectronics

(Part 2)


Funding: SNF*

Subject: Total Simulation Between Electrical and Thermal Effect for Automobile IGBT

Modules

Partner: Toyota Central Laboratories Inc., Aichi (Japan)

Period: February 01 — January 02

Funding: Toyota Central Laboratories Inc., Aichi (Japan)

Subject: Modelling of the High-Frequency SOI Power MOSFET

Partner: Nippon Telegraph and Telephone Corporation, Tokyo (Japan)



Funding: Nippon Telegraph and Telephone Corporation, Tokyo (Japan)

Bio Electromagnetics and Electromagnetic Compatibility

Subject: REFLEX — Risk Evaluation of Potential Environmental Hazards from Low

Energy Electromagnetic Field Exposure Using Sensitive In Vitro Methods


Partner: Stiftung f r Verhalten und Umwelt (VERUM), M nchen (Germany)

Universit tsklinikum Benjamin Franklin der freien Universit t Berlin,

Berlin (Germany)

Universit tsklinik f r Innere Medizin IV Klinische Abteilung Arbeitsmedizin,

Wien (Austria)

Institut f r Pflanzengenetik und Kulturpflanzenforschung Gatersleben,

Gatersleben (Germany)

Investigacion Bioelectromagnetismo Hospital Ramon y Cajal, Madrid (Spain)

STUK Helsinki — Radiation and Nuclear Safety Authority, Helsinki (Finland)

Institut f r Biophysik Universit t Hannover, Hannover (Germany)

Universita degli Studi di Bologna Dipartimento di Fisica, Bologna (Italy)

Ecole Nationale Sup rieure de Chimie et de Physique de Bordeaux,

Talence (France)

Universita degli Studi di Milano, Milano (Italy)

Period: February 00 — August 03


130

Subject: SEMCAD++: Extension/Improvement of the TCAD Engine SEMCAD for

Antenna/EMC

Partner: Foundation for Research on Information Technologies in Society (IT IS),

Z rich (Switzerland)

Schmid & Partner Engineering AG, Z rich (Switzerland)



Funding: KTI*

IT IS, Z rich (Switzerland)


Subject: TD Sensor




Period: November 02 — October 03

Funding: KTI*


Subject: Definieren der Messmethodik und Verkleinern der Messunsicherheit bei

Immissionsmessungen in Wohn- und Gesch ftsh usern

(Definition of Measurement Methodology and Reduction of Measurement

Uncertainty of Electromagnetic Field Measurements in Living and Business

Rooms)



Period: August 00 — July 02

Funding: FNM, Z rich (Switzerland)

Subject: Untersuchung der SAR-Verteilung in elektromagnetisch exponierten

Versuchstieren

(Investigation of the SAR-Distribution in Electromagnetic Exposed

Experimental Animals)

Partner: Bundesamt f r Strahlenschutz, Salzgitter (Germany)


Funding: Bundesamt f r Strahlenschutz, Salzgitter (Germany)

Subject: Forschungskooperation IT IS — ETH Z rich

(Research Cooperation IT IS — ETH Z rich)



Period: since January 00

Funding: IT IS, Z rich (Switzerland)

Abbreviations

BBT Federal Office for Professional Education and Technology

(a Swiss Government Agency)

BBW Federal Office for Education and Science


KTI Commission for Technology and Innovation


SNF Swiss National Science Foundation

TOP NANO 21 Technology Oriented Program for Nano Sciences

(Research and Technical Development Cooperations between Swiss Universities,

Institutes, and Swiss Enterprises, funded by the Swiss Government)

131

Presentations

2002

G. Acunto, M. Sans, A. Burg, W. Fichtner

An ASIC Implementation of Adaptive Arithmetic Coding ,

36th Asilomar Conference on Signals, Systems and Computers, USA, Nov. 3—6, 2002.

G. Brenna, D. Tschopp, D. Pfaff, Q. Huang

A 2GHz Direct-Conversion WCDMA Modulator in 0.25 μm CMOS ,

IEEE International Solid-State Circuits Conference, San Francisco, USA, Feb. 3—7, 2002.

F. M. Bufler

Calibration with Monte Carlo Simulation and Practical Aspects Using SPARTA ,

Toshiba Corporation, Yokohama, Japan, Sept. 2, 2002.

F. M. Bufler, C. Zechner, A. Schenk, W. Fichtner

Self-Consistent Single-Particle Simulation ,

Int. Conf. on Simulation of Semiconductor Processes and Devices (SISPAD 2002), Kobe, Japan, Sept. 4—6,

2002.

F. M. Bufler

SPARTA−Single-PARTicle Approach to Self-Consistent Monte Carlo Device Simulation and How to Use

SPARTA ,

ST Microelectronics, Crolles, France, Dec. 12, 2002.

A. Burg, E. Beck, M. Rupp, D. Perels, N. Felber, W. Fichtner

FPGA Implementation of a MIMO Receiver Front-End for UMTS ,

International Zurich Seminar on Broadband Communication, Zurich, Switzerland, Feb. 18—21, 2002.

F. Carbognani, M. Ciappa, P. Cova, W. Fichtner

A Novel Thermomechanics-Based Lifetime Prediction Model for Cycle Fatigue Failure Mechanisms in Power

Semiconductors ,

13th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, Rimini, Italy,

Oct. 7—11, 2002.

N. Chavannes

TCAD of Mobile Phones: Guidelines for MTE Design Using FDTD ,

AP-S International Symposium and USNC/URSI National Radio Science Meeting, San Antonio, USA,

June 16—21, 2002.

N. Chavannes

RF Design of Mobile Phones by TCAD: Suitability and Limitations of FDTD ,

27th General Assembly of the International Union of Radio Science, Maastricht, Netherlands, Aug. 17—24,

2002.

N. Chavannes, N. Kuster

2-Day Tutorial Workshop: RF Design of Mobile Telecommunications Equipment with TCAD ,

Korea Design Center, Seoul, Korea, Nov. 18—19, 2002.

N. Chavannes

Latest Progress in Numerical RF Design of Mobile Telecommunications Equipment (Invited) ,

Technical Seminar at Matsushita Communication Engineering Co., Ltd., Yokohama, Japan, Nov. 25, 2002.

N. Chavannes

Novel RF Design Tools for Analysis and Design of Handheld Transceivers (Invited) ,

Technical Seminar at Chiba University, Chiba, Japan, Nov. 29, 2002.

N. Chavannes


2002 Interim International Symposium on Antennas and Propagation (ISAP i-2002), Yokusuka, Japan,

Nov. 26—28, 2002.

132

M. Ciappa

Building In Reliability in Power Electronics ,

Workshop organized by the Technical University of Denmark, Kolding and Lyngby, Denmark, Aug. 19—20,

2002

M. Ciappa (Moderator)

Workshop on Reliability in Automotive Power Electronics ,


Oct. 7—11, 2002.

S. Dragone

Tightly Coupled Coprocessors in Network Applications ,

Seminar Talk at IBM Zurich Research Laboratory, R schlikon, Switzerland, Dec. 13, 2002.

S. Dragone

Tightly Coupled Coprocessors in Network Processors ,

Seminar Talk at the Institute of Computer Engineering, University of L beck , L beck, Germany, Dec. 18,

2002.

S. Ebert

Introduction to the PERFORM A Exposure System for Large Scale In Vivo Health Risk Assessment Studies

with Rats at 902MHz and 1747MHz ,

RCC Ltd., Liestal, Switzerland, Apr. 17, 2002.

S. Ebert

Simulating Environmental GSM Features for Use in Bioexperiments ,

24th Annual Meeting of the Bioelectromagnetics Society, Quebec, Canada, June 23—27, 2002.

S. Ebert

Advanced 900MHz Exposure System for Rats ,

Austrian Research Centers Seibersdorf, Seibersdorf, Austria, June 12, 2002.

S. Ebert

In Vivo Exposure System for Rats at 900MHz for Health Risk Assessment Studies ,

Zhejiang University School of Medicine, Hang Zhou, China, Aug. 28, 2002.

J. Fr hlich

Rigorous Analysis of EM Absorption in High Resolution Anatomical Models Using FDTD ,

AP-S International Symposium and USNC / URSI National Radio Science Meeting, San Antonio, USA,

June 16—21, 2002.

J. Fr hlich

Ratio of Spatial Peak and Whole Body SAR Dependent on Frequency and Polarization in Animals and

Humans ,


2002.

F. K. G rkaynak

An Introduction to the GALS Methodology at ETH Zurich ,

CANDE (Computer—Aided Network Design) 2002 Workshop, Anchorage, USA, Sept. 22—24, 2002.

F. K. G rkaynak

Globally-Asynchronous Locally-Synchronous System Design ,

Microelectronic Systems Laboratory (LSM) Seminar, Lausanne, Switzerland, Nov. 29, 2002.

F. O. Heinz, A. Schenk, W. Fichtner

Conductance of Nano-Scale Silicon-On-Insulator Single Electron Transistors ,

9th MEL-ARI / NID Workshop, Catania, Italy, Feb. 6—8, 2002.

F. O. Heinz, A. Schenk, W. Fichtner

Conductance in Single Electron Transistors with Quantum Confinement ,

2nd International Conference on Semiconductor Quantum Dots, Tokyo, Japan, Sept. 30—Oct. 3, 2002.

133

T. H hr, A. Schenk, A. Wettstein, W. Fichtner

On Density-Gradient Modeling of Tunneling through Insulators ,


2002.

Q. Huang, C. Hammerschmied, T. Burger

Meeting the Challenge of High Dynamic Range, High Speed A/D Conversion for Software-Defined Radio

(SDR) ,

5th Wireless World Research Forum (WWRF) Meeting, Tempe, USA, Mar. 7—8, 2002.

Q. Huang

Trends and Challenges in Transceivers for Wireless Communications ,

Epcos AG, Munich, Germany, Apr. 18—19, 2002.

Q. Huang

Challenges of RF Transceivers in a Software-Defined Radio ,

Presentation of SDR White Paper to WG 3, WWRF, London, United Kingdom, June 25—26, 2002.

Q. Huang

Integrated Circuit Design for Communications ,

Harbin Inst. of Technology, Harbin, China, Aug. 7, 2002.

Q. Huang

Analog Signal Processing and Related Bipolar and CMOS Circuit Design ,

CEI Course, Nice, France, Nov. 25—27, 2002.

R. Huber, A. A. Borb ly, J. M. Gottselig, N. Kuster, H. P. Landolt, J. Schuderer, E. Werth, P. Achermann

Electromagnetic Fields and Sleep EEG: Effect of Signal Modulation ,

ESRS Congress, Reykjavik, Iceland, June 3—7, 2002.

R. Huber, A. A. Borb ly, J. M. Gottselig, N. Kuster, H. P. Landolt, J. Schuderer, E. Werth, P. Achermann

Effects of Electromagnetic Fields of Mobile Phones on the Human Sleep EEG ,

APSS Congress,16th Annual Meeting, Seattle, USA, June 8—13, 2002.

N. Kuster

Trends in Antenna Design & SAR Measurements (Invited Tutorial) ,

SAMSUNG Electronics, Seoul, Korea, Mar. 4, 2002.

N. Kuster

Update on Safety Standards & SAR Measurements (Invited Tutorial) ,

South African Bureau of Standards, Pretoria, South Africa, Apr. 23, 2002.

N. Kuster

Advanced Exposure Systems for In Vivo Studies (Invited) ,

Technical Seminar at Research Labs NTTDoCoMo, Tokyo, Japan, July 11, 2002.

N. Kuster

Improved Calibration Techniques (Invited) ,

Technical Seminar at CRL, Tokyo, Japan, July 12, 2002.

N. Kuster

Exposure Setups for Large Scale In Vivo RF Studies (Invited Tutorial) ,

Zhejiang University, Hangzhou, China, Sept. 4, 2002.

N. Kuster

Human Head Phantoms for Compliance and Communication Performance Testing of Mobile Communica-

tions Equipment at 900MHz ,

2002 Interim International Symposium on Antennas and Propagation (ISAP i-2002), Yokusuka, Japan,

Nov. 26—28, 2002.

D. Leszczynski, R. Kuokka, S. Joenv r , T. Toivo, A. Sihvonen, J. Schuderer, K. Jokela, N. Kuster

Indirect Evidence of Non-Thermal Biological Effects Induced by Mobile Phone Radiation In Vitro ,

Cost 281 Management Committee Meeting, London, United Kingdom, Nov. 12—13, 2002.

134

M. Luisier, M. Pfeiffer, W. Fichtner

Advanced Laser Simulation Using the DESSIS Physical Model Interface ,

Int. Conf. on Numerical Simulation of Semiconductor Optoelectronic Devices (NUSOD 02),

Zurich, Switzerland, Sept. 25—27, 2002.

D. C. M ller

Deactivation of Arsenic in Silicon: Ab Initio Study on the Electronic Structure of As-V Clusters ,

Conference on Computer Simulation of Radiation Effects in Solids, Dresden, Germany, June 23—28, 2002.

N. Nikoloski

Exposure Setups for Simultaneous Exposure of 17 Rats for Risk Assessment Studies at 902MHz and

1747MHz ,


W. Oesch

Requirements for Controlling & Monitoring Software of Exposure Systems in (Double-)Blinded Bio

Experiments ,


S. Oetiker, T. Villiger, F. K. G rkaynak, H. Kaeslin, N. Felber, W. Fichtner

High Resolution Clock Generators for Globally-Asynchronous Locally-Synchronous Designs ,

Second Asynchronous Circuit Design Workshop of the European Commissions Fifth Framework

Programme, Munich, Germany, Jan. 28—29, 2002.

D. Pfaff, Q. Huang

An 18mW 1800MHz Quadrature Demodulator in 0.18 μm CMOS ,


R. Reutemann, P. Balmelli, Q. Huang

A 33mW 14b 2.5MSample/s ΣΔ Converter in 0.25μm Digital CMOS ,


S. R llin, W. Fichtner

Use of Nonsymmetric Permutations and Scalings in Semiconductor Device Simulation ,

Latsis-Symposium on Iterative Solvers for Large Linear Systems, Zurich, Switzerland, Feb. 18—21, 2002.

S. R llin, W. Fichtner

Parallel Incomplete LU-Factorisation on Shared Memory Multiprocessors in Semiconductor Device

Simulation ,

Parallel Matrix Algorithms and Applications (PMAA 02), Neuchatel, Switzerland, Nov. 9—10, 2002.

T. Samaras

Maximum Temperature Increase in the Brain Tissues of Adults and Children During Usage of Mobile

Phones ,


2002.

T. Samaras, J. Schuderer, N. Kuster

Temperature Distributions Inside Cell Cultures Exposed to Electromagnetic Fields In Vitro ,

Cost 281 Management Committee Meeting, London, United Kingdom, Nov. 12—13, 2002.

A. Schenk, A. Wettstein

Electron Mobility in Thin DGSOI MOSFETs ,

Integrated System Engineering Inc., San Jose, USA, Mar. 6, 2002.

A. Schenk

Simulation of RF Noise in the Energy-Balance Model ,


A. Schenk, A. von Allmen, F. Bufler, C. Zechner, A. Erlebach

Hot Carrier Degradation in CMOS Devices ,


135

A. Schenk

Inability of the Density-Gradient Model for Simulation of Barrier Tunneling ,



2D Analysis of Source-to-Drain Tunneling in Decananometer MOSFETs with the Density Gradient Model ,

5th Int. Conference on Modeling and Simulation of Microsystems (MSM 02), San Juan, Puerto Rico,

Apr. 21—25, 2002.


Simulation of DGSOI MOSFETs with a Schr dinger-Poisson Based Mobility Model ,


2002.

B. Schmidt, T. Pliska, N. Matuschek, R. Badii, S. Mohrdiek, T. Kellner, S. Pawlik, J. M ller, B. Sverdlov,

A. Witzig, M. Pfeiffer

Simulation and Design of Pump Laser Diodes for Un-Cooled Applications ,

18th International Semiconductor Laser Conference (ISLC), Garmisch, Germany, Sept. 29—Oct. 3, 2002.

B. Schmith sen

Grid Adaptation for the Stationary Two-Dimensional Drift-Diffusion Model with DESSIS ,

Integrated System Engineering Inc., San Jose, USA, Mar. 4—15, 2002.

L. Schneider, C.-Z. Ning

Modeling and Simulation of a 2D Photonic-Crystal Defect-Mode Laser ,

Workshop and European Optical Society Topical Meeting on Two-Dimensional Photonic Crystals, Ascona,

Switzerland, Aug. 25—30, 2002.

L. Schneider, A. Witzig, M. Streiff, M. Pfeiffer, A. Bregy, B. Schmidt, W. Fichtner

2D Simulation of a Buried-Heterostructure Tunable Twin-Guide DFB Laser Diode ,


2002.





J. Schuderer

In Vitro Exposure Systems and Dosimetric Quality Control for Risk Assessment Studies ,

Technical Seminar at Keele University, Stoke-on-Trent, United Kingdom, Mar. 5, 2002.

J. Schuderer

In Vitro Exposure System for GSM/DCS Signal Schemes ,

Technical Seminar at STUK — Radiation and Nuclear Safety Authority, Helsinki, Finland, Mar. 20, 2002.

J. Schuderer

Effects of Electromagnetic Fields with Two Different SAR Distributions on the Human Sleep EEG and Heart

Rate ,


J. Schuderer

In Vitro Exposure Setup for ELF Magnetic Fields Enabling Flexible Signal Schemes and Double Blind

Protocols ,


J. Schuderer

Exposure Systems and Dosimetric Quality Control in the REFLEX Project ,

Proc. 24th Annual Meeting of the Bioelectromagnetics Society, Quebec, Canada, June 23—27, 2002.

J. Schuderer

Advanced Exposure Systems for Controlled RF Exposure Conditions In Vitro ,

Technical Seminar at Research Labs NTTDoCoMo, Tokyo, Japan, July 12, 2002.

136

J. Schuderer

Novel High Resolution Temperature Probe for RF Dosimetry ,


2002.

J. Schuderer

Requirements for Radiofrequency Exposure Setups ,

Technical Seminar at University of Rostock, Rostock, Germany, Dec. 12, 2002.

J. Schuderer

Optimized Exposure Setups for GSM and UMTS Modulation Schemes ,

Technical Seminar at AKH Wien, Vienna, Austria, Dec. 18, 2002.

M. Stangoni, M. Ciappa, M. Buzzo, M. Leicht, W. Fichtner

Simulation and Experimental Validation of Scanning Capacitance Microscopy Measurements Across Low-

doped Epitaxial PN-Junctions ,


Oct. 7—11, 2002.

M. Stangoni, M. Ciappa

2D Dopant Profiling by Scanning Capacitance Microscopy Measurements ,

Infineon, Villach, Austria, Nov. 5, 2002.

M. Stangoni, M. Ciappa

The Use of Simulations in Quantification of Scanning Capacitance Microscopy Measurements ,

Infineon User Group Meeting AFM, Munich, Germany, Dec. 20, 2002.

M. Streiff, A. Witzig, M. Pfeiffer, L. Schneider, W. Fichtner

Comprehensive VCSEL Device Simulation ,




Numerical Simulation of Vertical-Cavity Surface-Emitting Laser Diodes ,

TOP NANO21 Annual Meeting, Bern, Switzerland, Oct. 1, 2002.

M. Streiff


D-ITET TOP NANO21 Day, Zurich, Switzerland, Nov. 20, 2002.

T. Villiger, F. K. G rkaynak, S. Oetiker, H. Kaeslin, N. Felber, W. Fichtner

Multi-Point Interconnect for Globally-Asynchronous Locally-Synchronous Systems ,

Second Asynchronous Circuit Design Workshop of the European Commissions Fifth Framework

Programme, Munich, Germany, Jan. 28—29, 2002.

A. Witzig, M. Streiff, F. Romer, C. Prott, H. Hillmer, W. Fichtner

Optical Eigenmodes in VCSEL Structures: Spectral Portrait and Convergence Behavior ,



A. Witzig, M. Streiff, W. Fichtner

Integration of a General Optical Mode Solver into Electro-Thermal Laser Simulation ,

10th International Workshop on Optical Waveguide Theory and Numerical Modelling (OWTNM 2002),

Nottingham, United Kingdom, Apr. 5—6, 2002.

137

Publications

2002

F. Adlkofer, H. Dertinger, R. Tauber, R. Fitzner, K. Schlatterer, D. Leszczynski, S. Joenv r , K. Kuokka,

J. Reivienen, H. A. Kolb, F. Bersani, C. Franceschi, I. Lagroye, B. Veryret, N. Kuster, J. Schuderer, F. Clementi,

D. Fornasari, C. Gotti, C. Maercker

Risk Evaluation of Potential Environmental Hazards from Low Energy Electromagnetic Field Exposure Using

Sensitive In Vitro Methods (REFLEX) — Introduction ,

in Proc. 24th Annual Meeting of the Bioelectromagnetics Society, Quebec, Canada, June 23—27, 2002, p. 91.

P. P. Altermatt, J. O. Schumacher, A. Cuevas, M. J. Kerr, S. W. Glunz, R. R. King, G. Heiser, A. Schenk

Numerical Modeling of Highly Doped Si: P Emitters Based on Fermi-Dirac Statistics and Self-Consistent

Material Parameters ,

Jour. Appl. Phys., vol. 92, no. 6, pp. 3187—3197, Sept. 2002.

F. Bersani, B. Billaidel, M. Capri, J. Czyz, P. E. Dulou, K. Guan, E. Haro, S. Joenv r , K. Kuokka, N. Kuster,

I. Lagroye, D. Leszczynksi, A. Meister, J. Reivienen, J. Schuderer, B. Veyret, A. M. Wobus, Q. Zeng

Do ELF or RF Fields Affect the Apoptotic Process? Data from the REFLEX Program ,


G. Brenna, D. Tschopp, D. Pfaff, Q. Huang

A 2GHz Direct-Conversion WCDMA Modulator in 0.25 μm CMOS ,

in ISSCC Dig. Tech. Papers, San Francisco, USA, Feb. 3—7, 2002, pp. 244—245.


Self-Consistent Single-Particle Simulation ,

in Proc. Int. Conf. on Simulation of Semiconductor Processes and Devices SISPAD 2002, Kobe, Japan,

Sept. 4—6, 2002, pp. 159—162.

F. M. Bufler, W. Fichtner

Hole and Electron Transport in Strained Si: Orthorhombic versus Biaxial Tensile Strain ,

Applied Physics Letters, vol. 81, no. 1, pp. 82—84, July 2002.


Hole Transport in Orthorhombically Strained Silicon ,

Journal of Computational Electronics, vol. 1, no. 1, pp. 175—177, July 2002.

F. M. Bufler, A. Schenk, C. Zechner, N. Inada, Y. Asahi, W. Fichtner

Comparison of Single-Particle Monte Carlo Simulation with Measured Output Characteristics of an 0.1μm

n-MOSFET ,

VLSI Design, vol. 15, no. 4, pp. 715—720, Dec. 2002.


FPGA Implementation of a MIMO Receiver Front-End for UMTS ,

in Proc. of the International Zurich Seminar on Broadband Communication, Zurich, Switzerland, Feb. 18—21,

2002, pp. 8.1—8.6.

T. Burger

Optimal Design of Operational Transconductance Amplifiers with Application for Low Power ΔΣ Modulators.

PhD Thesis ETH-No. 14716, Hartung-Gorre Printing House, Konstanz, Germany, 2002.

A. Christ, J. Fr hlich, N. Kuster

Correction of Numerical Phase Velocity Errors in Nonuniform FDTD Meshes ,

IEICE Transactions on Communications, vol. E85-B, no. 12, pp. 2904—2915, Dec. 2002.

N. Chavannes, R. Tay, N. Nikoloski, A. Christ, N. Kuster

TCAD of Mobile Phones: Guidelines for MTE Design Using FDTD ,

in Proc. AP-S International Symposium and USNC/URSI National Radio Science Meeting, San Antonio, USA,

June 16—21, 2002, p. 421.

138

N. Chavannes, R. Tay, N. Nikoloski, N. Kuster


in Proc. 27th General Assembly of the International Union of Radio Science, Maastricht, Netherlands,

Aug. 17—24, 2002, p. 2199.

N. Chavannes, R. Tay, N. Nikoloski, N. Kuster


in Proc. 2002 Interim International Symposium on Antennas and Propagation (ISAP i-2002), Yokusuka,

Japan, Nov. 26—28, 2002, pp. 416—419.

N. Chavannes

Local Mesh Refinement Algorithms for Enhanced Modeling Capabilities in the FDTD Method.

Ph.D. Thesis ETH-No. 14577, Hartung-Gorre Printing House, Konstanz, Germany, 2002.

L. Ciampolini, M. Ciappa, P. Malberti, W. Fichtner

Computational Investigation of the Accuracy of Constant-DC Scanning Capacitance Microscopy for Ultra-

Shallow Doping Profile Characterization ,

Solid-State Electronics, vol. 46, no. 3, pp. 445—449, Mar. 2002.

L. Ciampolini

Scanning Capacitance Microscope Imaging and Modelling.


M. Ciappa

Selected Failure Mechanisms of Modern Power Devices (Invited Paper) ,

Microelectronics Reliability, vol. 42, no. 4—5, pp. 653—667, Apr.—May 2002.

M. Ciappa, F. Carbognani, P. Cova, W. Fichtner


Semiconductors ,

Microelectronics Reliability, vol. 42, no. 9—11, pp. 1653—1658, Sept.—Nov. 2002.

M. Ciappa, F. Carbognani, P. Cova, W. Fichtner


Semiconductors ,

in Proc. 13th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, Rimini,

Italy, Oct. 7—11, 2002, pp. 1653—1658.

A. Deiss

A Low Power 200MHz Receiver for Wireless Hearing Aid Systems.


S. Ebert, J. Fr hlich, W. Oesch, R. Mertens, N. Kuster

Characterization and Dosimetry of the PERFORM A In Vivo Exposure System at the Mobile Communication

Frequencies 902MHz and 1747MHz ,

in Proc. 24th Annual Meeting of the Bioelectromagnetics Society, Quebec, Canada, June 23—27, 2002,

pp. 109—110.

K. Esmark

Device Simulation of ESD Protection Elements.


M. Frauscher, J. Fr hlich, S. Cecil, G. Neubauer, N. Kuster,

Exposure Functions for Uniform Dose in Rats at 902MHz and 1747MHz ,


pp. 107—108.

J. Fr hlich, E. Cherubini, N. Kuster

Implementation of the New IEEE Standard for Computational Dosimetry ,


pp. 167—168.

139

J. Fr hlich, N. Chavannes, N. Kuster

Rigorous Analysis of EM Absorption in High Resolution Anatomical Models Using FDTD ,

in Proc. AP-S International Symposium and USNC/URSI National Radio Science Meeting, San Antonio, USA,

June 16—21, 2002, p. 50.

J. Fr hlich, N. Chavannes, N. Kuster

Ratio of Spatial Peak and Whole Body SAR Dependent on Frequency and Polarization in Animals and

Humans ,


Aug. 17—24, 2002, p. 1897.

F. K. G rkaynak, T. Villiger, S. Oetiker, N. Felber, H. Kaeslin, W. Fichtner

A Functional Test Methodology for Globally-Asynchronous Locally Synchronous Systems ,

in Proc. Int. Symposium on Asynchronous Circuits and Systems, Manchester, United Kingdom, Apr. 8—11,

2002, pp. 181—189.

F. O. Heinz, A. Schenk, A. Scholze, W. Fichtner

Full Quantum Simulation of Silicon-On-Insulator Single-Electron Devices ,

Journal of Computational Electronics, vol. 1, no. 1, pp. 161—164, July 2002.


On Density-Gradient Modeling of Tunneling through Insulators ,


Sept. 4—6, 2002, pp. 275—278.

R. Huber, V. Treyer, A. A. Borb ly, J. Schuderer, J. M. Gottselig, H.-P. Landolt, E. Werth, T. Berthold,

N. Kuster, A. Buck, P. Achermann

Pulsed Electromagnetic Fields as Emitted by Mobile Phones Affect Regional Cerebral Blood Flow and Sleep

EEG ,

Journal of Sleep Research, vol. 11, no. 4, pp. 289—295, Dec. 2002.

R. Huber, A. A. Borb ly, J. M. Gottselig, N. Kuster, H.-P. Landolt, J. Schuderer, E. Werth, P. Achermann

Electromagnetic Fields and Sleep EEG: Effect of Signal Modulation ,

in Journal of Sleep Research, ESRS Congress, Reykjavik, Iceland, June 3—7, 2002, vol. 11 (Suppl. 1), p. 213.

R. Huber, A. A. Borb ly, J. M. Gottselig, N. Kuster, H.-P. Landolt, J. Schuderer, E. Werth, P. Achermann

Effects of Electromagnetic Fields of Mobile Phones on the Human Sleep EEG ,

in Proc. Sleep, APSS Congress, Seattle, USA, June 8—13, 2002, vol. 25 (Suppl.), p. 399.

A. Kramer, J. Fr hlich, N. Kuster

Towards Danger of Mobile Phones in Planes, Trains, Cars and Elevators ,

Journal of the Physical Society of Japan, vol. 71, no. 12, p. 3100, Dec. 2002.

N. Kuster, A. Christ, N. Chavannes, N. Nikoloski, J. Fr hlich

Human Head Phantoms for Compliance and Communication Performance Testing of Mobile Communica-

tions Equipment at 900MHz ,

in Proc. 2002 Interim International Symposium on Antennas and Propagation (ISAP i-2002), Yokusuka,

Japan, Nov. 26—28, 2002, pp. 385—391.

M. Luisier, M. Pfeiffer, W. Fichtner

Advanced Laser Simulation Using the DESSIS Physical Model Interface ,

in Proc. NUSOD 02, Zurich, Switzerland, Sept. 25—27, 2002, pp. 46—47.

A. K. Lutz, J. Treichler, F. K. G rkaynak, H. Kaeslin, G. Basler, A. Erni, S. Reichmuth, P. Rommens, S. Oetiker,

W. Fichtner

2Gbit/s Hardware Realizations of RIJNDAEL and SERPENT: A Comparative Analysis ,

in Proc. Cryptographic Hardware and Embedded Systems, Redwood Shores, USA, Aug. 13—15, 2002.

C. Maercker, J. Czyz, S. Ivancsits, H. W. Ruediger, O. Jahn, E. Diem, A. Pilger, A. Rolletschek, J. Schuderer,

N. Kuster, K. Guan, A. Trillo, E. Bazan, D. Reimers, D. Fornasari, F. Clementi, K. Schlatterer, R. Tauber,

R. Fitzner, F. Adlkofer, A. M. Wobus

Gene Expression Profiling Studies on Global cDNA Arrays Show Sensitivity of Human and Mouse Cell Lines

to ELF-EMF Exposure ,


140

R. Mertens, W. Kainz, N. Kuster

Simulating Environmental GSM Features for Use in Bioexperiments ,


p. 106.

N. Nikoloski, W. Kainz, M. Frauscher, J. Fr hlich, N. Kuster

Exposure Setups for Simultaneous Exposure of 17 Rats for Risk Assessment Studies at 902MHz and

1747MHz ,


pp. 108—109.

M. Oberle, R. Reutemann, J. Hertle, Q. Huang

A 10mW Two-Channel Fully Integrated System-on-Chip for Eddy-Current Position Sensing ,

IEEE J. Solid-State Circuits, vol. 37, no. 7, pp. 916—925, July 2002.

M. Oberle

Low Power Systems-on-Chip for Biomedical Applications.


W. Oesch, H.-U. Gerber, N. Kuster

Requirements for Controlling & Monitoring Software of Exposure Systems in (Double-)Blinded Bio

Experiments ,


pp. 152—153.

S. Oetiker, T. Villiger, F. K. G rkaynak, H. Kaeslin, N. Felber, W. Fichtner

High Resolution Clock Generators for Globally-Asynchronous Locally-Synchronous Designs ,

in Handouts of the Second ACiD-WG Workshop, Munich, Germany, Jan. 28—29, 2002.

D. Pfaff, Q. Huang

An 18mW 1800MHz Quadrature Demodulator in 0.18 μm CMOS ,


J. Piprek, W. Fichtner, A. Witzig, D. Aemmer (editors)

Proc. of the 2nd Int. Conference on Numerical Simulation of Semiconductor Optoelectronic Devices

(NUSOD-02).

Hartung-Gorre Printing House, Konstanz, Germany, 2002.

S. Reggiani, M. Valdinoci, L. Colalongo, M. Rudan, G. Baccarani, A. Stricker, F. Illien,

N. Felber, W. Fichtner, L. Zullino

Electron and Hole Mobility in Silicon at Large Operating Temperatures. Part I — Bulk Mobility ,

IEEE Transactions on Electron Devices, vol. 49, no. 3, pp. 490—499, Mar. 2002.

R. Reutemann, P. Balmelli, Q. Huang

A 33mW 14b 2.5MSample/s ΣΔ Converter in 0.25μm Digital CMOS ,


M. Rupp, A. Burg

Algorithms for Adaptive Equalization in Wireless Applications ,

in Adaptive Signal Processing: Applications to Real-World Problems.

Chapter 9, pp. 249—281, Springer Press, 2002.

T. Samaras, N. Chavannes, N Kuster

Maximum Temperature Increase in the Brain Tissues of Adults and Children During Usage of Mobile

Phones ,


Aug. 17—24, 2002, p. 667.


Simulation of DGSOI MOSFETs with a Schr dinger-Poisson Based Mobility Model ,


Sept. 4—6, 2002, pp. 21—24.

141


2D Analysis of Source-to-Drain Tunneling in Decananometer MOSFETs with the Density Gradient Model ,

in Proc. 5th Int. Conf. on Modeling and Simulation of Microsystems MSM 02, San Juan, Puerto Rico,

Apr. 21—25, 2002, pp. 552—555.

M. Schenkel

Substrate Current Effects in Smart Power ICs.


B. Schmidt, T. Pliska, N. Matuschek, R. Badii, S. Mohrdiek, T. Kellner, S. Pawlik, J. M ller, B. Sverdlov,

A. Witzig, M. Pfeiffer

Simulation and Design of Pump Laser Diodes for Un-Cooled Applications ,

in Proc. of the 18th International Semiconductor Laser Conference (ISLC), Garmisch, Germany,

Sept. 29—Okt. 3, 2002, pp. 159—160.

B. Schmith sen

Grid Adaptation for the Stationary Two-Dimensional Drift-Diffusion Model in Semiconductor Device

Simulation.





Sept. 4—6, 2002, pp. 55—58.



in Proc. NUSOD-02, Zurich, Switzerland, Sept. 25—27, 2002, pp. 24—25.

J. Schuderer, N. Kuster

The Effect of the Meniscus at the Solid/Liquid Interface on the SAR in Petri Dishes and Flasks ,

Bioelectromagnetics, vol. 24, no. 2, pp. 103—108, Feb. 2003.

J. Schuderer, R. Huber, A. A. Borb ly, T. Graf, N. Kuster, P. Achermann

Effects of Electromagnetic Fields with Two Different SAR Distributions on the Human Sleep EEG and Heart

Rate ,


pp. 261—262.

J. Schuderer, W. Oesch, N. Kuster

In Vitro Exposure Setup for ELF Magnetic Fields Enabling Flexible Signal Schemes and Double Blind

Protocols ,


pp. 105—106.

J. Schuderer, W. Oesch, R. Mertens, U. Frauenknecht, N. Kuster

Exposure Systems and Dosimetric Quality Control in the REFLEX Project ,


pp. 93—94.

J. Schuderer, T. Schmid, G. Urban, N. Kuster

Novel High Resolution Temperature Probe for RF Dosimetry ,


Aug. 17—24, 2002, p. 2110.




in Proc. 13th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, Rimini,

Italy, Oct. 7—11, 2002, pp. 1701—1706.

142




Microelectronics Reliability, vol. 42, no. 9—11, pp. 1701—1706, Sept.—Nov. 2002.

M. Streiff, A. Witzig, W. Fichtner

Computing Optical Modes for VCSEL Device Simulation ,

IEE Proc. on Optoelectronics, vol. 149, no. 4, pp. 166—173, Aug. 2002.


Comprehensive VCSEL Device Simulation ,

in Proc. NUSOD-02, Zurich, Switzerland, Sept. 25—27, 2002, pp. 30—31.



in TOP NANO 21 Third Annual Report, Bern, Switzerland, Oct. 1, 2002, pp. 70—71.

T. Villiger, F. K. G rkaynak, S. Oetiker, H. Kaeslin, N. Felber, W. Fichtner

Multi-Point Interconnect for Globally-Asynchronous Locally-Synchronous Systems ,

in Handouts of the Second ACiD-WG Workshop, Munich, Germany, Jan. 28—29, 2002.

A. Witzig, M. Streiff, W. Fichtner

Integration of a General Optical Mode Solver into Electro-Thermal Laser Simulation ,

in OWTNM 2002, Nottingham, United Kingdom, Apr. 5—6, 2002, p. 37.

A. Witzig, M. Streiff, F. R mer, C. Prott, H. Hillmer, W. Fichtner

Optical Eigenmodes in VCSEL Structures: Spectral Portrait and Convergence Behavior ,

Late-News Contribution at NUSOD-02, Zurich, Switzerland, Sept. 25—27, 2002.

A. Witzig

Modeling the Optical Processes in Semiconductor Lasers.


H. Yabuhara, M. Ciappa, W. Fichtner

Scanning Capacitance Microscopy Measurements Using Diamond-Coated Probes ,

Journal of Vacuum Science & Technology B, vol. 20, no. 3, pp. 783—786, May 2002.

143

Technical Reports

M. Streiff, A. Witzig, W. Fichtner

Computing Optical Modes for VCSEL Device Simulation

Technical Report 2002/1

F. Geelhaar

Quasi-Exciton Densities and Band Gap Narrowing in Bulk Silicon at Room Temperature



FPGA Implementation of a MIMO Receiver Front-End for the UMTS Downlink


F. K. G rkaynak, T. Villiger, S. Oetiker, N. Felber, H. Kaeslin, W. Fichtner

A Functional Test Methodology for Globally-Asynchronous Locally-Synchronous Systems


A. K. Lutz, J. Treichler, F. K. G rkaynak, H. Kaeslin, G. Basler, A. Erni, S. Reichmuth, S. Oetiker,

P. Rommens, W. Fichtner

2Gbit/s Hardware Realizations of RIJNDAEL and SERPENT: A Comparative Analysis



Hole and Electron Transport in Strained Si: Orthorhombic versus Biaxial Tensile Strain



Self-Consistent Single-Particle Simulation


F. K. G rkaynak, T. Villiger, S. Oetiker

An Introduction to the GALS Methodology at ETH Zurich



On Density-Gradient Modeling of Tunneling through Insulators



Hole Transport in Orthorhombically Strained Silicon


F. M. Bufler, A. Schenk, C. Zechner, N. Inada, Y. Asahi, W. Fichtner

Comparison of Single-Particle Monte Carlo Simulation with Measured Output Characteristics of an

0.1μm n-MOSFET


F. O. Heinz, A. Schenk, A. Scholze, W. Fichtner

Full Quantum Simulation of Silicon-On-Insulator Single-Electron Devices


G. Acunto, M. Sans, A. Burg, W. Fichtner

An ASIC Implementation of Adaptive Arithmetic Coding


Technical Reports can be ordered from:

Ms. Verena Roffler

Integrated Systems Laboratory

ETH Zentrum

CH-8092 Z rich/Switzerland

Fax: +41 1 632 11 94

e-mail: [email protected]

144

Design, Electronic Test, and Physical Characterization

Equipment

ECAD and TCAD Software

SYNOPSYS Simulation, Synthesis, and Test Tools

CADENCE Digital and Analog IC Design Tools

HEWLETT PACKARD IC-CAP Measurement Control and Parameter Extraction Tools

MENTOR GRAPHICS Modelsim HDL Simulation Package and Calibre Physical Design Verification

XILINX FGPA Tools

ISE-TCAD Software for Process and Device Development

Equipment for Electronic Test

Verification Systems and Logic Analyzers Quantity

HP83000, ASIC Verification System, 660MHz 1

IMS XL60, Mixed Signal ASIC Verification System, 60MHz 1

HP16702A, Logic Analysis System, IEEE 2

Tektronix 1240, Logic Analyzer 1

Spectrum and Network Analyzers Quantity

Audio Precision System S1, Audio Analyzer 1

Rhode & Schwarz FSIQ3, Signal Analyzer, 20Hz—3.5GHz 1

Rhode & Schwarz FSP7, Spectrum Analyzer, 9Hz—7GHz 1

Agilent 8591E, RF Spectrum Analyzer, 9kHz—1.8GHz 1

HP35670A, Dynamic Signal Analyzer, DC—100kHz 1

HP89441A, Vector Signal Analyzer, DC—2650MHz 1

HP8563E, Spectrum Analyzer, 27GHz 1

Digital Signal Analyzer IIS, 100MS/s, 24bit, 128KSamples 1

Digital Signal Analyzer IIS, 1MS/s, 24bit, 96MSamples 1

Stanford SR785, 2-Channel Dynamic Signal Analyzer 1

HP5501B, Phase Noise Measurement System, 1.6GHz 1

HP8720D, Network Analyzer, 50MHz—20GHz 1

HP8751A, Network Analyzer, 5Hz—500MHz, with HP87511A S-Parameter Set 1

HP8753E, Network Analyzer, 30kHz—6GHz 1

Rhode & Schwarz FSEB30, Spectrum Analyzer, 20Hz—7GHz 1

Tektronix TLS216, 16-Channel Logic Scope, 500MHz 2GS/s, IEEE 1

Oscilloscopes Quantity

HP54601A, 4-Channel Digitizing Scope, 100MHz 1

HP5460A, 2-Channel Digitizing Scope 1

Tektronix 2440, 2-Channel Digitizing Scope, 300MHz 500MS/s, IEEE 1

HP54510B, 2-Channel Digitizing Scope, 250MHz 1GS/s, IEEE 1

HP54512B, 4-Channel Digitizing Scope, 300MHz 1GS/s, IEEE 2

HP54542A, 4-Channel Digitizing Scope, 500MHz 2GS/s, IEEE 1

HP54750A, 2-Channel Digitizing Scope, 50GHz, IEEE 1

HP54754A, 2-Channel Differential TDR Module for HP54750A 1

Tektronix TDS684A, 4-Channel Digitizing Scope, 1GHz 5GS/s, IEEE 1

Tektronix TDS784, 4-Channel Digitizing Scope, 1GHz 4GS/s, IEEE 2

Tektronix TDS794D, 4-Channel Digitizing Scope, 2GHz 8GS/s, IEEE 1

Kikusui 5041, Scope, 40MHz 3

145

Iwatsu 6611, Scope, 60MHz 5

Iwatsu 5711, Scope, 100MHz 1

Tektronix 2235, Scope, 100MHz 2

Tektronix 2467B, Scope, 400MHz, Microchannel 1

Tektronix TDS820, 2-Channel Sampling Scope, 6GHz, IEEE 1

Signal Sources, Function Generators Quantity

Rhode & Schwarz SML01, RF Signal Generator, 1GHz 3

Rhode & Schwarz SML03, RF Signal Generator, 3.3GHz 3

Tektronix SG505, Low-Distortion Oscillator, 10—100kHz, TM502A Power Rack 1

Stanford Research DS360, Low-Noise and -Distortion Function Generator, 200kHz 1

Rhode & Schwarz SMHU 58, Signal Generator, 100kHz—4.320GHz 1

Rhode & Schwarz SMIQ6, RF Vector Signal Generator, 300kHz—6.4GHz 1

Marconi 2042, Low-Noise Signal Generator, 10kHz—5.4GHz 1

Rhode & Schwarz AMIQ, 2 Channel Arbitrary Waveform Generator, 100MS/s 1

HP33120A, Function and Arbitrary Waveform Generator, 15MHz 4

Wavetek 145, Pulse/Function Generator, 20MHz 5

HP8116A, Pulse/Function Generator, 50MHz 1

HP8110A, Pulse Generator, 150MHz 1

MiniZap ESD-Simulator and HBM-Network 1

Meters Quantity

HP8970B, Noise Figure Meter, 2GHz 1

HP3478A, Multimeter, IEEE 1

Keithley 197, Autoranging Microvolt DMM 5

Keithley 197, Autoranging Microvolt DMM, IEEE 1

HP4140B DCV SRC, Picoampere Meter 1

Keithley 485, Autoranging Picoampere Meter 5

Keithley 485, Autoranging Picoampere Meter, IEEE 1

Keithley 2002, 9.5-Digit Multimeter 5

Metex M3650, 3.5-Digit Multimeter 8

Metex M4650, 3.5-Digit Multimeter 4

Roline 3660D, 3.5-Digit Multimeter 10

Escort ELC131D, Digital LCR-Meter 1

HP4284A, LCR Meter, 20Hz—1MHz, IEEE 1

Rhode & Schwarz NRV D, RF Power Meter 1

Rhode & Schwarz NRV Z5, Diode Power Sensor 1

Rhode & Schwarz NRV Z5J, Thermal Power Sensor 1

Magnetic Field Meter IIS, 50mT 1

UDT S380, 2-Channel Optometer, IEEE 1

Laboratory Systems Quantity

HPE1401A, High-Power Mainframe for VXI-Bus 1

HPE1328A, VXI 4-Channel D/A Converter 1

HPE1406A, VXI Command Module 1

HPE1458A, VXI 96-Channel Digital I/O 1

HPE1490A, VXI Register Based Breadboard 2

HPZ2417A, VXI 32-Channel C Switch 1

Roline MS9150, Universal Power Supply, Wave Generator and Multimeter System 1

Counters Quantity

Iwatsu SC7203, Universal Counter, DC—150MHz, 50MHz—1.3GHz 5

146

Power Supplies Quantity

Kikusui PAK6-60A, Power Supply, 6V/60A 1

Kikusui PAK20-18A, Power Supply, 20V/18A 2

HP6626A, System DC Power Supply, 4×0—16/50V, 2/0.5A, IEEE 2

Thurlby PL310, Power Supply, 30V/1A 20

Thurlby PL320 TGP, Power Supply, 2×30V/1A, IEEE 2

Thurlby PL330, Power Supply, 30V/3A 10

Topward TPS4000, Power Supply, 2×30V/2.5A 1

Farnell PDD3010A, Power Supply, 2×0—30V/10A 1

Heinzinger LNG100-2, Power Supply, 100V/2A 1

Heinzinger LNC3000-20, Power Supply, 3kV/20mA 1

FUG HCN 700-12500, Power Supply, 12,5kV/50mA, IEEE 1

Active Probes, Amplifiers, and Attenuators Quantity

Agilent 87405A, Preamplifier 22dB, 10MHz—3GHz 1

HP41802A, Input Adapter, 5Hz—100MHz, 1MOhm 4

HP54701A, Active Probe, DC—2.5GHz, 100kOhm 2

Tektronix P6015, High-Voltage Probe, 20kV 1

Tektronix P6206, FET Probe, DC—1GHz, 1MOhm 4

Tektronix P6217, FET Probe, DC—4GHz, 100kOhm 2

Tektronix P627, FET Probe, DC—1GHz, differential, 100kOhm 1

SI 9000, Differential Probe 2

Tektronix AM503, A6302 Current Probe, TM502A Power Rack 1

Tektronix AM503A, A6303 Current Probe, TM502A Power Rack 1

Tektronix CT1, 5mV/mA Current Transformer 2

Tektronix CT2, 1mV/mA Current Transformer 2

Chase CPA 9231, Preamplifier, 9kHz—1GHz 1

MITEQ AMF-20-001080-20-10P, RF Amplifier, 100MHz—8GHz 1

Stanford Research SR560, Low-Noise Preamplifier 1

Stanford Research SR570, Low-Noise Current Preamplifier 1

Rhode & Schwarz RF Step Attenuator RSH, DC—5.2GHz 1

Equipment for Physical Characterization

Physical Analysis Quantity

Balzers SCD 40, Sputter System 1

Cambridge Stereoscan 360, Electron Microscope 1

Ebic Amplifier 1

Electron Microscope 1

Froilabo A, Thermo System 1

FT1020 DLTS 1

Mazali A510Q1, Thermo Test Module 1

Nanoscope Dimension 3100, Atomic Force Microscope System 1

RH2010, Hall Effect Measurement System 1

Schlieter 125l, Thermo Chamber 1

Weiss 305 SB/10Ju40DU, Environmental Testing Chamber 1

Parameter Analyzers Quantity

HP4156A, Precision Semiconductor Parameter Analyzer 3

Tektronix Curve Tracer 370 1

HP4142B, Modular DC Source/Monitor 1

HP41420A, Source/Monitor Unit, 4μV—200V/20fA—1A 2

HP41421B, Source/Monitor Unit, 40μV—100V/20fA—100mA 4

147

HP41422A, High-Current Source/Monitor Unit, 40μV—10V/20nA—10A 2

HP41423A, High-Voltage Source/Monitor Unit, 2mV—1000V/2pA—10mA 2

HP41424A, Voltage Source/Voltage Monitor Unit 1

HP4085/4084, Switching Matrix/Control 1

Probers and Utilities Quantity

Hamamatsu, Emission Microscope System 1

Wentworth AVT-703, Antivibration Table 1

Cascade Summit 9600, Thermal Probe Station 1

PWS Probe II, Automatic Wafer Prober 1

Suss PA150, Semi Automatic Prober 1

Suss PSM6, Submicron Prober 1

Suss PH100, Micropositioner 12

Suss PH150, Micropositioner 9

Alessi MH4, Micropositioner 2

Temptronic Thermo Chuck, 0 to 200°C 1

Temptronic TPO3010B, Thermo Chuck System, 0 to 200°C 1

Temptronic TPO4000, Thermo Stream, —60 to 140°C 1

Temptronic TPO700A, Thermo Chuck System 1

Alessi LG2, Green Laser Cutting System 1

ERSA IR500A, PCB Repair System 1

Picoprobe, Active Probe 1

Optical Microscopes Quantity

Nikon Optiphot 66, Stereo Microscope 1

Olympus SZ4045, Stereo Microscope 1

Olympus SZ3060, Microscope 1

Zeiss Axiophot, Microscope 1

Zeiss Stemi SV8, Stereo Microscope 1

Photo, Video, and Audio Equipment Quantity

COHU 8390, CCD RGB Video Camera 1

HITACHI VK-C2000E, Color Video Camera 1

Hughes TVS200, Thermal Video System 1

NIKON Coolpix 5700, Digital Camera 1

NIKON Coolpix 950, Digital Camera 1

SONY DXC930, 3-CCD Color Video Camera 1

SONY VTX-100EC, TV Tuner 1

HITACHI VT-168EM, Multi-System Video Recorder 1

PANASONIC AG5700, S-VHS NTSC Video Recorder 2

PANASONIC AG5700, S-VHS PAL Video Recorder 2

PANASONIC NV-H1000, S-VHS PAL Video Recorder 1

PANASONIC FT2900, Color Video Monitor 1

PANASONIC WV-CM100, Color Video Monitor 1

SONY KX20-PS1, Color Video Monitor 1

SONY KX27-PS1, Color Video Monitor 1

HITACHI VY300E, Color Video Printer 1

Marantz PM7000, Audio Amplifier, 100W 1

Marantz MM9000, 5-Channel Audio Amplifier 1

Marantz CD5000, CD-Player 1

DENON DCD2560, CD-Player 1

Infinity Reference 40, Loudspeaker 2

B&W DM600S3, Surround Speaker 5

B&W ASW600, Subwoofer 1

148

Computer Equipment

Computers are most relevant tools in teaching and

research at IIS. Examples are design of integrated cir-

cuits, simulation of circuits, devices and technologies for

microelectronics and optoelectronics, development of

application software, and information transfer.

Besides optimal reliability and uncompromising perfor-

mance, homogeneity of the computing environment and

user friendliness are also important. To meet these goals,

the computing environment uses the operating system

Unix (Solaris, True64, Debian Linux), networking with

TCP/IP and NFS, the X-Window System, and the pro-

gramming languages C, C++, and Fortran 90/95. Besides

the Unix machines in the scientific and technical area,

Macintosh computers are widely applied for administra-

tion and presentation tasks. A Windows2000 terminal

server for mainly office applications is also provided. Sev-

eral PCs are installed for controlling measurement equip-

ment, for lab classes, and for other special applications.

Load of a 4-CPU Compaq Alpha Server:

Load = number of processes in running queue

Processes = number of CPU-intensive processes

(>15% of CPU capacity)

Since the teaching and research activities span many

areas, computer systems of various vendors are utilized.

They range from file servers to standard workstations,

compute servers, and workstations with specialized dedi-

cated hardware. All Unix computers run SVR4 or BSD, or

variants thereof. The file systems of all computers are

assembled via NFS into what appears to the user as a

single file system. The networking of IIS computers and

external computers is based on switched 100Mbit and

Gigabit Ethernet, and on the TCP/IP protocol. Important

applications in the technical area are ECAD (Modelsim,

Synopsys, Cadence, Mentor Graphics), TCAD (ISE AG),

as well as publishing and office applications on Macin-

tosh computers.

Memory usage of a 4-CPU Compaq Alpha Server:

physical memory allocation of CPU-intensive processes

(total size of process). ’max’ indicates peak value of all

data points collected within 14 hours. All other values

are average values of all data points collected within 14

hours. Data points were sampled every five minutes.

The computing equipment of IIS counts one Unix file

server, one windows terminal server, 127 Unix worksta-

tions, 25 Macintosh computers, 19 PCs, and 17 powerful

shared-memory compute servers for physical simula-

tions. The detailed configuration of computers at the Inte-

grated Systems Laboratory, the Department of

Information Technology and Electrical Engineering

(D-ITET), and the high-power and parallel computing

facilities of CSCS (The Swiss Center for Scientific Com-

puting in Manno/Ticino) is shown on the following page.

Representative figures of performance of computers at the Integrated Systems Laboratory: Floating-point performance per CPU

(SPECfp2000 benchmark) and memory size (MBytes) of compute servers and Unix workstations

149

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