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Memristor characteristics reset, and set process
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 12, DECEMBER 2012 3243 Balancing SET/RESET Pulse for > 10 10 Endurance in HfO 2 /Hf 1T1R Bipolar RRAM Yang Yin Chen, Student Member, IEEE, Bogdan Govoreanu, Senior Member, IEEE, Ludovic Goux, Robin Degraeve, Andrea Fantini, Gouri Sankar Kar, Dirk. J. Wouters, Member, IEEE, Guido Groeseneken, Fellow, IEEE, Jorge A. Kittl, Malgorzata Jurczak, Member, IEEE, and Laith Altimime Abstract—By tuning the SET/RESET pulse amplitude condi- tions, the pulse endurance of our 40-nm HfO 2 /Hf 1T1R resistive- random-access-memory devices demonstrates varying failure behaviors after 10 6 cycles. For unbalanced SET/RESET pulse amplitude conditions, both low-resistance state (LRS) and high- resistance state (HRS) failures may occur, while varying the pulsewidths influences the LRS/HRS window and the stability of the LRS/HRS states. The failure of the HRS or LRS state during cycling is ascribed to the depletion or excess of oxygen vacancies at the switching interface. Through a dc SET/RESET recovery operation, LRS/HRS states can be recovered after failure, indicat- ing that the distribution of oxygen vacancies can be restored. By optimally balancing the SET/RESET pulse conditions, more than 10 10 pulse endurance cycles is achieved. Index Terms—HfO 2 , low-resistance state (LRS)/high-resistance state (HRS) failure recovery, pulse endurance, resistive random access memory (RRAM), SET/RESET balance. I. I NTRODUCTION T HE HfO 2 -based resistive random access memory (RRAM), with robust scaling ability down to 10 nm and excellent performance and reliability, is emerging as a potential candidate for NAND Flash memory replacement beyond the 16-nm node [1]–[4]. Promising endurance performance was demonstrated up to 10 10 cycles on HfO 2 -based RRAM devices [5], [6] and even 10 11 cycles on TaO x -based RRAM devices [7], [8]. An endurance failure mechanism was also proposed based on a 100-μm 2 large area RRAM device with a > 1-mA operation current [9]. However, a good understanding of the degradation mechanism during cycling and an endurance failure prediction model are still missing for the scaled 1T1R devices at low RESET current level. Manuscript received May 10, 2012; revised July 5, 2012 and September 4, 2012; accepted September 5, 2012. Date of publication October 15, 2012; date of current version November 16, 2012. This work was supported by the Interuniversity Microelectronics Center Core CMOS/INSITE Program on Emerging Memory. The review of this paper was arranged by Editor M. J. Kumar. Y. Y. Chen, A. Fantini, D. J. Wouters, and G. Groeseneken are with the Interuniversity Microelectronics Center, B-3001 Leuven, Belgium, and also with the Department of Electrical Engineering (ESAT), Katholieke Univer- steit Leuven, 3000 Leuven, Belgium (e-mail: [email protected]; andrea. [email protected]; [email protected]; [email protected]). B. Govoreanu, L. Goux, R. Degraeve, G. S. Kar, J. A. Kittl, M. Jurczak, and L. Altimime are with the Interuniversity Microelectronics Center, B-3001 Leuven, Belgium (e-mail: [email protected]; ludovic. [email protected]; [email protected]; [email protected]; jorge.kittl@ imec.be; [email protected]; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2012.2218607 In this paper, we investigated the endurance failure behavior of 40 nm × 40 nm HfO 2 /Hf bipolar switching RRAM devices in a 1T1R cell configuration. Endurance tests carried out with unoptimized SET/RESET pulses may lead to early failure, in either low- (LRS) or high-resistive state (HRS). The failure mode depends on the “strength” of the SET/RESET pulses, relative to each other. In this paper, we study the impact of the SET/RESET pulse amplitudes and width on the failure mode and show how, for targeted LRS/HRS levels (LRS 20 kΩ), careful tuning of the cycling conditions leads to balanced SET and RESET operations and allows for improved endurance of over 10 10 cycles. Therefore, aside from the application of RRAM for NAND Flash replacement, the HfO 2 /Hf RRAM de- vices also have a potential for embedded memory applications. This paper is organized as follows. Section II presents the details of the 1T1R RRAM test vehicle process and discusses the testing methodology. Section III is divided into five sections. Section III-A discusses the influence of the SET/RESET pulse amplitude on endurance failure mode; Section III-B discusses the influence of the SET/RESET pulsewidth on endurance performance; Section III-C shows the LRS/HRS recovery of the endurance failure [4]; Section III-D proposes the failure mechanism of the unbalanced SET/RESET operations; and in Section III-E, endurance of > 10 10 cycles from our HfO 2 /Hf 1T1R RRAM is demonstrated by using the optimized balance SET/RESET conditions, which is an improvement of over four orders of magnitude relative to that achieved with the unopti- mized SET/RESET pulses.Section IV concludes this paper. II. EXPERIMENTS N-channel MOS transistors of 0.13-μm channel length were processed in a 65-nm process technology, with adjusted gate stack definition, so as to allow for operating voltages com- patible with RRAM forming and SET/RESET operation. The resistive switching stack, consisting of 65-nm PVD TiN/5-nm ALD HfO 2 /10-nm PVD Hf/30-nm PVD TiN, was fabricated afterward with a back-end-compatible thermal budget, not ex- ceeding 400 C [see Fig. 1(a) and (b)]. The RRAM device was patterned in a cross-point shape with a 40 nm × 40 nm size. Finally, a dual-layer SiO 2 /SiN passivation scheme has been employed to complete the process. The pulsed endurance was performed by applying voltage pulses at the source line (SL: source of the transistor), the word line (WL: gate of the transistor), and the bit line (BL: top electrode of resistive element), respectively. The transistor bulk 0018-9383/$31.00 © 2012 IEEE
Transcript
Page 1: Resistive memory switching

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 12, DECEMBER 2012 3243

Balancing SET/RESET Pulse for > 1010 Endurancein HfO2/Hf 1T1R Bipolar RRAM

Yang Yin Chen, Student Member, IEEE, Bogdan Govoreanu, Senior Member, IEEE, Ludovic Goux, Robin Degraeve,Andrea Fantini, Gouri Sankar Kar, Dirk. J. Wouters, Member, IEEE, Guido Groeseneken, Fellow, IEEE,

Jorge A. Kittl, Malgorzata Jurczak, Member, IEEE, and Laith Altimime

Abstract—By tuning the SET/RESET pulse amplitude condi-tions, the pulse endurance of our 40-nm HfO2/Hf 1T1R resistive-random-access-memory devices demonstrates varying failurebehaviors after 106 cycles. For unbalanced SET/RESET pulseamplitude conditions, both low-resistance state (LRS) and high-resistance state (HRS) failures may occur, while varying thepulsewidths influences the LRS/HRS window and the stability ofthe LRS/HRS states. The failure of the HRS or LRS state duringcycling is ascribed to the depletion or excess of oxygen vacanciesat the switching interface. Through a dc SET/RESET recoveryoperation, LRS/HRS states can be recovered after failure, indicat-ing that the distribution of oxygen vacancies can be restored. Byoptimally balancing the SET/RESET pulse conditions, more than1010 pulse endurance cycles is achieved.

Index Terms—HfO2, low-resistance state (LRS)/high-resistancestate (HRS) failure recovery, pulse endurance, resistive randomaccess memory (RRAM), SET/RESET balance.

I. INTRODUCTION

THE HfO2-based resistive random access memory(RRAM), with robust scaling ability down to 10 nm and

excellent performance and reliability, is emerging as a potentialcandidate for NAND Flash memory replacement beyond the16-nm node [1]–[4]. Promising endurance performance wasdemonstrated up to 1010 cycles on HfO2-based RRAM devices[5], [6] and even 1011 cycles on TaOx-based RRAM devices[7], [8]. An endurance failure mechanism was also proposedbased on a 100-μm2 large area RRAM device with a > 1-mAoperation current [9]. However, a good understanding of thedegradation mechanism during cycling and an endurancefailure prediction model are still missing for the scaled 1T1Rdevices at low RESET current level.

Manuscript received May 10, 2012; revised July 5, 2012 and September 4,2012; accepted September 5, 2012. Date of publication October 15, 2012;date of current version November 16, 2012. This work was supported bythe Interuniversity Microelectronics Center Core CMOS/INSITE Programon Emerging Memory. The review of this paper was arranged by EditorM. J. Kumar.

Y. Y. Chen, A. Fantini, D. J. Wouters, and G. Groeseneken are with theInteruniversity Microelectronics Center, B-3001 Leuven, Belgium, and alsowith the Department of Electrical Engineering (ESAT), Katholieke Univer-steit Leuven, 3000 Leuven, Belgium (e-mail: [email protected]; [email protected]; [email protected]; [email protected]).

B. Govoreanu, L. Goux, R. Degraeve, G. S. Kar, J. A. Kittl, M. Jurczak,and L. Altimime are with the Interuniversity Microelectronics Center,B-3001 Leuven, Belgium (e-mail: [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TED.2012.2218607

In this paper, we investigated the endurance failure behaviorof 40 nm × 40 nm HfO2/Hf bipolar switching RRAM devicesin a 1T1R cell configuration. Endurance tests carried out withunoptimized SET/RESET pulses may lead to early failure, ineither low- (LRS) or high-resistive state (HRS). The failuremode depends on the “strength” of the SET/RESET pulses,relative to each other. In this paper, we study the impact of theSET/RESET pulse amplitudes and width on the failure modeand show how, for targeted LRS/HRS levels (LRS ∼ 20 kΩ),careful tuning of the cycling conditions leads to balanced SETand RESET operations and allows for improved enduranceof over 1010 cycles. Therefore, aside from the application ofRRAM for NAND Flash replacement, the HfO2/Hf RRAM de-vices also have a potential for embedded memory applications.

This paper is organized as follows. Section II presents thedetails of the 1T1R RRAM test vehicle process and discussesthe testing methodology. Section III is divided into five sections.Section III-A discusses the influence of the SET/RESET pulseamplitude on endurance failure mode; Section III-B discussesthe influence of the SET/RESET pulsewidth on enduranceperformance; Section III-C shows the LRS/HRS recovery ofthe endurance failure [4]; Section III-D proposes the failuremechanism of the unbalanced SET/RESET operations; and inSection III-E, endurance of > 1010 cycles from our HfO2/Hf1T1R RRAM is demonstrated by using the optimized balanceSET/RESET conditions, which is an improvement of over fourorders of magnitude relative to that achieved with the unopti-mized SET/RESET pulses.Section IV concludes this paper.

II. EXPERIMENTS

N-channel MOS transistors of 0.13-μm channel length wereprocessed in a 65-nm process technology, with adjusted gatestack definition, so as to allow for operating voltages com-patible with RRAM forming and SET/RESET operation. Theresistive switching stack, consisting of 65-nm PVD TiN/5-nmALD HfO2/10-nm PVD Hf/30-nm PVD TiN, was fabricatedafterward with a back-end-compatible thermal budget, not ex-ceeding 400 ◦C [see Fig. 1(a) and (b)]. The RRAM device waspatterned in a cross-point shape with a 40 nm × 40 nm size.Finally, a dual-layer SiO2/SiN passivation scheme has beenemployed to complete the process.

The pulsed endurance was performed by applying voltagepulses at the source line (SL: source of the transistor), theword line (WL: gate of the transistor), and the bit line (BL: topelectrode of resistive element), respectively. The transistor bulk

0018-9383/$31.00 © 2012 IEEE

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3244 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 12, DECEMBER 2012

Fig. 1. (a) TEM cross-sectional picture of Hf/HfO2 1T1R RRAM device. TheHf/HfO2 RRAM stack is standing above the drain of the transistor. (b) TEMcross-sectional picture of the 10-nm PVD Hf/5-nm ALD HfO2 material stack.(c) Bias scheme for FORMING/SET and Read on the 1T1R device. Positivebias on BL and WL. SL and transistor bulk are grounded. (d) Bias scheme forRESET on the 1T1R device. Positive bias on SL and WL. BL and transistorbulk are grounded.

Fig. 2. (a) IDS/W − VDS curves of the 0.13-μm channel length NMOS inthe 1T1R configuration (VG: 0.5 V ∼0.9 V). (b) DC FORMING I–V sweeps(VG = 0.6 V) from the 1T1R HfO2/Hf RRAM cells.

bias of the 1T1R structure was fixed at 0 V by a dc source meter.The current readout of LRS/HRS resistance was also measuredby the dc source meter at 0.1 V.

In this paper, the FORMING on our HfO2/Hf device wasdone in dc sweep mode, with the transistor as the currentlimiter, which eliminates the need of using the instrumentcompliance [IDS/W (IDS current normalized by the width ofthe transistor); VDS of the NMOS is shown in Fig. 2(a), anddc FORMING I–V sweeps are shown in Fig. 2(b)]. The SETswitching is done by applying positive pulses at WL and BL andgrounding SL and bulk [see Fig. 1(c)]. The RESET switching isdone by applying positive pulses at WL and SL and groundingBL and bulk [see Fig. 1(d)]. The WL pulse has a longer widththan that on BL or SL so that the transistor is always ready toswitch the resistive stack in both SET/RESET operations.

III. RESULTS AND DISCUSSIONS

In this paper, we defined the LRS target level as ∼10 kΩto ∼20 kΩ and the HRS level as ∼10× LRS during theendurance test of our 1T1R HfO2/Hf RRAM devices. Notethat the definition of the LRS/HRS resistance levels dependson the particularities of the switching stack as well as the

Fig. 3. Pulse endurance behavior of the 40-nm Hf/HfO2 1T1R devices, withfixed RESET pulse at WL = 3 V, SL = 1.8 V, and 10 ns. The SET pulseamplitude was varied using different WL pulses: (a) 0.9 V, (b) 1.0 V, (c) 1.2 V,and (d) 1.4 V. The SET pulsewidth is fixed at 100 ns and 1.8 V on BL. Withincreasing SET WL voltage, endurance failure mode shifts from (a) LRS failureto (d) HRS failure.

practical requirements derived from a target application. Al-though switching-energy considerations of the HfO2/Hf RRAMdevices [4] suggest competitiveness in relation to other emerg-ing technologies and potential to reach the NAND Flash realm,when considering future technology nodes in the 1 × rangeand below, electromigration issues in the local interconnectsmay call for a further reduction of the operating currents formass storage applications and, consequently, a reduction of theLRS/HRS resistance levels as from this study. As for embeddedmemory applications, high speed, low-voltage operation, andendurance may take over at the expense of density, which thenrequire lower LRS/HRS resistance levels, similar in this study.

Furthermore, in this study, the endurance failure criterion isdefined as the decrease of the HRS/LRS resistance ratio (on/offwindow) to below 3. The influence of SET/RESET pulse am-plitudes and pulsewidth is studied, and a pulse endurance of> 1010 cycles is achieved by a better balanced SET/RESETpulse combination.

A. Impact of the SET/RESET Pulse Amplitude onEndurance Failure

In this part of the study, the SET pulse amplitude (varied bythe WL pulse) and the RESET pulse amplitude (varied by theSL pulse) are individually tuned, while the SET pulsewidth (BLpulse) and the RESET pulsewidth (SL pulse) are kept constantat 100 and 10 ns, respectively.

Fig. 3 shows the pulse endurance behaviors under differentSET pulse amplitudes and a fixed RESET pulse amplitude(1.8 V and 10 ns). The LRS level was intentionally keptaround 10 kΩ in the low RESET current operation region. Byincreasing the SET pulse amplitude from 0.9 to 1.4 V [seeFig. 3(a)–(d)], the endurance failure mode gradually shifts from

parasitic current
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CHEN et al.: BALANCING SET/RESET PULSE FOR ENDURANCE IN 1T1R BIPOLAR RRAM 3245

Fig. 4. Pulse endurance behavior on 40-nm Hf/HfO2 1T1R devices, withfixed SET pulse at WL = 0.9 V, BL = 1.8 V, and 100 ns. The RESET pulseamplitude was varied on the SL: (a) 1.6 V, (b) 1.8 V, (c) 2.0 V, and (d) 2.2 V.The RESET pulsewidth was fixed at 10 ns, and the WL amplitude was fixedat 3.5 V. With increasing RESET SL voltage, endurance LRS failure occursat lower cycle number: (a) 106 cycles, (b) 5 × 105 cycles, (c) 105 cycles, and(d) 500 cycles.

the LRS failure [or SET failure in Fig. 3(a)] to the HRS failure[or RESET failure in Fig. 3(d)]. Too strong SET pulses result inHRS failure, and too weak SET pulses result in LRS failure.A “balance” between the SET and RESET pulses could beobtained by adjusting the SET WL pulse amplitude to 1 V.By screening the SET pulse amplitude conditions, a balancepoint of the SET/RESET pulses can be reached. For a SETpulse amplitude of 1 V [see Fig. 3(b)], a 106 endurance canbe reached with a stable LRS/HRS resistance window of onedecade, indicating that these SET/RESET pulse conditions arebetter balanced for enabling improved device endurance.

For the RESET pulse amplitude tuning, as shown in Fig. 4,the SET pulse was fixed at 0.9 V and 100 ns, and the RESETpulse amplitude was varied on SL. By increasing the RESET SLpulse amplitude from 1.6 to 2.5 V [see Fig. 4(a)–(d)], the LRSfails earlier during cycling [(a) after 106 cycles, (b) after 5 ×105 cycles, (c) after 105 cycles, and (d) after only 500 cycles),demonstrating that a too strong RESET pulse shifts theSET/RESET pulse combination further away from the balancepoint, leading to an earlier failure of the LRS state.

B. Impact of the SET/RESET Pulsewidth on EndurancePerformance

Fig. 5 shows the effect of the SET pulsewidth tuning on theendurance of 40-nm Hf/HfO2 devices. The SET/RESET pulseamplitudes were kept constant (SET: WL = 1 V and BL =1.8 V; RESET: WL = 3 V and SL = 1.8 V), while the SETpulsewidth was decreased from 100 ns down to 2.5 ns on BL[see Fig. 5(a)–(d)]. The RESET pulsewidth was fixed at 10 ns.From the endurance behavior under varying SET pulsewidthsand from the LRS stability, it appears that the SET pulsewidth

Fig. 5. Pulse endurance behavior on 40-nm Hf/HfO2 1T1R devices, with fixedRESET pulse at WL = 3 V, SL = 1.8 V, and 10 ns. The SET pulsewidth wasvaried on the BL: (a) 100 ns, (b) 10 ns, (c) 5 ns, and (d) 2.5 ns. The SET pulseamplitude was fixed at WL = 1 V and BL = 1.8 V. With decreasing SETBL pulsewidth, LRS state was not influenced, and successful 106 cycles can bereached in all cases.

Fig. 6. Pulse endurance behavior on 40-nm Hf/HfO2 1T1R devices, with fixedSET pulse at WL = 1 V, BL = 1.8 V, and 10 ns. The RESET pulsewidth wasvaried on the SL: (a) 10 ns and (b) 5 ns. The RESET pulse amplitude was fixedat WL = 3 V and SL = 1.8 V. With decreasing RESET BL pulsewidth, HRSresistance also decreased, and the LRS/HRS resistance window closed downfrom (a) 10 × to (b) 4 ×.

does not significantly influence the pulse endurance over thewhole pulsewidth range between 2.5 and 100 ns. Short SEToperation down to 2.5 ns could still enable successful enduranceup to 106 cycles.

Fig. 6 shows the RESET pulsewidth tuning on the 40-nmHf/HfO2 1T1R devices. The SET/RESET pulse amplitudeswere kept constant (SET: WL = 1 V and BL = 1.8 V; RESET:WL = 3 V and SL = 1.8 V), while the RESET pulsewidthwas decreased from 10 ns down to 5 ns on SL [see Fig. 6(a)and (b)]. Differently from the SET pulsewidth tuning, the HRSresistance decreases when the RESET pulsewidth is reducedto a 5-ns range, and the LRS/HRS resistance window reducesfrom a factor of 10 to a factor of 4. Short RESET operationdown to 5 ns could still give endurance up to 106 cycles, butwith a smaller LRS/HRS window. Compared to the short SET

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3246 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 12, DECEMBER 2012

TABLE ISUMMARY OF SET/RESET PULSE TUNING CONDITIONS STUDIED IN SECTION III. STRONG SET PULSE LEADS TO HRS FAILURE (NO RESET),

AND STRONG RESET PULSE LEADS TO LRS FAILURE (NO SET)

Fig. 7. (a) HRS failure after 106 cycles (SET pulse: WL = 1.4 V, BL = 1.8 V, and 100 ns; RESET pulse: WL = 3 V, SL = 1.8 V, and 10 ns).(b) DC RESET sweep of recovering the HRS state. (c) 104 cycles after the RESET recovery operation [same SET/RESET pulse as (a)].

Fig. 8. (a) LRS failure after 105 cycles (SET pulse: WL = 0.9 V, BL = 1.8 V, and 100 ns; RESET pulse: WL = 3 V, SL = 2 V, and 10 ns). (b) DC SETsweep of recovering the LRS state. (c) 5 × 105 cycles after the SET recovery operation [same SET/RESET pulse as (a)].

pulsewidth, a short RESET pulsewidth has larger influence onthe endurance behavior in the sub-10-ns range.

Compared to varying the SET/RESET pulse amplitude inSection III-A, tuning the SET/RESET pulsewidth did not sig-nificantly change the failure mode of the endurance. Gener-ally, short RESET pulse demonstrates larger influence on theendurance stability, as compared to the SET pulse. This is re-flected on the level of the HRS resistance. Moreover, successful106 endurance by short SET/RESET pulsewidth indicates thatthe fast drift of oxygen vacancies within the 5-nm HfO2 filmprobably has a small time constant < 5 ns, which made theinfluence of pulsewidth insignificant down to the sub-10-nsrange in this investigation.

Table I summarizes the impact of tuning the SET/RESETpulse amplitude and pulsewidth during cycling. The endurancefailure mode in the LRS current operation region (LRS resis-tance of ∼10 kΩ) can be modulated into either HRS failureor earlier/delayed LRS failure. A too strong SET pulse leadsto HRS failure, and a too strong RESET pulse leads to LRSfailure. By optimizing the balance between the SET/RESETpulses, the cycling ability of the Hf/HfO2 RRAM devices canbe improved. It is to be noted that the balance point of theSET/RESET pulses possibly depends on the operation range

of the cycling test and can be different for different LRS/HRSlevels. In this paper, we targeted the LRS resistance of ∼10 kΩor higher, in order to evaluate the endurance reliability closeto the practical situation of the NAND Flash or embeddedapplications.

C. Recovery of the LRS/HRS Endurance failure

After the endurance failure, such as the HRS failure inFig. 3(d) or the LRS failure in Fig. 4(c), a recovery phenomenonof the failed states is observed, which restores the cycling of thefailed cell.

1) After the HRS failure at 106 cycles, the failed HRS state[shown in Fig. 7(a) and replotted from Fig. 3(d)] canbe restored by a dc RESET operation [see Fig. 7(b)].After the HRS recovery, the cell could cycle again up to104 cycles [see Fig. 7(c)], with the same pulse conditionsas in Fig. 7(a).

2) After the LRS failure at 105 cycles, the failed LRS state[shown in Fig. 8(a) and replotted from Fig. 4(c)] canbe recovered by a dc SET operation [see Fig. 8(b)].After the LRS recovery, the cell could cycle again up to

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CHEN et al.: BALANCING SET/RESET PULSE FOR ENDURANCE IN 1T1R BIPOLAR RRAM 3247

Fig. 9. (a) Balanced SET/RESET. Vox drifts along the electrical field in HfO2. (b) With too strong RESET, too many Vox drift back to reservoir, and part of thefilament becomes less conductive, leading to LRS state failure. (c) With too strong SET, excess Vox drift, leading to HRS state failure.

5 × 105 cycles [see Fig. 8(c)]. Such recovery processescan also be repeated to extend the endurance longer.

The recovery of the failed LRS/HRS states indicates that theendurance failure from unbalanced SET/RESET pulses doesnot permanently degrade the HfO2/Hf material stack but onlychanges the distribution of the oxygen vacancy profile, which isbelieved to be essential for the bipolar switching in the HfO2/Hfstack [3], [12]. By the dc SET/RESET recovery operation, thepreferred distribution profile of oxygen vacancies is restored,and the endurance can continue. Moreover, during the study,we find that the SET/RESET recovery operation can also beachieved by applying pulses instead of dc sweep. Detailedstudy is planned to characterize the pulse SET/RESET recoveryphenomena, which is more relevant for the practical deviceoperation.

D. Failure Mechanism of the UnbalancedSET/RESET Operation

As the bipolar switching of TMO/metal capping stacks isunderstood by the drift of oxygen vacancies in the bilayer struc-ture [10]–[14], we can explain the unbalanced SET/RESETpulse during endurance in terms of the gradual accumulation oftoo many oxygen vacancies at one side of the bilayer structurewhich results in the endurance failure, when the same cyclingconditions are used.

Fig. 9(a)–(c) proposes a possible mechanism for the LRSfailure due to too strong RESET pulse and the HRS failure dueto too strong SET pulse. In the balanced SET/RESET schemein Fig. 9(a), the same amount of oxygen vacancies was driftedby the SET and the RESET pulses in the HfO2 film, and thus, ahigh number of endurance cycles can be expected for this case.A too strong RESET pulse [see Fig. 9(b)] would move too manyoxygen vacancies away from the switching interface, causing aredistribution of the oxygen vacancies in the HfO2/Hf stack.The depletion of oxygen vacancies at the switching interfacemakes the filament reconstruction more and more difficult bythe initial SET pulse. Only after a dc SET recovery operation, asshown in Fig. 8, can the balanced oxygen vacancy distributionbe restored, and SET/RESET cycling could continue. On theother hand, a too strong SET pulse [see Fig. 9(c)] would moveexcess oxygen vacancies to the switching interface in HfO2,causing again a redistribution of the oxygen vacancies. Theexcess of oxygen vacancies at the switching interface makes

Fig. 10. By balancing the SET pulse at WL = 1 V, BL = 1.8 V, and 5 nsand the RESET pulse at WL = 3 V, SL = 1.8 V, and 10 ns, 1010 pulseendurance was achieved on 40-nm Hf/HfO2 1T1R devices.

the RESET pulse unable to efficiently rupture the filament.Only after a dc RESET recovery operation, as shown in Fig. 7,can the balanced oxygen vacancy distribution be restored, andSET/RESET cycling can continue again. Therefore, the effectof oxygen vacancy depletion (strong RESET) and oxygen va-cancy excess (strong SET) from the unbalanced SET/RESETpulses leads to a progressive redistribution of oxygen vacanciesin the HfO2/Hf stack. Such an unbalanced redistribution resultsin the LRS/HRS failure during cycling. With optimal balancedSET/RESET pulses, the oxygen vacancy depletion/excess re-distribution could be suppressed, and longer pulse enduranceexceeding 1010 cycles can be achieved, as it will be demon-strated in the next section.

From the endurance behaviors under varying pulse ampli-tudes and pulsewidths in Section III-A and B, the redistributionof the oxygen vacancies is greatly influenced by the unbal-anced SET/RESET pulse amplitude, while the influence frompulsewidth is less significant. The dc SET/RESET recoverycan restore the proper oxygen vacancy distribution and can beincluded as an improved algorithm [15] to extend the maximumendurance cycles.

E. 1010 Cycles by Optimally Balancing the SET/RESETPulse Conditions

One of the purposes of balancing SET/RESET pulses isto extend the maximum endurance cycle. Fig. 10 shows a1010 pulse endurance obtained on the 40-nm HfO2/Hf 1T1RRRAM device by applying optimally balanced SET/RESETpulse conditions obtained from Section III-A and C (SET:WL = 1 V, BL = 1.8 V, and 5 ns; RESET: WL = 3 V,SL = 1.8 V, and 10 ns). The LRS state resistance waskept ∼20 kΩ. A stable ∼15× resistance window could be

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3248 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 12, DECEMBER 2012

maintained up to 1010 cycles for the fast SET/RESET pulses(5 ns/10 ns). In addition, this endurance test had no applicationof any dc recovery steps, and no indication of window closurewas visible at the moment when the test was stopped (after1010 cycles, while the device is still working). This result notonly clearly outperforms the endurance achievable with NAND

Flash memory, typically in the range of 104–105 cy, but alsodemonstrates the huge potential of this type of RRAM stacksfor high-endurance applications, such as embedded memory.

IV. CONCLUSION

In this paper, we investigated the endurance behavior andstudied the failure modes of 40-nm HfO2/Hf RRAM devicesin a 1T1R cell configuration by tuning the SET/RESET pulseconditions. With unbalanced SET/RESET pulse amplitudes, theendurance may fail either at the LRS or the HRS states. Thegradual redistribution of oxygen vacancies in HfO2 resultingfrom too strong SET/too strong RESET pulses causes theHRS/LRS endurance failure. Too strong RESET pulses result inthe depletion of the oxygen vacancies at the switching interfaceso that the SET pulse is unable to reconstruct the filament.By contrast, too strong SET pulses lead to an excess amountof oxygen vacancies induced at the switching interface sothat the RESET pulse is unable to rupture the filament. Thisdepletion/excess event of oxygen vacancies can be recovered byapplying dc SET/RESET recovery operation, which can restorethe a suitable profile of oxygen vacancy distribution, whichenables further switching and extends the device operationlifetime. Variations of the pulsewidth in the range of 2.5–100 nsshow less influence on the endurance failure mode but mayaffect the LRS/HRS resistance window. By optimally balanc-ing the SET/RESET pulse conditions, the endurance of our40-nm HfO2/Hf 1T1R device can be extended to more than1010 cycles, with an LRS level of ∼20 kΩ.

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[2] H. Y. Lee, P. S. Chen, T. Y. Wu, Y. S. Chen, C. C. Wang, P. J. Tzeng,C. H. Lin, F. Chen, C. H. Lien, and M.-J. Tsai, “Low power and high speedbipolar switching with a thin reactive Ti buffer layer in robust HfO2 basedRRAM,” in IEDM Tech Dig., 2008, pp. 1–4.

[3] J. Lee, J. Shin, D. Lee, W. Lee, S. Jung, M. Jo, J. Park, K. P. Biju,S. Kim, S. Park, and H. Hwang, “Diode-less nano-scale ZrOx/HfOxRRAM device with excellent switching uniformity and reliability forhigh-density cross-point memory applications,” in IEDM Tech. Dig.,2010, pp. 19.5.1–19.5.4.

[4] B. Govoreanu, G. S. Kar, Y.-Y. Chen, V. Paraschiv, A. Fantini, I. P. Radu,L. Goux, S. Clima, R. Degraeve, N. Jossart, O. Richard, T. Vandeweyer,K. Seo, P. Hendrickx, G. Pourtois, H. Bender, L. Altimime, D. J. Wouters,J. A. Kittl, and M. Jurczak, “10 nm × 10 nm Hf/HfOx crossbar resistiveRAM with excellent performance, reliability and low-energy operation,”in IEDM Tech. Dig., 2011, pp. 31.6.1–31.6.4.

[5] Y.-S. Chen, H.-Y. Lee, P.-S. Chen, W.-H. Liu, S.-M. Wang, P.-Y. Gu,Y.-Y. Hsu, C.-H. Tsai, W.-S. Chen, F. Chen, M.-J. Tsai, and C. Lien,“Robust high-resistance state and improved endurance of HfOX resistivememory by suppression of current overshoot,” IEEE Electron DeviceLett., vol. 32, no. 11, pp. 1585–1587, Nov. 2011.

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W. S. Chen, F. T. Chen, C. H. Lien, and M.-J. Tsai, “Evidence andsolution of over-RESET problem for HfOX based resistive memory withsub-ns switching speed and high endurance,” in IEDM Tech Dig., 2010,pp. 19.7.1–19.7.4.

[7] J. J. Yang, M.-X. Zhang, J. P. Strachan, F. Miao, M. D. Pickett,R. D. Kelley, G. Medeiros-Ribeiro, and R. Stanley Williams, “Highswitching endurance in TaOx memristive devices,” Appl. Phys. Lett,vol. 97, no. 23, pp. 232102-1–232102-3, Dec. 2010.

[8] Y.-B. Kim, S. R. Lee, D. Lee, C. B. Lee, M. Chang, J. H. Hur, M.-J. Lee,G.-S. Park, C. J. Kim, U.-I. Chung, I.-K. Yoo, and K. Kim, “Bi-layeredRRAM with unlimited endurance and extremely uniform switching,” inVLSI Tech. Dig., 2011, pp. 52–53.

[9] B. Chen, Y. Lu, B. Gao, Y. H. Fu, F. F. Zhang, P. Huang, Y. S. Chen,L. F. Liu, X. Y. Liu, J. F. Kang, Y. Y. Wang, Z. Fang, H. Y. Yu, X. Li,X. P. Wang, N. Singh, G. Q. Lo, and D. L. Kwong, “Physical mechanismsof endurance degradation in TMO-RRAM,” in IEDM Tech Dig., 2011,pp. 12.3.1–12.3.4.

[10] R. Waser and M. Aono, “Nanoionics-based resistive switching memo-ries,” Nat. Mater., vol. 6, no. 11, pp. 833–840, Nov. 2007.

[11] J. J. Yang, M. D. Pickett, X. Li, D. A. A. Ohlberg, D. R. Stewart, andR. S. Willams, “Memristive switching mechanism for metal/oxide/metalnanodevices,” Nat. Nanotechnol., vol. 3, no. 7, pp. 429–433, Jul. 2008.

[12] Y. S. Chen, H. Y. Lee, P. S. Chen, P. Y. Gu, C. W. Chen, W. P. Lin,W. H. Liu, Y. Y. Hsu, S. S. Sheu, P. C. Chiang, W. S. Chen, F. T. Chen,C. H. Lien, and M.-J. Tsai, “Highly scalable hafnium oxide memorywith improvements of resistive distribution and read disturb immunity,”in IEDM Tech. Dig., 2009, pp. 1–4.

[13] L. Goux, P. Czarnecki, Y. Y. Chen, L. Pantisano, X. P. Wang, R. Degraeve,B. Govoreanu, M. Jurczak, D. J. Wouters, and L. Altimime, “Evidences ofoxygen-mediated resistive-switching mechanism in TiN\HfO2\Pt cells,”Appl. Phy. Lett., vol. 97, no. 24, pp. 243509-1–243509-3, Dec. 2010.

[14] L. Goux, J. G. Lisoni, M. Jurczak, D. J. Wouters, L. Courtade, andC. Muller, “Coexistence of the bipolar and unipolar resistive-switchingmodes in NiO cells made by thermal oxidation of Ni layers,” J. Appl.Phys., vol. 107, no. 2, pp. 024512-1–024512-7, Jan. 2010.

[15] L. Goux, D. T. Castro, G. A. M. Hurkx, J. G. Lisoni, R. Delhougne,D. J. Gravesteijn, K. Attenborough, and D. J. Wouters, “Degradation ofthe reset switching during endurance testing of a phase-change line cell,”IEEE Trans. Electron Devices, vol. 56, no. 2, pp. 354–358, Feb. 2009.

Yang Yin Chen (S’06) received the joint M.S. de-gree from Katholieke Universteit Leuven, Leuven,Belgium/Chalmers Tekniska Högskola, Göteborg,Sweden. He is currently working toward the Ph.D.degree at the Interuniversity Microelectronics Cen-ter, Leuven.

Bogdan Govoreanu (M’05–SM’11) received thePh.D. degree in applied sciences from the KatholiekeUniversiteit Leuven, Leuven, Belgium, in 2004.

He is currently a Principal Scientist with the In-teruniversity Microelectronics Center, Leuven.

Ludovic Goux received the Ph.D. degree in engi-neering science from the University of Tours, Tours,France, in 2002.

Since then he has been with the InteruniversityMicroelectronics Center, Leuven, Belgium, where heis currently in charge of the CBRAM technologydevelopment.

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CHEN et al.: BALANCING SET/RESET PULSE FOR ENDURANCE IN 1T1R BIPOLAR RRAM 3249

Robin Degraeve received the Ph.D. degree from theCatholic University of Leuven, Leuven, Belgium,in 1998.

In 1992, he joined the CMOS Reliability Group,Interuniversity Microelectronics Center, Leuven,where he is a Principal Scientist.

Andrea Fantini received the M.Sc. and Ph.D. de-grees in electronic engineering from the Universityof Pavia, Pavia, Italy, in 2003 and 2007, respectively.

In 2010, he joined the Interuniversity Microelec-tronics Center, Leuven, Belgium.

Gouri Sankar Kar received the Ph.D. degree inphysics from the Indian Institute of Technology,Kharagpur, India, in 2002.

In 2009, he joined the Interuniversity Microelec-tronics Center, Leuven, Belgium, where he is cur-rently a Program Manager.

Dirk. J. Wouters (M’92) received the M.S. andPh.D. degrees in electrical engineering from the Uni-versity of Leuven, Leuven, Belgium, in 1982 and1989, respectively.

He is currently a Principal Scientist Memory withthe Interuniversity Microelectronics Center, Leuven.

Guido Groeseneken (F’07) received the Ph.D. de-gree in applied sciences from KU Leuven, Leuven,Belgium, in 1986.

In 1987, he joined the Interuniversity Microelec-tronics Center, Leuven where he became IMECFellow in 2005. He is also Professor at the KULeuven since 2001.

Jorge. A. Kittl, photograph and biography not available at the time ofpublication.

Malgorzata Jurczak (M’08) received the Ph.D. de-gree from the Warsaw University of Technology,Warsaw, Poland, in 1997.

Since 2011, she has been the Director of theEmerging Memories Program at the InteruniversityMicroelectronics Center, Leuven, Belgium.

Laith Altimime received the M.S. degree fromHeriot Watt University, Edinburgh, U.K., in 1989.

In April 2009, he joined the Interuniversity Mi-croelectronics Center, Leuven, Belgium, where heis currently the Director of the CMOS TechnologyDepartment.


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