INTRODUCTION We are li vi ng in a wo rl d dr iv en by va ri ous el ectroni cs equipments. Semiconductor forms the fundamental building blocks of the modern electr oni c wor ld providi ng the brains and the memor y of the produc t all around us from washing machines to super computers. Semiconductor consis ts of arr ay of tra nsi stors wit h eac h tra nsis tor bei ng a single swi tch between electrical 0 and 1.Now often bundled together in their 10’s of million they form highly complex ,intelligent, reliable semiconductor chips, which are small and cheap enough for proliferation into products all around us. Identification of new materials has been, and still is, the primary means in the development of next generation semiconductors. For the past 30 years, relentless scaling of CMOS IC technology to smaller di mens ions ha s enabled the continual intro duction of compl ex microelectronics system functions. However, this trend is not likely to continue indefinit ely beyond the semiconductor technology roadmap. As silicon technology approaches its material limit, and as we reach the end ofthe roadmap, an understanding of eme rgin g research devices will be offoremost importance in the identification of new materials to address the corresponding technological requirements.If scaling is to continue to and below the 65nm node, alternatives to CMOS designs will be needed to provide a path to device scaling beyond the end of the roadmap. However, these emerging research technologies will be faced with an uphill technology challenge. For digital applications, these challenges include exponentially increasing the leakage current (gate, channel, and source/drain junctions), short channel effects, etc. while for analogue or RF applications, among the challenges are sustained linearity, low noise figure, power added efficiency and transistor matching. One of the fundamental approaches to manage this challenge is using new materials to build the next generation transistors.
Every computer system contains a variety of devices to store theinstructions and data required for its operation. These storage devices plusthe algorithms needed to control or manage the stored information constitute
the memory system of the computer. In general, it is desirable thatprocessors should have immediate and interrupted access to memory, so thetime required to transfer information between the processor and memoryshould be such that the processor can operate at, close to, its maximumspeed. Unfortunately, memories that operate at speeds comparable toprocessors speed are very costly. It is not feasible to employ a single memoryusing just one type of technology. Instead the stored information isdistributed in complex fashion over a variety of different memory units withvery different physical characteristics.
The memory components of a computer can be subdivided intothree main groups:
1) Internal processor memory: this usually comprises of a small set of highspeed registers used as working registers for temporary storage of instructions and data.
2) Main memory: this is a relatively large fast memory used for program anddata storage during computer operation. It is characterized by the factthat location in the main memory can be directly accessed by the CPUinstruction set. The principal technologies used for main memory aresemiconductor integrated circuits and ferrite cores.
3) Secondary memory: this is generally much larger in capacity but also
much slower than main memory. It is used for storing system programsand large data files and the likes which are not continually required by theCPU; it also serves as an overflow memory when the capacity of the mainmemory is exceeded. Information in secondary storage is usuallyaccessed directly via special programs that first transfer the requiredinformation to main memory. Representative technologies used forsecondary memory are magnetic disks and tapes.
The major objective in designing any memory is to provide adequatestorage capacity with an acceptable level of performance at a reasonablecost.
Memory device characteristics
The computer architect is faced with a bewildering variety of memory devicesto use. However; all memories are based on a relatively small number of physical phenomena and employ relatively few organizational principles. The
characteristics and the underlying physical principles of some specificrepresentative technologies are also discussed.
Cost:The cost of a memory unit is almost meaningfully measured by the
purchase or lease price to the user of the complete unit. The price shouldinclude not only the cost of the information storage cells themselves but alsothe cost of the peripheral equipment or access circuitry essential to theoperation of the memory.
Access time and access rate:The performance of a memory device is primarily determined by the
rate at which information can be read from or written into the memory. Aconvenient performance measure is the average time required to read a fixedamount of information from the memory. This is termed read access time.
The write access time is defined similarly; it is typically but not always equalto the read access time. Access time depends on the physical characteristics
of the storage medium, and also on the type of access mechanism used. It isusually calculated from the time a read request is received by the memoryand to the time at which all the requested information has been madeavailable at the memory output terminals. The access rate of the memory isdefined is the inverse of the access time.
Clearly low cost and high access rate are desirable memorycharacteristics; unfortunately they appear to be largely compatible. Memoryunits with high access rates are generally expensive, while low cost memoryare relatively slow.
Access mode- random and serial:An important property of a memory device is the order or sequence
in which information can be accessed. If locations may be accessed in anyorder and the access time is independent of the location being accessed, thememory is termed as a random access memory.
Ferrite core memory and semiconductor memory are usually of thistype. Memories where storage locations can be accessed only in a certainpredetermined sequence are called serial access memories. Magnetic tapeunits and magnetic bubble memories employ serial access methods.
In a random access memory each storage location can be accessedindependently of the other locations. There is, in effect, a separate accessmechanism, or read-write, for every location. In serial memories, on the otherhand, the access mechanism is shared among different locations. It must beassigned to different locations at different times. This is accomplished bymoving the stored information, the read write head or both. Many serialaccess memories operate by continually moving the storage locations arounda closed path or track. A particular location can be accessed only when itpasses the fixed read write head; thus the time required to access aparticular location depends on the relative location of the read/write headwhen the access request is received.
Since every location has its own addressing mechanism, randomaccess memory tends to be more costly than the serial type. In serial type
memory, however the time required bringing the desired location intocorrespondence with a read/write head increases the effective access time,so access tends to be slower than the random access. Thus the access modeemployed contributes significantly to the inverse relation between cost andaccess time.
Some memory devices such as magnetic disks and d rums contain
large number of independently rotating tracks. If each track has its own read-write head, the track may be accessed randomly, although access withintrack in serial. In such cases the access mode is sometimes called semirandom or direct access. It should be noted that the access Is a function of the memory technology used.
Alterability-ROMS:
The method used to write information into a memory may beirreversible, in that once the information has been written, it cannot bealtered while the memory is in use,i.e.,online. Punching holes in cards andprinting on paper are examples of essentially permanent storage techniques.Memories whose contents cannot be altered online are called read onlymemories. A Rom is therefore a non alterable storage device. ROMs arewidely used for storing control programs such as micro programs. ROMswhose contents can be changed are called programmable read onlymemories (PROMs).Memories in which reading or writing can be done withimpunity online are sometimes called read-write memories (RWMs) tocontrast them with ROMs. All memories used for temporary storage areRWMs.
Permanence of storage:The physical processes involved in storage are sometimes inherently
unstable, so that the stored information may be lost over a period of time
unless appropriate action is taken. There are important memorycharacteristics that can destroy information:1. Destructive read out2. Dynamic volatility3. Volatility
Ferrite core memories have the property that the method of reading thememory alters, i.e., destroys, the stored information; this phenomenon iscalled destructive read out (DRO). Memories in which reading does not affectthe stored data are said to have nondestructive readout (NRDO). In DROmemories, each read operation must be followed by a write operationfollowed by a write operation that restores the original state of the memory.
This restoration is usually carried out by automatically using a buffer register.Certain memory devices have the property that a stored 1 tends to become a0, or vice versa, due to some physical decay processes. Over a period of time, a stored charge tends to leak away, causing a loss of information unlessthe stored charge is restored. This process of restoring is called refreshing.Memories which require periodic refreshing are called dynamic memories, asopposed to static memories, which require no refreshing. Most memories thatusing magnetic storage techniques are static. Refreshing in dynamic
memories can be carried out in the same way data is restored in a DROmemory. The contents of every location are transferred systematically to abuffer register and then returned, in suitably amplified form, to their originallocations. Another physical process that can destroy the contents of amemory is the failure of power supply. A memory is said to be volatile if thestored information can be destroyed by a power failure. Most semiconductor
memories are volatile, while most magnetic memories are non volatile.
Cycle time and data transfer rate:The access time of a memory is defined as the time between the
receipt of a read request and the delivery of the requested information to itsexternal output terminals. In DRO and dynamic memories, it may not bepossible to initiate another memory access until a restore or refreshoperation has been carried out. This means that the minimum time that mustelapse between the initiations of two different accesses by the memory canbe greater than the access time: this rather loosely defined time is called thecycle time of the memory.
It is generally convenient to assume the cycle time as the time neededto complete any read or write operation in the memory. Hence the maximumamount of information that can be transferred to or from the memory everysecond is the reciprocal of cycle time. This quantity is called the data transferrate or band width.
Random access memory
Random access memories are characterized by the fact that everylocation can be accessed independently. The access time and the cycle time
are constant independent of the position. Figure below gives the maincomponents of a random access unit. The storage cell unit comprises N cellseach of which can store one bit of information. The memory operates asfollows. The address of the required location is transferred via the addressbus to the memory address register. The address is then processed by theaddress decoder which selects the required location in the storage cell unit. Aread-write select control line specifies the type of access to be performed. If read is requested, the contents of the selected location is transferred to theoutput data register. If write is requested, the word to be written is firstplaced in the memory input data register and then transferred to the selectedcell. Since it is not usually desirable to permit simultaneous reading andwriting, the input and the output data registers are frequently combined to
form a single data register.Each storage cell has a number of lines connected to it. The address
lines are used to select the cell for either reading or writing, as determined bythe read-write control lines. A set of data lines is used for transferring data toand from the memory. The actual of physical lines connected to a storage cellis very much a function of the technology being used. Frequently onephysical line has several functions, e.g., it may be used as both an addressand a data line.RAMs are available in the static and the dynamic versions.
FLASHAn interesting MOS device is the flash memory which is an important
type of non volatile memory. It is very simple and compact and looks like aMOSFET, except that it has two gate electrodes one on top of another. Thetop electrode is the one that we have direct access to, and is known as thecontrol gate. Below that we have the so called floating gate that is capacitivecoupled to the control gate and the underlying silicon. The basic cell
operation involves putting charge on the floating gate or removing gate, inorder to program the MOSFET to have two different VT’s, corresponding totwo logic levels.
To program the cell, we apply a high field to both the drain and thefloating gate such that the MOSFET is in saturation. The high longitudinalelectric fielding the pinch off region accelerates electrons towards the drainand make them energetic. If the kinetic energy of the electrons is highenough, a few can become hot enough to be scattered into the floating gate.Once they get into the floating gate, electrons become trapped in thepotential well between the floating polysilicon gate and the oxide on eitherside. This barrier is extremely high for a trapped electron. Therefore thetrapped electrons essentially stay in the floating gate forever, unless the cellsare intentionally erased. That’s why a flash memory is non volatile. To erasethe cell, we use Fowler Nordheim tunneling between the floating gate and thesource in the overlap region. A high voltage is applied to the source with thecontrol gate grounded. The polarity of the field is such that the electronstunnel from the floating gate, through the oxide barrier.
As stated, revising the memory technology fields ruled by silicontechnology is of great importance. Digital Memory is and has been a closecomrade of each and every technical advancement in Information
Technology. The current memory technologies have a lot of limitations.DRAM is volatile and difficult to integrate. RAM is high cost and volatile.Flash has slower writes and lesser number of write/erase cycles compared
to others. These memory technologies when needed to expand will allowexpansion only two-dimensional space. Hence area required will beincreased. They will not allow stacking of one memory chip over the other.Also the storage capacities are not enough to fulfill the exponentiallyincreasing need. Hence industry is searching for “Holy Grail” futurememory technologies that are efficient to provide a good solution. Nextgeneration memories are trying tradeoffs between size and cost. Thesemake them good possibilities for development.
EMERGING MEMORY TECHNOLOGIES
Many new memory technologies were introduced when it isunderstood that semiconductor memory technology has to be replaced, orupdated by its successor since scaling with semiconductor memoryreached its material limit. These memory technologies are referred as‘Next Generation Memories”. Next Generation Memories satisfy all of thegood attributes of memory. The most important one among them is theirability to support expansion in three-dimensional spaces. Intel, the biggestmaker of computer processors, is also the largest maker of flash-memorychips is trying to combine the processing features and space requirementsfeature and several next generation memories are being studied in thisperspective. They include MRAM, FeRAM, Polymer Memory Ovonic UnifiedMemory, ETOX-4BPC, NRAM etc. One or two of them will become the
mainstream.
FUNDAMENTAL IDEAS OF EMERGINGMEMORIES
The fundamental idea of all these technologies is the bistablenature possible for the selected material. FeRAM works on the basis of the bistable nature of the centre atom of selected crystalline material. Avoltage is applied upon the crystal, which in turn polarizes the internaldipoles up or down. I.e. actually the difference between these states is thedifference in conductivity. Non –Linear FeRAM read capacitor, i.e., the
crystal unit placed in between two electrodes will remain in the directionpolarized (state) by the applied electric field until another field capable of polarizing the crystal’s central atom to another state is applied.
In the case of Polymer memory data stored by changing thepolarization of the polymer between metal lines (electrodes). To activatethis cell structure, a voltage is applied between the top and bottomelectrodes, modifying the organic material. Different voltage polarities are
used to write and read the cells. Application of an electric field to a celllowers the polymer’s resistance, thus increasing its ability to conductcurrent; the polymer maintains its state until a field of opposite polarity isapplied to raise its resistance back to its original level. The differentconductivity States represent bits of information.
In the case of NROM memory ONO stacks are used to storecharges at specific locations. This requires a charge pump for producingthe charges required for writing into the memory cell. Here charge isstored at the ON junctions.
Phase change memory also called ovonic unified memory(OUM), is based on rapid reversible phase change effect in materialsunder the influence of electric current pulses. The OUM uses the reversiblestructural phase-change in thin-film material (e.g., chalcogenides) as thedata storage mechanism. The small volume of active media acts as aprogrammable resistor between a high and low resistance with > 40Xdynamic range. Ones and zeros are represented by crystalline versusamorphous phase states of active material. Phase states are programmed
by the application of a current pulse through a MOSFET, which drives thememory cell into a high or low resistance state, depending on currentmagnitude. Measuring resistance changes in the cell performs the functionof reading data. OUM cells can be programmed to intermediate resistancevalues; e.g., for multistage data storage.
MRAMs are based on the magneto resistive effects in magneticmaterials and structures that exhibit a resistance change when anexternal magnetic field is applied. In the MRAM, data are stored byapplying magnetic fields that cause magnetic materials to be magnetizedinto one of two possible magnetic states. Measuring resistance changes inthe cell compared to a reference performs reading data. Passing currents
nearby or through the magnetic structure creates the magnetic fieldsapplied to each cell.
Introduction to OUM
Almost 25% of the world wide chip markets are memory
devices, each type used for their specific advantages: the high speed of anSRAM, the high integration density of a DRAM, or the nonvolatile capability of a FLASH memory device. These applications are already available based onexisting memory technology, but for a successful market penetration. Ahigher performance at a lower price is required. The existing technologies are
characterized by the following limitations. DRAMs are difficult tointergrate.SRAMs are expensive. FLASH memory can have only a limitednumber of read and write cycles.EPROMs had high power requirement andpoor flexibility.
None of the present memory technologies combine featureslike
• The ability to retain stored charge for long periods with zeroapplied or refreshed power.
Among the above-mentioned non-volatile Memories, OvonicUnified Memory is the most promising one. “Ovonic Unified Memory” is theregistered name for the non-volatile memory based on the material calledchalcogenide. The term “chalcogen” refers to the Group VI elements of the periodic table. “Chalcogenide” refers to alloys containing at least oneof these elements such as the alloy of germanium, antimony, andtellurium discussed here. Energy Conversion Devices, Inc. has used thisparticular alloy to develop a phase-change memory technology used incommercially available rewriteable CD and DVD disks. This phase changetechnology uses a thermally activated, rapid, reversible change in thestructure of the alloy to store data. Since the binary information is
represented by two different phases of the material it is inherently non-volatile, requiring no energy to keep the material in either of its two stablestructural states. The two structural states of the chalcogenide alloy, asshown in Figure 1, are an amorphous state and a polycrystalline state.Relative to the amorphous state, the polycrystalline state shows adramatic increase in free electron density, similar to a metal. Thisdifference in free electron density gives rise to a difference in reflectivityand resistivity. In the case of the re-writeable CD and DVD disktechnology, a laser is used to heat the material to change states. Directinga low-power laser at the material and detecting the difference inreflectivity between the two phases read the state of the memory.
FIGURE 1
Ovonyx, Inc., under license from Energy Conversion Devices, Inc.,is working with several commercial partners to develop a solid-statenonvolatile memory technology using the chalcogenide phase changematerial. To implement a memory the device is incorporated as a twoterminal resistor element with standard CMOS processing. Resistiveheating is used to change the phase of the chalcogenide material.
Depending upon the temperature profile applied, the material is eithermelted by taking it above the melting temperature (Tm) to form theamorphous state, or crystallized by holding it at a lower temperature (Tx)for a slightly longer period of time, as shown in Figure 2. The time neededto program either state is = 400ns. Multiple resistance states betweenthese two extremes have been demonstrated, enabling multi-bit storage
per memory cell. However, current development activities are focused onsingle-bit applications. Once programmed, the memory state of the cell isdetermined by reading its resistance
FIGURE 2
Since the data in a chalcogenide memory element is stored as astructural phase rather than an electrical charge or state, it is expected tobe impervious to ionizing radiation effects. This inherent radiationtolerance of the chalcogenide material and demonstrated write speeds
more than 1000 times faster than commercially available nonvolatilememories make it attractive for space based applications. A radiationhardened semiconductor technology incorporating chalcogenide basedmemory elements will address both critical and enabling space systemneeds, including standalone memory modules and embedded cores formicroprocessors and ASICs. Previously, BAE SYSTEMS and Ovonyx have
reported on the results of discrete memory elements fabricated in BAESYSTEMS’ Manassas, Virginia facility. These devices were manufacturedusing standard semiconductor process equipment to sputter and etch thechalcogenide material. While built in the same line used to fabricateradiation-hardened CMOS products, these memory elements were not yetintegrated with transistors. They were discrete two-terminalprogrammable resistors, requiring approximately 0.6 mA to set the deviceinto a low resistance state, and 1.3 mA to reset it to the high resistancestate. One billion (1E9) write cycles between these two states weredemonstrated. Reading the state of the device is non-destructive and hasno impact on device wear out (unlimited read cycles).
OUM ATTRIBUTES
• Non volatile in nature
• High density ensures large storage of data within a small area
• Non destructive read:-ensures that the data is not corrupted during aread cycle.
• Uses very low voltage and power from a single source.
• Write/erase cycles of 10e12 are demonstrated
• Poly crystalline
• This technology offers the potential of easy addition of non volatilememory to a standard CMOS process.
The above figure shows the memory structure of OUMA memory cell consists of a top electrode, a layer of the chalcogenide, anda resistive heating element. The base of the heater is connected to a diode.As with MRAM, reading the micrometer-sized cell is done by measuring itsresistance. But unlike MRAM the resistance change is very large-more thana factor of 100. Thermal insulators are also attached to the memorystructure in order to avoid data lose due to destruction of material at hightemperatures. To write data into the cell, the chalcogenide is heated pastits melting point and then rapidly cooled to make it amorphous. Tomake it crystalline, it is heated to just below its melting point and held there
for approximately 50ns, giving the atoms time to position themselves intheir crystal locations.
INTEGRATION WITH CMOS
Under contract to the Space Vehicles Directorate of the Air ForceResearch Laboratory (AFRL), BAE SYSTEMS and Ovonyx began the currentprogram in August of 2001 to integrate the chalcogenide-based memoryelement into a radiation-hardened CMOS process. The initial goal of thiseffort was to develop the processes necessary to connect the memoryelement to CMOS transistors and metal wiring, without degrading theoperation of either the memory elements or the transistors. It also wasdesired to maximize the potential memory density of the technology byplacing the memory element directly above the transistors and below thefirst level of metal as shown in a simplified diagram in Figure 3.
To accomplish this process integration task, it was necessaryto design a test chip with appropriate structures. This vehicle was calledthe Access Device Test Chip (ADTC) since each memory cell requires anaccess device (transistor) in addition to the chalcogenide memoryelement. Such a memory cell, comprised of one access transistor and onechalcogenide resistor, is herein referred to as a 1T1R cell. The ADTCincluded 272 macros, each with 2 columns of 10 probe pads. Of these, 163macros were borrowed from existing BAE SYSTEMS’ test structures andused to verify normal transistor operation. There were 109 new macros
designed to address the memory element features. These included sheetresistance and contact resistance measurement structures, discretememory elements of various sizes and configurations, and two 16-bit 1T1Rmemory arrays.
Short loop (partial flow) experiments were processed usingsubsets of the full ADTC mask set. These experiments were used tooptimize the process steps used to connect the bottom electrode of thememory element to underlying tungsten studs and to connect anadditional tungsten stud level between Metal 1 and the top electrode of the memory element. A full flow experiment was then processed todemonstrate integrated transistors and memory elements.
Figure 4 shows the I-V characteristic for a 1T1R memory cell successfullyfabricated using the ADTC vehicle. At low voltages, the device exhibits eithera low resistance (~1k) or high resistance (>100k), depending on itsprogrammed state. This is the read region of operation. To program thedevice, a pulse of sufficient voltage is applied to drive the device into a highconduction “dynamic on state”. For a reset device, this requires a voltagegreater than Vth.Vth is the device design parameter and for current memoryapplication is chosen to be in the range of 0.5 to 0.9 V. The voltage is appliedto one of the two terminals of the chalcogenide resistor, and the accesstransistor (biased on) is between the other resistor terminal and ground. Thehigh resistance amorphous material shows very little current below athreshold voltage (VT) of 1.2V. In this same region the low resistancepolycrystalline material shows a significantly higher current. The state of thememory cell is read using the difference in I-V characteristics below VT.Above VT, both materials display identical I-V characteristics, with a dynamicresistance (RDYNAMIC) of ˜1k. In itself, this transition to a low resistanceelectrical state does not change the structural phase of the material.However, it does allow for heating of the material to program it to the lowresistance state (1) or the high resistance state (0). Extrapolation of theportion of the I-V curve that is above VT to the X-axis yields a point referredto as a holding voltage (VH). The applied voltage must be reduced below VHto exit the programming mode.
Figure 5 shows the operation of a 1T1R memory, again with theaccess transistor biased on. The plotted resistance values were measuredbelow V T, while the current used to program these resistances wasmeasured above V T. Similar to the previously demonstrated stand-alonememory elements, these devices require approximately 0.6 mA to set tothe low resistance state (RSET) and 1.2 mA to reset to the high resistancestate (RRESET). The circuit was verified to be electrically open with theaccess transistor biased off.
In order to test the behavior of chalcogenide cells as circuitelements, the Chalcogenide Technology Characterization Vehicle (CTCV)
was developed. The CTCV contains a variety of memory arrays withdifferent architecture, circuit, and layout variations. Key goals in the designof the CTCV were: 1) to make the read and write circuits robust with respectto potential variations in cell electrical characteristics; 2) to test the effectof the memory cell layout on performance; and 3) to maximize the amountof useful data obtained that could later be used for product design. TheCTCV was sub-divided into four chiplets, each containing variations of 1T1Rcell memory arrays and various standalone sub circuits. Standalone copiesof the array sub circuits were included in each chiplet for processmonitoring and read/write current experiments.
FIGURE 7
A diagram of one of the chiplets is shown in Figure 7. The arrays allcontain 64k 1T1R cells, arranged as 256 rows by 256 columns. This islarge enough to make meaningful analyses of parasitic capacitanceeffects, while still permitting four variations of the array to be placed oneach chiplet. The primary differences between arrays consist of the typeof sense amp (single-ended or differential) and variations in the locationand number of contacts in the memory cell. The data in the single-endedarrays is formatted as 4096 16-bit words (64k bits), and in the differentialarrays as 4096 8-bit words (32k bits). The 256 columns are divided into 16groups of 16. One sense amplifier services each group, and the 16columns in each group are selected one at a time based on the four most
significant address bits. In simulations, stray capacitance was predicted tocause excessive read settling time when more than 16 columns wereconnected to a sense amp. Each column has its own write current river,which also performs the column select function for write operations. Thesingle-ended sense amplifier reads the current drawn by a single cellwhen a voltage is applied to it. The differential amplifier measures the
currents in two selected cells that have previously been written withcomplementary data, and senses the difference in current between them.
This cuts the available memory size in half, but increases noise marginand sensitivity. In both the single-ended and differential sense amplifiers,a voltage limiting circuit prevents the chalcogenide element voltage fromexceeding V T, so that the cell is not inadvertently re-programmed. On onechiplet, there are two arrays designed without sense amplifiers. Instead,the selected column outputs are routed directly to the 16 I/O pins wherethe data outputs would normally be connected. This enables direct analogmeasurements to be made on a selected cell. A third array on this chiplethas both the column select switches and the sense amplifiers deleted.Eight of the 256 columns are brought out to I/O pins. This enables further
analog measurements to be made, without an intervening column selecttransistor.
“Conservative” and “aggressive” layout versions of thechalcogenide cell were made. The conservative cell is larger, and has fourcontacts to bring current through to the bottom and top electrodes of thememory cell. The aggressive cell contains only two contacts per electrode,reducing its size. The pitch of the larger cell was used to establish row andcolumn spacing in all arrays. The aggressive cell could thus be easilysubstituted for the conservative cell. Short wires were added to thesmaller cell to map its connection points to those of the larger. Thispermitted testing both cells in one array layout without requiringsignificant additional layout labor. A final variation in the cell design
involved contact spacing. The contacts on the bottom electrode weremoved to be either closer to or farther away from the chalcogenide "pore."
This allows assessment of the effect of contact spacing on the thermal andelectrical characteristics of the chalcogenide pore. Process monitoringstructures were included on each chiplet to aid in calibration of memoryarray test data. These consist of a standalone replica of each of the Writeand Read (single-ended) circuits, a CMOS inverter, and a 1T1R cell. Theoutputs of each of these circuits were brought out to permit measurementof currents versus bias voltages.
Pins were provided on the CTCV for external bias voltage inputs tovary the read and write current levels. The standalone copies of theread/write circuits are provided with all key nodes brought out to pins.
These replica circuits permit the read and write currents to beprogrammed by varying the bias voltages. This allows more in-depthcharacterization to be performed in advance of designing a product. In anactual product, on-chip reference circuits would generate bias voltages. Inthe write circuit, a PFET driver is connected to each column, and isnormally turned off by setting its gate bias to VDD. When a write is tooccur, the selected driver’s gate is switched to one of two external bias
voltages for the required write pulse time. The bias voltages can becalibrated to set the write drive currents to the levels needed to reliablywrite a one or a zero. The data inputs determine which bias voltage isapplied to each write driver. For the read circuit, several cell resistance-sensing schemes were investigated during CTCV development. Theadopted scheme applies a controlled voltage to the cell to be read, and
the resulting current is measured. Care is taken not to exceed V T during aread cycle. The sense amplifier reflects the read current into aprogrammable NFET load, thus generating a high (1) or low (0) output.
The gate bias of all sense amplifier loads can be varied in parallel tochange the current level at which the output voltage switches. The biaslevels are calibrated via a standalone copy of the read circuit that has allkey nodes brought out to pins. The NFET load's output is buffered by astring of CMOS inverters to provide full CMOS logic voltage swing, andthen routed to the correct data output I/O pad driver.
When a read circuit supplies a current to a selected cell, the cell'scorresponding column charges up toward the steady state read voltage.
The column voltage waveform is affected by the programmed resistanceand internal capacitances of each of the cells in the column, and thus ispattern dependent. The combined charge from all of the column's cellsduring this charging process may travel into the sense amplifier input,momentarily causing it to experience a transient, which could prevent theaccessed cells’ data from being read correctly. To minimize this effect,each column is discharged after a write, and recharged before a read.
Transistor parametric and discrete memory element test structures weretested on the CTCV lot at the wafer level. These tests served twopurposes. The first goal was to confirm that the extra processing stepsinvolved in inserting the chalcogenide flow had no effect on the baseCMOS technology. No statistical differences in transistor parametric values
were noted between these wafers and standard 0.5µm RHCMOS product. The second goal of wafer test was to measure the set, reset and dynamicprogramming resistances (RSET, RRESET and RDYNAMIC), threshold and holdingvoltages (V T and VH), and required programming currents (ISET and IRESET) of stand-alone, two terminal chalcogenide memory elements. These valueswere used to set the operating points of the write driver circuits and thebias point of the sense amp.
To allow debug of the CTCV module test setup in parallel with thewafer test effort, one wafer was selected and diced to remove the CTCVdie. Five die of one of the four chiplets, (chip 1) were sent ahead throughthe packaging process. Chip 1 has four different array configurations, two64 Kbit, single ended sense amp arrays and two 32 Kbit, differential senseamp arrays. Two of the arrays were constructed with the conservative celllayout and two with the aggressive cell layout. Functional test patternsused on these send-ahead devices included all zeros, all ones,checkerboard and checkerboard bar. The results of this testing showedthat all circuit functional blocks (control circuits, addressing, data I/O,write 0/1, and sense amp) performed as designed. All four of the arrayconfigurations present on the chip showed functional memory elements,
i.e., memory cells could be programmed to zero or one and subsequentlyread out. As more packaged parts become available, more exhaustive testpatterns will be employed for full characterization.
The five send-ahead devices were also used for determining theoptimum bias points of the three externally adjustable parameters: write 0
drives current, write 1 drive current, and the sense amp switching point.An Integrated Measurements Systems XTS-Blazer tester was used toprovide stimulus and measure response curves. A wide range of loadconditions was chosen based on the measurements performed at wafertest. A family of drive current vs. bias voltage curves was constructed forboth on-chip programming drive circuits across various values of RDYNAMIC.
These curves validate design simulations and demonstrate adequateoperating range of each of the circuits. Likewise, a family of switchingpoint curves was generated at various RSET and RRESET values using thestandalone sense amp built onto each die. These curves were used todetermine the optimal sense amp DC bias point for the test chips anddemonstrated the ability of the sense amp to distinguish the 0 and 1 state
within the range of chalcogenide resistance values measured at wafer test
About Chalcogenide alloy
Chalcogenide or phase change alloys is a ternary system of Gallium,Antimony and Tellurium. Chemically it is Ge2Sb2Te5.
Production Process: Powders for the phase change targets are produced bystate-of –the art alloying through melting of the raw material and subsequent
milling. This achieves the defined particle size distribution. Then powders areprocessed to discs through Hot Isotactic Pressing
• It makes no effect on measured CMOS transistor parametric.
• Endurance
• Read write performance
• Low programming energy
• Process simplicity
Write endurance is competitive with other potential non volatile memorytechnology, is superior to Flash. Read endurance is unlimited. The write/readperformance is comparable to DRAM. The OUM technology offers overwritecapability, and bit/byte data can be written randomly with no block eraserequired. Scaling is a key advantage of OUM.Write speed and writes energyboth scales with programmed volume. Its low voltage operation is compatible
with continued CMOS feature and power supply scaling. Low voltageoperation and short programming pulse widths yield low energy operation forthe OUM, a key metric for mobile portable applications.
CONCLUSION
Non volatile OUM with fast read and write speeds, highendurance, low voltage/low energy operation, ease of integration and
competitive cost structure is suitable for ultra high density ,stand aloneand embedded memory applications. These attributes make OUM anattractive alternative to flash memory technology and potentiallycompetitive with volatile memory technologies. Unlike conventional flashmemory Ovonic unified memory can be randomly addressed. OUM cell canbe written 10 trillion times when compared with conventional flashmemory. The computers using OUM would not be subjected to critical dataloss when the system hangs up or when power is abruptly lost as are
present day computers using DRAM a/o SRAM. OUM requires fewer stepsin an IC manufacturing process resulting in reduced cycle times, fewerdefects, and greater manufacturing flexibility. These properties essentiallymake OUM an ideal commercial memory. Current commercialtechnologies do not satisfy the density, radiation tolerance, or endurancerequirements for space applications. OUM technology offers great
potential for low power operation and radiation tolerance, which assuresits compatibility in space applications. OUM has direct applications in allproducts presently using solid state memory, including computers, cellphones, graphics-3D rendering, GPS, video conferencing, multi-media,Internet networking and interfacing, digital TV, telecom, PDA, digital voicerecorders, modems, DVD, networking (ATM), Ethernet, and pagers. OUMoffers a way to realize full system-on-a-chip capability through integratingunified memory, linear, and logic on the same silicon chip.
1. OUM – a 180 nm non volatile memory cell element technology for standalone and embedded applications – Stefan Lai and Tyler Lowrey
2. Current status of Phase change memory – Stefan Lai
3. Computer Organization – V Carl Hamacher, Zvonko G Vranesic, Safwat GZaky4. Computer Architecture and Organization - John P Hayes.5. Solid State Devices- Ben G Streetman,Sanjay Banerjee
6. www.intel.com7. www.ovonyx.com8. www.baesystems.com9. www.aero.org10.IEEE SPECTRUM, March 2003
