RF Linearity Potential of Carbon-Nanotube Transistors Versus MOSFETs

340 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 12, NO. 3, MAY 2013

RF Linearity Potential of Carbon-NanotubeTransistors Versus MOSFETs

Ahsan Ul Alam, Christopher Martin Sinclair Rogers, Navid Paydavosi, Kyle David Holland, Sabbir Ahmed,and Mani Vaidyanathan, Member, IEEE

Abstract—Carbon-nanotube, field-effect transistors (CNFETs)are among the candidates for emerging radio-frequency applica-tions, and improved linearity has recently been identified as oneof the performance advantages they might offer. In this paper, thepotential for improved linearity has been investigated by consider-ing an array-based device structure under the best-case scenario ofballistic transport. A nonlinear equivalent circuit for ballistic field-effect transistors is used to compare the linearity of CNFETs toconventional MOSFETs. We show that nanotube devices workingat high frequencies are not inherently linear, as recently suggestedin the literature, and that CNFETs exhibit overall linearity that iscomparable to their MOSFET counterparts. The nonlinear quan-tum capacitance is identified to be a major source of high-frequencynonlinearity in CNFETs. The impacts of device parameters suchas oxide capacitance, channel width, and tube pitch are alsoinvestigated.

Index Terms—Carbon nanotube (CN), field-effect transistor(FET), high-frequency behavior, input-intercept point (IIP3),linearity, small-signal circuit, top-of-the-barrier model, tubepitch.

I. INTRODUCTION

CARBON-NANOTUBE, field-effect transistors (CNFETs)are promising candidates for emerging radio-frequency1

(RF) electronics [1], and they have recently been predicted tooffer “inherent linearity” [2]. Linearity is an extremely desirableproperty for transistors operating at high frequencies, particu-larly for wireless communications [1]; for example, a small ad-vantage in linearity could simplify the design and implementa-tion of low-noise amplifiers used in wireless receivers and hence

Manuscript received June 11, 2012; accepted December 26, 2012. Date ofpublication February 20, 2013; date of current version May 6, 2013. This workwas supported in part by the Natural Sciences and Engineering Research Coun-cil of Canada, in part by the Queen Elizabeth II Graduate Scholarship, in part byAlberta Innovates, and in part by Alberta Advanced Education and Technology.The review of this paper was arranged by Associate Editor C. Zhou.

A. U. Alam, K. D. Holland, S. Ahmed, and M. Vaidyanathan are with theDepartment of Electrical and Computer Engineering, University of Alberta,Edmonton, AB T6G 2V4, Canada (e-mail: [email protected]).

C. M. S. Rogers was with the Department of Electrical and Computer Engi-neering, University of Alberta, Edmonton, AB T6G 2V4. He is now with theDepartment of Electrical Engineering, Stanford University, Stanford, CA 94305USA.

N. Paydavosi was with the Department of Electrical and Computer Engineer-ing, University of Alberta, Edmonton, AB T6G 2V4, Canada. He is now withthe BSIM Group, University of California, Berkeley, CA 94720 USA.

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TNANO.2013.22480191The terms “high-frequency” and “RF” are used interchangeably in this paper.

reduce the overall production cost. Given the potentially highvalues of unity-current-gain frequency fT [3], [4] and unity-power-gain frequency fmax [4], [5] attainable by CNFETs, theirpotential for linear behavior merits further investigation.

To date, the study of CNFET linearity has been limited.In 2007, Baumgardner et al. [2] analytically showed that thecurrent–voltage relationship of a ballistic CNFET can become“inherently linear” under certain conditions; while their ap-proach considered only the transport current as a source ofnonlinearity within the device, the claim of “inherent linearity”was nevertheless intriguing. In 2008, Curutchet et al. [6] mea-sured the nonlinear behavior of a CNFET at a fundamental fre-quency of 600 MHz and suggested a simple model to predict thethird-order intermodulation distortion. More recently, in 2011,Wang et al. [7] reported promising linearity figures of merit fora nanotube transistor working at 1 GHz. As far as we know, nofurther studies of the linearity of CNFETs have emerged, and amore comprehensive investigation is thus warranted.

When it comes to classifying CNFETs based on their opera-tion, there are mainly two types: the “MOSFET-like” [8]–[16]and the “zero-Schottky-barrier” [15]–[20] structures. From anexperimental viewpoint, the fabrication of the latter is easier;however, MOSFET-like structures have been predicted to out-perform their zero-Schottky-barrier counterparts in both dig-ital [21], [22] and RF [23], [24] applications. In addition, forpractical implementations, it is now well known that array-basedCNFETs (versus single tubes) must be used [1], [25]. This paperthus concentrates on the linearity of array-based, MOSFET-likeCNFETs.

The starting point of our analysis is to develop a simplifiedmodel for the nonlinear behavior of a ballistic single-tube CN-FET based on a “top-of-the-barrier” approach [26], [27]; theassumption of ballistic transport can be justified by the ongoingscaling of device size and by the aim of performing a best caseassessment. Despite being simple in nature, the model is shownto be capable of capturing the nonlinear voltage dependenciesof key device properties determined from a more detailed sim-ulator [28], such as the voltage dependencies of the drain cur-rent and fT . Once the intrinsic nonlinear components of thesingle-tube transistor are extracted, they are used to generatethe intrinsic components of an array-based CNFET. The exter-nal parasitics of the array-based structure are then calculatedwith the aid of COMSOL [29] and are appropriately added toget the complete extrinsic nonlinear model.

The harmonic balance (HB) simulator “Microwave Office(MWO)” [30] from AWR Corporation is used to simulate thedeveloped nonlinear model (equivalent circuit). The simulator

1536-125X/$31.00 © 2013 IEEE

ALAM et al.: RF LINEARITY POTENTIAL OF CARBON-NANOTUBE TRANSISTORS VERSUS MOSFETs 341

Fig. 1. Schematics of (a) array-based CNFET structure, (b) portion of the transistor consisting of a single tube that can be considered as a single-tube CNFET,and (c) conventional MOSFET counterpart. The figures are not drawn to scale.

is used to measure the third-order input-intercept point (IIP3)[31] for a two-tone input, a widely accepted linearity figureof merit. With this approach, the linearity of an array-basedCNFET is investigated for both typical and limiting structures,such as a structure in which the gate electrostatic capacitanceis much larger than the quantum capacitance, a scenario thatmight substantially enhance the device linearity, as predicted byBaumgardner et al. [2].

The main contribution of this paper is a comparative studyof the linearity of CNFETs versus their MOSFET counterparts.Our work reveals that CNFETs are unlikely to offer a major ad-vantage over conventional MOSFETs in terms of RF linearity,owing to the distortion arising from the nonlinear quantum ca-pacitance in CNFETs. We also examine the channel-width andtube-pitch dependency of CNFET linearity.

Section II presents the device structure and the developmentof the nonlinear equivalent circuit based on the top-of-the-barrierapproach. Section III compares the linearity of CNFETs withconventional CMOS transistors of similar specifications andalso probes the overall high-frequency linearity of array-basedCNFETs in terms of device parameters. The conclusions of ourstudy are summarized in Section IV.

II. APPROACH

A. Device Structure

Fig. 1(a) shows the structure of the top-gated, array-basedCNFET used in this paper, and Fig. 1(b) shows a portion of thetransistor consisting of a single tube that can be considered asa single-tube CNFET. The tubes in the structure are all zigzag(16, 0) carbon nanotubes with the following characteristics: adiameter of 1.25 nm; doped source and drain regions (outsidethe gate) that each have a background n-type doping level of109 m−1 and a length of 50 nm; and an undoped i region (un-derneath the gate) of length 20 nm. The gate (or channel) lengthof 20 nm was chosen purely for demonstration purposes; the

results will apply to any gate length for which the transport canbe considered ballistic or simply as a best-case assessment. Theplanar gate oxide has a thickness of 2 nm and a relative di-electric constant of 16 (i.e., hafnium oxide), and the gate metalhas a thickness of 50 nm and a work function of 4.5 eV (e.g.,chrome or tungsten). The tubes sit on a thick (100-nm) layer ofsilicon oxide, and the total channel width is taken to be 1 μmfor demonstration purposes.

Fig. 1(c) shows the conventional n-channel, Si MOSFET usedfor comparison. The gate/channel length is 20 nm and the oxidethickness is 3 nm with a relative dielectric constant of 16 (i.e.,hafnium oxide). The heavily doped source and drain regionshave a doping density of 1020 cm−3 . The body is considered tobe large enough to neglect the effect of the substrate for the sakeof simplicity.

The CNFET gate capacitance is matched to that of its MOS-FET counterpart by taking the number of tubes per μm to be 100,yielding a tube pitch of 10 nm. Existing literature shows that thisis the maximum achievable density for CNFET arrays withoutsignificant tube-to-tube screening [32]. It is worth mentioningthat a structure similar to that in Fig. 1(a) (but with a longerchannel length and wider tube pitch) has been experimentallydemonstrated [13].

B. Intrinsic Equivalent Circuit

In this paper, we focus on small-signal nonlinear operation,i.e., of interest is the nonlinear behavior of small signals super-imposed on dc bias values; we hence use Taylor-series expan-sions for all components in the small-signal equivalent circuit,where the coefficients of the series are specified by appropri-ate derivatives [evaluated at the bias (operating) point] of thecorresponding large-signal device equations. Fig. 2 shows thetopology of such a circuit for a single-tube CNFET, adaptedfrom a purely linear small-signal equivalent circuit [27] basedon the top-of-the-barrier model of Rahman et al. [26].


Fig. 2. Nonlinear equivalent circuit for a single-tube ballistic CNFET basedon the purely linear topology developed in [27].

The elements in Fig. 2 are as follows: Cge , Cse , and Cde arethe electrostatic capacitances of the CNFET and are presumedlinear, an assumption justified further below; Csq and Cdq are thenonlinear source and drain quantum capacitances, respectively;and its and itd are nonlinear sources that model the quasi-statictransport currents2 of the device. Based on the small-signalassumption and the relationships discussed in [26] and [27], thecharge–voltage or current–voltage behavior of each nonlinearelement is represented by a Taylor-series expansion up to thirdorder

qsq = Csq1 (vs − vscf ) + Csq2 (vs − vscf )2

+ Csq3 (vs − vscf )3 (1)

qdq = Cdq1 (vd − vscf ) + Cdq2 (vd − vscf )2

+ Cdq3 (vd − vscf )3 (2)

its = gsq1 (vs − vscf ) + gsq2 (vs − vscf )2

+ gsq3 (vs − vscf )3 (3)

itd = gdq1 (vd − vscf ) + gdq2 (vd − vscf )2

+ gdq3 (vd − vscf )3 (4)

where qsq and qdq are the small-signal charges held by thequantum capacitances Csq and Cdq , respectively, vs and vd arethe small-signal source and drain voltages, respectively, and vscfis the small-signal channel potential.

To extract the values of the coefficients in (1)–(4), the large-signal top-of-the-barrier equations in [26] and [27] were firstsolved and fitted to the output of the more detailed BTE-Poissonsolver reported in [28]; with the method provided in [26], the

2In this paper, we use the following convention: small-signal voltages andcurrents are denoted by lowercase letters with lowercase subscripts whereastotal (large-signal) voltages and currents are denoted by lowercase letters withuppercase subscripts. For convenience, bias (dc) voltages and currents, whichare equal to the large-signal values at the operating point, are referenced by thesame notation as the large-signal quantities, with the meaning clear from thecontext.

Fig. 3. (a) Family of current versus bias voltage curves and (b) unity-current-gain frequency fT versus gate bias for a 20-nm single-tube CNFET. The solidlines represent the values from the top-of-the-barrier approach [26], [27] andthe black dots represent data from the BTE-Poisson solver reported in [27].

values of the relevant fitting parameters from this process wereEF = −0.25 eV, Cge/Ce = 0.87, and Cde/Ce = 0.01, whereCe ≡ Cge + Cse + Cde is the total electrostatic capacitance.Fig. 3(a) and (b) shows the resulting agreement between thelarge-signal equations and the numerical solver [28]. With thisagreement established, the coefficients in (1)–(4) could easily beobtained from the large-signal equations at any operating pointof interest. The agreement in Fig. 3(a) shows that the nonlinearcurrent–voltage behavior will be properly modeled by this pro-cedure. Similarly, the agreement in Fig. 3(b), while more crude,shows that the overall nonlinear charge–voltage behavior of thedevice will be properly modeled [33] to an extent sufficient forthe purposes of this paper, i.e., for a preliminary linearity assess-ment; it also shows that the agreement can be obtained underthe assumption of linear electrostatic capacitances.

C. Extrinsic Equivalent Circuit

1) Array-Based Structure: To model the behavior of anarray-based structure (as opposed to a single tube), we assumeall the individual single-tube CNFETs of an array have identicalbias points; this can be justified by the negligible dc voltage


Fig. 4. Cross section of the array-based CNFET structure used in this paper.

drop on the metal gate (since the dc gate current is zero) and bythe assumption that the source and drain biases are applied toall the tubes from the sides [from the left and right in Fig. 1(a)].Since the tubes of an array are hence essentially in parallel, theintrinsic equivalent circuit for an n-tube array can be obtainedsimply by multiplying the power-series coefficients for each ofthe elements in Fig. 2 by n.

2) Parasitics: In practical CNFETs, the extrinsic (parasitic)circuit elements due to the metallic contacts are the main reasonfor the degradation of the cutoff frequencies (fT and fmax) fromthe theoretically predicted values. The impact of these parasiticson the linearity should also be assessed. Fig. 4 shows a cross sec-tion of an array-based structure with the extrinsic capacitancesmarked, along with the dimensions of the gate and source/drainregions. The dashed portion of the figure (excluding the labeledextrinsic capacitances) can be modeled by the circuit of Fig. 2with the element values multiplied by n, as already discussed.To such a circuit, we then add the labeled extrinsic capacitances,along with the contact resistances Rg ,eff , Rs , and Rd of the gate,drain, and source, respectively; all these parasitics were foundas described in [4] with the aid of COMSOL [29] and by usingthe contact dimensions specified below in Section III-C. Thefinal circuit is shown in Fig. 5, where vs, vd , and vg are the in-ternal node voltages on the CNTs of an array and vs,ext , vd,ext ,and vg ,ext represent the external terminal voltages of the overalldevice. Table I in Section III-C lists all the component values(both intrinsic and extrinsic) for the device.

III. RESULTS AND DISCUSSION

A. Condition for “Inherent Linearity”

In order to investigate the potential for “inherent linearity” inCNFETs, we need to establish the condition under which thelarge-signal transport current iT ≡ iTS + iTD becomes a linearfunction of the gate voltage vG , where iTS and iTD refer to thesource- and drain-injected components of the current, respec-tively, and where the source is taken as the reference (vS ≡ 0 V).As shown in the Appendix, under the assumption of a high drainvoltage, where iT ≈ iTS , the condition of Baumgardner et al. [2]for inherent linearity is equivalent to requiring that the ratio of

Fig. 5. Complete nonlinear small-signal equivalent circuit for an array-basedCNFET.

channel charge to gate-oxide capacitance be much smaller thanthe gate voltage:

∣∣∣∣

λ

Cge

∣∣∣∣� vG (5)

where λ represents the channel charge. Based on condition (5),a MOSFET-like CNFET might hold promise for highly linearbehavior, since the 1-D density of states of a nanotube willtend to keep the channel charge λ small for a given vG , whilethe use of high-k dielectrics can result in a large gate-oxidecapacitance Cge . However, (5) is derived while considering onlythe nonlinearity due to the transport current iT ≈ iTS , i.e., itneglects distortion arising from the quantum capacitances Csqand Cdq ; this is equivalent to retaining the nonlinear small-signalcurrent source its in Fig. 2 (with itd ≈ 0), while neglecting alldistortion due to Csq and Cdq . Hence, the overall nonlinearityof CNFETs, even if (5) is well satisfied, remains unclear, and itmust be tested and compared to other devices.

B. CNFET Versus CMOS Transistor

1) Basis and Method for Comparison: In order to determinewhether a CNFET offers any advantage over its conventionalMOSFET counterpart in terms of RF linearity, we also investi-gate the linearity of the MOSFET shown in Fig. 1(c) using thesame top-of-the-barrier [26], [27] approach used for the CN-FET. Besides having identical gate capacitances, the MOSFETis also assumed to have identical dimensions to the CNFET,including the channel length and width, and the size and orien-tation of the gate, source, and drain contacts. The barrier heightat the top-of-the-barrier under equilibrium is kept identical tothe CNFET at 0.25 eV.

MWO was used to simulate the nonlinear circuits of the CN-FET and MOSFET using the HB technique; the circuit in Fig. 2was used for both devices, with the component values replaced


Fig. 6. Intrinsic IIP3 versus gate bias for a 20-nm ballistic array-based CNFETand ballistic MOSFET, considering only nonlinear transport current.

by total values in the case of the MOSFET and single-tubevalues multiplied by the number of tubes n in the case of theCNFET. The load impedance was set to 50 Ω, the usual charac-teristic impedance for RF applications. A two-tone source withan impedance of 50 Ω and an operating frequency of 24 GHz—which is an application frequency of interest as identified bythe 2011 ITRS [34]—and a difference of 100 kHz between thetones were used. The source was grounded, the drain bias vD

was fixed at 0.8 V, and the gate bias vG was varied from 0.2 to1.0 V.

2) Nonlinearity Due Only to Transport Current: To investi-gate the effect of the nonlinear transport current, both transistorswere simulated with the nonlinear current sources its and itd inFig. 2 fully active but with linearized quantum capacitances Csqand Cdq , i.e., with all the coefficients in (3) and (4) retained butwith the higher order coefficients in (1) and (2) set to zero. TheIIP3 at different gate biases is shown in Fig. 6.

The basic shape of the IIP3 versus gate bias is comparable forthe two devices, including the presence of an IIP3 sweet-spot inthe low-bias region and an improvement in IIP3 with increasingbias; more importantly, as shown, with only the transport-currentnonlinearity, the CNFET has a significantly higher IIP3 at highbias.

The reason for the better linearity of the CNFET at high biasin Fig. 6 can be discerned from the curves in Fig. 7, where it isshown that the CNFET has a significantly lower channel chargeat high gate bias (vG ≥ 0.5 V), causing (5) to be better satisfied.To examine this outcome in greater detail, we first compare thebias dependence of the self-consistent channel potential of thetwo devices, and then use the result of that comparison to showhow the difference in the densities of states in the two materialsresults in the variation in channel charge depicted in Fig. 7 andhence in the linearity according to (5).

a) Bias dependence of self-consistent channel potential:Fig. 8(a) shows the result for the self-consistent channel poten-tial vSCF as a function of the gate bias voltage vG ; as shown, thevalues of vSCF at each vG are approximately equal in the twodevices. To understand this result, which is not entirely obvious,

Fig. 7. Channel charge (electron) density of the 20-nm ballistic array-basedCNFET and ballistic MOSFET.

we first note that for typical structures and for sufficiently largedrain bias, the large-signal input equivalent circuit looking intothe gate consists primarily of the series combination of Cge andCsq , with the latter being a nonlinear function of the voltagev across it. The stored charge on each of these two capacitorsmust be equal and represents the channel charge λ:

Cge × (vG − vSCF) = λ =

vS C F∫

0

Csq (v) dv (6)

where Csq is written as Csq(v) to emphasize its dependence onv. By differentiating both sides of (6) with respect to vSCF andrearranging the result, we can find an expression for the rate ofchange of vSCF with respect to vG :

dvSCF

dvG=

Cge

[Cge + Csq(vSCF)]. (7)

Fig. 8(b) shows Csq and Cge versus gate bias for both theCNFET and the MOSFET. As shown, Cge is the same constantvalue in the two devices. On the other hand, the behavior ofCsq depends on the density of states; once the gate bias is highenough (above 0.2 V for the devices considered in this paper)to push the top of the barrier down to the source Fermi level,a plot of Csq versus gate bias will closely follow the shape ofthe density of states versus energy. For the CNFET (governedby a 1-D density of states), we can thus expect Csq to riseto a peak and then rapidly diminish, while for the MOSFET(governed by a 2-D density of states), we can expect Csq to riseto a constant value. This behavior is indeed present in Fig. 8(b),but appreciable differences in the resulting values of Csq areobservable only for gate biases beyond ∼0.35 V. According to(7), vSCF will thus rise with vG in a similar fashion in the twodevices at least until vG ∼0.35 V; beyond this point, first-orderdifferences in the slopes of the vSCF versus vG curves do occur,consistent with (7), but they are insufficient to create appreciabledifferences in the values of vSCF at each vG .

b) Effect of density of states on channel charge: Theself-consistent potential vSCF determines the position of theconduction-band edge at the top of the barrier with respect tothe source Fermi level [35], and since we have established that


Fig. 8. (a) Self-consistent channel potential and (b) electrostatic and quantumcapacitances (Cge and Csq ) versus gate bias for a 20-nm ballistic array-basedCNFET and ballistic MOSFET.

vSCF is approximately the same at each vG in the two devices,the band edges will be aligned. The reason for lower charge inthe CNFET at high bias then readily follows from Fig. 9, wherethe density of states for the two devices is plotted for vG = 0.8V,along with the source Fermi function; in the figures, the sourceFermi level is at 0, and the conduction-band edges are just be-low –0.25 eV. The charge is given by the area under the productof the Fermi function and the density of states, as shown bythe shaded regions in Fig. 9. The diminishing density of statesabove the band edge in the CNFET [Fig. 9(a)] causes the area(charge) to be much lower than that in the MOSFET [Fig. 9(b)],which has a constant density of states above the band edge.

Thus, despite being equivalent in all other aspects (e.g., gateelectrostatic capacitance, dimensions, equilibrium source–drainbarrier height, and applied bias), the lower density of states inthe CNFET ultimately causes it to have less channel charge athigh gate bias, leading to (5) being better satisfied, and henceleading to better linearity. However, this discussion assumesthat the transport current is the only source of nonlinearity inthe device.

3) Overall Nonlinearity: So far, we have considered thenonlinearity due only to the transport current. The quantum

Fig. 9. Density of states at the top of the barrier and the source Fermi functionversus energy, plotted for gate and drain bias voltages both equal to 0.8 V, atroom temperature (300 K) for a 20-nm (a) ballistic array-based CNFET and (b)ballistic MOSFET. The source Fermi level is taken as the reference (set to 0) andthe conduction-band edge EC , which is common for the two devices, is marked.The shaded region indicates the overlap of the Fermi function with the densityof states and its area indicates the approximate amount of charge in the channel.

capacitance is another major source of nonlinearity in thesedevices that must be considered.

Fig. 10 shows the overall IIP3 of the two devices, i.e., itshows the IIP3 found from MWO with all the coefficients in(1)–(4) retained. Most interestingly, with the inclusion of allthe nonlinear elements, the linearity of the CNFET at high gatebias substantially degrades, and it becomes comparable to (oreven worse than) that of the MOSFET. The reason behind thislinearity degradation is the nonlinear behavior of the quantumcapacitance Csq . In the CNFET, the same 1-D density of statesthat causes (5) to be well-satisfied (as discussed in conjunc-tion with Fig. 9) also yields a smaller and highly nonlinearCsq in comparison to that of the MOSFET. Fig. 11 shows thequantum capacitances in the two devices as a function of theself-consistent channel potential vSCF ; the figure is very similarto Fig. 8(b), owing to the essentially linear dependence of vSCFon vG [Fig. 8(a)]. By definition, the value of capacitance Csq ateach point on the curve is the first coefficient Csq1 in the expres-sion of the nonlinear small-signal charge qsq in (1). The second


Fig. 10. Intrinsic IIP3 versus gate bias for a 20-nm ballistic array-based CN-FET and ballistic MOSFET.

Fig. 11. Quantum capacitance Csq versus self-consistent channel potentialfor a 20-nm ballistic array-based CNFET and ballistic MOSFET.

and third coefficients, Csq2 and Csq3 , respectively, are thereforethe first and second derivatives of the curves in Fig. 11. At highbias (vG ≥ 0.5 V, i.e., vSCF ≥ 0.35 V), the highly nonlinearcurve for the CNFET results in pronounced values for Csq2 andCsq3 , and hence a highly nonlinear qsq in (1), leading to substan-tial linearity degradation. On the other hand, the constant valueof Csq in the MOSFET at high bias, which is a direct outcomeof the constant 2-D density of states for the MOSFET, results inessentially zero values for Csq2 and Csq3 , reducing (1) for qsqinto an essentially linear equation; in fact, the overall IIP3 ofthe MOSFET in Fig. 10 is not very different from the IIP3 dueonly to the transport current in Fig. 6.

Based on our study, a key difference between the sources ofnonlinearity in a ballistic MOSFET and CNFET can be iden-tified. We have summarized the results in Fig. 12(a) and (b),which show the overall IIP3 of each device along with theIIP3 found by selectively excluding either the transport-currentor quantum-capacitance nonlinearities. Fig. 12(a) shows thatthe nonlinearity of the MOSFET remains relatively unaffectedwhen the nonlinearity of the quantum capacitance is neglected,

Fig. 12. Intrinsic IIP3 versus gate bias for (a) 20-nm ballistic MOSFET and (b)20-nm ballistic array-based CNFET, with the different sources of nonlinearityselectively included.

indicating that the transport current is the major source of non-linearity in a MOSFET. On the other hand, Fig. 12(b) showsthat the nonlinearity of the CNFET at high bias remains unaf-fected if the nonlinearity of the transport current is neglected,indicating that the nonlinear quantum capacitance is a majorsource of nonlinearity in a CNFET.

C. Linearity of Array-Based CNFETs

In this section, we focus on the extrinsic linearity of CN-FETs, i.e., the linearity found including the effects of the deviceparasitics. We examine the impact of various parameters of anarray-based structure, including device width, gate oxide, andtube pitch, with the aim of understanding their potential in en-hancing device linearity.

1) Calculation of Parasitics: To calculate the extrinsic par-asitics, the gate metal is assumed to be made out of tungstenwith dimensions W × Lg × tg of 1 μm × 20 nm × 50 nm; the4.24–5.3 eV [36] work function of tungsten is comparable to thatof an intrinsic nanotube [37]. Based on the existing literatureon resistivity of RF sputtered tungsten thin films [38], the total


TABLE IINTRINSIC AND EXTRINSIC CIRCUIT COMPONENTS OF THE

ARRAY-BASED CNFET

film resistance Rg of the gate metal is calculated to be 200 Ωat 24 GHz; the distributed gate resistance can then be mod-eled as a lumped resistance Rg ,eff = Rg/3. The source/draincontacts are assumed to be made of yttrium with dimensionsW × Ls/d × ts/d of 1 μm × 20 nm × 20 nm. Yttrium has beenexperimentally used to form an ohmic contact with the conduc-tion band of a nanotube [39]. Based on the resistivity of yttriumthin films in [40], the total film resistances Rs and Rd for thesource and drain contacts are calculated to be 1.77 Ω.

Simulating the open-pad structure in COMSOL, the parasiticcapacitances are calculated to be Cgs,ext = 20.7 aF, Cgd,ext =20.8 aF, and Csd,ext = 4.99 aF. Table I lists the intrinsic andextrinsic component values of the 100-tube, 1-μm wide CNFETstudied in this paper; the bias-dependent values are shown forgate and drain voltages both equal to 0.8 V.

2) Effect of Gate Oxide: Although the discussion inSection II-B clearly indicates that it is the nonlinear quantumcapacitance that limits CNFET linearity, it is nevertheless inter-esting to test the outcome of satisfying condition (5) in a realisticextrinsic structure, which should at least linearize the transportcurrent.

To do so, we consider an extrinsic array-based structure withthe gate oxide changed from hafnium oxide to a fictitious ox-ide that has a tenfold increase in relative permittivity. This in-crease in the relative permittivity will aid in achieving the de-rived condition for “inherent linearity” in (5) by increasing Cge .Fig. 13 shows the linearity figures of merit for both the original(εr = 16) and new (εr = 160) transistors, obtained from MWOand the full extrinsic circuit of Fig. 5.

The results in Fig. 13 are best understood by consideringthe three bias regions delineated in the figure and focusing onthe solid (εr = 16) and dashed (εr = 160, first subband only)curves, leaving aside the dotted and stippled curves for the mo-ment. The following observations can be made.

1) In the central-bias region (0.4V ≤ vG ≤ 0.8V), the CN-FET does become more linear, and this is a result ofcondition (5) being better satisfied in the presence of alarger oxide capacitance, as illustrated by the curves inFig. 14(a). However, in the low-bias (vG ≤ 0.4V) andhigh-bias (vG ≥ 0.8V) regions, the linearity degrades.

Fig. 13. Extrinsic IIP3 versus gate bias for a 20-nm ballistic array-basedCNFET with different gate oxides.

Fig. 14. (a) Ratio |λ/Cge | related to condition (5) for “inherent linearity”and (b) plot of source quantum capacitance Csq versus gate bias for a 20-nmballistic array-based CNFET with different gate-oxide values. The inset in (b)shows the drain quantum capacitance Cdq versus gate bias.


2) The degradation at low bias can be explained by the be-havior of the source quantum capacitance Csq , which isalso the first coefficient in the expression of qsq in (1) andwhich is plotted in Fig. 14(b) versus gate bias. In bothcases (εr = 16 and εr = 160), the curves in Fig. 14(b)rise sharply and then gradually fall as the gate bias is in-creased, which is consistent with the shape of the 1-Ddensity of states of the nanotube. However, in the caseof the larger εr , an applied gate bias has a superior con-trol over the channel potential, i.e., the conduction-bandedge is more easily pushed down by the gate bias, causingthe Csq curve for the CNFET to have a squeezed shape(narrower peak) as the conduction-band states get filledfaster. The squeezed shape makes the curve more nonlin-ear, leading to substantial linearity degradation at low bias(vG ≤ 0.4V).

3) The degradation at large gate bias (vG ≥ 0.8V) can be ex-plained by the influence of the drain quantum capacitance.In this case, when εr is large, the applied gate bias can pushthe conduction band in the channel low enough to causea significant amount of drain-injected electrons to enterthe channel. As a result, the drain quantum capacitanceCdq acts as a second source of capacitive nonlinearity inthe device (over and above Csq ), reducing the IIP3. Theeffect is pronounced only at sufficiently large gate bias(vG ≥ 0.8V), where Cdq becomes appreciable, as shownin the inset in Fig. 14(b); the corresponding impact on theIIP3 is emphasized by the dotted curve in Fig. 13, wherewe have plotted the IIP3 at high bias in the presence of alinearized Cdq .

Overall, the results in Fig. 13 demonstrate that an increase ingate-oxide capacitance Cge does have the potential to improvelinearity, subject to the caveat of degradations at low and highbias arising from the impacts of the quantum capacitances, Csqand Cdq .

3) Impact of the Second Subband: So far in our simulations,we have neglected the second subband because it does not comeinto play for the CNFET structure considered in this paper, i.e.,with HfO2 as the gate oxide (εr = 16), until very high gate bias(vG > 1.0V). However, it should be noted that for the case ofthe very large εr just discussed, the second subband does comeinto play much earlier and needs to be considered in order tocapture the overall linearity of the CNFET. The stippled curvein Fig. 13 shows that when the second subband is taken intoaccount, the IIP3 of the CNFET with higher gate capacitance(εr = 160) goes below the IIP3 of the CNFET with hafniumoxide (εr = 16) for gate biases in excess of 0.5 V. This behaviorcan be explained by the plots of the source quantum capacitanceCsq and the transconductance gsq1 given in (3), as shown in thetwo parts of Fig. 15; as illustrated, when the second subbandbegins to get filled, Csq and the gsq1 become highly nonlinear,and this can cause the overall nonlinearity to be worse witha high oxide capacitance. The potential impact of the secondsubband should be kept in mind if an increase in Cge is used inan attempt to improve the linearity according to (5).

4) Effect of Tube Pitch and Channel Width: So far in thispaper, we have assumed a channel width of 1 μm and a tube

Fig. 15. (a) Source quantum capacitance Csq and (b) transconductance gsq1versus gate bias for an array-based CNFET with large gate electrostatic capaci-tance Cge .

pitch of 10 nm. Generally, a low tube pitch is preferred in array-based structures, since it has been reported to offer multiplebenefits, ranging from improved cutoff frequencies to a largerdrive current and better impedance matching for the overallCNFET [1], [41]. It is hence important to assess the impact oftube pitch on the RF linearity.

Fig. 16(a) shows the IIP3 versus gate bias for three 1-μmwide array-based CNFETs with varying tube pitch. It is evidentfrom the plots that the linearity of the device is almost insensi-tive to the tube pitch. However, for devices with wider channels(above 30 μm), where the extrinsic components are more pro-nounced than in the 1-μm wide device, the linearity improvesconsiderably with a reduction in the tube pitch [see Fig. 16(b)].This improvement can be attributed to the linearizing feedback[42, p. 101] provided by the extrinsic circuit components, aneffect that becomes more pronounced as the number of tubesincreases (i.e., as the pitch decreases) and as the drive cur-rent through the extrinsic components thus increases; we foundthe extrinsic components Rg ,eff and Cgd,ext to be primarily


Fig. 16. Extrinsic IIP3 versus gate bias of (a) 1-μm-wide and (b) 30-μm-widearray-based CNFETs for different tube pitches.

responsible for the improvement. A low tube pitch, which hasalready been flagged in the literature [1], [41] as being impor-tant for a variety of device metrics, can thus also be flaggedas aiding device linearity (when the device width is sufficientlylarge). It is worth mentioning that although we would expectsimilar behavior in a MOSFET with respect to channel width(i.e., better linearity arising from the larger extrinsic parasiticsof a wider device), the linearity enhancement due to tube pitchis unique to the CNFET.

IV. CONCLUSION

The following conclusions can be drawn regarding the lin-earity potential of an array-based CNFET [Fig. 1(a)] versus itsMOSFET counterpart [Fig. 1(c)].

1) Under the assumption of ballistic transport, the linearity ofan array-based CNFET is comparable to that of its MOS-FET counterpart (having similar dimensions and electro-static capacitances), as shown by the results in Fig. 10.

2) The highly nonlinear quantum capacitance is the mainsource of nonlinearity in a CNFET, whereas the transportnonlinearity dominates the linearity of its conventionalMOSFET counterpart (Fig. 12).

3) The array-based CNFET does not become “inherently lin-ear” even under extreme situations, such as the case of ahuge oxide capacitance [2], as shown in Fig. 13; exten-uating factors include the impact of the source and drainquantum capacitances and the impact of the second sub-band.

4) The tube pitch of the array-based CNFET does not affectthe linearity for narrow devices (W � 30 μm), as shownin Fig. 16(a). However, for wider devices (W ≥ 30 μm),the CNFET linearity increases as the tube pitch is de-creased [Fig. 16(b)]. This is a rather favorable observationsince it implies that lowering the tube pitch to increase thedrive current and improve the cutoff frequency will alsoimprove the linearity.

While CNFETs may not be “inherently linear,” they shouldoffer at least comparable linearity to their MOSFET counter-parts. Given the already reported potential for superior fT andfmax of array-based CNFETs, they hence continue to be promis-ing candidates for RF applications.

APPENDIX

DERIVATION OF CONDITION FOR “INHERENT LINEARITY”

The condition for inherent linearity was first derived byBaumgardner et al. in [2]. Here, we outline the derivation tobe consistent with our top-of-the-barrier [26], [27] equationsand for the convenience of the readers.

Under the assumption of a sufficiently high drain bias to ne-glect the drain-injected charge at the top of the source–drainbarrier, the transport equations for the channel charge and cur-rent can be written as follows [26], [27]:

λ = −q

2

∞∫

EC , e q

D (E) f [E − qvSCF − EF + qvS ] dE (8)

and

iT ≈ iTS =4q

h

∞∫

EC , e q

f [E − qvSCF − EF + qvS ] dE (9)

where EC ,eq is the equilibrium position of the conduction bandand vSCF is defined to be zero at equilibrium. In addition,neglecting the capacitances Cse and Cde for simplicity, theelectrostatics demands the following relation for the channelcharge [26], [27]:

λ = −Cge (vG − vSCF) . (10)

Equating (8) and (10), and setting vS to zero, we get

− Cge (vG − vSCF)

= −q

2

∫ ∞

EC , e q

D (E) f [E − qvSCF − EF ] dE. (11)


Solving (11) for vSCF then results in

vSCF = vG +− q

2

∫ ∞EC , e q

D (E) f [E − qvSCF − EF ] dE

Cge

≡ vG +λ

Cge. (12)

For the case∣∣∣

λCg e

∣∣∣ � vG , the right side of (12) collapses to

vG , and the channel potential follows the gate bias directly,i.e., vSCF ≈ vG . Using this solution for vSCF with vS ≡ 0, thetransport current can then be rewritten from (9) as

iT =4q

h

∞∫

EC , e q

f [E − qvG − EF ] dE

= kB T4q

hln

[

1 + eq (v G −v T )

k B T

]

(13)

where qvT = EC ,eq − EF is the height of the source–drain bar-rier at equilibrium. The value of qvT is typically small for nan-otubes; for example, for the CNFET considered in our study,qvT = 0.25 eV.

Once q(vG −vT )kB T 1, the right side of (13) becomes the loga-

rithm of an exponent, and the transport current becomes “inher-ently linear” with vG :

iT =4q2

h(vG − vT ) . (14)

ACKNOWLEDGMENT

The authors would like to thank AWR Corporation, El Se-gundo, CA, for providing Microwave Office and technicalsupport.

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[41] C. Kocabas, J. K. Seong, T. Ozel, M. Shim, and J. A. Rogers, “Improvedsynthesis of aligned arrays of single-walled carbon nanotubes and theirimplementation in thin film type transistors,” J. Phys. Chem. C, vol. 111,pp. 17879–17886, Dec. 2007.

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Ahsan Ul Alam received the B.Sc. and M.Sc. de-grees in electrical and electronic engineering fromthe Bangladesh University of Engineering and Tech-nology (BUET), Dhaka, Bangladesh, in 2005 and2007, respectively. He is currently on study leavefrom BUET and working toward the Ph.D. degree atthe University of Alberta, Edmonton, AB, Canada.

From 2005 to 2008, he was a Lecturer at BUET,teaching courses and performing research in the areaof semiconductor devices. His research interests in-clude the theory and modeling of semiconductor de-

vices, where he has worked on topics ranging from the study of spin transport incarbon-based devices to the modeling of high-frequency distortion for wirelessapplications.

Mr. Alam received the Kintar-ul Huq Lashkar Gold Medal from BUET forsecuring the top position in his undergraduate studies. He also received the F.S. Chia Ph.D. Scholarship in the first two years and the Queen Elizabeth IIGraduate Scholarship in the third, fourth, and fifth years of his Ph.D. studies atthe University of Alberta.

Christopher Martin Sinclair Rogers received theB.Sc. degree in engineering physics (nanoengineer-ing option) from the University of Alberta, Edmon-ton, AB, Canada, in 2012. Since fall 2012, he has beenworking toward the Ph.D. degree in electrical engi-neering at Stanford University, Stanford, CA, USA.

His current research interests include the physicsand modeling of nanoscale electronic devices, withan emphasis on radio-frequency characteristics and2-D materials.

Mr. Rogers received NSERC Undergraduate Stu-dent Research Awards at the University of Alberta during the summers of 2011and 2012. During his B.Sc. degree, he received a President’s Citation from theUniversity of Alberta. He also received a Governor General’s Silver Medal andThe Rt. Hon. C.D. Howe Memorial Fellowship.

Navid Paydavosi received the B.A.Sc. degree in elec-trical engineering from Shahid Beheshti University,Tehran, Iran, in 2005, and the Ph.D. degree in electri-cal engineering from the University of Alberta, Ed-monton, AB, Canada, in 2011.

He is currently a Postdoctoral Scholar in theBSIM Group, University of California, Berkeley,USA. His research interests include the theory andmodeling of future alternatives to ordinary silicontransistors, including carbon-based and III–V high-electron-mobility devices, with an emphasis on the

high-frequency characteristics relevant for RF applications, such as the extrin-sic cutoff frequency, the attainable power gain, the unity-power-gain frequency,and linearity.

Dr. Paydavosi received the Queen Elizabeth II Graduate Scholarship forSeptember 2009 and January 2010, and two Tuition Supplement Awards inSeptember 2006 and April 2007 from the University of Alberta.

Kyle David Holland received the B.Sc. degree inengineering physics (nanoengineering option) fromthe University of Alberta, Edmonton, AB, Canada, in2009, where he is currently working toward the Ph.D.degree in electrical engineering.

His research interests include the quantum simu-lation of carbon-based nanoelectronics, with an em-phasis on modeling the high-frequency performanceof graphene devices.

Mr. Holland currently holds the NSERC Alexan-der Graham Bell Canada Graduate Scholarship and

the Alberta Innovates Graduate Student Scholarship, and he also received theRalph Steinhauer Award of Distinction.

Sabbir Ahmed received the B.Sc. and M.Sc. degreesin electrical and electronic engineering (EEE) fromthe Bangladesh University of Engineering and Tech-nology (BUET), Dhaka, Bangladesh, in 2005 and2007, respectively. Since 2008, he has been workingtoward the Ph.D. degree at the University of Alberta,Edmonton, AB, Canada, and is currently on leavefrom BUET.

He was a Lecturer in the Department of EEE,BUET from 2005 to 2008. His research interestsinclude the theory, modeling, and simulation of

nanoscale electronic devices, with an emphasis on the high-frequency andcircuit-level performance of III–V high-electron-mobility transistors, carbon-based transistors and solar-cell devices.

Mr. Ahmed received the F. S. Chia Doctoral Scholarship in 2008 and 2009,and the Queen Elizabeth II Graduate Scholarship in 2010, 2011, and 2012 at theUniversity of Alberta.

Mani Vaidyanathan (M’99) received the Ph.D. degree in electrical engineeringfrom the University of British Columbia, Vancouver, BC, Canada, in 1999.

He is currently an Associate Professor in the Department of Electrical andComputer Engineering, University of Alberta, Edmonton, AB, Canada. Hisresearch interests include the modeling, simulation, and understanding of elec-tronic devices for future technologies.

Dr. Vaidyanathan received the University of Alberta’s Provost’s Award andthe University of Alberta’s Alexander Rutherford Award, both for excellence inteaching.

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RF Linearity Potential of Carbon-Nanotube Transistors Versus MOSFETs

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