Micro-RDCMicroelectronics Research Development Corporation

RHBD Standard Cell Library Approach

Presented byDavid G. MavisPaul H. Eaton

Microelectronics Research Development Corporation

8102 Menaul Blvd. NE, Suite BAlbuquerque NM 87110

505-294-1962

4775 Centennial Blvd. Suite 130Colorado Springs CO 80919

719-531-0805

2

Key Technical Personnel – Design Hardening Dave Mavis – Chief Scientist Micro-RDC

B.S. Physics, University of Wisconsin Ph.D. Nuclear Physics, Stanford University Post Doctoral Fellow, Stanford University; Faculty, University of

Wisconsin; Ion Source Design Consultant, Sentec, GenevaSwitzerland; MRI Consultant, USFRIL, South San Francisco, CA;Technical Staff, Mission Research, Albuquerque, NM

Founder Micro-RDC

Relevant Experience Assisted numerous vendors (BAE, Honeywell, TI, Boeing, & others) to

harden, characterize, and model product offerings Led commercial and Government contract efforts in device physics

modeling; SEE circuit analyses; device parameter extraction; thermalmanagement; CAD tool development; RHBD cell library, SRAM, FPGA,and Structured ASIC design; novel test method and data reductiontechnique development

3

Key Technical Personnel – Radiation Testing Paul Eaton – Chief Engineer Micro-RDC

B.S. Texas Tech University M.S. Texas Tech University Technical Staff, Sandia National Laboratory, Albuquerque; Technical

Staff, Mission Research, Albuquerque, NM Founder Micro-RDC

Recent Activities Key role in SEE circuit analyses; structured ASIC qualification vehicle

design; various circuit verifications and characterizations Led commercial and Government contract efforts in DSET

characterization circuit design, simulation, layout, packaging, andtesting; FPGA-based generic test board design; heavy-ion dataacquisition and data analysis software development

4

Several Key Library Considerations TID

Not expected to be a factor for 300 kRad(Si) requirement

SEL Should not be an issue, especially if fabricated on epi

SEU Latches and SRAM require circuit mitigation techniques

DSET Transient filtering needed in data, clock, and control

Library timing characterization Need, especially for DSET, realistic SPICE current sources

5

RHBD Library Development Approach Baseline the fabrication process

Determine TID and SEL hardness levels through test (and SEU/DSET towhatever extent possible) with existing structures and circuits

Audit library layout for potential problems (e.g. well/substrate contacts)

Fabricate/test radiation environment specific characterization chip Appropriate circuits for characterizing SEU baseline error rates without

mitigation (e.g. with redundancy and/or EDAC) Appropriate circuits for quantifying DSET pulse width distributions in

the combinatorial logic (to establish required filtering delays) Appropriate structures for determining required critical node spacing

(primarily to bound EDAC scrubbing rates)

Finish using conventional library development procedures Modify old layouts and generate new layouts as required Generate the various library views, with only timing impacted by RHBD Final heavy-ion testing, Milli-Beam to supplement broad-beam

6

Presentation Overview Quick description of our Equivalent Collection Model (ECM)

Described fully in our 2007 IRPS invited presentation Presently only available at Micro-RDC

Circuit redundancy issues for latch and SRAM designs Latch critical node and SRAM bit separations are key Much learned from our DARPA RHBD design & characterization efforts Area must be traded for hardness

DSET transient filtering Newly discovered pitfalls need to be addressed The "Temporal Filtering Latch" surmounts several intractable problems

recently encountered with DICE-based and TMR-based latch designs(as described in our 2002 IRPS invited presentation)

Speed must be traded for hardness irrespective of which filteringapproach is taken

7

Realistic DSET Modeling in SPICE Transient widths were much larger than previously thought Current source waveforms could not account for the data Circuit response was missing from the simulation model

LET (MeV-cm 2/mg)0 10 20 30 40 50 60 70 80

T

(ps)

0

500

1000

1500

2000

2500

180 nm Bulk CMOS Experimental Data(Eaton et.al.)

SPICEDouble ExponentialCurrent Source

SPICE PWL of(Ferlet-Cavrois et.al)

8

Collection dynamics must be established by circuit response Currents must decrease as voltages collapse (reduced E fields) Pulse broadening will occur naturally (longer times will be needed to

clear a fixed charge from the substrate)

The ECM reflects these dynamics Captures the effects of node voltage collapse Variational calculus to solve integral equation with variable limits:

Note that I(t) is implicitly defined from an integral whose limit ofintegration varies according to the circuit response

Exponentials are easy:

Salient Features of the Model

)()()(:)()(

0 sQ,sQdt't'ItI

stgivenforSolve

)()(,)1()( then,If 0/

0/

0

tQItIeItQeII(t) tt

ModulateWith

Voltage

9

ECM Currents Depend on Circuit Response Formulate an integral equation for the double exponential

Hard rail reduces to SPICE waveform Real circuit pulse broadening in response to voltage collapse

TSMC 180 nm CMOSUnit Inverter, Fan Out 2Collection Q=400 fCVdd = 1.8 V

10 ps rise 100 ps fall

Time (ns)9.0 9.5 10.0 10.5 11.0 11.5 12.0

Cur

rent

(mA

)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

LegendSPICE Double ExponentialECM Double Exp (P100 Pullup)ECM Double Exp (P4 Pullup)ECM Double Exp (P1 Pullup)

Total charge remains invariantShape altered by circuit responsePulse width automatically lengthens

ee t/τt/τττ

Qtot 12

)( 12

10

Circuit ECM Agrees with 3d Physical Model CFDRC simulation results

TSMC 180 nm CMOS Vdd = 1.8 V LET = 20 MeV-cm2/mg ~200 fC collected charge Final pulse width of 700 ps

SPICE simulation with the ECM CFDRC inspired waveform 200 fC collected charge Excellent agreement over all times

with full 3d simulations Collection current equilibrates with

PMOS pull up, accounting forDSET pulse width

Time (ns)0.0 0.5 1.0 1.5

Volta

ge (V

)

0.0

0.5

1.0

1.5

2.0

Current (m

A)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

Equivalent CollectionModel SPICESimulation

Node Voltage

Collected Current

Time (ns)0.0 0.5 1.0 1.5

Volta

ge (V

)

0.0

0.5

1.0

1.5

2.0

Node Voltage

Collected Current

Fully Coupled3d-Device PhysicsSimulation

Current (m

A)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

11

Typical Micro-RDC Test Chip (90 nm IBM 9LP)

HomogenousResettable,Read-Only

RAM

TemporalLatch

Shift Registers

Time To DigitalConverter (TDC)

and RO ofTDC Stages

Prop Chainsand DICE

Shift Registers

BeamMonitorChips

12

Time to Digital Converter (TDC) Measure differential transient pulse width distributions

Gated thermometer code generator (128 stages) High water "1 of N" detector OR-gate-based fat-tree priority encoder (7 output bits)

Upset hardened (1 in every 4x106 data may be corrupt) Generator susceptible only when processing a transient DICE-based RSFF controls the processing

Propagates an edge – not a pulseX0

TDC_0128V_CORE

INP

SAMP

INIT

OTP

EVENT

BIT[6:0]

VDDVSS

VAPVAN

XRSFF0

RSFF_DICE

S

NR Q

NQ

SP

NRP QP

NQP

VDDVSS

VDD

SA SAMP

NSA

INIT

X?

INV1X1

1 2X?

INV1X1

1 2X?

BUF1X1

1 2PULSE

OTP

REINI

13

X0128TO1

XOR_1_OF_0128

I[127:0]

OVRFLO

O[127:0]

VDDVSS

XBIT6 OR_0128X

I[127:0]

B[31:0]

C[15:0]

D[7:0]

E[3:0]

F[1:0]

G0

OT

VDDVSS

XBIT0 OR_0064

I[63:0] OT

VDDVSS

XBIT1 OR_0032

I[31:0] OT

VDDVSS

XBIT2 OR_0016

I[15:0] OT

VDDVSS

XBIT3 OR_0008

I[7:0] OT

VDDVSS

XBIT4 OR_0004

I[3:0] OT

VDDVSS

XBIT5 OR_0002

I[1:0] OT

VDDVSS

BIT6

BIT3

BIT4

BIT1

BIT5

BIT0

BIT2

F[1:0]

E[3:0]

D[7:0]

C[15:0]

B[31:0]

A33I67

A34I69

A35I71

A36I73

A37I75

A38I77

A39I79

A40I81

A41I83

A42I85

A43I87

A44I89

A45I91

A46I93

A47I95

A48I97

A49I99

A50I101

A51I103

A52I105

A53I107

A54I109

A55I111

A56I113

A57I115

A58I117

A59I119

A60I121

A61I123

A62I125

A22I45

A26I53

A21I43

A20I41

A19I39

A18I37

A24I49

A17I35

A16I33

A15I31

A14I29

A13I27

A12I25

A11I23

A2I5

A25I51

I[127:0]

A3I7

A27I55

A23I47

A31I63

A28I57

A0I1

A[63:0]

A29I59

A6I13

A5I11

A4I9

A30I61

A7I15

A32I65

A63I127

A10I21

A9I19

A8I17

A1I3

EVENT

BIT[6:0]

XDET0128 DET_0128V

INP

SA

MP

INIT

Q[127:0]

OTP

VDDVSSVAPVAN

VSS

T[127:0]

INP

SAMP

INIT

OTP

128 Stage TDC Version

Fat-TreePriority Encoder

1-of-NDetect

128 StageCode Generator

14

SEE Mitigation Methods Well de-biasing known to cause problems

90 nm and smaller technology nodes Seen in SRAM MBU measurements Seen in DICE-based latch layouts

Test chip includes several shift register designs DICE-based latch with multiple n-wells Temporal Latch with shared n-well Temporal Latch with multiple n-wells

15

DICE Latch Considerations Gained popularity because of internal redundancy

Immune to upset from a single node strike Separating critical nodes thought to provide acceptable error rates

Loosing popularity due to new radiation response mechanisms Well de-biasing makes node separation difficult Separations of 10 to 20 microns not adequate in real applications Susceptible to DSETs on data inputs, clock inputs, and control lines Transient filtering required on each of these signals Basic DICE-implementation must be correct or the guard gate itself will

be a non-filterable DSET target that will cause errors

Recommendation Use a latch that is inherently immune to transients on any node and is

immune to multiple node strikes (which can actually be accomplishedby replacing spatial redundancy with temporal redundancy)

16

By analogy, build a DITLAT from a DICE SRAM cell:

Each signal now has a "prime" D and D' SA and SA' HO and HO' etc for any set signals etc for any reset signals

Need to assert both a signal and its prime to invoke an operation This is the key for transient filtering

How to Correctly Implement DICE

Vss

Vdd

Vss

Vdd Vdd

Vss Vss

Vdd

NQQ QP NQP

XP1P11

2

3

XN1N1

1

2

3

XP2P11

2

3

XN2N1

1

2

3

XN3N1

1

2

3

XP3P11

2

3

XN4N1

1

2

3

XP4P11

2

3

Vss

Vdd

Vss

Vdd Vdd

Vdd

Vdd

Vdd

Vss

Vss

Vss

Vss

SA

HO SA

HO

SAP

HOP SAP

HOP

XN5N2

1

2

3

XN7N2

1

2

3

XP5P21

2

3

XP6P2 1

2

3

XP7P21

2

3

XN6N2

1

2

3

XN2N1

1

2

3

XN8N2

1

2

3

XN10N2

1

2

3

XP8P21

2

3

XP9P2 1

2

3

XP10P21

2

3

XN9N2

1

2

3

XP4P11

2

3

XP2P11

2

3

XP3P2 1

2

3

XP1P2 1

2

3

XN3N2

1

2

3

XN1N2

1

2

3

XN4N1

1

2

3

D

SA

HO

Q

NQ

DP

SAP

HOP

QP

NQP

U.S. Patent No. 5,570,313

17

Correct Transient Filtering on DICE Latches Only need to delay the "primed" signal with respect to the signal

Delay of T filters transients of width T and shorter Increases latch setup and hold times by 2T

D

SAHO

SN

R

QNQ

DP

SAPHOP

SPN

RP

QPNQP

SET

DATA

SAMP

HOLD

NRESET

QNQ

QPNQP

U.S. Patent No. 6,326,809

18

Incorrect Transient Filtering on DICE Latches Guard gate includes the filtering delay

Again increases latch setup and hold times by 2T Only removes transients incident on the guard gate Guard gate itself becomes a DSET susceptible target Who's guarding the guard gate???

Vss

Vdd

D

SAHO

SN

R

QNQ

DP

SAPHOP

SPN

RP

QPNQP

DATA

Similar treatment of other inputs

DSET Susceptible Nodes

U.S. Patent No. 6,326,809

19

Requirements for Separation of Critical Nodes Initial efforts directed toward DARPA RHBD SRAM design

Designed, fabricated, and packaged a special SRAM device Performed true 90° heavy-ion testing (89° won't cut it)

Results applicable to other circuit designs DICE-based latch cells Older TMR approaches

Discovered a few unexpected results Collection funneling depths not as deep as hoped Shallow P+ or BOX engineered substrates not very helpful

SOI with <50 nm Silicon thickness hoped to be the solution DARPA RHBD and DTRA RHM focusing on 45 nm and 32 nm SOI Charge track diameters may negate any value gained (50 nm diameters

for earth based testing, much larger for 1 GeV/nucleon Fe in space)

20

True 90° SRAM Testing Specially designed IC in conjunction with novel die attach

21

Edge on Illumination of SRAMs

N Ne Ar Cu Kr

Edge of Silicon

N Ne Ar Cu Kr

Edge of Silicon

Depth (um)0 100 200 300 400 500 600

LET

(MeV

-cm

2 /mg)

0

10

20

30

40

50

Kr

Cu

Ar

NeN

16 MeV/nucleon beam formaximum penetration

Berkeley "base" and "face"angles can be accuratelyvaried in 0.1º steps

Measure various SEU andMBU cross sections

Map bit error addresses tobit cell physical locations

Edge on results agree withSRIM predictions

Can see threshold LETeffects in Nitrogen beamresults

22

Data Acquisition Software Real-time visualization

Invaluable for locating θ-φ sweet spot in an acceptable amount of time Filtering options for error multiplicity Options for refresh rate Also critical for initial location & calibration of the Milli-Beam

23

LET (MeV-cm 2/mg)0 5 10 15 20 25 30 35 40

Cro

ss S

ectio

n (c

m2 /b

it)

10-13

10-12

10-11

10-10

10-9

10-8

10-7Bulk 90-deg and 0-deg Data

Angle of Incidence90 degrees 0 degrees

LET (MeV-cm 2/mg)0 5 10 15 20 25 30 35 40

Cro

ss S

ectio

n (c

m2 /b

it)

10-13

10-12

10-11

10-10

10-9

10-8

10-7SOI 90-deg and 0-deg Data

Angle of Incidence90 degrees 0 degrees

Bulk and 0.7 µm SOI -- 90º and 0º Results

SOI Results No significant reduction in

saturated cross section No significant increase in

threshold LET Also implies very shallow

collection depths

Bulk Results Collection length appears

to be longer for 90º beam Saturated cross section

smaller for 90º beam Implies very shallow

collection depths

24

Required Critical Node Separations

90° incident heavy ions Ne ion in the LBL 16A MeV

cocktail Range ~240 µm

Step angle of incidence Measure separation of each MBU Least-squares fit provides MBU

integration over solid angle Compare the MBU integrated error

rates to 2 • SEU rate

Angle of Incidence (degrees)86 87 88 89 90 91 92 93 94

Cro

ss-S

ectio

n (A

U)

0.0

2.0

4.0

6.0

8.0

10.0

12.0

100 mCell Separation

25

Error Rate Estimate for Redundant Circuit Error rate for no redundancy = R0

Reduction factor at cell separation = F(ds) Hardened design error rate then = R0 · F(ds)

Cell Separation dS ( m)10 100 1000

MB

U R

educ

tion

Fact

or

10-6

10-5

10-4

10-3

10-2

10-1

(Separation)-2

26

Temporal Latch Solution

Triple spatial redundancy achieved through temporal sampling Inherently immune to transients of width <T on any node Can be made immune to multiple node strikes of any multiplicity

Make T > transient width + loop delay Lay out so T, 2T, and MUX/MAJ are in separate rows

Well de-biasing problems when T and MUX/MAJ shared an n-well New T design solved this (to be patented from our SASIC SBIR) New design proven non-upsetable in recent AFRL heavy-ion tests

CLOCK

OUTIN

MAJ

MUX

2ΔT

ΔT

CLOCK

OUTIN

MAJ

MUX

2ΔT

ΔT

U.S. Patent No. 6,127,864

27

Tradeoffs Between DICE and Temporal Full up Set/Reset DICE transparent latch

28 transistors + 5 T delay elements

Full up Set/Reset Temporal transparent latch 28 transistors + 3 T delay elements

Full up Set/Reset DICE DFF 48 transistors + 5 T delay elements

Full up Set/Reset Temporal DFF 52 transistors + 6 T delay elements

Same speed loss for each (2T setup/hold time increase)

Temporal TLAT and DFFs immune to multiple node strikes

28

0.00

0.20

0.40

0.60

0.80

1.00

Freq

uenc

y R

educ

tion

Fact

or

0 200 400 600 800 1000Original Frequency (MHz)

100 ps

Sampling T

200 ps

400 ps

800 ps

Speed Tradeoffs for Various T Values Formulate as a frequency reduction factor (F1/F0)

Will depend on original operating frequency F0

Assume a setup/hold increase time of 2T

TFF

211

01

29

Recent Relevant Micro-RDC Efforts Extended our earlier DSET investigations

Characterize, model, simulate DSET effects in emerging technologies Upgrade and develop new test hardware and data analysis methods Improve several earlier DSET test structures Develop new DSET characterization structures and methods

Developed our heavy-ion Milli-Beam™ for use at the LBL cyclotron New hardware and software to raster scan complex ICs Achieve spatial resolutions between 10 µm and 500 µm

Initial hardening investigations of a PLL Identified candidate designs Performed coarse Milli-Beam scans

30

Example Propagation Chain Layouts Up-Down transient propagation 8 chains adjacent to one another Wide separations between vertical stripes (for Milli-Beam testing)

150 µm tonext stripe

150 µm tonext stripe

4.8 µm

31

Sample Differential Pulse Width Distributions Broadening effects clear for "0" state data Multi-Transistor modulation might be altering the "1" state data

Kr (30 MeV-cm 2/mg) 2048 Stages

Input = 0

Input = 1

Cou

nts

0

50

100

150

200

250

300

T (ps)0 500 1000 1500 2000 2500 3000 3500 4000

32

Mean Pulse Width vs. Length, Input=‘0’, INV1

Mean Pulse Width vs Length, Input = '0'

Propagation Chain Length0 500 1000 1500 2000 2500

Puls

e W

idth

(ps)

0

500

1000

1500

2000

LegendXeKrCuAr

33

Heavy-Ion Milli-Beam at the LBL Cyclotron Precise beam collimation for use at the LBL cyclotron

New hardware and software to raster scan complex ICs Achieve spatial resolutions between 5 µm and 500 µm

Hardware Primary square aperture (2-orthogonal slits) stepped <1 µm precision Secondary scattering cleanup aperture controlled from second stage Displacement sensors provide error feedback signal for corrections

Software Computes coordinate transformations, sets beam position, controls run Provides FPGA test board with positions for inclusion in error message

Independent ICs for beam characterization and dosimetry Homogeneous RAM for location and intensity profile measurement Specially designed beam monitor ICs placed upstream of apertures At preset fluences: block the beam, stop data acquisition, step apertures,

update FPGA test board with new position, resume data acquisition,unblock the beam

34

Milli-Beam Schematic

Beam

DUT

PrimaryAperture

SecondaryAperture

Beam FluenceMonitor ICs

Rapid, Dual,Symmetric Shutter

Vacuum ChamberEntrance Port

DisplacementSensors

35

Numerous Physical Considerations Displacement and rotation of DUT w.r.t. calibration SRAM

SRAM Y-axis rotation w.r.t. Milli-Beam Y-actuator

Non-orthogonally of Milli-Beam X and Y acutuators

Berkeley Stage Y-axis rotation w.r.t. Milli-Beam Y-actuator†

Non-orthogonally of Berkeley X and Y acutuators†

Dimensional scaling of each actuator†

†Only if need to move Berkeley Stage to bring DUT into Milli-Beam Range

36

Final Form of the Transformation Transformation to compute Milli-Beam raster scan movements

D

D

dut

dut

m

m

y

x

y

x

y

xO 1

R 1DR

R 1R 1

O S

b

b

D

D

D

D

y

x

y

x

y

x

o

o

Inverse transformation used to compute DUT location, along withan estimate of the variance, for each Milli-Beam raster position

SRAM w.r.t. Milli-Beam; D DUT w.r.t. SRAM Berkeley w.r.t. Milli-Beam; b Berkeley stage movement

37

Complete Assembly in Berkeley Chamber

PrimaryAperture

Actuators

SecondaryApertureActuators

BeamEntrancePort

UpstreamChamber

Wall

38

Primary Aperture Assembly

39

Aperture Mounting Assembly

Bracketto Mountto Stage

Slit Holder

PressurePlate

NeodymiumMagnets (4)

40

Aperture Construction

Outside ViewHorizontal Slit

Inside ViewHorizontal Slit

Outside ViewVertical Slit

Inside ViewVertical Slit

Fold to Assemble:

41

Beam Monitor in Relation to Primary Aperture

Y-Stage

X-Stage

PrimaryAperture

Slit Holder &Pressure

Plate

BeamMonitor

Assembly

42

View as Seen by the Heavy-Ion Beam

PGA, ZIF Socket, PERF Board

Zoomed View of Die

3.0 mm

43

Beam Fluence Monitor Accuracy Average the 4 monitor chip counts to predict beam flux at aperture

Run Time (s)0 50 100 150 200 250 300

Flue

nce

(Arb

. Uni

ts)

0

500

1000

1500

LegendAperture PredictionMonitor 1Monitor 2Monitor 3Monitor 4Aperture Position

44

Milli-Beam Intensity Profile Calibration

0 50 100 150 200 250 300 350 400

0

50

100

150200

250300

350400

0

10

20

30

40

50

60

0 50 100 150 200 250 300 350 400

0

50

100

150200

250300

350400

0

10

20

30

40

50

60

100 µm square aperture Located 5 cm to SRAM Sharper edge definition

100 µm square aperture Located 40 cm to SRAM Edge washout due to angular

spread

45

LSQ Fits to the Intensity Profile Function

2-d Convolution of a Gaussian product z(x)z(y) with an x-y-z box Center, width, length of aperture determined to < 1 µm accuracy Gaussian x and y determined to <0.1 µm accuracy values consistent with distance times tangent of 0.0025° at 5 cm distance measured to be ~2 µm in x and y directions

0 50 100 150 200 250 300 350 400

0

50

100150

200250

300350

400

0

10

20

30

40

50

60

0 50 100 150 200 250 300 350 400

0

50

100150

200250

300350

400

0

10

20

30

40

50

60

46

Beam Fluence Monitor Four special ICs

Mounted just upstream of the Milli-Beam Primary Aperture Incorporates 8 chains of 1024 set-reset-flip-flops (RSFF) Electrically selectable cross section

• Min = 1024 x 4 chips = 4,196 RSFF cells• Max = 8192 x 4 chips = 32,768 RSFF cells

Extremely small dead time (~0.02% for 107 ions/(cm2sec))

Calibrated to an accuracy of better than 1% Independent of the Berkeley dosimetry system Aperture of know size (as measured on a 90 nm SRAM) Particle detector counts individual heavy-ions through aperture Beam monitor IC events measured as a function of LET

47

Recent Beam Monitor Calibration Data 10 ions available in the 10 MeV/nucleon cocktail

System cross-section calibrated from 0.89 to 58.8 MeV-cm2/mg

Count events in each of the 4 beam monitor chips Subject only to Poisson statistical uncertainties

Collimate beam with known size aperture (~100 µm ~100µm) Measure precisely using our calibration RAM

Use partially depleted Silicon particle detector to measure fluence Count each and every heavy-ion passing through the aperture

Determine cross-section as usual = (Number of Events) / Fluence

48

Beam Monitor Calibration Schematic

Beam

ParticleDetector

100 µm 100µmAperture

Beam FluenceMonitor ICs

Vacuum ChamberEntrance Port

49

Aperture height H and width W determine area A:

Particle detector counts Npd then determine fluence F:

Total beam monitor counts Nbm determine cross section "":

Given the uncertainties dH, dW, dNpd = (Npd)1/2 , and dNbm = (Nbm)1/2

Calibration Equations

WHA

ANF pd /

FNbm /

2211

W

dW

H

dH

NN

d

pdbm

50

Final Beam Monitor Cross Section System saturated cross section ~1.5x10-4 cm2

1500 counts/s at a modest Milli-Beam flux of 1x107 cm-2 s-1

Achieves 1% accuracy in ~7 seconds at each raster step

Lognormal Fit

Weibull Fit

LET (MeV-cm2/mg)0 10 20 30 40 50 60

RSF

F C

ell C

ross

Sec

tion

(cm

2 )

10-12

10-11

10-10

10-9

10-8

10-7

Multiply by 32768 to getBeam Monitor MaximumSaturated Cross Section of~1.5x10-4 cm2

(Data Error Bars Smaller than Plotted Points)

51

How Good is the Berkeley Dosimetry? They use 4 peripheral scintillators and a center scintillator

Calibration of the center to peripheral ratio periodically performed Center scintillator removed to put beam on target Periperal scintillators then used to predict target flux

This is particularly sensitive to changes in beam focus If beam focus tighter, center flux higher but predicted to be lower If beam defocuses, center flux lower, but predicted to be higher Beam focus likely to change whenever switch ions

Particle detector with aperture provides independent test Beam monitor calibration made 5 runs for each ion Each run stopped at 1x108 ions/cm2 fluence on Berkeley system Can compare true fluence measurements with Berkeley values

52

Actual Measured Fluence vs Berkeley Values ~10% variations when just repeat runs (common knowledge) Similar variations when return to an ion (should check further) >3x errors between species (this was a big surprise)

Run Number0 5 10 15 20 25 30 35 40 45 50 55 60

Flue

nce

Rat

io (

Act

ual/B

erke

ley)

0.0

0.2

0.4

0.6

0.8

1.0

Xe

Ag

Kr Cu V V

Ar

Si

Ne

O

B

10 MeV/Nucleon Cocktail

53

Beam Focus Drifts Seen in Beam Monitor Chips Monitor each beam monitor chip independently Normalize counts so average of all data at each ion equals 1.0 Beam profile variations evident over time and between species

Run Number0 5 10 15 20 25 30 35 40 45 50 55 60

Ral

ativ

e C

hip

Even

t Rat

es

0.50

0.75

1.00

1.25

1.50

Xe Ag Kr Cu V VAr Si Ne O

B

10 MeV/Nucleon CocktailBM ChipNWNESESW

54

Example of a Raster Scan 114 µm x 101 µm aperture

As determined from LSQ fit

5 cm from SRAM

>>1 x 106 Ar ions/(cm2-sec) 10x normal beam intensity

Use aperture size for step size x step = 114 µm y step = 101 µm

Scan in a serpentine pattern ~1.5 seconds/step ~300 errors at each position

55

SRAM Raster Scan Data Example Scan an SRAM on one of our earlier test chips

Two different cell designs – hardened layout on right half Decode locations clearly seen in center of each array Variations outside of statistical uncertainties due to beam fluctuations Demonstrates the need to perform independent fluence monitoring

XY

Err

-5000

5001000

15002000

25003000 -200

0200

400600

8001000

12000

500

1000

1500

2000

2500

3000

56

Micro-RDC's PLL Hardening Efforts Designed a simple PLL, following commercial-like designs

Under our AFRL Structured ASIC program TID and SEL hardened with channel stops and edgeless NMOS SEU and DSET susceptible

Performed coarse Milli-Beam scans Better approach than attempting to test standalone circuit components Used 100 µm 100 µm aperture Stepped over active layout in 100 µm X and Y steps Monitored PLL loss of lock and time needed to regain lock Correlate observed errors to specific circuits (CP, VCO, PSD, /N, xM)

57

Correlate PLL Errors to Physical Layout

Design Layout Milli-Beam Error Contours

1 4 7 10 13 16 19 22 25 28 31 34 37 40 43 46 49 52 55 58 61 64 67 70 73 76 79 82 85 88 91 94 97 100

103

106

109

112

115

118

S1

S4

S7

S10

S13

S16

S19

S22

S25

S28

S31

S34

S37

S40

S43

S46

S49

S52

S55

S58

S61

115-120110-115105-110100-10595-10090-9585-9080-8575-8070-7565-7060-6555-6050-5545-5040-4535-4030-3525-3020-2515-2010-155-100-5

View Direction for3D Surface Plot

58

Recommendation Summary Avoid use of spatial redundancy for SEU mitigation

Node separations much too large for DICE and TMR Use "by 1" block architecture with EDAC for SRAMs

Use Temporal Sampling Latches for SEU and DSET mitigation Automatically achieves immunity to DSETs on any node With new well de-biasing mitigation, automatically immune to multiple

node strikes

Tune the design to optimize hardness vs. speed vs. area Not all latches need the same T filtering delay Not all combinatorial gates generate the same sized transients

Keep hardening implementation transparent to designer Reflect the RHBD consequences within the synthesis library Require no HDL modifications to use the library