Roadmap for Future Semicnductor Development From Itswjs

7/29/2019 Roadmap for Future Semicnductor Development From Itswjs

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Fraunhofer IZM, Germany 23.05.2011

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Fraunhofer IZM

ITRS Packaging Roadmap

M. Jrgen Wolf

Fraunhofer IZM,Berlin, Dresden, Germany

[email protected]

Fraunhofer IZM

M.J. Wolf

Moores Law

The observation made in 1965 by Gordon Moore,co-founder of Intel, that the number of transistorsper square inch on integrated circuits haddoubled every year since the integrated circuitwas invented. Moore predicted that this trend

would continue for the foreseeable future.


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Fraunhofer IZM

M.J. Wolf

Interacting with peopleand environmentNon-digital contentSystem-in-Package (SiP)

Moores Law Scaling can not maintain the Pace of

Progress and Packaging enables equivalent Scaling

BeyondCMOS

InformationProcessingDigital content

System-on-Chip(SOC)

Biochips

Fluidics

Sensors

Actuators

HV

PowerAnalog/RF Passives

More than Moore :

Functional Diversification

130nm

90nm

65nm

45nm

32nm

..22nm

More

Moore:

Scaling

Baseline CMOS:CPU, Memory, Logic

Fraunhofer IZM

M.J. Wolf

Technology Scenario Driven by Applications

DevicesDevices

RequiredRequired TechnologiesTechnologies 3D integration with stacked Si devices / MPU, Memory Si-interposer with TSV and integrated passive devices High density and capacity memories Electrical /optical interconnect Multi-functional board with embedded components Heterogenous integration of sensors, memory, processors

and power supply

Energymanagement

Efficient powersupplies and

intelligent stand-by solutions Power IC packaging Digital power

conversion Lighting

Ultra-small sensor nodesfor car networks

Tire Pressure MonitoringSystem (TPMS),

Driver assistance Car-to-car/road

communication sensors and actuators for

air and fuel injection

Parallel processor, architecture 3D MPUs, GPUs Advanced sensor nodes Distributed Sensor Networks

Transport &Transport &MobilityMobility

Energy &Environment

Security &Safety

Communication& Consumer

Electronics

Healthmonitoringsystems

Neural implants

Hearing devices Visual aids

Image sensors Admission control Biometrical control

systems

RFID systems

Navigation systems Wireless

communication Localization

Portable TV

ApplicationsApplications

Health &Care


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Fraunhofer IZM

M.J. Wolf

ITRS Roadmapping www.itrs.net

At this time of major shifts in market and technology, ITRS servesthe role of up-to-date knowledge base for industry, academia,and research institutes.

The ITRS roadmap is a touchstone for industry roadmaps. ITRSwould then be a first stop for people who wish to learn aboutthe directions and roadblocks for both near term and long terminto the future.

Industry can us the roadmap to build their own companyroadmaps.

Academia and Research Institutes can us it to validate the

selection and pacing of new technologies in to the future.

Fraunhofer IZM

M.J. Wolf

Forces of Change

Global Consumer Market Functions & Cost

Technology Convergence More Moore & More than Moore

Packaging has become the crucial link in the supply chain

Technology Landscape

Redefining WB & FC

New Architectures

WLP going main stream

Embedded technologies

SiP + 3D

ITRS Roadmap Assembly and Packaging


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Fraunhofer IZM

M.J. Wolf

SiP - System in Package

Horizontal Placement

S tacked

S tructure

Interposer Type

Interposer-less

Type

Wire Bonding T ype Flip Chip Type

Wire Bonding

Type

Wire Bonding +

Flip Chip Type Flip Chip Type

Terminal Through Via T ype

Embedded S tructure

Chip(WLP) Embedded +

Chip on Surface Type

3D Chip Embedded

Type

WLP E mbedded + Chip on

S urface Type

PiP, PoP and more

Fraunhofer IZM

M.J. Wolf

System-in-Package Requirements

Year of Production 2009 2011 2013 2015 2017

Number of terminalslow cost handheld 800 900 1000 1000 1000

Number of terminalshigh performance(digital)

3350 3684 4053 4458 4904

Number of terminalsmaximum RF 200 200 200 200 200

Low cost handheld / #die / stack 9 11 13 14 15

high performance / die / stack 3 4 5 5 6

Low cost handheld / #die / SiP 9 12 14 14 15

high performance / #die / SiP 6 7 8 8 9

Minimum component size (micron)400x200

400x200

200x100

200x100

200x100

Minimum TSV pitch 6 4 3,6 3,3 2,9

TSV maximum aspect ratio** 10 10 10 10 10

TSV exit diameter(um) 3 2 1,8 1,6 1,5

TSV layer thickness for minimum pitch 15 10 10 8 8

Reflow temperature for Pb free (C) 245 245 220 200 180


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Fraunhofer IZM

M.J. Wolf

Packaging Global Changes

2010Year of Wafer Level Packaging

WLCSP Shipment Growth - 25%

WLCSP Fanout High Volume Shipment

TSV + Silicon InterposersEmbedded Technologies

Source: W.Chen, ASE

Fraunhofer IZM

M.J. Wolf

Growth of Wafer Level Chip Scale Packages (WLCSP)

Year 2000 WLCSPs were small, low I/O, expensive, and with limitedmanufacturing infrastructures

On Semi Analog -ASE

TI Nanostar Digital - ASE

Vishays Power MOSFET TechSearch

Year 2010 Billions shipped, >300 I/Os, Established infrastructure,with high volume manufacturing

Broadcom 182L 6.5x6.5WLCSP ASE

Fujitsu Power Management WLCSP308 L 7.7x7.7mm-TechSearch - TPSS

Qualcomm 169L WLCSP ASE

361 L WLCSP ASE

Infineon BAW filters TechSearch

Source: W.Chen, ASE


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Fraunhofer IZM

M.J. Wolf

Form Factor & MiniaturizationReduced volume and weightReduced footprint

PerformanceImproved integration densityReduced interconnect lengthImproved transmission speedReduced power consumption

Heterogeneous Integration & FunctionalityMixed functional Integration

MEMS, Optical, AD SP, Transceiver

Manufacturing Cost Reduction

Driving ForcesDriving Forcesfor 3D SiP

Fraunhofer IZM

M.J. Wolf

Generations of 3D Packaging / 3D System Integration

We are at the doorstep of the largest shift in thesemiconductor industry ever, one that will dwarfthe PC and even the consumer electronics era".

Dr. Chang-Gyu, Samsung

Package on Package (POP) Stacked Die 3D ICPackage on Package (POP) Stacked Die 3D IC

Ref. B Chen


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Fraunhofer IZM

M.J. Wolf

3D TSV Roadmap

Source: Yole

Fraunhofer IZM

M.J. Wolf

Wafer-Level-Package for Optical Applications

Tapered Vias & Streets

controlled sidewall angle for sribe line

controlled sidewall angle for via holes


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Fraunhofer IZM

M.J. Wolf

Si TSV Interposer RF Module

Dimension 7,5mm x 8 mm

RF Mobile Transceiver (2,4 x 3,6 mmSnAg Solder Bumps (diameter: 50 m)Si Carrier (300 m thickness)TSV (8x8x 300 m)RDL Cu 20 m line /spaceSolder Balls (diam. 250 m /500 m pitch)

F. Binder, IFX

Fraunhofer IZM

M.J. Wolf

3D TSV Approaches

Wafer Level (BE)Wafer Level (BE)Circuit Level (FE)Circuit Level (FE)

Die2Wafer Stacking(w/o TSV)

W2W Stacking (w TSV)

- Si Interposer w TSV -

Thin Chip Integration (TCI)

Package /Board LevelPackage /Board Level

Stacked Package

Folded Substrate

Die in Board Embedding(CiP)

Die in Flex Embedding

Embedded Wafer Level Packaging(eWLP)

Stacked device layer TSV & Stack formation

--- IC devices w TSV ---

Via First

Via Middle

Via Last


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Fraunhofer IZM

M.J. Wolf

Interposer Technology

Source:Yole

Fraunhofer IZM

M.J. Wolf

3D System Architectures TSV Interposer

Interposer with embeddeddevices in RDL

Interposer with TSV & stackeddevices (w TSV)

Stacked modular Interposer w. TSV

Silicon interposer as device carrier

between devices and package / boardfor high IO count and high

interconnect density (multi-layer (RDL),

5-10 m line/space)

RDL:T.W/CuTop Die(190m)

Base -Die

embeddeddie(35m) interconnection:TiW/Cu

RDL:T.W/CuTop Die(190m)

Base -Die

embeddeddie(35m) interconnection:TiW/Cu


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Fraunhofer IZM

M.J. Wolf

Through Silicon Via Interposer / HD-Multi Device Carrier

Cu-TSV (> 10000/cm)

High density Multi-LayerRedistribution (4 L Cu)

Flip chip compatible IO-Pads

Cu-Pillar Bumps

SnAg Micro Solder Bumps

Fraunhofer IZM

M.J. Wolf

Chip Interconnection

Technology:

Solder, IMC, Cu-Cu, Nano-Interconnects

Bonding (reflow, TC)

Stacking (D2W, D2W)

Interconnect structure (Cu, ...)

Challenges:

Low temperatur bonding

fluxfree, self alignment

Bonding on carrier vs. wafer

Reliability, test, repair

Productivity, throughput, yield

Bottom Device

Al

Top-Chip(17 m)

Cu

Cu

Cu3Sn

AlILD

12 m

Bottom Device

Al

Top-Chip(17 m)

Cu

Cu

Cu3Sn

AlILD

12 m


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Fraunhofer IZM

M.J. Wolf

TSV-Interposer

Silicon Interposer Apps#1: high TSV count (>10000/vm)high density TSV (5-10m),small pitch (50m -20m)high density Line/Spacemultilayer front/back side (#4)electrical & optical Interconnect

Silicon Interposer Apps#2: med. TSV countmed. TSV (10-20m), pitch (>100 m)ASR (5-15)multilayer front/back sideMEMS integrationCu pillar interface to board/package

Potential: passive device integrationoptical interconnectsheterogeneous device integration (e.g. TX, MEMS),e.g. thin chip integrationthermal management (cooling)

Fraunhofer IZM

M.J. Wolf

Tera-scale Computing

Ref. B Bottems, ITRS


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Fraunhofer IZM

M.J. Wolf

Roadmap - 3D WL System Integration

Year

eWLPeWLPeWLPeWLP

Stacked TCI w TSV

IPD & RDL

Controller /Memory Stacks

3D Interposerw. Cooling

2006 2007 2010 2012 201420092008

3DInterconnectComplexity

2005

3D CPUs

3DInterconnectComplexity Functional

LayeredStack eGrain

eWLP

HDI TSV Interposer

Hetero Integration

3D TCT/TSV

eWLPw TMV

WLP w. TSV

Stacked Memory onTSV Interposer

3D Image Sensors

Fraunhofer IZM 08/2009

Fraunhofer IZMResearch Center ofMicroperiphericTechnologies

Photonic Packaging @ ITRS

Packaging of optoelectronic and MEMS components has beentreated by ITRS in the section ASSEMBLY AND PACKAGINGunder packaging for specialized functions

Optoelectronics packaging covers an expanding range of newtechnical requirements depending on their applications.

Examples of optoelectronic packages and their applications arepresented

There are many difficult challenges remaining for opticalpackaging and they will become increasingly critical as theoptical communication gets ever closer to the chip.

A list of these challenges, technology requirements, potentialsolutions and the Cross TWG are presented.

Review of Packaging of Optoelectronic,Photonic, and MEMSComponents IEEE JSTQE (2011)DOI:10.1109/JSTQE.2011.2113171


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Silicon Photonics Packaging Concepts by Fraunhofer IZM

Smart-Pack for (de)multiplexing

Generic-Pack for multiport electrooptic SOI

T. Tekin, H. Schroeder, L. Zimmermann, P. Dumon, W. Bogaerts "Fibre-array optical interconnection for silicon photonics" Proc. of ECOC, Vol. 5, pp. 93-94 (2008).L. Zimmermann, T. Tekin, H. Schroeder, P. Dumon, W. Bogaerts. "How to bring nanophotonics to application - silicon photonics packaging". LEOS Newsletter December 2008.


Silicon Photonics Packaging Design Rules

Established Silicon PhotonicsPackaging Design Rules aresummarized in following fields:

Fiber Pigtailing

Flip-Chip & Die Bonding

Wire Bonding

Available

www.izm.fraunhofer.de/EN/abteilungen/siit/technology/photonic/spic.jsp

Hall C1 Booth 312

uv-curingepoxy

fiber-array

SOI chip

uv-curingepoxy


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Fraunhofer IZM

M.J. Wolf

Summary

Assembly & Packaging is converting into complex systemIntegration Technology

ITRS /A&P helps and supports to identify major newdevelopments directions and specifications with respect tothe targets of new product generations

3D System Integration (A&P) is an key enabler for theHeterogenous Integration of MEMS, MOEMs, MPUs,ASICs, Memories

Fraunhofer IZM

M.J. Wolf

Wafer Level All Silicon System IntegrationWafer Level All Silicon System Integration -- ASSID @ FhG IZMASSID @ FhG IZM

IZM / ASSID develops leading edge technologies for 3D-WLSystem-Integration and provide solutions ready for productintegration to industrial partners.

IZM / ASSID offers capacity and support for equipment andmaterial evaluation to semiconductor industry.

IZM / ASSID offers services by using qualified processcapacities and demonstrate stable processes on a 300mmTSV process line.

Fraunhofer IZM vision is to integrate heterogeneous chip

functionalities into one package (SiP) by using enhanced 3D-

integration, assembly and interconnect technologies.


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Fraunhofer IZM

M.J. Wolf

THANK YOU FOR YOUR ATTENTION

Acknowledgement:TWG A&P ITRSFraunhofer IZM, TU BerlinIFX, GF, NXP, ASE, Philips,Joule, EMC3D

Contact:

M. Juergen [email protected]

Fraunhofer IZMAll rights:

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Roadmap for Future Semicnductor Development From Itswjs

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