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Jiri Ocenasek, Magwel NV, Belgium 1July 2008
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Jiri Ocenasek, Magwel NV, Belgium 2
Robust circuit sizing:EDA for EDA
Jiri Ocenasek, Magwel NV, Belgium 3
MAGWEL was founded in April 2003 Spinoff from IMEC in Belgium Initially focused on 3D deviceEM simulation With acquisition of Kimotion Technologies
− Expanding into Robust Design and Verification of Analog and RF circuits
Customers: TI, NXP, IMEC, UCL …. Participant in EU research projects
Company Overview
Jiri Ocenasek, Magwel NV, Belgium 4
Design variables
Robust sizing of Analog & RF building blocks
Process and Environment
Performance models
Specifications
Optimized netlist Specification corners
EldoTM
SpectreTM
HspiceTM
KtModelsADVanceMSTM
…
Jiri Ocenasek, Magwel NV, Belgium 5
Example: Gainboosted op. amplifier* [M.Waltari, “circuit techniques for low-voltage and high-speed A/D converters, PhD.]
Jiri Ocenasek, Magwel NV, Belgium 6
Terminology I
Design variables D− The designer can prescribe them within some accuracy− Example: W and L of transistors, bias current, …
Operational variables O− The circuit has to work under all operational conditions within
specified limits− Example: Temperature, Supply voltage, …
Technology variables T− Variation of manufacturing process, statistically distributed− Example: Doping parameters of substrate
Jiri Ocenasek, Magwel NV, Belgium 7
Terminology II
VGS1
IDS1
VGS2
IDS2
Mismatch in T
Mismatch in D+
Transistors are not identical !
Mismatch variables M
Jiri Ocenasek, Magwel NV, Belgium 8
Response variables R− Extracted from simulator’s output: r = simulate(d,o,t,m )− Example: Noise, Gain, Power, Die area, ...
Constraint cost for ith constraint Ci(r) Ci(r) ≥ 0 if satisfied, Ci(r) < 0 if violated Example: Power is below 100 mW: “100mW Power”
Goal cost for jth goal Gj(r)
Terminology III
Jiri Ocenasek, Magwel NV, Belgium 9
Probability density function ρ(t,m ) Typically normal or uniform
Advanced manufacturing processes the design d has to be robust against variations of t and m yield(d) = ∫t,m F(d,t,m) ρ(t,m) dt dm
where F(d,t,m) indicates whether all constraints Ci are satisfied under all permissible operational conditions o:
F(d,t,m)=1 if ∀i, ∀οϵΟ : Ci(simulate(d,o,t,m))≥0 F(d,t,m)=0 otherwise
Yield explanation
Jiri Ocenasek, Magwel NV, Belgium 10
Optimization target
First stage: nominal optimization− find d such that ∀i: Ci(simulate(d,o=nominal,t=0,m=0))≥0− can be replaced by userprovided solution
Second stage: yield maximization− find/improve d such that yield(d) is maximized
Third stage: when yield( d ) > 0.997− minimize sum of goals ∑j Gj(d,o=nominal,t=0,m=0,r)
while keeping the yield
Jiri Ocenasek, Magwel NV, Belgium 11
Results: gainboosted amplifier
# devices 56# design variables 22# constraints 63# tech.+mm. variables 30# operational variables 4starting point none
# simulations 12626runtime 251 mintotal yield 99.8%goal 1goal 2 power = 13.7 mW
area = 7970 μm2
Jiri Ocenasek, Magwel NV, Belgium 12
Results: gainboosted amplifier
Number of fitness evaluations
Jiri Ocenasek, Magwel NV, Belgium 13
Jiri Ocenasek, Magwel NV, Belgium 14
Why are Estimation of Distribution Algorithms suitable?
Decomposability of the problem− the circuit is composed of subblocks
Complicated fitness landscape− multimodality: several local optima− nonlinearities: responses are hard to be modeled− discontinuities: simulator switches modes− missing data: regions where simulation fails
Jiri Ocenasek, Magwel NV, Belgium 15
Conclusion
Robust Optimizer− Can handle tough circuits where others fail− Capable of handling fairly large blocks
Produces quality results with high yield− 3 step approach, does not require user intervention− Provides insight: yield distributions, sensitivities, tradeoffs
Integration− Cadence design environment− Simulators: Spectre, Eldo, Hspice (others can be added)− Supports LSF for distributed simulation
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Thank you