RRAM Status and Opportunities

Resistive RAM: Technology Status and Future Opportunities

Deepak C. Sekar Rambus Labs

2014 Memory Symposium @ the IEEE Santa Clara Valley Electron Devices Society

2 ©2014 Rambus Inc.

Outline

Background on RRAM RRAM as an Embedded Non-Volatile Memory

RRAM as a Standalone Memory Conclusions

Vertical electrode Memory cell

Horizontal

electrode


Background on RRAM


Resistive RAM

Top

electrode

Bottom

electrode

Transition

Metal Oxide

Examples

Top electrode Pt, TiN/Ti, TiN, Ru, Ni …

Transition Metal Oxide TiOx, NiOx, HfOx, WOx, TaOx,

VOx, CuOx , …

Bottom Electrode TiN, TaN, W, Pt, …

• Memory Effect: ON = 100kΩ, OFF = 10MΩ

Can change from one resistance to another by applying voltage.

• Many types of RRAM. Metal Oxide RRAM most popular focus of this talk.


What is RRAM?

Simple materials, but still good switching:

Key reason for the excitement about RRAM

Single cell @ 45nm node

Phase Change Memory

STT-MRAM RRAM

Materials TiN/GeSbTe/TiN Ta/PtMn/CoFe/Ru/CoFeB/MgO/CoFeB/Ta

TiN/Ti/HfOx/TiN

Write Power 300uW 60uW 50uW

Switching Time

100ns 4ns 5ns

Endurance 1012 >1014 1010

Retention 10 years, 85oC 10 years, 85oC 10 years, 85oC

Ref: PCM – Numonyx @ IEDM’09, MRAM: Literature from 2008-2010, RRAM – ITRI @ IEDM 2008, 2009


RRAM Switching Mechanism

Filamentary switching with oxygen vacancies

Before FORM After +4V FORM After -2V RESET After +2V SET

HfO2

Electrode

TiN

HfO2

Electrode

TiN

HfO2

Electrode

TiN

HfO2

Electrode

TiN

Ultra-high Z

>1GΩ Low Z

~10kΩ

High Z

~1MΩ

Low Z

~10kΩ

Image of a filament

Ref: D-H. Kwon, et

al., Nature Nanotechnology,

2010.

TiN


Most Major Players Developing RRAM

Japan

Panasonic

Renesas

Fujitsu

Korea

Samsung

Hynix

China

SMIC

Taiwan

TSMC

UMC

ITRI

Macronix

EU

IMEC

ST US

Micron

SanDisk

Rambus

Adesto

Atmel

HP

Microchip

Crossbar


Transient current control during SET crucial for RRAM…

Ref: [1] Y. Sato, et al., TED 2008

Filament

size

determined

by SET

current


Status

Bipolar RRAM Devices Repeatable Results

Write Voltage <2.5V

Write Current ~20-100µA

Switching Time <10ns

Endurance 105

Data Retention at 85oC 1 year for 20-50µA

10 years for 100µA

What type of products can benefit from this memory device?

And what can happen as the memory device improves?


RRAM as an Embedded Non-Volatile Memory


First commercial adoption of RRAM as an Embedded Non-Volatile Memory…


Embedded NVM: Reasons for Commercial Interest

Our estimation for a

65nm e-NVM macro

RRAM Cypress

SONOS

4Mb macro size 1.4mm2 2.5mm2

Power for write 0.8mA 10mA

Read cycle 40ns 28ns

Write time for 4kb 4.3ms 10ms

Retention 85C 10 yrs 85C 10 yrs

Added masks 3 3

Maturity Low High

RRAM worst-case write power: 70uA, 2V, 32 pulses of

30ns each

Lower power

2-3V instead of 7.5-15V

20% lower cost vs. eFlash

(3 extra masks vs. 10)

BEOL Memory Good compatibility with

Finfets, HKMG Reuse standard SoC IP blocks

10-100x faster write time

vs. eFlash

Retention: 85oC 10yrs (products),

110oC 10 yrs (research). Not as good as eFlash yet


IoT Expected to Drive Adoption of RRAM

MCUs with embedded NVM the

workhorse for IoT.

Power, cost RRAM a much better fit than eFlash


Common RRAM cells pursued for eNVM

TiN

Conductive TaOx

HfO2

TiN

Old Rambus cell: pioneered the concept of using a Conductive

Metal Oxide [@ NVMTS, Nov 2008]

Ir

Ta2O5

Conductive TaOx

Electrode

Panasonic

[@ IEDM, Dec. 2008]

Pt

Conductive Metal

Oxide (eg. PCMO)

ZrO2

Pt

Rambus’ latest fab-friendly cell,

focused on

eNVM [@ IEDM 2014]

TiN

Ti

HfO2

TiN

ITRI

[@ IEDM 2008]


Challenges for RRAM to be “an Industry-Standard eNVM”: (1) Data Retention at 125oC, and hopefully 150oC

110oC

• Consumer,

Communication: 85oC

• Industrial: 125oC

• Automotive: 150oC

Product-stage: 85oC

Research-stage: 110oC

[Source: Panasonic, IMW 2012]

Paths to boost retention

• Reduce defects in HfO2

less vacancy diffusion

or generation

• Dope or modify HfO2

less oxygen diffusion

• Sophisticated FORM

algos, etc Revenues of different MCU market segments, 2012


Challenges for RRAM to be “an Industry-Standard eNVM”: (2) Competitive Cell Sizes at Smaller Nodes

Max oxide

voltage = 4V

Oxide

breakdown a

challenge

70µA write 28nm 65nm 130nm

Max. FORM voltage

with core FET

1.9V 3.3V 5.9V

Selector

I/O FET

Core FET

I/O FET

Core

FET

Cell Size for

1T-1R RRAM

0.066um2

0.3-

0.46um2

Cell Size for eFlash 0.045um2 0.14um2

0.3-

0.45um2 FORM bias for 10us

pulses at 85oC Trailing edge nodes

1T-1R RRAM good

Leading edge

nodes need

innovation

Note: Quoted cell sizes are for shared SL/contact architectures. Picture shown above simplified.


Challenges for RRAM to be “an Industry-Standard eNVM”: (2) Competitive Cell Sizes at Smaller Nodes

Solutions to tackle the

cell size problem:

• Lower write currents

(eg) using conductive metal

oxide electrodes, other

ideas…

• Alternative architectures:

- Vertical BJT-based [ITRI, IEDM 2010]

- Rambus array architecture, not published yet


RRAM as a Standalone Memory


3D RRAM as a NAND-Replacement

Bipolar RRAM:

Results for

Single Cells

Today’s Status Target for

NAND-

Replacement

Write Voltage <2.5V <2.5V

Write Current ~20-50µA <2µA

Switching Time <10ns <100ns

Endurance 105 103

Data

Retention

1 year 1 year

Array

Architecture

TBD

Reduced industry

emphasis on this now

since:

(1) 3D NAND has won

(2) Technical

challenges of 3D

RRAM for storage


3D RRAM as a Storage Class Memory

Motivation

Cost per bit gap between

NAND and DRAM

increasing

SCM great for big

data


RRAM’s applicability as a SCM

Minimum Required

Bit-level Endurance

109

Bit-level Retention

5 days

Chip Latency 200ns-1µs

Write current <5µA

Cost per Bit Between DRAM

and Flash

Requirements for SCM

[Source: ITRS, private comm.]

Single memory device that can meet ALL requirements still under

development… but things look feasible


Architectures for 3D RRAM: (1) 3D Crosspoint Memory

Multiple layers of memory made with the same set of litho steps keeps litho cost down

(eg) 30 layers of memory in a 8F2 footprint 0.25F2

The key challenge: • Multiple memory devices share a transistor selector, so sneak leakage paths possible • Makes read and write difficult. Complicates RRAM device design significantly.

RRAM dielectric (eg) ZrO2 Top electrode (Local BL)

Deposit bilayers of WL

(eg. W) and SiO2

Hole etch

(Shared litho step)

Deposit RRAM

Dielectric

Deposit Top Electrode,

Which serves s the

Local BL


Architectures for 3D RRAM: (1) Crosspoint Memory (contd.)

While these silicon results look reasonable, a long way to go to get a product

Our memory device could tackle sneak paths and have sub-1µA write, but couldn’t meet 109 cycles endurance + 5 day retention

64Mb crosspoint chip, ISSCC 2010

Silicon results from Unity Semiconductor (now Rambus)

Needed specially optimized memory devices and circuits to avoid sneak paths


Architectures for 3D RRAM: (2) 3D 1T-1R RRAM

(a) Deposit

multiple SiO2/poly Si layers. Or use ion-

cut to make SiO2/c-Si layers.

(b) Pattern

(shared litho step)

(c) Form gate of select

transistors

(shared litho step)

(d) Pattern SL, then silicide

(shared litho step)

(e) Form RRAM dielectric and

electrode for multi-level 1T-1R cells.

(shared litho step)

(g) Form BLs

Ref: D. C. Sekar, IEEE S3S 2014,

invented with Zvi Or-Bach


Architectures for 3D RRAM: (2) 3D 1T-1R RRAM

• At the 20nm node, effective cell size for 15 memory layers is 5x lower than DRAM

• Early days for this architecture still… Benefit is that it does not have sneak path issues

Junction-free transistor selector, like 3D NAND.


Conclusions


Conclusions

• RRAM making it into the marketplace, as an Embedded NVM. Has important

implications for IoT

• 3D RRAM actively researched as a storage-class memory. Still a fair bit of work to

do to make it to the product stage…

Our estimation for a

65nm e-NVM macro

RRAM Cypress

SONOS

4Mb macro size 1.4mm2 2.5mm2

Power for write 0.8mA 10mA

Write time for 4kb 4.3ms 10ms

Retention 85C 10 yrs 85C 10 yrs

Added masks 3 3

Rambus’ 64Mb 3D RRAM chip

ISSCC 2010

Thank You


Backup slides


The Non-Ohmic Device (NOD) Approach: Some Candidates

30

Diode selectors

Punch-through diodes MIM

(npn, MSM, oxides)

Other switching materials as selectors

OTS MIEC

[Mihnea, Sekar, et al.] SanDisk, US Patent

8274130

[A. Kawahara, et al.]

Panasonic, ISSCC 2012

[D. Kau, et al.]

Intel, IEDM 2010

[G. Burr, et al.] IBM, VLSI 2012


Why the NOD approach has largely lost traction in memory companies today

After 5-10 years of research, yet

to find a NOD which: • Drives high current • Gives low leakage for

unselected cells during FORM and regular write

• Gives 1013 read endurance

I-V curve of a hypothetical good diode

Date post:	16-Jul-2015
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RRAM Status and Opportunities

Engineering