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S. Saha and B. Gadepally
Technology CAD: Technology Modeling, Device Design and Simulation
S. Saha and B. Gadepally
2004 VLSI Design Tutorial, January 5, 2004 Mumbai, India
S. Saha and B. Gadepally
Coordinator: Prof. Bhaskar GadepallyAdjunct Prof., Electrical Engineering, IIT BombayChairman, Reliance Software Consulting, Inc.155 E. Campbell Ave., Campbell, CA 95008 (USA)[email protected]
2004 VLSI Design Tutorial, January 5, 2004Mumbai, India
Technology CAD: Technology Modeling, Device Design and Simulation
S. Saha and B. Gadepally
Instructor: Dr. Samar SahaSilicon Storage Technology, Inc.1171 Sonora CourtSunnyvale, CA 94086 (USA)[email protected]
2004 VLSI Design Tutorial, January 5, 2004Mumbai, India
Technology CAD: Technology Modeling, Device Design and Simulation
S. Saha and B. Gadepally 4Mumbai, India
Tutorial Outline
• Prof. B. Gadepally:
– Introduction and Tutorial Overview.
• Dr. S. Saha:
– Front-end Process Technology CAD (TCAD) Models and Process Simulations
– Device TCAD Models and Device Simulations
– Industrial Application of TCAD
Calibration of Process and Device Models
– Industrial Application of TCAD in
Device Research
Compact / SPICE Modeling.
Bhaskar Gadepally
Technology CAD: Technology Modeling, Device Design and Simulation
Introduction and Tutorial Overview
2004 VLSI Design Tutorial, January 5, 2004 Mumbai, India
Bhaskar Gadepally 6Mumbai, India
Overview of IC Technology
• In the past three decades:
– device densities have grown exponentially
– device and technology complexities have increased significantly
– design constraints are many-fold:
ultra thin oxide
interconnect
power supply
– technology development cost has increased enormously.
Bhaskar Gadepally 7Mumbai, India
Overview of IC Technology
Channel Engineering - non-uniform channel doping - Quantum Mechanical effects - low-diffusivity impurities - threshold voltage control
Source-Drain Engineering - ultra-shallow extensions - low-energy implants - RTA/LTA techniques - halo optimization
p-substrate
p-well n-well
n+
PMOS
n+ p+p+STI
Halo
P+ polySpacer
NMOS
STI(ShallowTrench Isolation)
Gate Engineering: Dielectric - ultra-thin gate oxide - direct tunneling - high-k dielectrics
Gate Engineering: Stack - dual-poly / poly depletion - work function engineering - interface properties
N+ poly
Bhaskar Gadepally 8Mumbai, India
Overview of IC Devices
• New device and device physics are continuously evolving:
– nano-scale devices
– microscopic diffusion
– quantum mechanical carrier transport
– molecular dynamics
– quantum chemistry
– high-frequency interconnect behavior.
Bhaskar Gadepally 9Mumbai, India
Technology CAD
• With the increased complexities in IC process and device physics:
– intuitive analysis is no longer possible to design advanced IC processes and devices
– TCAD tools are crucial for efficient technology and device design
to quantify potential roadblocks
to indicate new solutions
for continuos scaling of devices.
Bhaskar Gadepally 10Mumbai, India
Technology CAD
• Scope of TCAD:
– front-end process modeling and simulation implant, diffusion, oxidation etc.
– numerical device modeling and simulation I - V, C - V etc. simulation
– topography modeling and simulation deposition, lithography, etching etc.
– device modeling for circuit simulation compact / SPICE modeling
– interconnect simulation capacitance, inductance etc.
Bhaskar Gadepally 11Mumbai, India
Tutorial Objective
• Offer insight into the physical basis of TCAD, especially, bulk-process and device TCAD.
• Describe systematic methodologies for an effective application of TCAD tools.
• Describe systematic calibration methodology for predictive usage of TCAD tools:
– process models
– device models.
• Offer users sufficient insight to leverage new tools.
Bhaskar Gadepally 12Mumbai, India
Session 1: Bulk-Process Simulation
• Front-end process models implemented in process TCAD tools:
– ion implantation models analytical Monte Carlo
– microscopic diffusion models point defects
– oxidation transient enhanced diffusion.
Bhaskar Gadepally 13Mumbai, India
Session 2: Device Simulation
• Device models implemented in device TCAD tools:
– fundamentals of carrier transport
drift-diffusion solution
hydrodynamic solution
carrier mobility models
– device physics of nanoscale technology
inversion layer quantization
– fundamental limits of MOSFETs.
Bhaskar Gadepally 14Mumbai, India
Session 3: Industry Application
• Introduction to process and device simulation tools.
• Mesh generation.
• Model selection.
• Predictive usage of TCAD:
– process model calibration
– device model calibration.
• Predictive simulation of CMOS technology.
Bhaskar Gadepally 15Mumbai, India
Session 3: Industry Application - Calibration
Calibration Effort
TD
Eff
ectiv
enes
s
Low Moderate High
Low
Mod
erat
eH
igh
No or a limited
calibration only
provides some
physical trends
and is useful
for a first-orderprocess and
device analysis.
Global calibration
provides higher
accuracy and
predictability of
simulation data.Local calibrationwith the previousgeneration oftechnology willprovide physicaltrends. Absolutevalues may notmatch real data.
Bhaskar Gadepally 16Mumbai, India
Session 4: TCAD in Research & Modeling
• Simulation tools in device research:
– simulation structure
– model selection
– examples
sub-100 nm MOSFETs
DG-MOSFETs - FinFETs.
• TCAD in device (compact) modeling:
– examples
substrate current model
flash memory cell macro-model.
Samar Saha
Technology CAD: Technology Modeling, Device Design and Simulation
Bulk-Process Simulation
2004 VLSI Design Tutorial, January 5, 2004 Mumbai, India
Samar Saha 18Mumbai, India
Outline
• Introduction.
• Bulk-process Models:
– Ion Implantation
– Diffusion
– Oxidation.
• Summary.
Samar Saha 19Mumbai, India
Introduction
• Front-end IC fabrication processes include:– implant: S/D and halo (low energy); well (high energy) etc.
– diffusion: Rapid thermal annealing (RTA) Transient Enhanced Diffusion (TED) and other anomalous effects
– oxidation: gate oxide, STI liner oxide etc.
p-substrate
p-well n-well
n+
PMOS
n+ p+p+STI
Gate oxide
Halo
P+ polySpacerN+ poly
NMOS
STI(ShallowTrench Isolation)
Source Source DrainDrain
Samar Saha 20Mumbai, India
Introduction
• Objective of this session:
– understanding of physical models implemented in a process TCAD tool
model hierarchy
model limitations
building new models
– basic understanding of general purpose simulator internals
– TCAD models in general without considering any particular tools.
Samar Saha 21Mumbai, India
Ion Implantation
• Ion Implantation Mechanisms.
• Ion Implant Models:
– Analytical
– Monte Carlo (MC).
• Implant-induced Damage Modeling.
• “Plus-one” Approximation.
• Summary.
Samar Saha 22Mumbai, India
Ion Implantation
• Bombard wafers with energetic ions energy, E 0.5 KeV - 1 MeV > Ebinding.
• Ions collide elastically with target atoms creating:– ion deflections, energy loss– displaced target atoms
(recoils).
• Ions suffer inelastic drag force from target electrons– ion energy loss– lattice heating.
Ion
Target
Rec
oil
channeling
Samar Saha 23Mumbai, India
Ion Implantation
• Channeling is caused by ions traveling with few collisions and little drag along certain crystal directions.
• Ions come to rest after losing all the energy on:
– elastic collisions (nuclear stopping)
– inelastic drag (electronic stopping).
Ion
Target
Rec
oil
channeling
Samar Saha 24Mumbai, India
Ion Energy Loss Mechanisms
• Nuclear stopping (Sn(E)):
– ion energy loss to target atom by interaction with the electric field of the target atom’s nucleus
– classical relationship of two colliding particles
– the scattering potential with the exponential screening function is given by
where Z1 = atomic number of incoming ion
Z2 = atomic number of target atom.
e a
r
ibarV i
r4ZZq
)( 1 2
2
DeflectedIon
Target
Recoil
Ion
Samar Saha 25Mumbai, India
Ion Energy Loss Mechanisms
• Electronic stopping (Se(E)) is due to the viscous drag force on moving ion in a dielectric medium.
EZZkS ee ,..., 21
– ke is a model parameter.
• Accurate model must account for the variation of Se in space.
• Stopping power S of an ion is given by:
electronicnuclear dx
dE
dx
dES
Samar Saha 26Mumbai, India
Ion Range Distribution
• Ions come to rest over a distribution of locations.
• Peak, depth, and lateral spread of distribution are determined by:
– ion mass, energy, dose, and incident angle
– target atom, composition, geometry, structure, and temperature.
• Implanted profile can be represented by:
– particles
– distribution functions.
Samar Saha 27Mumbai, India
Ion Range Distribution
Samar Saha 28Mumbai, India
Ion Range Distribution
• The as-implanted 1D distribution function is described by a series of coefficients called moments.
• 2D distribution of the implanted profile is constructed from 1D distribution function taking lateral spread
vertical spread.
Samar Saha 29Mumbai, India
1D Analytical Ion Implantation Models
• Gaussian distribution:
– amorphous targets
– two coefficients
where
Q = implant dose (#/cm-2)
Rp = projected range normalized first moment
p = straggle/standard deviation second moment.
2
2
2exp
2)(
p
p
p
RxQxN x
Rp
N
Samar Saha 30Mumbai, India
1D Analytical Ion Implantation Models
• Pearson-IV:
– crystalline targets without channeling
four coefficients (Rp, p, skewness, kurtosis)
– crystalline targets with channeling, tilt, and rotation.
six coefficients.
• Dual Pearson-IV:
– crystalline targets with channeling, tilt, and rotation
– second profile to model the channeling
– nine coefficients.
• Legendre Polynomials - 19 coefficients.
Samar Saha 31Mumbai, India
1D Analytical Ion Implantation Models
• Coefficients are fit to the measured doping profiles.
• Coefficient-set for each distribution is tabulated for different:
– ion mass (As, B, In, P, Sb)
– dose, energy, tilt, and rotation
– target type.
• Multi-layer targets:
– each material is treated separately and scaled by its Rp.
– dose absorbed on the top layer is calculated and is used as the dose matching thickness for the layer below.
Samar Saha 32Mumbai, India
2D/3D Analytical Ion Implantation Models
• Each 1D profile along a vertical line is converted to 2D or 3D distribution by multiplying it by a function of lateral coordinates:
here lateral straggle, l p
• Multi-layer targets and sloped surfaces are converted to 2D/3D by dose matching approach.
• More complex models have l(x).
• Low energy profiles need non-separable point-response functions.
l
l
y
xNyxN
2
2exp
)(),(
2
1
Samar Saha 33Mumbai, India
Monte Carlo Modeling of Ion Implantation
• The collision energy loss is modeled by binary collision approximation (BCA), that is, each ion collides with one target atom at a time.
• The energy loss (E) is modeled in terms of:– incident energy, E0 and scattering angle, 0 of ion
– separation between two particles
– coulomb potential between two particles
– impact parameter.
• BCA requires special formulation for:– ion channeling
– low energies when lattice movements come into play.
Samar Saha 34Mumbai, India
Monte Carlo Modeling of Ion Implantation
• Ongoing development in MC modeling is to improve:– speed of calculations
– electronic stopping power, Se model
detailed local model for Se
local and non-local split in energy loss due to Se
where
fnl = fraction of non-local energy split
a = universal screening length
p = impact parameter.
• Overall accuracy of MC implant model is excellent.
enl
nl Sa
p
a
fNLfE
exp
2
12
Samar Saha 35Mumbai, India
Ion Channeling in Crystalline Silicon
• Along certain angles in crystal, ion may encounter no target atoms.
Ion• Repeated small-angle
collisions steer the ion back into the channel.
• Channeling was first discovered by MC simulation.
• Channeling is: – important at any energy
– critical at low energy where <110> channels steer Boron ions under MOS gate.
• Analytic channeling model is complex.
Samar Saha 36Mumbai, India
Ion Channeling in Crystalline Silicon
Samar Saha 37Mumbai, India
Damage Creation Models
• Each incoming ions generates damage seen by subsequent ions:– recoils target atoms knocked out of lattice sites
– amorphous pockets.
• The effect of damage is significant on as-implanted profile as well as during subsequent diffusion.
• Models based on Kinchin-Pease formulation is used to estimate damage density: n = Er/2Ed
where Er = recoil energy
Ed = target displacement energy (~ 15 eV for Silicon).
Samar Saha 38Mumbai, India
“Plus-one” Damage Model
• Most recoiled interstitials (I) find a vacancy (V) and recombine rapidly either during the implantation or the first instants of annealing.
• Distribution of remaining recoils shows:
– net excess of V near the surface
– net excess of I toward bulk.
• At low ion mass and/or moderate energy:
– population of net I and net V is less than the population of I due to dopant atoms taking substitutional sites
– one “extra-ion” is created for each dopant atom taking a substitutional site.
Samar Saha 39Mumbai, India
Deviation from “Plus-one” Model
• “Plus-one” approximation often fails for:
– heavy ions
as the population of recoils can become quite large relative to extra ion population
– low energy
– low dose.
• An effective “plus-n” factor as a function of ion species, energy, and dose is used. Typical values:
As: n 3.5 @ E 5 KeV; n 1.2 @ E 500 KeV
B: n 1.2 @ E 5 KeV; n 1.0 for E > 20 KeV
P: n 2.2 @ E 5 KeV; n 1.0 @ E 500 KeV.
Samar Saha 40Mumbai, India
Ion Implantation: Summary
• Ion implantation with ion energy > Ebinding of target atoms is used to implant impurity atoms into target.
• Analytical ion implantation model:
– the impurity profile is represented by moments for different species, dose, energy, tilt, and rotation
– the moments are extracted from the experimental profile to create look-up table
– simulation is performed using this look-up table.
• MC ion implantation model is more accurate, particularly for low energy.
• The implant damage is modeled by “plus-n” model.
Samar Saha 41Mumbai, India
Diffusion
• Fundamentals of Dopant Diffusion– Fick’s Laws
– Oxidation Enhanced Diffusion (OED)
– Oxidation Retarded Diffusion (ORD)
– Transient Enhanced Diffusion (TED).
• Point Defect Model.
• Clusters and Precipitates.
• Polysilicon Diffusion.
• Impurity Profiling.
• Summary.
Samar Saha 42Mumbai, India
Fick’s Laws of Diffusion
• Fick’s first law:– describes flux (F) through any surface
– diffusion is downhill - high low concentration, “- sign”
• Fick’s second law law of conservation of particles
• Low concentration diffusion in silicon is Fickian - each dopant A satisfies:
CDx
CDF
Ft
C.
ADt
CA
A 0.
Fin Fout
x
C
(D diffusivity = constant)
Samar Saha 43Mumbai, India
Concentration-Dependent Diffusion
• Typically, intrinsic carrier concentrations (ni) at processing temperatures are high 1019 cm-3.
• For high doping concentrations, C ni, dopant diffusion shows enhancements of the form:
• Diffusion enhancement is due to the variation of point defect population with Fermi level.
• The effective extrinsic diffusivity is given by:
iii n
pc
n
nb
n
na
D
D2
01
;2
imm
im
ipx n
nD
n
nD
n
pDDD
mmmpxo DDDDD
where
Samar Saha 44Mumbai, India
Surface Effects on Bulk Diffusion: OED/ORD
• Experimental data show that processes which modify the surface can affect diffusion in the bulk.
• Enhancement of diffusivity in one species while retardation in another is the evidence of two different diffusion mechanisms I and V.
Diffusion processSpecies /defects Oxidation Oxinitridation Nitridation
B, P, I Enhanced Enhanced RetardedAs Enhanced Enhanced Enhanced
Sb Enhancedthen retarded
Enhancedthen retarded
Enhanced
StackingFaults
Grow Grow Shrink
Samar Saha 45Mumbai, India
Transient Enhanced Diffusion (TED)
• Anomalous displacement of implanted dopants during low temperature anneals.
• Reverse temperature effect: displacement larger at lower temperatures - up to 0.3-0.4 m.
• Displacement increases with implant dose and energy.
• Corresponds to temporary increase in diffusivity ~ 10,000X.
• Implant of one species can drive diffusion of another.
• Enhancement is transient.
• Spatially non-uniform diffusion enhancements.
• Reduced activation.
Samar Saha 46Mumbai, India
Transient Enhanced Diffusion (TED)
• As implanted over a buried B layer.
• As implant creates damage deep into the substrate.
• The implant damage causes a significant enhancement in B diffusion deep into the substrate during 20 sec. anneal at 850 °C.
Simulation results
Samar Saha 47Mumbai, India
Point Defect Model for Dopant Diffusion
• Point defects (I and V) model explains:
– most of the observed trends in dopant diffusion by relating them to the properties of I and V
– “action-at-a-distance” effect of the surface on bulk diffusion.
Vacancy mechanism As, Sb
Kick-out mechanism B, P, In, As, Au, Zn, P
above 900 °C
Frank-Turnbullmechanism
Zn, below 900 °C
Samar Saha 48Mumbai, India
Defect Charge States
• Defects which have states in the gap will have a distribution of charge states.
• The concentration of charged point defects depends on Fermi level.
• Dopants can diffuse with any of the defect charge states, some combinations have higher probability.
• In principle, must solve a set of: PDEs one for each combination.
• “Five-stream” diffusion model solves equations:
• “Three-stream” model solves equations.
echdefectdopant NNN arg
echdefectdopant NNN arg
echdopantdefectdopant NNNN arg
defectdopant NN
Samar Saha 49Mumbai, India
“Electric-field” Effects
For high doping concentration > ni at the processing temperature, the electric field set up by ionized dopants affects diffusivity.
Example: As + B co-diffusion
at 900 °C, 15 min.
B- pulled towards the N+ region due to e-field effects.
Samar Saha 50Mumbai, India
Generation/Recombination of Defects
• General flux model:
where = fraction of silicon atom injected
– Vm = silicon atom/cm3
– assumed generation growth rate, G.
– recombination rate surface excess I - I* and increases under a growing surface.
• Lateral diffusion of defects during OED is governed by the ratio of DI/Kinert 10 m.
recgensurf FFF
).()(1
,
**
0
0
IIKIIG
GKKF
G
GGVF
total
k
rinertrec
g
mgen
Samar Saha 51Mumbai, India
Surface Generation/Recombination
• During OED, recombination/generation fluxes are large and must balance:
• Fixed interstitial super-saturations, also, occur under nitride, silicide surfaces.
• During TED, recombination appears to be fast, even at inert surfaces, recombination rate:
• Several models are available.
• Optimize Kinert for TED and adjust to fit OED at the
expense of lateral OED decay length.
total
gen
K
FII *
.1.0 mKD inertI
Samar Saha 52Mumbai, India
Gradient Effects in Transient Diffusion
• Dopant flux arises from diffusion of defects-dopant pairs:
boron flux = DBI[BI].
• Number of pairs is proportional to the boron and interstitial concentrations:
boron flux = DBIkpair(IB + BI)
where IB = interstitials enhance boron diffusion I = boron diffusion due to defect gradient
• During TED, I is large near the surface causing:– extra dopant flux to the surface– surface pile-up (and possible interface loss) of dopant.
Samar Saha 53Mumbai, India
Interstitial Clustering Model
• The growth and dissolution is given by:
where kd is the decay constant
kc is the growth constant
C = concentration of clustered interstitials
I = concentration of unclustered interstitials.
• After implantation I is large, C/t = C(kcI) clusters grow exponentially until I = kd/kc.
• When I is small, clusters decay exponentially with time constant 1/kd.
CIkCkt
Ccd
Samar Saha 54Mumbai, India
{311} Cluster Dissolution
• {311} defects:
– rod-shaped defect clusters condensed from “+1” amount of damaged silicon-I at annealing T > 400 °C
– precipitate on {311} planes and extend in the <110> directions to form planar defects.
• Time scale for {311} evaporation is similar to the time scale for TED.
• Simple reaction-based model offers first-order account of evaporation curve.
• Steady super saturation of dopant diffusion is observed during TED.
Samar Saha 55Mumbai, India
Dopant Clustering/Precipitation
• Dopants are only soluble up to a limit at any temperature (solid solubility limit).
• Dopants also show deactivation below the solid solubility limit.
• Due to the clusters of size m dopant atoms such as As with m = 4,
– clustering reaction emits interstitials to generate required V.
Can generate enhanced diffusion at the same level as TED.
As
V As
As
As
Samar Saha 56Mumbai, India
Chemical Pump Effects
• Dopant atom A interacting with I form A + I AI interstitial-assisted mobile species.
• When AI pairs diffuse out of a region of high I* to a region of low I*, pairs are out of equilibrium and must dissociate, AI A + I.
• A is deposited while I diffuses (“pumped”) away from the surface enhancing diffusion in bulk.
• Surface dopant layer may cause enhanced diffusion in bulk - e.g. D/D* = 70 at 900 °C.
• Causes cooperative diffusion, e.g. emitter push effect in bipolar junction transistors.
Samar Saha 57Mumbai, India
Diffusion in Polysilicon
• Point defects usually pinned near equilibrium in poly due to grain boundaries.
• Dopants diffuse in two streams via grain and in boundary.
• An effective model includes:– two streams
– dopant transfer from grain to grain boundary
– grain growth with time
– dopant transfer to grain boundary.
• Segregation coefficient, growth rate, and re-growth rate = f(temperature, grain size, Fermi level).
Samar Saha 58Mumbai, India
Metrology for Developing Diffusion Models
• Spreading resistance profile (SRP)
– 1D carrier profiles
– good sensitivity
– modest depth resolution
– carrier spilling
– difficult to use for shallow junctions.
1.E+15
1.E+16
1.E+17
1.E+18
1.E+19
1.E+20
1.E+21
0.0 0.2 0.4 0.6 0.8 1.0 1.2Depth (m)
Lo
g(C
on
cen
trat
ion
(cm
-3)) n
p
Samar Saha 59Mumbai, India
Metrology for Developing Diffusion Models
• Secondary Ion Mass Spectroscopy (SIMS)– 1D chemical profiles
– good sensitivity to all dopants
– excellent depth resolution
– surface region troublesome.
• 2D carrier profiling with excellent space resolution:– scanning capacitance microscopy (SCM)
measurement affects sample
– transmission electron holography (TEH) measures electrostatic potential
difficult sample preparation.
Samar Saha 60Mumbai, India
Monte Carlo Diffusion Methods: Algorithm
Monte Carlo diffusion program (MARLOWE, UT-Austin) offersaccurate diffusion modeling.
MARLOWEGenerates initial I, V positions
THEORETICALCALCULATIONS
Energy of interactionsand
diffusion barriers
EXPERIMENTS
MONTE CARLO DIFFUSION CODE
- Diffusion - Clustering - I - V recombination - Surface annihilation - I, V trapping - Boron kick-out, kick-in
Samar Saha 61Mumbai, India
• Diffusion is critical to activate the implanted dopants in the semiconductor devices.
• Dopants diffuse in silicon by interacting with point defects through a number of possible atomic-scale mechanisms.
• For short times, the diffusion is dominated by TED because of high concentration of point defects.
• Point defect concentrations depend on temperature, Fermi level, implant damage, and surface processes like oxidation.
• 1D/2D metrology is used to calibrate diffusion model.
Diffusion: Summary
Samar Saha 62Mumbai, India
Oxidation
• Fundamentals of Thermal Oxidation.
• Oxide Growth Model:
– Deal-Grove Model
– Thin Oxide Model.
• Oxidation Chemistry.
• Oxide Flow:
– Oxidation-induced Stress
– Visco-elastic Model.
• Summary.
Samar Saha 63Mumbai, India
Oxidation: Diffusion, Reaction, Flow
• Oxidation proceeds by three sequential processes:– oxidant diffuses through existing oxide
– oxidant reacts at silicon surface to create new oxide
– overlying oxide flows to accommodate new volume.
• Process is at first limited by reaction but diffusion through growing oxide becomes limiting.
O2 or H2O ambient
Oxidant
Reactionzone
Nitride
Silicon
Samar Saha 64Mumbai, India
Oxidation: Deal-Grove Model
C0
CL
SiliconSiO2
L
CCDF L
diff0
Freac = kCL
D = diffusivity of oxidant
CL = concentration at Si-SiO2 interface
C0 = concentration at the SiO2 surface
L = oxide thickness
k = interface reaction rate constant
Samar Saha 65Mumbai, India
Oxidation: Deal-Grove Model
C0
CL
SiliconSiO2
L
CCDF L
diff0
Freac = kCL
• At equilibrium: Fdiff = Freac, CL = C0 / [1 + kL/D]
• Oxidation growth rate is given by:
where
C* = equil. oxidant conc.; Ns = # oxidant/cm3 in oxide
BL
ABt
L21
1
ss NCkABNDCB *;*2
Samar Saha 66Mumbai, India
Thin Oxide Models
• Deal-Grove model does not fit the early part of oxidation curve.
• The data in thin regime can be fitted with an addition to Deal-Grove model given by:
where and
C0 3.6x108 m/hr, EA 2.35 eV, and 7 nm in
<111> or <100> oriented silicon substrates.
• This model can be found in TCAD tools like SUPREM4.
L
C
BL
ABt
Lexp
211
kT
ECC Aexp0
Samar Saha 67Mumbai, India
Oxidation - Planar Growth
• Two-step oxidation shows a significant difference in oxide density.
• Planar growth generates an intrinsic stress in oxide during growth process:– modest stress (3x109 dynes/cm2)– density increases (< 3%)– refractive index increases (1%) relative to fully relaxed
oxides.First oxidation
Second oxidation
1100 C 800 C
900 C900 C
L grown in the second step varies depending on the thermal history of oxide (not just on L).
Samar Saha 68Mumbai, India
Oxidation - Planar Growth
• Intrinsic stress is an atomistic process.
• Relaxes gradually with annealing at a rate which steadily decreases.
• Recent measurements show that relaxation rate is independent of stress level.
• History effects are not accounted for in most process simulators.
• Measured linear/parabolic coefficients describe oxidation in a state of intrinsic stress.
1D stress already accounted for in one-step oxidation.
Samar Saha 69Mumbai, India
Oxidation Chemistry
• Oxidation rate coefficients are sensitive to ambient additives:– steam 20 - 50 times faster than O2
– 3% Cl2 increases growth rate by 20 - 30%
– 100 ppm NF2 increases growth rate by 2 - 5
– heavy substrate doping increases rate by 2 - 10 according to the relation
– all easily accounted for by building table of B, B/A vs. additive or dopant concentration.
– NO, NO2 are not supported in most process TCAD tools.
2
0
iii n
nd
n
pc
n
nba
k
k
Samar Saha 70Mumbai, India
Oxide Flow
• Oxide growing on a curved surface must flow.
• Resulting deformations (and stresses) can be large! LOCOS top surface must stretch by 15 - 20%.
• Elastic limit of glass << 1%
Si3N4
Silicon
Oxide
Silicon
Old Oxide
New Oxide
Samar Saha 71Mumbai, India
Oxide Flow
• Large deformations on a curved surface during oxidation mean viscous flow must occur.
• Viscous flow model used to model stress during oxide growth includes:
– incompressible viscous flow
– linear elasticity.
• Visco-elastic flow model:
– allows oxide to be “slightly” compressible
– eliminates pressure equation
– offers a significant numerical benefit.
Samar Saha 72Mumbai, India
Visco-elastic Model: Stress Simulation
• Oxide stress after local oxidation.
• Length of stress vector amount of stress.
Compression
Tension
SiO2
Si3N4
Samar Saha 73Mumbai, India
Oxidation: Summary
• Basic growth mechanism of thermal oxide:– oxidant transport through the SiO2 layer to Si/SiO2
interface
– chemical reaction at the interface to produce the new layer of oxide.
• The growth is linear parabolic law.
• The basic Deal-Grove model is extended to explain:– thin oxide growth
– mixed ambient oxidation.
• Important effects of thermal oxidation include OED, ORD, and impurity redistribution and segregation.
Samar Saha 74Mumbai, India
Bulk-Process Simulation: Summary
• Accurate process models and TCAD tools are extremely critical for continuous scaling of IC’s .
• Workstation performance is continuously improving for cost-effective computer experiments.
• Existing models and TCAD tools treat different aspects of process simulation quite well.
• As new understanding develops, new models are incorporated in TCAD tools to improve predictability.
• Successful process TCAD will require a firm grasp of the controlling process physics.
Samar Saha
Technology CAD: Technology Modeling, Device Design and Simulation
Device Simulation
2004 VLSI Design Tutorial, January 5, 2004 Mumbai, India
Samar Saha 76Mumbai, India
Outline
• Introduction.
• Carrier Transport Models.
• Inversion Layer Mobility.
• Quantum Mechanical Confinement.
• Discrete Dopant Effects.
• Numerical Methods.
• Summary.
Samar Saha 77Mumbai, India
Introduction
p-substrate
p-well
n+n+
ST
I
Poly
ST
I
hot carriers
Non-local transport(velocity overshoot)
QM tunneling
Electrostatics: - 2D/3D effects - discrete charges
Atomicscale
effects
QM confinement
Surface scattering
Quasi-ballistic transport
• A device TCAD tool solves a set of equations to deal with various physical phenomena in semiconductor devices:
Samar Saha 78Mumbai, India
Introduction
• Objectives of this session is to:
– focus on the underlying physics and models for practical application of device TCAD such as
identify device physics issues for simulation
discuss and compare simulation approaches
identify
limitations
uncertainties
challenges.
Samar Saha 79Mumbai, India
Carrier Transport Models
• A device TCAD tool generates device characteristics by solving:
– Poisson’s [.D = (r)] + carrier transport equations self-consistently.
• Carrier transport models include:– drift-diffusion (DD) - standard
– Monte Carlo (MC)
– molecular dynamics
– hydrodynamic (HD)
– Boltzmann equation
– quantum balance equations.
Samar Saha 80Mumbai, India
Carrier Transport Models
• The basic concept in transport theory is the carrier distribution function = f(r,px,t).
• f(r,px,t) = probability of a carrier at the position r with momentum px at any instant t.
• f(r,px,t) is a Maxwellian distribution function with:– area = carrier density, n(r,t)
– the spread depends on carrier temperature
– first moment is velocity
– second moment is kinetic energy.
f(r,px,t)
pxEquilibrium
Samar Saha 81Mumbai, India
Carrier Transport Models
• At equilibrium, f(r,px,t) is symmetric around px = 0.
• If an e-field is applied along the negative px direction: – electron distribution is distorted and displaced from the
origin– causes electron scattering.
• Device TCAD challenge is to solve f(r,px,t).
f(r,px,t)
pxEquilibrium
f(r,px,t)
pxNon-equilibrium
x
Samar Saha 82Mumbai, India
Carrier Transport Models
• To solve for f(r,p,t) - Boltzmann Transport Equation (BTE):
– six dimensions
three in position space
three in momentum space
– solution techniques:
MC simulation
spherical harmonics
scattering matrix
and so on.
Samar Saha 83Mumbai, India
Carrier Transport Models
• Solving f(r,p,t), we can find the quantities that device engineers deal with directly such as:– carrier density, n(r,t)
– current density, Jn(r,t)
– energy current, JE(r,t)
– average kinetic energy, un(r,t)
– electron temperature, Tn(r,t)
– heat flux, Qn(r,t).
• Six-dimensional equation is difficult to solve and computationally demanding.
In TCAD, we directly solve for the quantities of interest.
Samar Saha 84Mumbai, India
Carrier Transport: Balance Equations
• Basic idea to solve for a quantity (n) of interest is to formulate a balance equation such as:– rate of increase in n= rate n flows into the volume + net
generation rate.
RGFt
n
Examples:
– n = n(x,t): continuity
equation.
– n = Jnx(x,t): current
equation.
R G
n
F
Samar Saha 85Mumbai, India
Carrier Transport Models
• Assuming slowly varying time, we can write the current equation:
where
= average time between collisions m* = effective mass of electrons.
• We need a balance equation for kinetic energy, uxx.
• For simplicity of computation:– approximate the effects of scattering in n
– close the balance equations by approximating uxx.
x
qnuqnJ xx
nxnnx
/2
*/)],,([ mqtprfn
Samar Saha 86Mumbai, India
Carrier Transport Models: Drift-Diffusion
• The simplest solution of carrier transport equation is local field or DD approach.
• In DD, is determined by scattering, scattering is determined by uxx, and uxx is determined by .
• For high fields in bulk silicon, (x) and uxx are constants or slowly varying:
here n = 0[N,TL,(x)]; Dn = (kBTL/q)n
• Then the current equation is given by:
Local field transport model: [n = f(local field)]
dx
dnTkxtxqntxJ nLBxnnx )(,,
Samar Saha 87Mumbai, India
Carrier Transport Models: Drift-Diffusion
• DD solution fails to predict device characteristics for small geometry ( 0.1 m) MOSFETs.
• We know:
here <> is related to the average carrier energy, un(Tn) and Tn = local electron temperature.
• Thus, the DD-transport model can be improved by assuming, n as a function of local energy.
Local energy transport model: n = f(local energy)
Alternatively, n = 0[N,TL,Tn]
*/)],,([ mqtprfn
Samar Saha 88Mumbai, India
Carrier Transport Models: Local Energy
• Solve for energy density, n = W(x,t) = nu:
whereE = relaxation time.
• n = JE(x,t):
• Unknowns: (x), n(x), p(x), un(x), and up(x)
dx
nDdqxnTkCtxJ n
xneBEEx
)()(,
E
xnxEx uun
xJdx
txdJ
)(
)(, 0
increase in energy flux
input e-field rate of energydissipation
Samar Saha 89Mumbai, India
Carrier Transport Models: DD vs. HD
DD vs. HD model data deviate significantly for 40 nm devices.
Samar Saha 90Mumbai, India
Macroscopic Transport Models: Summary
• Models are derived directly from BTE.
• Require numerous simplifying assumptions: closure, scattering.
• Difficult to assess the validity of assumptions.
• Many flavors: HD, energy transport (ET).
• Beyond DD, adds significant numerical complexity.
• HD/ET generally provide good estimates of:
– average carrier energy
– current density.
• Significant differences between various models.
Samar Saha 91Mumbai, India
Carrier Transport Models: MC Simulation
• MC is a rigorous transport model.
• The essence of the model is:
qdt
dp
electron
r1
r2
r3, r4
r1 r2
r3, r4
r1
r1: free flight duration
r2: scattering event
r3: direction after scattering r4
Samar Saha 92Mumbai, India
MC Simulation: Summary
• Advantages:
– numerical method for solving the BTE with e-e correlation
– advanced physics is readily treated (e.g. scattering and complete band structures)
– most reliable transport method for treating hot electron distributions and for assessing novel devices.
• Disadvantage:
– computationally demanding:
under near-equilibrium conditions
for examining rare events.
Samar Saha 93Mumbai, India
Carrier Transport Models: Quantum
• Different techniques available include:
(1) equilibrium or ballistic transport
simplest form is used for MOS capacitor simulation
(2) wave propagation with phase randomizing scattering
non equilibrium Green’s function approach (Wigner functions, density matrix)
(3) density gradient/QM potential approach
ErEm C )(
*22
n
n
qmnqDVnqJ
n
nnnn
2
*
2
6
Samar Saha 94Mumbai, India
Carrier Transport Models: Summary
• Drift-diffusion (local field model): = f(local field)
• Balance equations (mostly local energy): = f(local energy)
Examples: HD, ET, etc.
• Boltzmann solvers:– MC
• Quantum transport:– Schrodinger-Poisson
– density gradient / quantum potential.
Samar Saha 95Mumbai, India
Inversion Layer Mobility
• Choice of mobility model can significantly alter the simulation results.
• Inversion layer mobility versus effective normal electric field show well-known characteristics:
– high fields: universal behavior independent of doping density.
– low fields: dependent on 1) doping density and 2) interface charge.
universal behavior
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Inversion Layer Mobility
• Mobility versus effective normal electric field curve is modeled using three components:– coulomb scattering (due to ionized impurity)
– phonon scattering - almost constant
– surface roughness scattering (at Si/SiO2 interface).
• At low normal fields: – less inversion charge density
– ionized impurity scattering dominates and eff = f(NA).
• At high normal fields:– higher inversion charge density close to the interface
– surface roughness scattering dominates.
Samar Saha 97Mumbai, India
Inversion Layer Mobility
• For higher normal fields, universal behavior as a function of effective normal field:
• The effective field is a non-local quantity.
• Local field mobility models preferred for device TCAD should produce universal behavior in terms of the computed effective field.
– Example: Lombardi Surface Mobility Model.
deplSSi
eff NNK
q 5.0
Samar Saha 98Mumbai, India
Inversion Layer Mobility
• For ultra-thin gate oxide thickness the inversion layer carrier wave function can extend through Si/SiO2 interface to SiO2/polysilicon interface.
• Mobility may depend on the surface roughness of SiO2/polysilicon interface “remote interface roughness” scattering.
p-substrate
p-well
n+n+
ST
I
NMOS
ST
I
Poly Gate OxideElectronwave function
Samar Saha 99Mumbai, India
Choice of Surface Mobility Models
Samar Saha 100Mumbai, India
Inversion Layer Mobility: Summary
• Mobility is extremely critical for advanced MOSFET device simulation.
• Choice of mobility model can effect simulation data.
• Local field mobility models are being extended for high normal fields and high doping densities.
• New effects may begin to be felt in ultra-thin oxide devices
– Example:
remote interface scattering.
Samar Saha 101Mumbai, India
Quantum Mechanical Confinement
• The charges near the silicon surface are confined to a potential well formed by:
– oxide barrier
– bend Si-conduction band due to applied gate potential.
• Due to QM confinement of charges near the surface:
– energy levels are grouped in discrete energy sub-bands
– each sub-band corresponds to a quantized level for carrier motion in the normal direction.
EC(y)
Depth into Si (y)
EFEn
erg
y
Samar Saha 102Mumbai, India
• Due to QM confinement, the inversion layer concentration:
– peaks below the SiO2/Si interface
0 at the interface and is determined by the boundary condition for the electron wave function.
Quantum Mechanical Confinement
Depth into Si (y)
n(y
)
Classical
Quantumz
z = shift in the centroid of charge in silicon away from the interface.
Equivalent oxide thickness for z is:
zQMTSi
OXOX
)(
Samar Saha 103Mumbai, India
• Classical:– CSi >> COX (accumulation / inversion)
– Ctotal ~ COX (accumulation / inversion)
• Quantum:– CSi ~ Si/z
– Ctotal < COX (accumulation / inversion)
• Impact of QM confinement:– Vth since more band bending is required to populate the
lowest sub-band
– TOXeff since a higher VG over-drive is required to produce a
given level of inversion charge density
– Ctotal since TOXeff = TOX + (OX/Si)z.
Quantum Mechanical Confinement
Cox
CSi
Vgate
Samar Saha 104Mumbai, India
QM Confinement: Modeling Approach
• van Dort’s model: amount of band-gap widening due to splitting of energy levels is given by:
where
B = constant
y = distance from Si/SiO2 interface
yref = reference distance for the material
En = normal electrical field
and,
refnsemi
g yyFEkT
ByE /4
)( 3
23
1
)())(1( 2 yFenyFnn kT
ECLi
CLii
g
Samar Saha 105Mumbai, India
QM Confinement: Modeling Approach
• Modified local density approximation (MLDA):
– robust and efficient formulation to compute quantization of carrier concentration near Si/SiO2 interface
– offers a good compromise between the accuracy and simulation time
– the confined carrier density is given by FD statistics
)(
)()()()(
and,
2(1exp1
2)(
121
0
0
yN
ynkTFyEyEyE
yjkTE
dNyn
c
QMFcg
nF
CQM
Samar Saha 106Mumbai, India
QM Confinement: COX Reduction
0
3
6
9
12
-2.5 -1.5 -0.5 0.5 1.5 2.5Gate Voltage (V)
Ca
pa
cit
an
ce
(fF
/m
2 )
QM-effects
w/o QM-effects N(p-sub) = 5E17 (cm-3);Tox = 3 nm
Simulation data obtained by simulation program TSUPREM4
Samar Saha 107Mumbai, India
QM Confinement: TOX Measurement
4
5
6
7
8
2 3 4 5 6TOX (nm)
T
OX/T
OX (
%)TOX TOX
eff - TOX
Samar Saha 108Mumbai, India
QM Confinement: Effect on Vth
• Vth increase due to QM effect depends on channel doping, Nch.
Maximum increase in Vth~ 100 mV for Nch ~ 1x1018 cm-3.
0.00
0.02
0.04
0.06
0.08
0.10
0 5 10 15 20 25 30
Transition Depth (nm)
Vth
(QM
) - V
th(C
L) (V
)
nMOSFETs
Leff = 100 nm; Tox = 3 nm
VDS = 50 mV; VBS = 0
1e18uniform
1e17
GR
ARST
Nch
(cm
-3)
Transitiondepth
1E18
1E17GR-GradedRetrograde
1E18
1E17AR-AbruptRetrograde
1E18
1E17
Depth
ConventionalStep, ST
Samar Saha 109Mumbai, India
QM Confinement: Effect on ION
0
5
10
15
20
0 5 10 15 20 25 30
Transition Depth (nm)
Io
n(C
L-Q
M)/I
on(C
L) (%
)
nMOSFETS
Leff = 100 nm; Tox = 3 nm
VGS = VDS = 1.5 V; VBS = 0
GR
ARST
1e18uniform1e17
• Ion decrease due to QM confinement depends on Nch.
• Maximum drop in Ion~ 20% for Nch ~ 1x1018 cm-3.
Samar Saha 110Mumbai, India
QM Confinement: Summary
• Impact of QM confinement becomes significant for TOX < 4 nm.
• QM confinement affects:
– TOX measurement
– drive current
– scaling limits.
• Modeling approaches:
– semi-physical (e.g. van Dort)
– quantum potentials - MLDA
– 1D self-consistent Schrodinger-Poisson.
Samar Saha 111Mumbai, India
Discrete Dopant Effects
• The volume of active channel region for an advanced MOSFET: V = (W) x (L) x (Xj)
• Typically: length, L = 40 nm
width, W = 100 nm;
junction depth, Xj = 25 nm;
Nchannel = 1x1018 cm-3
Ntot = 100 impurity atoms.
The number of dopants in V is a statistical quantity.
V
P (NA cm-3)
Source
Drain
Xj
Samar Saha 112Mumbai, India
Discrete Dopant Effects
• Effects of discrete dopants:– significant threshold (Vth)
variation,Vth (10’s of mV)
– lower average Vth (10’s of mV)
– asymmetry in drive current, IDS.
• 3D transport leads to inhomogeneous conduction in sub-100 nm devices.
• Continuum diffusion models are inadequate to model discrete dopant effects in sub-100 nm MOSFETs.
Source
Drain
Samar Saha 113Mumbai, India
Discrete Dopant Effects: Summary
• 2D continuum models can predict spread in Vth.
• Full 3D simulation is necessary to predict mean.
• The role of continuum versus granular models will become increasingly important as devices continue to shrink.
Samar Saha 114Mumbai, India
Hot Electron Effects
• Effect:
– hot electron injection.
• Outcome:
– substrate current.
• Trends:
– power supplies are decreasing
– electric fields are increasing.
Samar Saha 115Mumbai, India
Hot-Carrier Effects
• Channel electron traveling through high electric field near the drain end can:
– become highly energetic, i.e. hot
– cause impact ionization and generate e and holes
holes go into the substrate creating substrate current, Isub.
• Some channel e have enough energy to overcome the SiO2-Si energy barrier generating gate current, Ig.
• The maximum e-field, Em near the drain has the greatest control of hot carrier effects.
Gate Ig
n+ Drainn+ Source
Isub
holehot e
Samar Saha 116Mumbai, India
Hot Electron Effects: Substrate Current
• Local field model (DD)
c = critical electrical field 1.2 MV/cm
= impact ionization coefficient.
– calibration of impact ionization model parameters are required to match silicon data
– tuned parameter values can be non-physical and non-predictive for a new technology.
c
n
e
qJrrGn
)(
][
Samar Saha 117Mumbai, India
Hot Electron Effects: Isub using DD Model
DD simulation results with default Isub model parameters do not match the measurement data.
Samar Saha 118Mumbai, India
Hot Electron Effects: Substrate Current
• Local energy model (HD / ET model)
“surface impact ionization”
– better predictive capability than DD approach, but still uses tuned parameters.
• Non-local energy model.
• Full band MC.
)()(
][
bulkMOSFETqJrurG n
nn
Samar Saha 119Mumbai, India
Hot Electron Effects: Summary
• Local field models are highly unphysical that result in unphysical calibrated parameters.
• Local energy models are more physical, but still require calibration of model parameters.
• Physically sound models that provide accurate results without calibration of model parameters are:
– full band MC
– non-local energy transport models.
Samar Saha 120Mumbai, India
Device TCAD: Summary
• As devices scale down to 0.1 m and below, new physical effects are coming into play.
• Existing tools treat different aspects of device simulation fairly well.
• No single tool treats all of the important physics.
• Successful device TCAD will require a firm grasp of the controlling device physics.
Samar Saha
Technology CAD: Technology Modeling, Device Design and Simulation
Industry Application: Calibration of Process and Device Models
2004 VLSI Design Tutorial, January 5, 2004 Mumbai, India
Samar Saha 122Mumbai, India
Outline
• Objectives.
• Technology and Industry Trends affecting TCAD.
• TCAD Challenges.
• TCAD Tool Set.
• Calibration:
– Process Models
– Device Models.
• Mesh Generation.
• TCAD in Technology Development.
• Summary.
Samar Saha 123Mumbai, India
Objectives
• Present issues and solutions for industrial TCAD:
– process simulation
calibration
– device simulation
key physical models
– mesh generation
optimal approach
– calibration examples
submicron process
submicron device.
Samar Saha 124Mumbai, India
Industry Trends affecting TCAD
• CMOS logic as technology driver:
– CMOS logic technology design-space much larger than
that of DRAM or BJT technologies
– CMOS logic generation life-span is extremely short
– CMOS simulation is essentially 2D.
• Logic technology offerings becoming broader:
– high-Vth devices
– thick-oxide devices
– low-Vth devices.
Samar Saha 125Mumbai, India
Industry Trends affecting TCAD
• System-on-a-chip (SOC) and logic derivatives:
– integration issues driving increasing share of TCAD
cycles
integrating memory and logic (NVRAM, DRAM)
BiCMOS
CMOS imaging
SiGe BJT and PFET.
• Net result:
Rapidly expanding opportunities for TCAD to contribute.
Samar Saha 126Mumbai, India
Industry Trends affecting TCAD
• Rapid thermal processing (RTP):
– easy process addition increases design space
– many subtle electrical effects.
• Larger wafer sizes:
– interaction of process variations on circuit performance becoming increasingly important new TCAD arena.
• New impurity species increase design options:
– In
– Ge
– N.
Samar Saha 127Mumbai, India
Industry Trends affecting TCAD
• New materials and methods:
– nitrided gate oxide
– high-K gate dielectric
– junction pre-amorphization
– SOI
– selective epitaxial growth
– laser thermal annealing (LTA).
• Net result:
– rapidly expanding design space for TCAD to cover
– process TCAD challenges predominate.
Samar Saha 128Mumbai, India
Industrial TCAD Challenges
• Challenge is to transform TCAD potential into valuable results for process and device engineers.
• Key tasks:
– system perspective
connect process recipes to device parametric/circuit performance (“virtual fab”)
organize TCAD process to make non-experts productive TCAD users and maximize productivity of experts
– process and device simulations
process simulation reflect actual process results
accurate electrical results for compact model extraction.
Samar Saha 129Mumbai, India
Industrial TCAD Challenges
• Critical assumptions for success:
– calibrate/characterize complex physical models for the present range of operation - global calibration
– timely development/implementation of required physical models
– timely calibration (local calibration) of process and device models to contribute significantly for the next generation
technology development
technology transfer.
• TCAD usage can be significantly broadened.
Samar Saha 130Mumbai, India
TCAD Tool Set
• Process simulation:
– 2D capability with
extensive detailed physical model set for implantation,
diffusion, oxidation, deposition, and etching
detailed knowledge of model formulation and
modification.
– examples based on
vendor supported SUPREM4-process platform
generalized calibration procedure.
Samar Saha 131Mumbai, India
TCAD Tool Set
• Device Simulation:
– general 2D capability based on moments of Boltzmann
equation
– control-volume discretization of DD/HD equations
– examples based on
vendor supported MEDICI-device platform
generalized calibration procedure
– user environment
vendor supported TWB-framework platform.
Samar Saha 132Mumbai, India
Calibration - Role of TCAD
• TCAD in research:– evaluate advanced device options– understand device physics.
• TCAD in technology development (TD):– perform tradeoffs for design options to reduce
experimental wafer starts– assess manufacturability and design options– diagnose device/layout problems.
• TCAD in manufacturing:– process simplification for production technologies– problem diagnosis and fix.
Accuracy is crucial, especially, for TD and manufacturing.
Samar Saha 133Mumbai, India
Need for Calibration
• Deviation of simulation and measured data:
– technology dependent:
different focus area and application
different physical models involved.
– site/fab dependent:
equipment
material
environment
measurement techniques
human interface.
Samar Saha 134Mumbai, India
Need for Calibration
• Limitation of physical models:
– secondary mechanisms become important
– model dependency on implementation details
– model short-fall in describing the target generation of process technology and devices.
• Limitation of model characterization/range:
– may not cover all possible process conditions
– may not cover all technologies
– may not be able to measure directly.
Samar Saha 135Mumbai, India
Calibration Challenges
• Experimental data:
– expensive to obtain, especially, SIMS profiles
– insufficient processing information
– statistical fluctuations.
• Model complexity:
– some parameters can not be directly measured
– more parameters than data points.
• Simulation accuracy:
– grid dependency
– practical limitation on CPU and memory.
Samar Saha 136Mumbai, India
Objective of Tool Calibration
• Device specific calibration:
– operation region (optimization)
– technology development
– items of importance.
• DOE and characterization.
• Calibration of model parameters.
• Supporting software utilities.
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General Calibration Methodology
• Use short flows to characterize process profiles:
– design process splits to cover design space.
• Use full flows to characterize devices with different dimensions (L and W dependencies).
• Tool calibration:
– match SIMS profiles
– use device data to correlate 2D effects
– match device characteristics.
• Two-phase process.
Samar Saha 138Mumbai, India
Process Simulation Overview
• Model calibration for process simulation:
– overview of calibration process
– Phase 1: 1D impurity calibration
methodology
example - nMOSFET channel profile
– Phase 2: 2D calibration (process + device)
methodology
example - reverse short channel effect (RSCE).
• Summary.
Samar Saha 139Mumbai, India
Process Modeling Approach
• Predictive capability for a wide range of logic and memory technologies necessitates:
– new implant tables with new species like In, Ge etc.
– 3-stream TED model for dopant, interstitials, and vacancies
– “plus-n” damage model with accumulated damage from multiple implants
– amorphization due to implant damage
– transient activation/deactivation of dopants
– dislocation loops as source/sink for interstitials
– 3-phase segregation model.
Samar Saha 140Mumbai, India
Process Simulation Calibration: Overview
• Model calibration (Phase 1)
– implant models
– diffusion models
– oxidation models
– etch/deposition models.
TEM/SEM cross-sections, SIMS profiles, key (1D) electrical parameters.
• Technology/2D calibration (Phase 2)
– key process model parameters
– selected set of 2D electrical parameters.
Samar Saha 141Mumbai, India
MOSFETs Process Model Calibration Flow
Match SIMS profilesAdjust for dose loss
Match Vth
RSCE
Two-dimensional CalibrationDIBLSurface recombinationDamage by S/D implant
One-dimensional CalibrationImplant moments/tableOEDSegregation (set by channel profile)Diffusivity (in oxide for dose loss)Tox (QM,Poly-depletion corrections)
One-dimensional CalibrationDiffusivity of dopant-defect pairDiffusivity of defects
Samar Saha 142Mumbai, India
MOSFETs 1D Process Model Calibration
p-substrate
p-well n-well
n+
PMOS
n+ p+p+STI
NMOS
A B C F E D
Cross-section for short loop experiments: A / D NMOS / PMOS channel
B / E NMOS / PMOS SDE
C / F NMOS / PMOS S/D.
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A Typical Short Loop Experiment for P-Well
Wafer No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14
Sacrificial oxide x x x x x x x x x x x x x xP-Well (B) implant x x x x x x x x x x x x x xN-PT (B) implant x x x x x x x x x x x x xWell drive x x x x x x x x x x x xnVth (BF2) implant x x x x x x x x x x xGate oxidation x x x x x x x x x xPoly re-oxidation x x x x x x x x xRTA1 x x x x x x x xSpacer dep/etch x x x x x x xS/D oxide x x x x x xN+ (As) implant x xRTA2 x x x
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Calibration Example: Channel Profile
• Use of detailed physical models to achieve 1D SIMS profile fit:
– typical Phase-1 calibration activity
– model updated over several technology generations.
• Channel profile after complete technology thermal cycle.
• Initial approach for implant and diffusion
– MC implant
significant CPU burden
– scaled solid solubility
– physics-based implant moments / implant table update.
Samar Saha 145Mumbai, India
Example: NMOS Channel Profile
P-Well B, 1E13 @ 200 KeVafter spacer deposition/etch
Depth (m)
log1
0 (B
oron
)
SIMS
Simulation
Samar Saha 146Mumbai, India
Technology Calibration - Phase 2
• Coupled process and device simulations using Phase 1 calibration data.
• Target output (electrical) parameters:– C - V curves
– Vth
– RSCE.
• Input variables (5 - 8 process model parameters):– point-defect distributions from implants
“plus-n” model
– key impurity segregation coefficients
– parabolic oxidation rate.
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2D Calibration Example: RSCE
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Process Modeling: Summary
• Systematic process model calibration methodology is critical.
• Observed success within a (CMOS) technology:
– process re-optimization offered a significant improvement in device performance
– process centering achieved at manufacturing co-location with minimum development effort.
• Observation:
– each successive technology generation requires a significant calibration effort (model update).
Samar Saha 149Mumbai, India
Device TCAD
• Role of device simulation in TCAD
• Key physical models and examples:
– mobility models for deep sub-micron CMOS
– quantum effects in scaled CMOS devices
– DD model.
• Device model calibration:
– impact ionization with DD model.
• Summary.
Samar Saha 150Mumbai, India
Device Simulation Role in TCAD
• Simulate device electrical behavior with sufficient accuracy to calibrate process simulation models:
– primarily 2D electrostatic simulation
Vth, DIBL, Ioff, body effect, capacitances
– expect DD model is sufficient for most requirements for MOSFETs with Leff 0.1 m.
• Provide capability for the physical simulation of wide range of device parameters:
– substrate current, latch-up, ESD, and so on.
• Support exploratory device simulation for research.
Samar Saha 151Mumbai, India
Device Simulation: CPU Burden
• Numerical issues associated with device simulation are well established:– core issue is repeated solution of large, sparse, ill-
conditioned, non-symmetric sets of linear equations
– typical industrial CMOS problem: ~ 10,000 mesh nodes
simultaneous solution for (, n, p)
– iterative solution methods often exhibit lack of convergence on problems of industrial interest.
• Optimized direct solution methods along with optimal mesh generation techniques can reduce CPU burden significantly without sacrificing accuracy.
Samar Saha 152Mumbai, India
Critical TCAD Models: Carrier Mobility
• Device-design trends arising from CMOS scaling require consideration of:
– coulombic scattering in the inversion layer
high substrate/channel doping levels
channel doping can vary significantly across the device
– inversion- and accumulation-layer mobility.
• Industrial use of a mobility model requires:
– strictly local calculation of mobility
minor increase in program complexity
no restrictions on device geometries or device designs.
Samar Saha 153Mumbai, India
Critical Device TCAD Models: QM Effects
• CMOS scaling requires inclusion of inversion-layer QM effects in device simulation for:– thinner gate oxides
– higher substrate doping.
• Inversion-layer QM correction model must be:– strictly local calculation of required physical quantities
minor increase in program complexity
no restrictions on device geometries or device designs
– acceptable CPU burden
– no significant degradation in robustness.
• Models: van Dort / MLDA.
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MOSFETs: Device Model Calibration Flow
Work functionQM modelLow field mobility
High field mobility
Band to band tunneling
Impact Ionization
IDS vs. VGS (Vth)
@ VBS = 0,VDS = 50 mV
Isub vs. VGS
@ VBS = 0,VGS = 0
IDS vs. VGS (IDS vs. VDS)
@ VBS = 0,VDS = VDD
IDS vs. VDS
@ VBS = 0,VGS = 0
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Example: Impact Ionization Model
DD-simulation over estimates Isub by more than an order.
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Example: Impact Ionization Model
• Impact Ionization model calibration:
– used calibrated process model (technology calibration)
– used calibrated device models (device calibration)
– calibrate impact ionization coefficients.
• The electron impact ionization rate:
where
Ai and Bi are empirical constants
Eeff = effective electric field due to non-local effect.
eff
iii E
BA exp
Samar Saha 157Mumbai, India
Example: Impact Ionization Model
For DD, transform the model in terms of local electric field, E. Assume, Eeff E,
Eeff = k *
where
k and are constants depending on the spatial variation of E near the drain-end of the channel.
Substituting for Eeff and defining Bi k * i, the
modified impact ionization coefficient is:
Optimize i and to fit the measurement data.
EA i
ii exp
Samar Saha 158Mumbai, India
Example: Impact Ionization Model
Calibrate device TCAD models: comparison of I - V data.
Samar Saha 159Mumbai, India
Example: Impact Ionization Model
Simulation with calibrated impact ionization coefficients.
Samar Saha 160Mumbai, India
Example: Impact Ionization Model
Simulation with calibrated impact ionization coefficients.
Samar Saha 161Mumbai, India
Device TCAD: Summary
• Vendor supported device TCAD tools work very well with the present applications such as:
– MOSFET I - V and C - V characteristics for technology development
logic
DRAM.
• Model selection and calibration show good results for sub-0.25 m technology development.
• Device TCAD effectiveness depends on:
– mobility model suitable for the target technology
– inversion-layer QM effects.
Samar Saha 162Mumbai, India
Mesh Generation for Simulation
• Role and Requirements.
• Methods:
– structured
– quadtree
– unstructured
– hybrid.
• Example:
– typical MOSFET mesh and gridding considerations.
• Summary.
Samar Saha 163Mumbai, India
Mesh Generation: Role and Requirements
• Requirement is to support complete automation of process-to-device simulation transition:
– highest barriers to expanded TCAD usage are
mesh generation
process simulation accuracy.
• Consistent and specialized grid distribution is an important key to simulation of high-performance MOSET devices:
– resolution of inversion layers and depletion regions
– resolution of mobility-model physical effects.
Samar Saha 164Mumbai, India
Mesh Generation: Role and Requirements
• Requirements:
– must accept device structures from detailed process simulation
– no restrictions on device structures
– mesh generation approach must minimize computational burden without compromising solution robustness and accuracy
key:
anisotropic grid-point distributions (the capability of supporting extreme differences in grid-point spacing in x- and y-directions).
Samar Saha 165Mumbai, India
Mesh Generation MethodsMethods Advantages Disadvantages
Structured:- algebraic- elliptic
- Precise grid control- Smooth grid transition- Supports anisotropic grid
scales.
- Requires significantstructural preprocessing
- Difficult to automate- Large grid sizes.
Unstructured - Very general- Easy to automate.
- Do not support anisotropicgrids
- Large grid size for industrialproblems.
Quadtree/Octree:- isotropic
recursivesubdivision
- Very general- Easy to automate.
- Needs advanced features tosupport anisotropic grids
- Large grid size for industrialproblems.
Hybrid:- recursive
subdivision foranisotropy
- unstructuredmesh algorithm
- Very general- Easy to automate- Precise and smooth grids- Supports grid scales- Minimizes mesh sizes- Minimizes CPU burden.
- Need to identify differentregions for gridding prior todevice simulation.
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Hybrid Mesh Generation: Half-MOSFET
x
y
Gate S/DC
han
nel Source/Drain
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Mesh Generation
Dependence of device performance on vertical grid-spacing.
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Mesh Generation
Dependence of device performance on horizontal grid-spacing.
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Mesh Generation: Summary
• Mesh generation is the critical component of an effective TCAD system.
• Simulation results vary significantly on mesh and may result in:
– unphysical calibration parameters
– unpredictable/inconsistent results.
• Robust mesh:
– allows process simulators to be consistently and robustly linked to device simulators by non-experts
– significantly reduces CPU burden for device simulation.
Samar Saha 170Mumbai, India
Industry Application: Summary
• Vendor supported TCAD tools offer most simulation capabilities for industrial usage.
• Systematic calibration procedure is required to support efficient:
– process technology optimization
– future technology development.
• Mesh generation is crucial for predictive technology simulation.
• Well calibrated physical models provide efficient predictive TCAD capability.
Samar Saha
Technology CAD: Technology Modeling, Device Design and Simulation
Industry Application: TCAD in Device Research and Compact Modeling
2004 VLSI Design Tutorial, January 5, 2004 Mumbai, India
Samar Saha 172Mumbai, India
Research Application: Overview
• Role of TCAD in device research:
– how it differs from development/manufacturing.
– examples
sub-100 nm MOSFET device design
design optimization of FinFETs.
• TCAD for compact modeling:
– TCAD-based compact model parameter extraction for substrate current modeling
– flash memory cell macro model.
• Summary.
Samar Saha 173Mumbai, India
Role of TCAD in Research
• Performance analysis of future device design options to guide development effort.
• Understand device physics for new device concepts.
• Typically, research TCAD is not the “virtual fab” paradigm:
– process simulation is not used, since device cannot be made with current process technologies.
• Circuit performance is directly evaluated from the output of device simulation using two different ways:
1 device simulation model extraction circuit simulation
2 mixed-mode device/circuit simulation.
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Example: Sub-100 nm MOSFET Design
• Design issues in achieving MOSFET devices near the lower limit of channel length:
– scaling requirements
– material limitations of scaling
– feasibility of continuous scaling.
• Methodology to generate sub-100nm MOSFET device characteristics vs. scaling parameters.
• Results and discussions.
• Summary.
Samar Saha 175Mumbai, India
Scaling Requirements vs. Limitations
Scaling Requirements Present Limitations
A reduction in gate oxidethickness, TOX in proportion tothe gate length, Lg to: control threshold voltage, Vth control drain-induced barrier
lowering (DIBL) improve drive current, IDSAT.
SiO2-Tox(eff) 2 nm to maintain: tolerable chip standby power ~
100 mW range tolerable direct-tunneling gate
leakage current, Ig ~ 1 A/cm2
off-state leakage current, Ioff ~ 1nA/m.
A reduction in source-drainextension junction depth, Xj
with scaling Lg to control: short channel effect (SCE).
Xj 30 nm to maintain: lower source-drain series
resistance, RSD higher IDSAT.
A reduction in Lg to: improve device performance.
Lg 60 nm to maintain: Xj 30 nm
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Feasibility of Continuous TOX and Xj Scaling
• Scaling Tox(eff) 2 nm is feasible with a highK
dielectric gate material to maintain:
– a thicker value of TOX(physical) for a tolerable value of Lg
– a target value of gate capacitance (COX) equivalent to
that of an ultra-thin SiO2 gate material.
• Scaling Xj 30 nm is essential to:
– scale down Lg, gate area, and COX
– improve ac device performance.
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Idealized Device Simulation Structure
• Channel doping profile: vertically and laterally non-uniform.
• SDE: heavily-doped source-drain extension regions with junction depth Xj.
• DSD: heavily-doped deep source-drain of junction depth Xjd.
• Halo: channel-type doping around SDE regions.
Leff
HaloXjd
Xj
HaloDSD
SDE
LextTOX
Lg
Body (B)
Poly-Si gate Spacer
Samar Saha 178Mumbai, India
Design Simulation Experiment
• Designed CMOS technologies for Leff = 25 nm with:
– {Lg = 40 nm, Xj 14 nm, Tox(eff) = {1,1.5, 2} nm}
– {Lg = 50 nm, Xj 20 nm, Tox(eff) = {1,1.5, 2} nm}
– {Lg = 60 nm, Xj 26 nm, Tox(eff) = {1,1.5, 2} nm}.
• For each technology:– non-uniform vertical channel doping profile was optimized
for the target long channel |Vth| 0.23 V
– two halo profiles (double halo architecture) were used to
reduce DIBL from both SDE and DSD regions
achieve non-uniform lateral channel doping profile with the target |Ioff| 10 nAm @ |VDD| = 1 V.
Samar Saha 179Mumbai, India
Simulation Strategy
• Optimized technology parameters:
– SDE peak concentration 2.5x1020 cm-3
– DSD peak concentration 3.7x1020 cm-3
– peak halo concentration 5x1018 - 1x1019 cm-3.
• Channel concentration dependent on Lg.
• Device characteristics were generated using MEDICI with:
– hydrodynamic model for semiconductors
– van Dort’s Quantum Mechanical model
– calibrated device models (global calibration!!).
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Simulated Channel Doping Contours
Lg
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-0.45
-0.35
-0.25
-0.15
-0.05
0.05
0.15
0.25
0.35
0.45
10 20 30 40 50 60 70 80 90 100
Leff (nm)
Vth
(V
)
Tox(eff) = 2.0 nmTox(eff) = 1.5 nmTox(eff) = 1.0 nm
40 nm Technology; Xj 14 nm
|VDS| = 0.05 V; VBS = 0
nMOSFET
pMOSFET
(a)
-0.45
-0.35
-0.25
-0.15
-0.05
0.05
0.15
0.25
0.35
0.45
10 20 30 40 50 60 70 80 90 100
Leff (nm)
Vth
(V
)
Tox(eff) = 2.0 nmTox(eff) = 1.5 nmTox(eff) = 1.0 nm
60 nm Technology; Xj 26 nm
|VDS| = 0.05 V; VBS = 0
pMOSFET
nMOSFET
(b)
• |Vth| increases with the increase in TOX(eff) for all devices.
• Devices with Leff = 25 nm and TOX(eff) = 2 nm, |Vth| > 0.4 V is too high
for high-performance operation @ |VDD| 1 V.
• TOX(eff) < 2 nm offers lower |Vth| for low power operation.
Simulated Vth vs. Leff for different TOX(eff)
Samar Saha 182Mumbai, India
Simulated IDSAT vs. Ioff for different TOX(eff)
• Devices with |Ioff| nAm represents Leff = 25 nm.
• At a constant |Ioff| 2 nA/m:
– |IDSAT| increases as TOX(eff) decreases
– TOX(eff) < 2 nm is essential to improve IDSAT for Leff = 25 nm devices.
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
5.0E-05 2.0E-04 3.5E-04 5.0E-04 6.5E-04 8.0E-04
|IDSAT| (A/m)
|Iof
f| (A
/m
)
Tox(eff) = 2.0 nmTox(eff) = 1.5 nmTox(eff) = 1.0 nm
|VDS| = 1 V; VBS = 0
nMO
SFE
T
pMO
SFE
T
40 nm Technology
Xj 14 nm(a)1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
5.0E-05 2.0E-04 3.5E-04 5.0E-04 6.5E-04 8.0E-04
|IDSAT| (A/m)
|Iof
f| (A
/m
)
Tox(eff) = 2.0 nmTox(eff) = 1.5 nmTox(eff) = 1.0 nm
pMO
SFE
T
nMO
SFE
T
|VDS| = 1 V; VBS = 0
60 nm Technology
Xj 26 nm(b)
Samar Saha 183Mumbai, India
• For a typical 50 nm technology with Leff = 25 nm and Tox(eff) = 1 nm:
– S 80 mV/decade
– |DIBL| 60 mV
– IDSAT(n) 680 A/m, |IDSAT(p)| 275 A/m @ |VGS| = 1 V = |VDS|.
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
-1.0 -0.5 0.0 0.5 1.0
V(Gate) (V)
|I(D
rain
)| (
A/
m)
|V(Drain)| = 1.00 V|V(Drain)| = 0.05 V
Tox(eff) = 1 nmLg = 50 nm
Xj 20 nm
Leff = 25 nmS 80 mV/decade|DIBL| 0.060 V
pMOSFETnMOSFET
(a)
V(Source) = 0V(Body) = 0
0.E+00
1.E-04
2.E-04
3.E-04
4.E-04
5.E-04
6.E-04
7.E-04
-1.0 -0.5 0.0 0.5 1.0
V(Drain) (V)
|I(D
rain
)| (
A/
m)
|V(Gate)| = 1.0 V|V(Gate)| = 0.8 V|V(Gate)| = 0.6 V|V(Gate)| = 0.4 V
pMOSFET
nMOSFET
Tox(eff) = 1 nm; Lg = 50 nm
Xj 20 nm; Leff = 25 nm
V(Source) = 0 = V(Body)
(b)
Simulated I - V Data for TOX(eff) = 1 nm
Samar Saha 184Mumbai, India
• For 25 nm devices of a 50 nm CMOS technology, as Tox(eff) increases from 1 nm 1.5 nm:– S increases [S 8 mV/decade]
– DIBL increases [(DIBL) 30 mV]
– |IDSAT| decreases [IDSAT(n) 102 A/m; IDSAT(p) 42 A/m].
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
-1.0 -0.5 0.0 0.5 1.0
V(Gate) (V)
|I(D
rain
)| (
A/
m)
|V(Drain)| = 1.00 V|V(Drain)| = 0.05 V
Tox(eff) =1.5 nmLg = 60 nm
Xj 20 nm
Leff = 25 nmS 88 mV/decade|DIBL| 0.090 V
pMOSFETnMOSFET
(a)
V(Source)=0V(Body)=0
0.E+00
1.E-04
2.E-04
3.E-04
4.E-04
5.E-04
6.E-04
-1.0 -0.5 0.0 0.5 1.0
V(Drain) (V)
|I(D
rain
)| (
A/
m)
|V(Gate)| = 1.0 V|V(Gate)| = 0.8 V|V(Gate)| = 0.6 V|V(Gate)| = 0.4 V
pMOSFETnMOSFET
Tox(eff) = 1.5 nm; Lg = 50 nm
Xj 20 nm; Leff = 25 nm
V(Source) = 0 = V(Body)
(b)
Simulated I - V Data for TOX(eff) = 1.5 nm
Samar Saha 185Mumbai, India
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
-1.0 -0.5 0.0 0.5 1.0
V(Gate) (V)
|I(D
rain
)| (
A/
m)
|V(Drain)| = 1.00 V|V(Drain)| = 0.05 V
Tox(eff) = 2 nmLg = 50 nm
Xj 20 nm
Leff = 25 nmS 96 mV/decade|DIBL| 0.12 V
pMOSFET nMOSFET
(a)
V(Source)=0V(Body)=0
0.E+00
1.E-04
2.E-04
3.E-04
4.E-04
5.E-04
-1.0 -0.5 0.0 0.5 1.0
V(Drain) (V)
|I(D
rain
)| (
A/
m)
|V(Gate)| = 1.0 V|V(Gate)| = 0.8 V|V(Gate)| = 0.6 V|V(Gate)| = 0.4 V
pMOSFET nMOSFET
Tox(eff) = 2 nm; Lg = 50 nm
Xj 20 nm; Leff = 25 nm
V(Source) = 0 = V(Body)
(b)
• For 25 nm devices of a 50 nm CMOS technology, as Tox(eff) increases from 1 nm 2 nm:– S increases [S 16 mV/decade]
– DIBL increases [(DIBL) 60 mV]
– |IDSAT| decreases [IDSAT(n) 214 A/m; IDSAT(p) 72 A/m].
Simulated I - V Data for TOX(eff) = 2 nm
Samar Saha 186Mumbai, India
Simulated Vth vs. Xj for Different TOX(eff)
-0.45
-0.35
-0.25
-0.15
-0.05
0.05
0.15
0.25
0.35
0.45
12 14 16 18 20 22 24 26 28
X j (nm)
Vth
(V
)
Tox(eff) = 2.0 nmTox(eff) = 1.5 nmTox(eff) = 1.0 nm
|VDS| = 0.05 V; VBS = 0
L eff = 25 nm; |I off | 10 nA/m
pMO
SF
ET
nMO
SF
ET
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Simulated IDSAT vs. Xj for Different TOX(eff)
1.8E-04
2.8E-04
3.8E-04
4.8E-04
5.8E-04
6.8E-04
12 14 16 18 20 22 24 26 28
X j (nm)
| I DS
AT
| (A
/m
)
Tox(eff) = 1.0 nm
Tox(eff) = 1.5 nmTox(eff) = 2.0 nm
nM
OS
FE
Tp
MO
SF
ET
|VGS| = |VDS|=1V; VBS=0|I off | @ 10 nA/mmL eff = 25 nm
Samar Saha 188Mumbai, India
Simulated DIBL vs. Xj for Different TOX(eff)
10
30
50
70
90
110
130
150
12 14 16 18 20 22 24 26 28X j (nm)
dV
th(D
IBL
) (m
V/V
)
Tox(eff) = 2.0 nm (nMOSFET)Tox(eff) = 1.5 nm (nMOSFET)Tox(eff) = 1.0 nm (nMOSFET)Tox(eff) = 2.0 nm (pMOSFET)Tox(eff) = 1.5 nm (pMOSFET)Tox(eff) = 1.0 nm (pMOSFET)
Leff = 25 nm
VBS = 0
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Simulated S vs. Xj for Different TOX(eff)
60
65
70
75
80
85
90
95
100
12 14 16 18 20 22 24 26 28
X j (nm)
S (
mV
/dec
ad
e)
Tox(eff) = 2.0 nm (nMOSFET)Tox(eff) = 1.5 nm (nMOSFET)Tox(eff) = 1.0 nm (nMOSFET)Tox(eff) = 2.0 nm (pMOSFET)Tox(eff) = 1.5 nm (pMOSFET)Tox(eff) = 1.0 nm (pMOSFET)
Leff = 25 nm
VBS = 0
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Simulated Delay for Different Xj and Lg
0
5
10
15
20
25
30
35
14 16 18 20 22 24 26 28X j (nm)
Incr
emen
tal G
ate
Del
ay,
(%
)
Tox(eff) = 2.0 nmTox(eff) = 1.5 nmTox(eff) = 1.0 nm
= [{(Xj) - (Xj = 14 nm)}/(Xj = 14 nm)]100
|VDD| = 1 V; Fanout = 1
Leff = 25 nm
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Sub-100 nm MOSFET Design: Summary
• The simulation results show the feasibility of 25 nm MOSFETs with:– TOX(eff) 2 nm to
maintain lower |Vth| for |VDD| 1 V operation
achieve higher |IDSAT| for a target value of |Ioff|
lower value of DIBL lower value of S 80 mV/decade
– Xj 30 nm to
scale Lg 60 nm improve device speed.
• 25 nm devices with Xj 14 nm and Lg 40 nm show a significant improvement in speed.
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• Design FinFET (double-gate MOSFET) Simulation
Structure.
• Optimize Different Fin-dimensions.
• Feasibility of 20 nm FinFET Device.
• Comparison of 20 nm Device Performance using
FinFET vs. Conventional MOSFET Architecture.
• Summary.
Example: Double Gate MOSFET Design
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Idealized Double Gate MOSFET Structure
Tox
Tox
TSiSource Drain
Top Gate
Bottom Gate
Lg
• Tox = Top/bottom gate oxide thickness.
• TSi = Un-doped/lightly-doped channel width.
• Lg = Channel length.
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Simulated DG-MOSFET FinFET Structure
Tfin
Hfin
Lg
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Major Process Steps to Generate FinFETs
1. D
efin
e S
i-F
in
2. G
ate
oxid
atio
n
3. P
oly-
Si g
ate
4. N
itri
de s
pace
r
S/D
impl
ant
5. H
alf-
stru
ctur
e
6. Full-structure
Oxide
Si-Fin
BOX
Nitride
Poly
Nit
ride
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Critical Parameters for FinFET Simulation
• Parameters used for simulation structure design:
– Tfin = 10 to 30 nm
– Hfin = 50 nm
– Lg = 10 to 50 nm
– Tox = 1.5 nm.
• For device simulation, channel doping was optimized to obtain Vth 0.1 V for Lg = 20 nm nFinFETs.
• Device structures and the characteristics were generated using 3D-simulation tool Taurus (from Synopsys).
Samar Saha 197Mumbai, India
Vth vs. Lg for Different Tfin; Hfin = 50 nm
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
0.3
10 20 30 40 50L (Gate) (nm)
Vth
(V)
Tfin = 10 nm
Tfin = 20 nm
Tfin = 30 nm
Samar Saha 198Mumbai, India
IDSAT vs. Lg for Different Tfin; Hfin = 50 nm
5.0E-04
1.0E-03
1.5E-03
2.0E-03
2.5E-03
10 20 30 40 50L (Gate) (nm)
I DS
AT
(A
/m
)
Tfin = 10 nm
Tfin = 20 nm
Tfin = 30 nm
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S vs. Lg for Different Tfin; Hfin = 50 nm
50
70
90
110
130
150
10 20 30 40 50
L (Gate) (nm)
S (m
V/d
ecad
e)
Tfin = 10 nm
Tfin = 20 nm
Tfin = 30 nm
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I V Characteristics of 20 nm FinFETs
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FinFETs vs. Conventional MOSFETs
DeviceParameters
Units FinFETs Double-haloMOSFETs
Leff nm 20 20Tox nm 1.5 1.5Vth V 0.13 0.35IDSAT (VGS = VDS = 1 V) A/m 775 587Ioff (VGS = 0, VDS = 1 V) A/m 3 0.05DIBL V 32 130S-factor mV/decade 83 100
20 nm FinFETs show superior device performance compared to 20 nm conventional MOSFETs.
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• TCAD is used to design and study FinFET device characteristics.
• The simulation data for nFinFETs with 10 nm < Lg < 50 nm and Hfin = 50 nm show:
– higher Vth roll-off as Lg decreases for thicker Tfin devices
– lower IDSAT in thinner Tfin devices due to higher s/d resistance
– increase in S with decrease in Lg for Tfin < 50-nm
– S 60 mV/decade for all Tfin with Lg >>40-nm.
• 20 nm FinFETs show superior device performance than 20 nm conventional bulk-MOSFETs.
FinFET Design: Summary
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Example: Compact Model Extraction for Isub
• Procedure for TCAD-based Compact Model Parameter Extraction.
• Simplification of Isub Model for TCAD-based Compact
Modeling.
• Model Extraction.
• Model Verification.
• Summary.
Samar Saha 204Mumbai, India
Substrate Current, Isub Model
Isub generated due to impact ionization is given by:
where
Ai and Bi are impact ionization parameters
lc = characteristic length of saturation region
Em = maximum lateral electric field near the drain
Ec = critical electric field for velocity saturation.
,exp
m
iDSmc
i
isub E
BIEl
B
AI
2
2
cc
DSATDS El
VV
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Substrate Current, Isub Model
At strong inversion (VDS >> VDSAT) Em is given by:
where
Leff = effective channel length of device
Vth = threshold voltage of device.
thGSeffc
thGSeffcDSAT VVLE
VVLEV
c
DSATDSm l
VVE
DSATDS
ciDSDSATDS
i
isub VV
lBIVV
B
AI exp
Samar Saha 206Mumbai, India
Substrate Current, Isub Model
• The bias dependence of Ec is given by:
Ec = Ec0 + EcgVGS + EcbVBS
where Ec0, Ecg, and Ecb are model parameters given by:
Ec0 = Ec @ VGS = VBS = 0
Ecg = slope of Ec vs. VGS plot @ VBS = constant
Ecb = slope of Ec vs. VBS plot @ VGS = constant
• The bias dependence of lc is given by:
lc = (lc0 + lc1VDS)TOX
here lc0 and lc1 are model parameters.
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Isub Model Parameters
• Empirical constants:– Ai = 1.65x106 (1/cm)
– Bi = 1.66x106 (V/cm)
• Technology dependent parameters:– Ec0 = bias independent constant (V/cm)
– Ecg= gate bias dependent parameter (1/cm)
– Ecb = back-gate bias dependent parameter (1/cm)
– lc0 = bias independent constant (cm)
– lc1 = bias dependent constant (cm/V).
We assume, lc = lc0 is a technology dependent constant for TCAD-based parameter extraction (i.e. ignore lc1).
Samar Saha 208Mumbai, India
TCAD-based Isub Model Extraction
VDSAT extraction
Ec extraction
lc extraction
SPICE simulation
Format I - V dataCompute Isub/IDS
DeviceSimulation
Device ModelCalibration
At each VGS, generate:IDS - VDS and Isub - VDS
ProcessSimulation
Process ModelCalibration
Generate:Device Structure
Extraction of{Ec0, Ecg, Ecb}
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Parameter Extraction: VDSAT
VDSAT is extracted by mapping constant Isub/IDS contours on IDS vs. VDS
family of simulated curves.
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Parameter Extraction: Ec0, Ecg, and Ecb
• Ec0 and Ecg extraction:
– extract VDSAT for different values of VGS at VBS = 0.
– compute Ec from:
– plot Ec vs. VGS to extract:
Ec0 = intercept @ VGS = 0
Ecg = slope.
• Same procedure to extract Ecb with VBS 0.
thGSeffc
thGSeffcDSAT VVLE
VVLEV
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Parameter Extraction: lc and Components
• The simplified from of the expression:
log(Y) = mX + C,
where
X = 1/(VDS - VDSAT)
Y = Isub/[IDS(VDS - VDSAT)]
• Parameters are extracted from log(Y) vs. X plots:
slope, m = - Bi lc
intercept, C = ln(Ai/Bi).
DSATDS
ciDSDSATDS
i
isub VV
lBIVV
B
AI exp
Samar Saha 212Mumbai, India
Parameter Extraction: lc and Components
Samar Saha 213Mumbai, India
TCAD-based Isub Models
• For nMOSFET devices of the target technology:
+ Ec0 = 5.50E+04 (V/cm)
+ Ecg = 3.50E+03 (1/cm)
+ lc = 1.38E-05 (cm)
+ Ai = 1.65E+06 (1/cm)
+ Bi = 1.66E+06 (V/cm)
Samar Saha 214Mumbai, India
Model Verification
Measurement and simulation data using the extracted models.
Samar Saha 215Mumbai, India
Model Verification
Measurement and simulation data using the extracted models.
Samar Saha 216Mumbai, India
Model Extraction for Isub: Summary
• The example shows the basic idea to use TCAD for compact model parameter extraction using:
– calibrated process models for process TCAD
– calibrated device models for device TCAD
– simplified equations and extraction routines, as needed.
• Process and device models were calibrated for the target technology.
• Isub model is simplified to extract model parameters.
• The simulation data using TCAD-based model agree very well with the measurement data.
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Example: Flash Memory Cell - Macro Model
• Flash Memory Cell Compact Modeling
– split gate cell
– two-transistor macro model
– necessity for TCAD-based macro model.
• Model extraction.
– procedure.
Samar Saha 218Mumbai, India
Flash Memory Cell - Split Gate Structure
• Cell consists of:
– WL transistor
– FG transistor.
• FG may not have contact pad for measurement.
• Typically, 1T-cell model is used.
• 2T-model provides more accurate cell characteristics.
TCAD-based.
Samar Saha 219Mumbai, India
Flash Memory Cell: TCAD-based Model
CalibratedDevice Model
CalibratedProcess Model
Extract SPICEModel for T1
Extract SPICEModel for T2
Model Verification
SimulateI - V for T1
SimulateTest Structures
SPICE/CircuitSimulation
GenerateMacro Model
Ca
libra
ted
De
vice
Mod
el
SimulateI - V for T2
Samar Saha 220Mumbai, India
TCAD in Research & Modeling: Summary
• Device TCAD can be successfully used in device research to:
– study different device options
– examine new device ideas
– optimize device design range for technology development guideline.
• Calibrated TCAD models can be used accurately to:
– predict device performance
– extract compact model
– predict circuit performance.
Samar Saha 221Mumbai, India
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Samar Saha 222Mumbai, India
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Samar Saha 223Mumbai, India
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Samar Saha 224Mumbai, India
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Samar Saha 225Mumbai, India
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Samar Saha 226Mumbai, India
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